diff mbox series

[11/13] net/mlx5: fix query for NIC flow cap

Message ID	20231029182300.227879-12-getelson@nvidia.com (mailing list archive)
State	Accepted, archived
Delegated to:	Raslan Darawsheh
Headers	Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C From: Gregory Etelson <getelson@nvidia.com> To: <dev@dpdk.org> CC: <getelson@nvidia.com>, <mkashani@nvidia.com>, <rasland@nvidia.com>, "Ori Kam" <orika@nvidia.com>, <bingz@nvidia.com>, Matan Azrad <matan@nvidia.com>, Viacheslav Ovsiienko <viacheslavo@nvidia.com>, Suanming Mou <suanmingm@nvidia.com> Subject: [PATCH 11/13] net/mlx5: fix query for NIC flow cap Date: Sun, 29 Oct 2023 20:22:58 +0200 Message-ID: <20231029182300.227879-12-getelson@nvidia.com> In-Reply-To: <20231029182300.227879-1-getelson@nvidia.com> References: <20231029182300.227879-1-getelson@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain Precedence: list Errors-To: dev-bounces@dpdk.org
Series	net/mlx5: support more REG C registers \| [00/13] net/mlx5: support more REG C registers [01/13] net/mlx5/hws: Definer, add mlx5dr context to definer_conv_data [02/13] net/mlx5: add flow_hw_get_reg_id_from_ctx() [03/13] net/mlx5/hws: Definer, use flow_hw_get_reg_id_from_ctx function call [04/13] net/mlx5: add rte_device parameter to locate HWS registers [05/13] net/mlx5: separate port REG_C registers usage [06/13] net/mlx5: merge REG_C aliases [07/13] net/mlx5: initialize HWS flow tags registers in shared dev context [08/13] net/mlx5/hws: adding method to query rule hash [09/13] net/mlx5: add support for calc hash [10/13] net/mlx5: fix insert by index [11/13] net/mlx5: fix query for NIC flow cap [12/13] net/mlx5: add support for more registers [13/13] net/mlx5: add validation support for tags

Checks

Context	Check	Description
ci/checkpatch	success	coding style OK

Commit Message

Gregory Etelson Oct. 29, 2023, 6:22 p.m. UTC

  From: Ori Kam <orika@nvidia.com>

Add query for nic flow table support bit.

Fixes: 5f44fb1958e5 ("common/mlx5: query capability of registers")
Cc: bingz@nvidia.com

Signed-off-by: Ori Kam <orika@nvidia.com>
---
 drivers/common/mlx5/mlx5_devx_cmds.c | 1 +
 1 file changed, 1 insertion(+)

Comments

Dariusz Sosnowski Oct. 30, 2023, 8:26 a.m. UTC | #1

Hi,

> -----Original Message-----
> From: Gregory Etelson <getelson@nvidia.com>
> Sent: Sunday, October 29, 2023 19:23
> To: dev@dpdk.org
> Cc: Gregory Etelson <getelson@nvidia.com>; Maayan Kashani
> <mkashani@nvidia.com>; Raslan Darawsheh <rasland@nvidia.com>; Ori Kam
> <orika@nvidia.com>; Bing Zhao <bingz@nvidia.com>; Matan Azrad
> <matan@nvidia.com>; Slava Ovsiienko <viacheslavo@nvidia.com>; Suanming
> Mou <suanmingm@nvidia.com>
> Subject: [PATCH 11/13] net/mlx5: fix query for NIC flow cap
> 
> External email: Use caution opening links or attachments
> 
> 
> From: Ori Kam <orika@nvidia.com>
> 
> Add query for nic flow table support bit.
> 
> Fixes: 5f44fb1958e5 ("common/mlx5: query capability of registers")
> Cc: bingz@nvidia.com
> 
> Signed-off-by: Ori Kam <orika@nvidia.com>
Acked-by: Dariusz Sosnowski <dsosnowski@nvidia.com>

Thanks,
Dariusz Sosnowski

diff mbox series

Patch

diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c
index ff2d6d10b7..3afb2e9f80 100644
--- a/drivers/common/mlx5/mlx5_devx_cmds.c
+++ b/drivers/common/mlx5/mlx5_devx_cmds.c
@@ -1082,6 +1082,7 @@  mlx5_devx_cmd_query_hca_attr(void *ctx,
 	attr->striding_rq = MLX5_GET(cmd_hca_cap, hcattr, striding_rq);
 	attr->ext_stride_num_range =
 		MLX5_GET(cmd_hca_cap, hcattr, ext_stride_num_range);
+	attr->nic_flow_table = MLX5_GET(cmd_hca_cap, hcattr, nic_flow_table);
 	attr->max_flow_counter_15_0 = MLX5_GET(cmd_hca_cap, hcattr,
 			max_flow_counter_15_0);
 	attr->max_flow_counter_31_16 = MLX5_GET(cmd_hca_cap, hcattr,