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Capabilities structure is a member of mlx5dr_context. Signed-off-by: Gregory Etelson Acked-by: Ori Kam --- drivers/net/mlx5/hws/mlx5dr_definer.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c index 0e1035c6bd..5d6ff516b3 100644 --- a/drivers/net/mlx5/hws/mlx5dr_definer.c +++ b/drivers/net/mlx5/hws/mlx5dr_definer.c @@ -1185,7 +1185,7 @@ mlx5dr_definer_conv_item_gtp(struct mlx5dr_definer_conv_data *cd, return rte_errno; } - if (m->hdr.teid) { + if (m->teid) { if (!(caps->flex_protocols & MLX5_HCA_FLEX_GTPU_TEID_ENABLED)) { rte_errno = ENOTSUP; return rte_errno; @@ -1211,7 +1211,7 @@ mlx5dr_definer_conv_item_gtp(struct mlx5dr_definer_conv_data *cd, } - if (m->hdr.msg_type) { + if (m->msg_type) { if (!(caps->flex_protocols & MLX5_HCA_FLEX_GTPU_DW_0_ENABLED)) { rte_errno = ENOTSUP; return rte_errno; From patchwork Sun Oct 29 18:22:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory Etelson X-Patchwork-Id: 133606 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A54EA43239; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Oct 2023 18:23:35.7501 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5b75ec75-4066-417c-39e6-08dbd8ac2a52 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044F3.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6495 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The new function call `flow_hw_get_reg_id_from_ctx()` maps input DR5 context and register type to REG_C register. Signed-off-by: Gregory Etelson Acked-by: Ori Kam --- drivers/net/mlx5/mlx5_flow.h | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h index 1fec295476..de31ab56bc 100644 --- a/drivers/net/mlx5/mlx5_flow.h +++ b/drivers/net/mlx5/mlx5_flow.h @@ -1714,6 +1714,28 @@ flow_hw_get_reg_id(enum rte_flow_item_type type, uint32_t id) } } +static __rte_always_inline int +flow_hw_get_reg_id_from_ctx(void *dr_ctx, + enum rte_flow_item_type type, uint32_t id) +{ +#ifdef HAVE_IBV_FLOW_DV_SUPPORT + uint16_t port; + + MLX5_ETH_FOREACH_DEV(port, NULL) { + struct mlx5_priv *priv; + + priv = rte_eth_devices[port].data->dev_private; + if (priv->dr_ctx == dr_ctx) + return flow_hw_get_reg_id(type, id); + } +#else + RTE_SET_USED(dr_ctx); + RTE_SET_USED(type); + RTE_SET_USED(id); +#endif + return REG_NON; +} + void flow_hw_set_port_info(struct rte_eth_dev *dev); void flow_hw_clear_port_info(struct rte_eth_dev *dev); From patchwork Sun Oct 29 18:22:50 2023 Content-Type: text/plain; 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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by CO1PEPF000044EE.mail.protection.outlook.com (10.167.241.68) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6933.15 via Frontend Transport; Sun, 29 Oct 2023 18:23:39 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Sun, 29 Oct 2023 11:23:26 -0700 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Sun, 29 Oct 2023 11:23:23 -0700 From: Gregory Etelson To: CC: , , , "Ori Kam" , Matan Azrad , Viacheslav Ovsiienko , Suanming Mou Subject: [PATCH 03/13] net/mlx5/hws: Definer, use flow_hw_get_reg_id_from_ctx function call Date: Sun, 29 Oct 2023 20:22:50 +0200 Message-ID: <20231029182300.227879-4-getelson@nvidia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231029182300.227879-1-getelson@nvidia.com> References: <20231029182300.227879-1-getelson@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044EE:EE_|CYXPR12MB9318:EE_ X-MS-Office365-Filtering-Correlation-Id: 88322019-0e00-43b9-a317-08dbd8ac2cc5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Signed-off-by: Gregory Etelson Acked-by: Ori Kam --- drivers/net/mlx5/hws/mlx5dr_definer.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c index 5d6ff516b3..7e1a92d78a 100644 --- a/drivers/net/mlx5/hws/mlx5dr_definer.c +++ b/drivers/net/mlx5/hws/mlx5dr_definer.c @@ -1541,7 +1541,9 @@ mlx5dr_definer_conv_item_tag(struct mlx5dr_definer_conv_data *cd, return 0; if (item->type == RTE_FLOW_ITEM_TYPE_TAG) - reg = flow_hw_get_reg_id(RTE_FLOW_ITEM_TYPE_TAG, v->index); + reg = flow_hw_get_reg_id_from_ctx(cd->ctx, + RTE_FLOW_ITEM_TYPE_TAG, + v->index); else reg = (int)v->index; @@ -1601,7 +1603,9 @@ mlx5dr_definer_conv_item_quota(struct mlx5dr_definer_conv_data *cd, __rte_unused struct rte_flow_item *item, int item_idx) { - int mtr_reg = flow_hw_get_reg_id(RTE_FLOW_ITEM_TYPE_METER_COLOR, 0); + int mtr_reg = + flow_hw_get_reg_id_from_ctx(cd->ctx, RTE_FLOW_ITEM_TYPE_METER_COLOR, + 0); struct mlx5dr_definer_fc *fc; if (mtr_reg < 0) { @@ -1631,7 +1635,7 @@ mlx5dr_definer_conv_item_metadata(struct mlx5dr_definer_conv_data *cd, if (!m) return 0; - reg = flow_hw_get_reg_id(RTE_FLOW_ITEM_TYPE_META, -1); + reg = flow_hw_get_reg_id_from_ctx(cd->ctx, RTE_FLOW_ITEM_TYPE_META, -1); if (reg <= 0) { DR_LOG(ERR, "Invalid register for item metadata"); rte_errno = EINVAL; @@ -1939,7 +1943,8 @@ mlx5dr_definer_conv_item_conntrack(struct mlx5dr_definer_conv_data *cd, if (!m) return 0; - reg = flow_hw_get_reg_id(RTE_FLOW_ITEM_TYPE_CONNTRACK, -1); + reg = flow_hw_get_reg_id_from_ctx(cd->ctx, RTE_FLOW_ITEM_TYPE_CONNTRACK, + -1); if (reg <= 0) { DR_LOG(ERR, "Invalid register for item conntrack"); rte_errno = EINVAL; @@ -2080,7 +2085,8 @@ mlx5dr_definer_conv_item_meter_color(struct mlx5dr_definer_conv_data *cd, if (!m) return 0; - reg = flow_hw_get_reg_id(RTE_FLOW_ITEM_TYPE_METER_COLOR, 0); + reg = flow_hw_get_reg_id_from_ctx(cd->ctx, + RTE_FLOW_ITEM_TYPE_METER_COLOR, 0); MLX5_ASSERT(reg > 0); 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Oct 2023 18:23:41.8619 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 85fba127-7b59-48b1-d06d-08dbd8ac2df6 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044EE.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB6755 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org 1. Add rte_eth_dev parameter to the `flow_hw_get_reg_id()` 2. Add mlx5_flow_hw_get_reg_id() Signed-off-by: Gregory Etelson Acked-by: Ori Kam --- drivers/net/mlx5/mlx5_flow.c | 2 +- drivers/net/mlx5/mlx5_flow.h | 13 +++++++++++-- drivers/net/mlx5/mlx5_flow_dv.c | 12 ++++++------ drivers/net/mlx5/mlx5_flow_hw.c | 7 +++---- 4 files changed, 21 insertions(+), 13 deletions(-) diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c index a500afd4f7..45a67607ed 100644 --- a/drivers/net/mlx5/mlx5_flow.c +++ b/drivers/net/mlx5/mlx5_flow.c @@ -1718,7 +1718,7 @@ flow_drv_rxq_flags_set(struct rte_eth_dev *dev, } } -static void +void flow_rxq_mark_flag_set(struct rte_eth_dev *dev) { struct mlx5_priv *priv = dev->data->dev_private; diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h index de31ab56bc..dc4ced711d 100644 --- a/drivers/net/mlx5/mlx5_flow.h +++ b/drivers/net/mlx5/mlx5_flow.h @@ -1681,8 +1681,10 @@ void flow_hw_clear_flow_metadata_config(void); * TODO: Per port / device, FDB or NIC for Meta matching. */ static __rte_always_inline int -flow_hw_get_reg_id(enum rte_flow_item_type type, uint32_t id) +flow_hw_get_reg_id(struct rte_eth_dev *dev, + enum rte_flow_item_type type, uint32_t id) { + RTE_SET_USED(dev); switch (type) { case RTE_FLOW_ITEM_TYPE_META: #ifdef HAVE_MLX5_HWS_SUPPORT @@ -1726,7 +1728,8 @@ flow_hw_get_reg_id_from_ctx(void *dr_ctx, priv = rte_eth_devices[port].data->dev_private; if (priv->dr_ctx == dr_ctx) - return flow_hw_get_reg_id(type, id); + return flow_hw_get_reg_id(&rte_eth_devices[port], + type, id); } #else RTE_SET_USED(dr_ctx); @@ -2877,6 +2880,12 @@ flow_hw_get_srh_flex_parser_byte_off_from_ctx(void *dr_ctx __rte_unused) } void mlx5_indirect_list_handles_release(struct rte_eth_dev *dev); +void +flow_rxq_mark_flag_set(struct rte_eth_dev *dev); +int +mlx5_flow_hw_get_reg_id(struct mlx5dr_context *ctx, + enum rte_flow_item_type type, uint32_t id); + #ifdef HAVE_MLX5_HWS_SUPPORT struct mlx5_mirror; void diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index 3dc2fe5c71..05a374493d 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -1919,8 +1919,8 @@ mlx5_flow_field_id_to_modify_info off_be = (tag_index == MLX5_LINEAR_HASH_TAG_INDEX) ? 16 - (data->offset + width) + 16 : data->offset; if (priv->sh->config.dv_flow_en == 2) - reg = flow_hw_get_reg_id(RTE_FLOW_ITEM_TYPE_TAG, - tag_index); + reg = flow_hw_get_reg_id(dev, RTE_FLOW_ITEM_TYPE_TAG, + data->level); else reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_index, error); @@ -2025,7 +2025,7 @@ mlx5_flow_field_id_to_modify_info if (priv->sh->config.dv_flow_en == 2) reg = flow_hw_get_reg_id - (RTE_FLOW_ITEM_TYPE_METER_COLOR, 0); + (dev, RTE_FLOW_ITEM_TYPE_METER_COLOR, 0); else reg = mlx5_flow_get_reg_id(dev, MLX5_MTR_COLOR, 0, error); @@ -10256,7 +10256,7 @@ flow_dv_translate_item_meta(struct rte_eth_dev *dev, if (!!(key_type & MLX5_SET_MATCHER_SW)) reg = flow_dv_get_metadata_reg(dev, attr, NULL); else - reg = flow_hw_get_reg_id(RTE_FLOW_ITEM_TYPE_META, 0); + reg = flow_hw_get_reg_id(dev, RTE_FLOW_ITEM_TYPE_META, 0); if (reg < 0) return; MLX5_ASSERT(reg != REG_NON); @@ -10359,7 +10359,7 @@ flow_dv_translate_item_tag(struct rte_eth_dev *dev, void *key, if (!!(key_type & MLX5_SET_MATCHER_SW)) reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, index, NULL); else - reg = flow_hw_get_reg_id(RTE_FLOW_ITEM_TYPE_TAG, index); + reg = flow_hw_get_reg_id(dev, RTE_FLOW_ITEM_TYPE_TAG, index); MLX5_ASSERT(reg > 0); flow_dv_match_meta_reg(key, (enum modify_reg)reg, tag_v->data, tag_m->data); } @@ -11057,7 +11057,7 @@ flow_dv_translate_item_meter_color(struct rte_eth_dev *dev, void *key, if (!!(key_type & MLX5_SET_MATCHER_SW)) reg = mlx5_flow_get_reg_id(dev, MLX5_MTR_COLOR, 0, NULL); else - reg = flow_hw_get_reg_id(RTE_FLOW_ITEM_TYPE_METER_COLOR, 0); + reg = flow_hw_get_reg_id(dev, RTE_FLOW_ITEM_TYPE_METER_COLOR, 0); if (reg == REG_NON) return; flow_dv_match_meta_reg(key, (enum modify_reg)reg, value, mask); diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index 1777cda9f7..ef55c41f83 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -5595,9 +5595,8 @@ flow_hw_pattern_validate(struct rte_eth_dev *dev, if (tag == NULL) return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, - NULL, - "Tag spec is NULL"); - tag_idx = flow_hw_get_reg_id(RTE_FLOW_ITEM_TYPE_TAG, tag->index); + NULL, "Tag spec is NULL"); + tag_idx = flow_hw_get_reg_id(dev, RTE_FLOW_ITEM_TYPE_TAG, tag->index); if (tag_idx == REG_NON) return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, @@ -5655,7 +5654,7 @@ flow_hw_pattern_validate(struct rte_eth_dev *dev, break; case RTE_FLOW_ITEM_TYPE_METER_COLOR: { - int reg = flow_hw_get_reg_id(RTE_FLOW_ITEM_TYPE_METER_COLOR, 0); + int reg = flow_hw_get_reg_id(dev, RTE_FLOW_ITEM_TYPE_METER_COLOR, 0); if (reg == REG_NON) return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, From patchwork Sun Oct 29 18:22:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory Etelson X-Patchwork-Id: 133610 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id BF97843239; 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As the result, PMD could not work properly with different port types that allocate REG_C registers differently. The patch stores registers available to a port in the port shared context. Register values will be assigned according to the port capabilities. Signed-off-by: Gregory Etelson Acked-by: Ori Kam --- drivers/common/mlx5/mlx5_prm.h | 12 +++ drivers/net/mlx5/linux/mlx5_os.c | 16 ++-- drivers/net/mlx5/mlx5.c | 4 - drivers/net/mlx5/mlx5.h | 11 ++- drivers/net/mlx5/mlx5_flow.c | 29 ++----- drivers/net/mlx5/mlx5_flow.h | 25 ++---- drivers/net/mlx5/mlx5_flow_dv.c | 13 +-- drivers/net/mlx5/mlx5_flow_hw.c | 129 ++++------------------------- drivers/net/mlx5/mlx5_flow_meter.c | 14 ++-- 9 files changed, 78 insertions(+), 175 deletions(-) diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index bced5a59dd..e13ca3cd22 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -864,6 +864,18 @@ enum modify_reg { REG_C_11, }; +static __rte_always_inline uint8_t +mlx5_regc_index(enum modify_reg regc_val) +{ + return (uint8_t)(regc_val - REG_C_0); +} + +static __rte_always_inline enum modify_reg +mlx5_regc_value(uint8_t regc_ix) +{ + return REG_C_0 + regc_ix; +} + /* Modification sub command. */ struct mlx5_modification_cmd { union { diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c index d5ef695e6d..96d32d11d8 100644 --- a/drivers/net/mlx5/linux/mlx5_os.c +++ b/drivers/net/mlx5/linux/mlx5_os.c @@ -1328,14 +1328,14 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, * Prefer REG_C_3 if it is available. */ if (reg_c_mask & (1 << (REG_C_3 - REG_C_0))) - priv->mtr_color_reg = REG_C_3; + sh->registers.mtr_color_reg = REG_C_3; else - priv->mtr_color_reg = ffs(reg_c_mask) - - 1 + REG_C_0; + sh->registers.mtr_color_reg = + ffs(reg_c_mask) - 1 + REG_C_0; priv->mtr_en = 1; priv->mtr_reg_share = hca_attr->qos.flow_meter; DRV_LOG(DEBUG, "The REG_C meter uses is %d", - priv->mtr_color_reg); + sh->registers.mtr_color_reg); } } if (hca_attr->qos.sup && hca_attr->qos.flow_meter_aso_sup) { @@ -1360,7 +1360,7 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, sh->tunnel_header_2_3 = 1; #endif #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO - if (hca_attr->flow_hit_aso && priv->mtr_color_reg == REG_C_3) { + if (hca_attr->flow_hit_aso && sh->registers.mtr_color_reg == REG_C_3) { sh->flow_hit_aso_en = 1; err = mlx5_flow_aso_age_mng_init(sh); if (err) { @@ -1374,7 +1374,7 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, defined (HAVE_MLX5_DR_ACTION_ASO_CT) /* HWS create CT ASO SQ based on HWS configure queue number. */ if (sh->config.dv_flow_en != 2 && - hca_attr->ct_offload && priv->mtr_color_reg == REG_C_3) { + hca_attr->ct_offload && sh->registers.mtr_color_reg == REG_C_3) { err = mlx5_flow_aso_ct_mng_init(sh); if (err) { err = -err; @@ -1618,8 +1618,8 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, goto error; } /* Only HWS requires this information. */ - flow_hw_init_tags_set(eth_dev); - flow_hw_init_flow_metadata_config(eth_dev); + if (sh->refcnt == 1) + flow_hw_init_tags_set(eth_dev); if (priv->sh->config.dv_esw_en && flow_hw_create_vport_action(eth_dev)) { DRV_LOG(ERR, "port %u failed to create vport action", diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c index 08b7b03365..c13ce2c13c 100644 --- a/drivers/net/mlx5/mlx5.c +++ b/drivers/net/mlx5/mlx5.c @@ -2173,10 +2173,6 @@ mlx5_dev_close(struct rte_eth_dev *dev) flow_hw_destroy_vport_action(dev); flow_hw_resource_release(dev); flow_hw_clear_port_info(dev); - if (priv->sh->config.dv_flow_en == 2) { - flow_hw_clear_flow_metadata_config(); - flow_hw_clear_tags_set(dev); - } #endif if (priv->rxq_privs != NULL) { /* XXX race condition if mlx5_rx_burst() is still running. */ diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index f3b872f59c..01cb21fc93 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -1373,6 +1373,14 @@ struct mlx5_hws_cnt_svc_mng { struct mlx5_hws_aso_mng aso_mng __rte_cache_aligned; }; +#define MLX5_FLOW_HW_TAGS_MAX 8 + +struct mlx5_dev_registers { + enum modify_reg mlx5_flow_hw_aso_tag; + enum modify_reg mtr_color_reg; /* Meter color match REG_C. */ + enum modify_reg hw_avl_tags[MLX5_FLOW_HW_TAGS_MAX]; +}; + /* * Shared Infiniband device context for Master/Representors * which belong to same IB device with multiple IB ports. @@ -1393,7 +1401,6 @@ struct mlx5_dev_ctx_shared { uint32_t drop_action_check_flag:1; /* Check Flag for drop action. */ uint32_t flow_priority_check_flag:1; /* Check Flag for flow priority. */ uint32_t metadata_regc_check_flag:1; /* Check Flag for metadata REGC. */ - uint32_t hws_tags:1; /* Check if tags info for HWS initialized. */ uint32_t shared_mark_enabled:1; /* If mark action is enabled on Rxqs (shared E-Switch domain). */ uint32_t lag_rx_port_affinity_en:1; @@ -1482,6 +1489,7 @@ struct mlx5_dev_ctx_shared { uint32_t host_shaper_rate:8; uint32_t lwm_triggered:1; struct mlx5_hws_cnt_svc_mng *cnt_svc; + struct mlx5_dev_registers registers; struct mlx5_dev_shared_port port[]; /* per device port data array. */ }; @@ -1811,7 +1819,6 @@ struct mlx5_priv { /* Hash table of Rx metadata register copy table. */ struct mlx5_mtr_config mtr_config; /* Meter configuration */ uint8_t mtr_sfx_reg; /* Meter prefix-suffix flow match REG_C. */ - uint8_t mtr_color_reg; /* Meter color match REG_C. */ struct mlx5_legacy_flow_meters flow_meters; /* MTR list. */ struct mlx5_l3t_tbl *mtr_profile_tbl; /* Meter index lookup table. */ struct mlx5_flow_meter_profile *mtr_profile_arr; /* Profile array. */ diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c index 45a67607ed..3ddc3ba772 100644 --- a/drivers/net/mlx5/mlx5_flow.c +++ b/drivers/net/mlx5/mlx5_flow.c @@ -39,18 +39,6 @@ */ struct flow_hw_port_info mlx5_flow_hw_port_infos[RTE_MAX_ETHPORTS]; -/* - * A global structure to save the available REG_C_x for tags usage. - * The Meter color REG (ASO) and the last available one will be reserved - * for PMD internal usage. - * Since there is no "port" concept in the driver, it is assumed that the - * available tags set will be the minimum intersection. - * 3 - in FDB mode / 5 - in legacy mode - */ -uint32_t mlx5_flow_hw_avl_tags_init_cnt; -enum modify_reg mlx5_flow_hw_avl_tags[MLX5_FLOW_HW_TAGS_MAX] = {REG_NON}; -enum modify_reg mlx5_flow_hw_aso_tag; - struct tunnel_default_miss_ctx { uint16_t *queue; __extension__ @@ -1320,6 +1308,7 @@ mlx5_flow_get_reg_id(struct rte_eth_dev *dev, { struct mlx5_priv *priv = dev->data->dev_private; struct mlx5_sh_config *config = &priv->sh->config; + struct mlx5_dev_registers *reg = &priv->sh->registers; enum modify_reg start_reg; bool skip_mtr_reg = false; @@ -1375,23 +1364,23 @@ mlx5_flow_get_reg_id(struct rte_eth_dev *dev, * should use the meter color register for match. */ if (priv->mtr_reg_share) - return priv->mtr_color_reg; + return reg->mtr_color_reg; else - return priv->mtr_color_reg != REG_C_2 ? REG_C_2 : + return reg->mtr_color_reg != REG_C_2 ? REG_C_2 : REG_C_3; case MLX5_MTR_COLOR: case MLX5_ASO_FLOW_HIT: case MLX5_ASO_CONNTRACK: case MLX5_SAMPLE_ID: /* All features use the same REG_C. */ - MLX5_ASSERT(priv->mtr_color_reg != REG_NON); - return priv->mtr_color_reg; + MLX5_ASSERT(reg->mtr_color_reg != REG_NON); + return reg->mtr_color_reg; case MLX5_COPY_MARK: /* * Metadata COPY_MARK register using is in meter suffix sub * flow while with meter. It's safe to share the same register. */ - return priv->mtr_color_reg != REG_C_2 ? REG_C_2 : REG_C_3; + return reg->mtr_color_reg != REG_C_2 ? REG_C_2 : REG_C_3; case MLX5_APP_TAG: /* * If meter is enable, it will engage the register for color @@ -1400,7 +1389,7 @@ mlx5_flow_get_reg_id(struct rte_eth_dev *dev, * match. * If meter is disable, free to use all available registers. */ - start_reg = priv->mtr_color_reg != REG_C_2 ? REG_C_2 : + start_reg = reg->mtr_color_reg != REG_C_2 ? REG_C_2 : (priv->mtr_reg_share ? REG_C_3 : REG_C_4); skip_mtr_reg = !!(priv->mtr_en && start_reg == REG_C_2); if (id > (uint32_t)(REG_C_7 - start_reg)) @@ -1418,7 +1407,7 @@ mlx5_flow_get_reg_id(struct rte_eth_dev *dev, * color register. */ if (skip_mtr_reg && priv->sh->flow_mreg_c - [id + start_reg - REG_C_0] >= priv->mtr_color_reg) { + [id + start_reg - REG_C_0] >= reg->mtr_color_reg) { if (id >= (uint32_t)(REG_C_7 - start_reg)) return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM, @@ -6491,7 +6480,7 @@ flow_sample_split_prep(struct rte_eth_dev *dev, * metadata regC is REG_NON, back to use application tag * index 0. */ - if (unlikely(priv->mtr_color_reg == REG_NON)) + if (unlikely(priv->sh->registers.mtr_color_reg == REG_NON)) ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, 0, error); else ret = mlx5_flow_get_reg_id(dev, MLX5_SAMPLE_ID, 0, error); diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h index dc4ced711d..ed8804dd0f 100644 --- a/drivers/net/mlx5/mlx5_flow.h +++ b/drivers/net/mlx5/mlx5_flow.h @@ -1621,11 +1621,6 @@ struct flow_hw_port_info { extern struct flow_hw_port_info mlx5_flow_hw_port_infos[RTE_MAX_ETHPORTS]; -#define MLX5_FLOW_HW_TAGS_MAX 8 -extern uint32_t mlx5_flow_hw_avl_tags_init_cnt; -extern enum modify_reg mlx5_flow_hw_avl_tags[]; -extern enum modify_reg mlx5_flow_hw_aso_tag; - /* * Get metadata match tag and mask for given rte_eth_dev port. * Used in HWS rule creation. @@ -1667,13 +1662,6 @@ flow_hw_get_wire_port(struct ibv_context *ibctx) } #endif -extern uint32_t mlx5_flow_hw_flow_metadata_config_refcnt; -extern uint8_t mlx5_flow_hw_flow_metadata_esw_en; -extern uint8_t mlx5_flow_hw_flow_metadata_xmeta_en; - -void flow_hw_init_flow_metadata_config(struct rte_eth_dev *dev); -void flow_hw_clear_flow_metadata_config(void); - /* * Convert metadata or tag to the actual register. * META: Can only be used to match in the FDB in this stage, fixed C_1. @@ -1684,12 +1672,14 @@ static __rte_always_inline int flow_hw_get_reg_id(struct rte_eth_dev *dev, enum rte_flow_item_type type, uint32_t id) { - RTE_SET_USED(dev); + struct mlx5_dev_ctx_shared *sh = MLX5_SH(dev); + struct mlx5_dev_registers *reg = &sh->registers; + switch (type) { case RTE_FLOW_ITEM_TYPE_META: #ifdef HAVE_MLX5_HWS_SUPPORT - if (mlx5_flow_hw_flow_metadata_esw_en && - mlx5_flow_hw_flow_metadata_xmeta_en == MLX5_XMETA_MODE_META32_HWS) { + if (sh->config.dv_esw_en && + sh->config.dv_xmeta_en == MLX5_XMETA_MODE_META32_HWS) { return REG_C_1; } #endif @@ -1705,12 +1695,12 @@ flow_hw_get_reg_id(struct rte_eth_dev *dev, return REG_A; case RTE_FLOW_ITEM_TYPE_CONNTRACK: case RTE_FLOW_ITEM_TYPE_METER_COLOR: - return mlx5_flow_hw_aso_tag; + return reg->mlx5_flow_hw_aso_tag; case RTE_FLOW_ITEM_TYPE_TAG: if (id == MLX5_LINEAR_HASH_TAG_INDEX) return REG_C_3; MLX5_ASSERT(id < MLX5_FLOW_HW_TAGS_MAX); - return mlx5_flow_hw_avl_tags[id]; + return reg->hw_avl_tags[id]; default: return REG_NON; } @@ -1743,7 +1733,6 @@ void flow_hw_set_port_info(struct rte_eth_dev *dev); void flow_hw_clear_port_info(struct rte_eth_dev *dev); void flow_hw_init_tags_set(struct rte_eth_dev *dev); -void flow_hw_clear_tags_set(struct rte_eth_dev *dev); int flow_hw_create_vport_action(struct rte_eth_dev *dev); void flow_hw_destroy_vport_action(struct rte_eth_dev *dev); diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index 05a374493d..024023abb5 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -1919,7 +1919,8 @@ mlx5_flow_field_id_to_modify_info off_be = (tag_index == MLX5_LINEAR_HASH_TAG_INDEX) ? 16 - (data->offset + width) + 16 : data->offset; if (priv->sh->config.dv_flow_en == 2) - reg = flow_hw_get_reg_id(dev, RTE_FLOW_ITEM_TYPE_TAG, + reg = flow_hw_get_reg_id(dev, + RTE_FLOW_ITEM_TYPE_TAG, data->level); else reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, @@ -2025,7 +2026,7 @@ mlx5_flow_field_id_to_modify_info if (priv->sh->config.dv_flow_en == 2) reg = flow_hw_get_reg_id - (dev, RTE_FLOW_ITEM_TYPE_METER_COLOR, 0); + (dev, RTE_FLOW_ITEM_TYPE_METER_COLOR, 0); else reg = mlx5_flow_get_reg_id(dev, MLX5_MTR_COLOR, 0, error); @@ -3922,7 +3923,7 @@ flow_dv_validate_item_meter_color(struct rte_eth_dev *dev, }; int ret; - if (priv->mtr_color_reg == REG_NON) + if (priv->sh->registers.mtr_color_reg == REG_NON) return rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, "meter color register" @@ -8373,7 +8374,8 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr, if (ret < 0) return ret; if ((action_flags & MLX5_FLOW_ACTION_SET_TAG) && - tag_id == 0 && priv->mtr_color_reg == REG_NON) + tag_id == 0 && + priv->sh->registers.mtr_color_reg == REG_NON) return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, NULL, "sample after tag action causes metadata tag index 0 corruption"); @@ -11057,7 +11059,8 @@ flow_dv_translate_item_meter_color(struct rte_eth_dev *dev, void *key, if (!!(key_type & MLX5_SET_MATCHER_SW)) reg = mlx5_flow_get_reg_id(dev, MLX5_MTR_COLOR, 0, NULL); else - reg = flow_hw_get_reg_id(dev, RTE_FLOW_ITEM_TYPE_METER_COLOR, 0); + reg = flow_hw_get_reg_id(dev, + RTE_FLOW_ITEM_TYPE_METER_COLOR, 0); if (reg == REG_NON) return; flow_dv_match_meta_reg(key, (enum modify_reg)reg, value, mask); diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index ef55c41f83..86e2891241 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -5654,7 +5654,9 @@ flow_hw_pattern_validate(struct rte_eth_dev *dev, break; case RTE_FLOW_ITEM_TYPE_METER_COLOR: { - int reg = flow_hw_get_reg_id(dev, RTE_FLOW_ITEM_TYPE_METER_COLOR, 0); + int reg = flow_hw_get_reg_id(dev, + RTE_FLOW_ITEM_TYPE_METER_COLOR, + 0); if (reg == REG_NON) return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, @@ -8457,126 +8459,29 @@ flow_hw_clear_port_info(struct rte_eth_dev *dev) */ void flow_hw_init_tags_set(struct rte_eth_dev *dev) { - struct mlx5_priv *priv = dev->data->dev_private; - uint32_t meta_mode = priv->sh->config.dv_xmeta_en; - uint8_t masks = (uint8_t)priv->sh->cdev->config.hca_attr.set_reg_c; - uint32_t i, j; - uint8_t reg_off; + struct mlx5_dev_ctx_shared *sh = MLX5_SH(dev); + struct mlx5_dev_registers *reg = &sh->registers; + uint32_t meta_mode = sh->config.dv_xmeta_en; + uint8_t masks = (uint8_t)sh->cdev->config.hca_attr.set_reg_c; uint8_t unset = 0; - uint8_t common_masks = 0; + uint32_t i, j; /* * The CAPA is global for common device but only used in net. * It is shared per eswitch domain. */ - if (!!priv->sh->hws_tags) - return; - unset |= 1 << (priv->mtr_color_reg - REG_C_0); - unset |= 1 << (REG_C_6 - REG_C_0); - if (priv->sh->config.dv_esw_en) - unset |= 1 << (REG_C_0 - REG_C_0); + unset |= 1 << mlx5_regc_index(reg->mtr_color_reg); + unset |= 1 << mlx5_regc_index(REG_C_6); + if (sh->config.dv_esw_en) + unset |= 1 << mlx5_regc_index(REG_C_0); if (meta_mode == MLX5_XMETA_MODE_META32_HWS) - unset |= 1 << (REG_C_1 - REG_C_0); + unset |= 1 << mlx5_regc_index(REG_C_1); masks &= ~unset; - /* - * If available tag registers were previously calculated, - * calculate a bitmask with an intersection of sets of: - * - registers supported by current port, - * - previously calculated available tag registers. - */ - if (mlx5_flow_hw_avl_tags_init_cnt) { - MLX5_ASSERT(mlx5_flow_hw_aso_tag == priv->mtr_color_reg); - for (i = 0; i < MLX5_FLOW_HW_TAGS_MAX; i++) { - if (mlx5_flow_hw_avl_tags[i] == REG_NON) - continue; - reg_off = mlx5_flow_hw_avl_tags[i] - REG_C_0; - if ((1 << reg_off) & masks) - common_masks |= (1 << reg_off); - } - if (common_masks != masks) - masks = common_masks; - else - goto after_avl_tags; + for (i = 0, j = 0; i < MLX5_FLOW_HW_TAGS_MAX; i++) { + if (!!((1 << i) & masks)) + reg->hw_avl_tags[j++] = mlx5_regc_value(i); } - j = 0; - for (i = 0; i < MLX5_FLOW_HW_TAGS_MAX; i++) { - if ((1 << i) & masks) - mlx5_flow_hw_avl_tags[j++] = (enum modify_reg)(i + (uint32_t)REG_C_0); - } - /* Clear the rest of unusable tag indexes. */ - for (; j < MLX5_FLOW_HW_TAGS_MAX; j++) - mlx5_flow_hw_avl_tags[j] = REG_NON; -after_avl_tags: - priv->sh->hws_tags = 1; - mlx5_flow_hw_aso_tag = (enum modify_reg)priv->mtr_color_reg; - mlx5_flow_hw_avl_tags_init_cnt++; -} - -/* - * Reset the available tag registers information to NONE. - * - * @param[in] dev - * Pointer to the rte_eth_dev structure. - */ -void flow_hw_clear_tags_set(struct rte_eth_dev *dev) -{ - struct mlx5_priv *priv = dev->data->dev_private; - - if (!priv->sh->hws_tags) - return; - priv->sh->hws_tags = 0; - mlx5_flow_hw_avl_tags_init_cnt--; - if (!mlx5_flow_hw_avl_tags_init_cnt) - memset(mlx5_flow_hw_avl_tags, REG_NON, - sizeof(enum modify_reg) * MLX5_FLOW_HW_TAGS_MAX); -} - -uint32_t mlx5_flow_hw_flow_metadata_config_refcnt; -uint8_t mlx5_flow_hw_flow_metadata_esw_en; -uint8_t mlx5_flow_hw_flow_metadata_xmeta_en; - -/** - * Initializes static configuration of META flow items. - * - * As a temporary workaround, META flow item is translated to a register, - * based on statically saved dv_esw_en and dv_xmeta_en device arguments. - * It is a workaround for flow_hw_get_reg_id() where port specific information - * is not available at runtime. - * - * Values of dv_esw_en and dv_xmeta_en device arguments are taken from the first opened port. - * This means that each mlx5 port will use the same configuration for translation - * of META flow items. - * - * @param[in] dev - * Pointer to Ethernet device. - */ -void -flow_hw_init_flow_metadata_config(struct rte_eth_dev *dev) -{ - uint32_t refcnt; - - refcnt = __atomic_fetch_add(&mlx5_flow_hw_flow_metadata_config_refcnt, 1, - __ATOMIC_RELAXED); - if (refcnt > 0) - return; - mlx5_flow_hw_flow_metadata_esw_en = MLX5_SH(dev)->config.dv_esw_en; - mlx5_flow_hw_flow_metadata_xmeta_en = MLX5_SH(dev)->config.dv_xmeta_en; -} - -/** - * Clears statically stored configuration related to META flow items. - */ -void -flow_hw_clear_flow_metadata_config(void) -{ - uint32_t refcnt; - - refcnt = __atomic_fetch_sub(&mlx5_flow_hw_flow_metadata_config_refcnt, 1, - __ATOMIC_RELAXED) - 1; - if (refcnt > 0) - return; - mlx5_flow_hw_flow_metadata_esw_en = 0; - mlx5_flow_hw_flow_metadata_xmeta_en = 0; + reg->mlx5_flow_hw_aso_tag = reg->mtr_color_reg; } static int diff --git a/drivers/net/mlx5/mlx5_flow_meter.c b/drivers/net/mlx5/mlx5_flow_meter.c index 14a435d157..eb88dfe39c 100644 --- a/drivers/net/mlx5/mlx5_flow_meter.c +++ b/drivers/net/mlx5/mlx5_flow_meter.c @@ -67,7 +67,7 @@ mlx5_flow_meter_action_create(struct mlx5_priv *priv, val = (ebs_eir >> ASO_DSEG_EBS_MAN_OFFSET) & ASO_DSEG_MAN_MASK; MLX5_SET(flow_meter_parameters, fmp, ebs_mantissa, val); mtr_init.next_table = def_policy->sub_policy.tbl_rsc->obj; - mtr_init.reg_c_index = priv->mtr_color_reg - REG_C_0; + mtr_init.reg_c_index = priv->sh->registers.mtr_color_reg - REG_C_0; mtr_init.flow_meter_parameter = fmp; mtr_init.flow_meter_parameter_sz = MLX5_ST_SZ_BYTES(flow_meter_parameters); @@ -1597,6 +1597,7 @@ mlx5_flow_meter_action_modify(struct mlx5_priv *priv, uint64_t modify_bits, uint32_t active_state, uint32_t is_enable) { #ifdef HAVE_MLX5_DR_CREATE_ACTION_FLOW_METER + struct mlx5_dev_ctx_shared *sh = priv->sh; uint32_t in[MLX5_ST_SZ_DW(flow_meter_parameters)] = { 0 }; uint32_t *attr; struct mlx5dv_dr_flow_meter_attr mod_attr = { 0 }; @@ -1604,19 +1605,20 @@ mlx5_flow_meter_action_modify(struct mlx5_priv *priv, struct mlx5_aso_mtr *aso_mtr = NULL; uint32_t cbs_cir, ebs_eir, val; - if (priv->sh->meter_aso_en) { + if (sh->meter_aso_en) { fm->is_enable = !!is_enable; aso_mtr = container_of(fm, struct mlx5_aso_mtr, fm); - ret = mlx5_aso_meter_update_by_wqe(priv->sh, MLX5_HW_INV_QUEUE, - aso_mtr, &priv->mtr_bulk, NULL, true); + ret = mlx5_aso_meter_update_by_wqe(sh, MLX5_HW_INV_QUEUE, + aso_mtr, &priv->mtr_bulk, + NULL, true); if (ret) return ret; - ret = mlx5_aso_mtr_wait(priv->sh, MLX5_HW_INV_QUEUE, aso_mtr); + ret = mlx5_aso_mtr_wait(sh, MLX5_HW_INV_QUEUE, aso_mtr); if (ret) return ret; } else { /* Fill command parameters. */ - mod_attr.reg_c_index = priv->mtr_color_reg - REG_C_0; + mod_attr.reg_c_index = sh->registers.mtr_color_reg - REG_C_0; mod_attr.flow_meter_parameter = in; mod_attr.flow_meter_parameter_sz = MLX5_ST_SZ_BYTES(flow_meter_parameters); From patchwork Sun Oct 29 18:22:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory Etelson X-Patchwork-Id: 133609 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1327343239; Sun, 29 Oct 2023 19:24:12 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 5E98440E54; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Oct 2023 18:23:44.7005 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0d93a498-c47f-48fb-57ab-08dbd8ac2faa X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044EF.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7933 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Merge `mtr_color_reg` and `mlx5_flow_hw_aso_tag` into `aso_reg` Signed-off-by: Gregory Etelson Acked-by: Ori Kam --- drivers/net/mlx5/linux/mlx5_os.c | 10 +++++----- drivers/net/mlx5/mlx5.h | 3 +-- drivers/net/mlx5/mlx5_flow.c | 16 ++++++++-------- drivers/net/mlx5/mlx5_flow.h | 3 +-- drivers/net/mlx5/mlx5_flow_dv.c | 7 ++++--- drivers/net/mlx5/mlx5_flow_hw.c | 3 +-- drivers/net/mlx5/mlx5_flow_meter.c | 4 ++-- 7 files changed, 22 insertions(+), 24 deletions(-) diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c index 96d32d11d8..ed273e14cf 100644 --- a/drivers/net/mlx5/linux/mlx5_os.c +++ b/drivers/net/mlx5/linux/mlx5_os.c @@ -1328,14 +1328,14 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, * Prefer REG_C_3 if it is available. */ if (reg_c_mask & (1 << (REG_C_3 - REG_C_0))) - sh->registers.mtr_color_reg = REG_C_3; + sh->registers.aso_reg = REG_C_3; else - sh->registers.mtr_color_reg = + sh->registers.aso_reg = ffs(reg_c_mask) - 1 + REG_C_0; priv->mtr_en = 1; priv->mtr_reg_share = hca_attr->qos.flow_meter; DRV_LOG(DEBUG, "The REG_C meter uses is %d", - sh->registers.mtr_color_reg); + sh->registers.aso_reg); } } if (hca_attr->qos.sup && hca_attr->qos.flow_meter_aso_sup) { @@ -1360,7 +1360,7 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, sh->tunnel_header_2_3 = 1; #endif #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO - if (hca_attr->flow_hit_aso && sh->registers.mtr_color_reg == REG_C_3) { + if (hca_attr->flow_hit_aso && sh->registers.aso_reg == REG_C_3) { sh->flow_hit_aso_en = 1; err = mlx5_flow_aso_age_mng_init(sh); if (err) { @@ -1374,7 +1374,7 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, defined (HAVE_MLX5_DR_ACTION_ASO_CT) /* HWS create CT ASO SQ based on HWS configure queue number. */ if (sh->config.dv_flow_en != 2 && - hca_attr->ct_offload && sh->registers.mtr_color_reg == REG_C_3) { + hca_attr->ct_offload && sh->registers.aso_reg == REG_C_3) { err = mlx5_flow_aso_ct_mng_init(sh); if (err) { err = -err; diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index 01cb21fc93..99a2ad88ed 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -1376,8 +1376,7 @@ struct mlx5_hws_cnt_svc_mng { #define MLX5_FLOW_HW_TAGS_MAX 8 struct mlx5_dev_registers { - enum modify_reg mlx5_flow_hw_aso_tag; - enum modify_reg mtr_color_reg; /* Meter color match REG_C. */ + enum modify_reg aso_reg; enum modify_reg hw_avl_tags[MLX5_FLOW_HW_TAGS_MAX]; }; diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c index 3ddc3ba772..ad9a2f2273 100644 --- a/drivers/net/mlx5/mlx5_flow.c +++ b/drivers/net/mlx5/mlx5_flow.c @@ -1364,23 +1364,23 @@ mlx5_flow_get_reg_id(struct rte_eth_dev *dev, * should use the meter color register for match. */ if (priv->mtr_reg_share) - return reg->mtr_color_reg; + return reg->aso_reg; else - return reg->mtr_color_reg != REG_C_2 ? REG_C_2 : + return reg->aso_reg != REG_C_2 ? REG_C_2 : REG_C_3; case MLX5_MTR_COLOR: case MLX5_ASO_FLOW_HIT: case MLX5_ASO_CONNTRACK: case MLX5_SAMPLE_ID: /* All features use the same REG_C. */ - MLX5_ASSERT(reg->mtr_color_reg != REG_NON); - return reg->mtr_color_reg; + MLX5_ASSERT(reg->aso_reg != REG_NON); + return reg->aso_reg; case MLX5_COPY_MARK: /* * Metadata COPY_MARK register using is in meter suffix sub * flow while with meter. It's safe to share the same register. */ - return reg->mtr_color_reg != REG_C_2 ? REG_C_2 : REG_C_3; + return reg->aso_reg != REG_C_2 ? REG_C_2 : REG_C_3; case MLX5_APP_TAG: /* * If meter is enable, it will engage the register for color @@ -1389,7 +1389,7 @@ mlx5_flow_get_reg_id(struct rte_eth_dev *dev, * match. * If meter is disable, free to use all available registers. */ - start_reg = reg->mtr_color_reg != REG_C_2 ? REG_C_2 : + start_reg = reg->aso_reg != REG_C_2 ? REG_C_2 : (priv->mtr_reg_share ? REG_C_3 : REG_C_4); skip_mtr_reg = !!(priv->mtr_en && start_reg == REG_C_2); if (id > (uint32_t)(REG_C_7 - start_reg)) @@ -1407,7 +1407,7 @@ mlx5_flow_get_reg_id(struct rte_eth_dev *dev, * color register. */ if (skip_mtr_reg && priv->sh->flow_mreg_c - [id + start_reg - REG_C_0] >= reg->mtr_color_reg) { + [id + start_reg - REG_C_0] >= reg->aso_reg) { if (id >= (uint32_t)(REG_C_7 - start_reg)) return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM, @@ -6480,7 +6480,7 @@ flow_sample_split_prep(struct rte_eth_dev *dev, * metadata regC is REG_NON, back to use application tag * index 0. */ - if (unlikely(priv->sh->registers.mtr_color_reg == REG_NON)) + if (unlikely(priv->sh->registers.aso_reg == REG_NON)) ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, 0, error); else ret = mlx5_flow_get_reg_id(dev, MLX5_SAMPLE_ID, 0, error); diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h index ed8804dd0f..643f9f4329 100644 --- a/drivers/net/mlx5/mlx5_flow.h +++ b/drivers/net/mlx5/mlx5_flow.h @@ -1666,7 +1666,6 @@ flow_hw_get_wire_port(struct ibv_context *ibctx) * Convert metadata or tag to the actual register. * META: Can only be used to match in the FDB in this stage, fixed C_1. * TAG: C_x expect meter color reg and the reserved ones. - * TODO: Per port / device, FDB or NIC for Meta matching. */ static __rte_always_inline int flow_hw_get_reg_id(struct rte_eth_dev *dev, @@ -1695,7 +1694,7 @@ flow_hw_get_reg_id(struct rte_eth_dev *dev, return REG_A; case RTE_FLOW_ITEM_TYPE_CONNTRACK: case RTE_FLOW_ITEM_TYPE_METER_COLOR: - return reg->mlx5_flow_hw_aso_tag; + return reg->aso_reg; case RTE_FLOW_ITEM_TYPE_TAG: if (id == MLX5_LINEAR_HASH_TAG_INDEX) return REG_C_3; diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index 024023abb5..9268a07c84 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -2026,7 +2026,8 @@ mlx5_flow_field_id_to_modify_info if (priv->sh->config.dv_flow_en == 2) reg = flow_hw_get_reg_id - (dev, RTE_FLOW_ITEM_TYPE_METER_COLOR, 0); + (dev, + RTE_FLOW_ITEM_TYPE_METER_COLOR, 0); else reg = mlx5_flow_get_reg_id(dev, MLX5_MTR_COLOR, 0, error); @@ -3923,7 +3924,7 @@ flow_dv_validate_item_meter_color(struct rte_eth_dev *dev, }; int ret; - if (priv->sh->registers.mtr_color_reg == REG_NON) + if (priv->sh->registers.aso_reg == REG_NON) return rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, "meter color register" @@ -8375,7 +8376,7 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr, return ret; if ((action_flags & MLX5_FLOW_ACTION_SET_TAG) && tag_id == 0 && - priv->sh->registers.mtr_color_reg == REG_NON) + priv->sh->registers.aso_reg == REG_NON) return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, NULL, "sample after tag action causes metadata tag index 0 corruption"); diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index 86e2891241..1c79a92fb3 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -8470,7 +8470,7 @@ void flow_hw_init_tags_set(struct rte_eth_dev *dev) * The CAPA is global for common device but only used in net. * It is shared per eswitch domain. */ - unset |= 1 << mlx5_regc_index(reg->mtr_color_reg); + unset |= 1 << mlx5_regc_index(reg->aso_reg); unset |= 1 << mlx5_regc_index(REG_C_6); if (sh->config.dv_esw_en) unset |= 1 << mlx5_regc_index(REG_C_0); @@ -8481,7 +8481,6 @@ void flow_hw_init_tags_set(struct rte_eth_dev *dev) if (!!((1 << i) & masks)) reg->hw_avl_tags[j++] = mlx5_regc_value(i); } - reg->mlx5_flow_hw_aso_tag = reg->mtr_color_reg; } static int diff --git a/drivers/net/mlx5/mlx5_flow_meter.c b/drivers/net/mlx5/mlx5_flow_meter.c index eb88dfe39c..7cbf772ea4 100644 --- a/drivers/net/mlx5/mlx5_flow_meter.c +++ b/drivers/net/mlx5/mlx5_flow_meter.c @@ -67,7 +67,7 @@ mlx5_flow_meter_action_create(struct mlx5_priv *priv, val = (ebs_eir >> ASO_DSEG_EBS_MAN_OFFSET) & ASO_DSEG_MAN_MASK; MLX5_SET(flow_meter_parameters, fmp, ebs_mantissa, val); mtr_init.next_table = def_policy->sub_policy.tbl_rsc->obj; - mtr_init.reg_c_index = priv->sh->registers.mtr_color_reg - REG_C_0; + mtr_init.reg_c_index = priv->sh->registers.aso_reg - REG_C_0; mtr_init.flow_meter_parameter = fmp; mtr_init.flow_meter_parameter_sz = MLX5_ST_SZ_BYTES(flow_meter_parameters); @@ -1618,7 +1618,7 @@ mlx5_flow_meter_action_modify(struct mlx5_priv *priv, return ret; } else { /* Fill command parameters. */ - mod_attr.reg_c_index = sh->registers.mtr_color_reg - REG_C_0; + mod_attr.reg_c_index = sh->registers.aso_reg - REG_C_0; mod_attr.flow_meter_parameter = in; mod_attr.flow_meter_parameter_sz = MLX5_ST_SZ_BYTES(flow_meter_parameters); From patchwork Sun Oct 29 18:22:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory Etelson X-Patchwork-Id: 133611 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2B25043239; Sun, 29 Oct 2023 19:24:31 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2C9FB410D3; Sun, 29 Oct 2023 19:23:54 +0100 (CET) Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2069.outbound.protection.outlook.com [40.107.244.69]) by mails.dpdk.org (Postfix) with ESMTP id EC84740E25 for ; Sun, 29 Oct 2023 19:23:51 +0100 (CET) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; 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Signed-off-by: Gregory Etelson Acked-by: Ori Kam --- drivers/net/mlx5/linux/mlx5_os.c | 35 ++------------- drivers/net/mlx5/mlx5.c | 75 ++++++++++++++++++++++++++++++++ drivers/net/mlx5/mlx5.h | 6 +++ drivers/net/mlx5/mlx5_flow.h | 3 -- drivers/net/mlx5/mlx5_flow_hw.c | 34 --------------- 5 files changed, 84 insertions(+), 69 deletions(-) diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c index ed273e14cf..ec067ef52c 100644 --- a/drivers/net/mlx5/linux/mlx5_os.c +++ b/drivers/net/mlx5/linux/mlx5_os.c @@ -1304,38 +1304,12 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, struct mlx5_hca_attr *hca_attr = &sh->cdev->config.hca_attr; sh->steering_format_version = hca_attr->steering_format_version; -#if defined(HAVE_MLX5DV_DR) && \ - (defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_METER) || \ - defined(HAVE_MLX5_DR_CREATE_ACTION_ASO)) +#if defined(HAVE_MLX5_DR_CREATE_ACTION_ASO_EXT) if (hca_attr->qos.sup && hca_attr->qos.flow_meter_old && sh->config.dv_flow_en) { - uint8_t reg_c_mask = hca_attr->qos.flow_meter_reg_c_ids; - /* - * Meter needs two REG_C's for color match and pre-sfx - * flow match. Here get the REG_C for color match. - * REG_C_0 and REG_C_1 is reserved for metadata feature. - */ - reg_c_mask &= 0xfc; - if (rte_popcount32(reg_c_mask) < 1) { - priv->mtr_en = 0; - DRV_LOG(WARNING, "No available register for" - " meter."); - } else { - /* - * The meter color register is used by the - * flow-hit feature as well. - * The flow-hit feature must use REG_C_3 - * Prefer REG_C_3 if it is available. - */ - if (reg_c_mask & (1 << (REG_C_3 - REG_C_0))) - sh->registers.aso_reg = REG_C_3; - else - sh->registers.aso_reg = - ffs(reg_c_mask) - 1 + REG_C_0; + if (sh->registers.aso_reg != REG_NON) { priv->mtr_en = 1; priv->mtr_reg_share = hca_attr->qos.flow_meter; - DRV_LOG(DEBUG, "The REG_C meter uses is %d", - sh->registers.aso_reg); } } if (hca_attr->qos.sup && hca_attr->qos.flow_meter_aso_sup) { @@ -1358,7 +1332,7 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, sh->tunnel_header_0_1 = 1; if (hca_attr->flow.tunnel_header_2_3) sh->tunnel_header_2_3 = 1; -#endif +#endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO_EXT */ #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO if (hca_attr->flow_hit_aso && sh->registers.aso_reg == REG_C_3) { sh->flow_hit_aso_en = 1; @@ -1617,9 +1591,6 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, err = ENOTSUP; goto error; } - /* Only HWS requires this information. */ - if (sh->refcnt == 1) - flow_hw_init_tags_set(eth_dev); if (priv->sh->config.dv_esw_en && flow_hw_create_vport_action(eth_dev)) { DRV_LOG(ERR, "port %u failed to create vport action", diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c index c13ce2c13c..840c566162 100644 --- a/drivers/net/mlx5/mlx5.c +++ b/drivers/net/mlx5/mlx5.c @@ -1599,6 +1599,80 @@ mlx5_rt_timestamp_config(struct mlx5_dev_ctx_shared *sh, } } +static void +mlx5_init_hws_flow_tags_registers(struct mlx5_dev_ctx_shared *sh) +{ + struct mlx5_dev_registers *reg = &sh->registers; + uint32_t meta_mode = sh->config.dv_xmeta_en; + uint8_t masks = (uint8_t)sh->cdev->config.hca_attr.set_reg_c; + uint8_t unset = 0; + uint32_t i, j; + + /* + * The CAPA is global for common device but only used in net. + * It is shared per eswitch domain. + */ + if (reg->aso_reg != REG_NON) + unset |= 1 << mlx5_regc_index(reg->aso_reg); + unset |= 1 << mlx5_regc_index(REG_C_6); + if (sh->config.dv_esw_en) + unset |= 1 << mlx5_regc_index(REG_C_0); + if (meta_mode == MLX5_XMETA_MODE_META32_HWS) + unset |= 1 << mlx5_regc_index(REG_C_1); + masks &= ~unset; + for (i = 0, j = 0; i < MLX5_FLOW_HW_TAGS_MAX; i++) { + if (!!((1 << i) & masks)) + reg->hw_avl_tags[j++] = mlx5_regc_value(i); + } +} + +static void +mlx5_init_aso_register(struct mlx5_dev_ctx_shared *sh) +{ +#if defined(HAVE_MLX5_DR_CREATE_ACTION_ASO_EXT) + const struct mlx5_hca_attr *hca_attr = &sh->cdev->config.hca_attr; + const struct mlx5_hca_qos_attr *qos = &hca_attr->qos; + uint8_t reg_c_mask = qos->flow_meter_reg_c_ids & 0xfc; + + if (!(qos->sup && qos->flow_meter_old && sh->config.dv_flow_en)) + return; + /* + * Meter needs two REG_C's for color match and pre-sfx + * flow match. Here get the REG_C for color match. + * REG_C_0 and REG_C_1 is reserved for metadata feature. + */ + if (__builtin_popcount(reg_c_mask) > 0) { + /* + * The meter color register is used by the + * flow-hit feature as well. + * The flow-hit feature must use REG_C_3 + * Prefer REG_C_3 if it is available. + */ + if (reg_c_mask & (1 << mlx5_regc_index(REG_C_3))) + sh->registers.aso_reg = REG_C_3; + else + sh->registers.aso_reg = + mlx5_regc_value(ffs(reg_c_mask) - 1); + } +#else + RTE_SET_USED(sh); +#endif +} + +static void +mlx5_init_shared_dev_registers(struct mlx5_dev_ctx_shared *sh) +{ + if (sh->cdev->config.devx) + mlx5_init_aso_register(sh); + if (sh->registers.aso_reg != REG_NON) { + DRV_LOG(DEBUG, "ASO register: REG_C%d", + mlx5_regc_index(sh->registers.aso_reg)); + } else { + DRV_LOG(DEBUG, "ASO register: NONE"); + } + mlx5_init_hws_flow_tags_registers(sh); +} + /** * Allocate shared device context. If there is multiport device the * master and representors will share this context, if there is single @@ -1720,6 +1794,7 @@ mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn, /* Add context to the global device list. */ LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next); rte_spinlock_init(&sh->geneve_tlv_opt_sl); + mlx5_init_shared_dev_registers(sh); exit: pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex); return sh; diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index 99a2ad88ed..a0dcd788b4 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -1380,6 +1380,12 @@ struct mlx5_dev_registers { enum modify_reg hw_avl_tags[MLX5_FLOW_HW_TAGS_MAX]; }; +#if defined(HAVE_MLX5DV_DR) && \ + (defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_METER) || \ + defined(HAVE_MLX5_DR_CREATE_ACTION_ASO)) +#define HAVE_MLX5_DR_CREATE_ACTION_ASO_EXT +#endif + /* * Shared Infiniband device context for Master/Representors * which belong to same IB device with multiple IB ports. diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h index 643f9f4329..81ec8fd7f1 100644 --- a/drivers/net/mlx5/mlx5_flow.h +++ b/drivers/net/mlx5/mlx5_flow.h @@ -1730,9 +1730,6 @@ flow_hw_get_reg_id_from_ctx(void *dr_ctx, void flow_hw_set_port_info(struct rte_eth_dev *dev); void flow_hw_clear_port_info(struct rte_eth_dev *dev); - -void flow_hw_init_tags_set(struct rte_eth_dev *dev); - int flow_hw_create_vport_action(struct rte_eth_dev *dev); void flow_hw_destroy_vport_action(struct rte_eth_dev *dev); diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index 1c79a92fb3..cccf7de13f 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -8449,40 +8449,6 @@ flow_hw_clear_port_info(struct rte_eth_dev *dev) info->is_wire = 0; } -/* - * Initialize the information of available tag registers and an intersection - * of all the probed devices' REG_C_Xs. - * PS. No port concept in steering part, right now it cannot be per port level. - * - * @param[in] dev - * Pointer to the rte_eth_dev structure. - */ -void flow_hw_init_tags_set(struct rte_eth_dev *dev) -{ - struct mlx5_dev_ctx_shared *sh = MLX5_SH(dev); - struct mlx5_dev_registers *reg = &sh->registers; - uint32_t meta_mode = sh->config.dv_xmeta_en; - uint8_t masks = (uint8_t)sh->cdev->config.hca_attr.set_reg_c; - uint8_t unset = 0; - uint32_t i, j; - - /* - * The CAPA is global for common device but only used in net. - * It is shared per eswitch domain. - */ - unset |= 1 << mlx5_regc_index(reg->aso_reg); - unset |= 1 << mlx5_regc_index(REG_C_6); - if (sh->config.dv_esw_en) - unset |= 1 << mlx5_regc_index(REG_C_0); - if (meta_mode == MLX5_XMETA_MODE_META32_HWS) - unset |= 1 << mlx5_regc_index(REG_C_1); - masks &= ~unset; - for (i = 0, j = 0; i < MLX5_FLOW_HW_TAGS_MAX; i++) { - if (!!((1 << i) & masks)) - reg->hw_avl_tags[j++] = mlx5_regc_value(i); - } -} - static int flow_hw_conntrack_destroy(struct rte_eth_dev *dev __rte_unused, uint32_t idx, From patchwork Sun Oct 29 18:22:55 2023 Content-Type: text/plain; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Oct 2023 18:23:54.6663 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0d09006a-6e9b-4e8a-d96b-08dbd8ac3593 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002636E.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4175 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Itamar Gozlan Add a method to the HW steering API that allows querying the hash result for a given matcher and a set of items. This can be used to predict the location of the rule in the hash table. Signed-off-by: Itamar Gozlan Acked-by: Ori Kam --- drivers/common/mlx5/mlx5_prm.h | 8 +++- drivers/net/mlx5/hws/meson.build | 1 + drivers/net/mlx5/hws/mlx5dr.h | 26 +++++++++++ drivers/net/mlx5/hws/mlx5dr_cmd.c | 3 ++ drivers/net/mlx5/hws/mlx5dr_cmd.h | 3 +- drivers/net/mlx5/hws/mlx5dr_crc32.c | 61 ++++++++++++++++++++++++++ drivers/net/mlx5/hws/mlx5dr_crc32.h | 13 ++++++ drivers/net/mlx5/hws/mlx5dr_internal.h | 1 + drivers/net/mlx5/hws/mlx5dr_rule.c | 37 ++++++++++++++++ drivers/net/mlx5/hws/mlx5dr_rule.h | 1 + 10 files changed, 152 insertions(+), 2 deletions(-) create mode 100644 drivers/net/mlx5/hws/mlx5dr_crc32.c create mode 100644 drivers/net/mlx5/hws/mlx5dr_crc32.h diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index e13ca3cd22..19c6d0282b 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -2279,6 +2279,9 @@ enum { MLX5_GENERATE_WQE_TYPE_FLOW_UPDATE = 1 << 1, }; +enum { + MLX5_FLOW_TABLE_HASH_TYPE_CRC32, +}; /* * HCA Capabilities 2 */ @@ -2328,7 +2331,10 @@ struct mlx5_ifc_cmd_hca_cap_2_bits { u8 format_select_dw_gtpu_dw_2[0x8]; u8 format_select_dw_gtpu_first_ext_dw_0[0x8]; u8 generate_wqe_type[0x20]; - u8 reserved_at_2c0[0x540]; + u8 reserved_at_2c0[0x160]; + u8 reserved_at_420[0x1c]; + u8 flow_table_hash_type[0x4]; + u8 reserved_at_440[0x3c0]; }; struct mlx5_ifc_esw_cap_bits { diff --git a/drivers/net/mlx5/hws/meson.build b/drivers/net/mlx5/hws/meson.build index 38776d5163..bbcc628557 100644 --- a/drivers/net/mlx5/hws/meson.build +++ b/drivers/net/mlx5/hws/meson.build @@ -19,4 +19,5 @@ sources += files( 'mlx5dr_definer.c', 'mlx5dr_debug.c', 'mlx5dr_pat_arg.c', + 'mlx5dr_crc32.c', ) diff --git a/drivers/net/mlx5/hws/mlx5dr.h b/drivers/net/mlx5/hws/mlx5dr.h index 1995c55132..39d902e762 100644 --- a/drivers/net/mlx5/hws/mlx5dr.h +++ b/drivers/net/mlx5/hws/mlx5dr.h @@ -118,6 +118,11 @@ enum mlx5dr_matcher_distribute_mode { MLX5DR_MATCHER_DISTRIBUTE_BY_LINEAR = 0x1, }; +enum mlx5dr_rule_hash_calc_mode { + MLX5DR_RULE_HASH_CALC_MODE_RAW, + MLX5DR_RULE_HASH_CALC_MODE_IDX, +}; + struct mlx5dr_matcher_attr { /* Processing priority inside table */ uint32_t priority; @@ -430,6 +435,27 @@ int mlx5dr_rule_action_update(struct mlx5dr_rule *rule_handle, struct mlx5dr_rule_action rule_actions[], struct mlx5dr_rule_attr *attr); +/* Calculate hash for a given set of items, which indicates rule location in + * the hash table. + * + * @param[in] matcher + * The matcher of the created rule. + * @param[in] items + * Matching pattern item definition. + * @param[in] mt_idx + * Match template index that the match was created with. + * @param[in] mode + * Hash calculation mode + * @param[in, out] ret_hash + * Returned calculated hash result + * @return zero on success non zero otherwise. + */ +int mlx5dr_rule_hash_calculate(struct mlx5dr_matcher *matcher, + const struct rte_flow_item items[], + uint8_t mt_idx, + enum mlx5dr_rule_hash_calc_mode mode, + uint32_t *ret_hash); + /* Create direct rule drop action. * * @param[in] ctx diff --git a/drivers/net/mlx5/hws/mlx5dr_cmd.c b/drivers/net/mlx5/hws/mlx5dr_cmd.c index 781de40c02..c52cdd0767 100644 --- a/drivers/net/mlx5/hws/mlx5dr_cmd.c +++ b/drivers/net/mlx5/hws/mlx5dr_cmd.c @@ -1154,6 +1154,9 @@ int mlx5dr_cmd_query_caps(struct ibv_context *ctx, (res & MLX5_CROSS_VHCA_ALLOWED_OBJS_FT) && (res & MLX5_CROSS_VHCA_ALLOWED_OBJS_RTC); + caps->flow_table_hash_type = MLX5_GET(query_hca_cap_out, out, + capability.cmd_hca_cap_2.flow_table_hash_type); + MLX5_SET(query_hca_cap_in, in, op_mod, MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE | MLX5_HCA_CAP_OPMOD_GET_CUR); diff --git a/drivers/net/mlx5/hws/mlx5dr_cmd.h b/drivers/net/mlx5/hws/mlx5dr_cmd.h index 28e5ea4726..03db62e2e2 100644 --- a/drivers/net/mlx5/hws/mlx5dr_cmd.h +++ b/drivers/net/mlx5/hws/mlx5dr_cmd.h @@ -217,10 +217,11 @@ struct mlx5dr_cmd_query_caps { uint8_t rtc_log_depth_max; uint8_t format_select_gtpu_dw_0; uint8_t format_select_gtpu_dw_1; + uint8_t flow_table_hash_type; uint8_t format_select_gtpu_dw_2; uint8_t format_select_gtpu_ext_dw_0; - uint32_t linear_match_definer; uint8_t access_index_mode; + uint32_t linear_match_definer; bool full_dw_jumbo_support; bool rtc_hash_split_table; bool rtc_linear_lookup_table; diff --git a/drivers/net/mlx5/hws/mlx5dr_crc32.c b/drivers/net/mlx5/hws/mlx5dr_crc32.c new file mode 100644 index 0000000000..9c454eda0c --- /dev/null +++ b/drivers/net/mlx5/hws/mlx5dr_crc32.c @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright (c) 2023 NVIDIA Corporation & Affiliates + */ + +#include "mlx5dr_internal.h" + +uint32_t dr_ste_crc_tab32[] = { + 0x0, 0x77073096, 0xee0e612c, 0x990951ba, 0x76dc419, 0x706af48f, + 0xe963a535, 0x9e6495a3, 0xedb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988, + 0x9b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91, 0x1db71064, 0x6ab020f2, + 0xf3b97148, 0x84be41de, 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7, + 0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, 0x14015c4f, 0x63066cd9, + 0xfa0f3d63, 0x8d080df5, 0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172, + 0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b, 0x35b5a8fa, 0x42b2986c, + 0xdbbbc9d6, 0xacbcf940, 0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59, + 0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116, 0x21b4f4b5, 0x56b3c423, + 0xcfba9599, 0xb8bda50f, 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924, + 0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, 0x76dc4190, 0x1db7106, + 0x98d220bc, 0xefd5102a, 0x71b18589, 0x6b6b51f, 0x9fbfe4a5, 0xe8b8d433, + 0x7807c9a2, 0xf00f934, 0x9609a88e, 0xe10e9818, 0x7f6a0dbb, 0x86d3d2d, + 0x91646c97, 0xe6635c01, 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e, + 0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457, 0x65b0d9c6, 0x12b7e950, + 0x8bbeb8ea, 0xfcb9887c, 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65, + 0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2, 0x4adfa541, 0x3dd895d7, + 0xa4d1c46d, 0xd3d6f4fb, 0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0, + 0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9, 0x5005713c, 0x270241aa, + 0xbe0b1010, 0xc90c2086, 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f, + 0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, 0x59b33d17, 0x2eb40d81, + 0xb7bd5c3b, 0xc0ba6cad, 0xedb88320, 0x9abfb3b6, 0x3b6e20c, 0x74b1d29a, + 0xead54739, 0x9dd277af, 0x4db2615, 0x73dc1683, 0xe3630b12, 0x94643b84, + 0xd6d6a3e, 0x7a6a5aa8, 0xe40ecf0b, 0x9309ff9d, 0xa00ae27, 0x7d079eb1, + 0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe, 0xf762575d, 0x806567cb, + 0x196c3671, 0x6e6b06e7, 0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc, + 0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5, 0xd6d6a3e8, 0xa1d1937e, + 0x38d8c2c4, 0x4fdff252, 0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b, + 0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60, 0xdf60efc3, 0xa867df55, + 0x316e8eef, 0x4669be79, 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236, + 0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, 0xc5ba3bbe, 0xb2bd0b28, + 0x2bb45a92, 0x5cb36a04, 0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d, + 0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x26d930a, 0x9c0906a9, 0xeb0e363f, + 0x72076785, 0x5005713, 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0xcb61b38, + 0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0xbdbdf21, 0x86d3d2d4, 0xf1d4e242, + 0x68ddb3f8, 0x1fda836e, 0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777, + 0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c, 0x8f659eff, 0xf862ae69, + 0x616bffd3, 0x166ccf45, 0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2, + 0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db, 0xaed16a4a, 0xd9d65adc, + 0x40df0b66, 0x37d83bf0, 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9, + 0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, 0xbad03605, 0xcdd70693, + 0x54de5729, 0x23d967bf, 0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94, + 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d +}; + +uint32_t mlx5dr_crc32_calc(uint8_t *p, size_t len) +{ + uint32_t crc = 0; + + while (len--) + crc = (crc >> 8) ^ dr_ste_crc_tab32[(crc ^ *p++) & 255]; + + return rte_be_to_cpu_32(crc); +} diff --git a/drivers/net/mlx5/hws/mlx5dr_crc32.h b/drivers/net/mlx5/hws/mlx5dr_crc32.h new file mode 100644 index 0000000000..9aab9e06ca --- /dev/null +++ b/drivers/net/mlx5/hws/mlx5dr_crc32.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright (c) 2023 NVIDIA Corporation & Affiliates + */ + +#ifndef MLX5DR_CRC32_C_ +#define MLX5DR_CRC32_C_ + +/* Ethernet AUTODIN II CRC32 (little-endian) + * CRC32_POLY 0xedb88320 + */ +uint32_t mlx5dr_crc32_calc(uint8_t *p, size_t len); + +#endif /* MLX5DR_CRC32_C_ */ diff --git a/drivers/net/mlx5/hws/mlx5dr_internal.h b/drivers/net/mlx5/hws/mlx5dr_internal.h index 3770d28e62..021d599a56 100644 --- a/drivers/net/mlx5/hws/mlx5dr_internal.h +++ b/drivers/net/mlx5/hws/mlx5dr_internal.h @@ -38,6 +38,7 @@ #include "mlx5dr_matcher.h" #include "mlx5dr_debug.h" #include "mlx5dr_pat_arg.h" +#include "mlx5dr_crc32.h" #define DW_SIZE 4 #define BITS_IN_BYTE 8 diff --git a/drivers/net/mlx5/hws/mlx5dr_rule.c b/drivers/net/mlx5/hws/mlx5dr_rule.c index 931c68b160..980a99b226 100644 --- a/drivers/net/mlx5/hws/mlx5dr_rule.c +++ b/drivers/net/mlx5/hws/mlx5dr_rule.c @@ -770,3 +770,40 @@ size_t mlx5dr_rule_get_handle_size(void) { return sizeof(struct mlx5dr_rule); } + +int mlx5dr_rule_hash_calculate(struct mlx5dr_matcher *matcher, + const struct rte_flow_item items[], + uint8_t mt_idx, + enum mlx5dr_rule_hash_calc_mode mode, + uint32_t *ret_hash) +{ + uint8_t tag[MLX5DR_STE_SZ] = {0}; + struct mlx5dr_match_template *mt; + + if (!matcher || !matcher->mt) { + rte_errno = EINVAL; + return -rte_errno; + } + + mt = &matcher->mt[mt_idx]; + + if (mlx5dr_matcher_req_fw_wqe(matcher) || + mlx5dr_table_is_root(matcher->tbl) || + matcher->tbl->ctx->caps->access_index_mode == MLX5DR_MATCHER_INSERT_BY_HASH || + matcher->tbl->ctx->caps->flow_table_hash_type != MLX5_FLOW_TABLE_HASH_TYPE_CRC32) { + rte_errno = ENOTSUP; + return -rte_errno; + } + + mlx5dr_definer_create_tag(items, mt->fc, mt->fc_sz, tag); + if (mlx5dr_matcher_mt_is_jumbo(mt)) + *ret_hash = mlx5dr_crc32_calc(tag, MLX5DR_JUMBO_TAG_SZ); + else + *ret_hash = mlx5dr_crc32_calc(tag + MLX5DR_ACTIONS_SZ, + MLX5DR_MATCH_TAG_SZ); + + if (mode == MLX5DR_RULE_HASH_CALC_MODE_IDX) + *ret_hash = *ret_hash & (BIT(matcher->attr.rule.num_log) - 1); + + return 0; +} diff --git a/drivers/net/mlx5/hws/mlx5dr_rule.h b/drivers/net/mlx5/hws/mlx5dr_rule.h index 886cf77992..f7d97eead5 100644 --- a/drivers/net/mlx5/hws/mlx5dr_rule.h +++ b/drivers/net/mlx5/hws/mlx5dr_rule.h @@ -10,6 +10,7 @@ enum { MLX5DR_ACTIONS_SZ = 12, MLX5DR_MATCH_TAG_SZ = 32, MLX5DR_JUMBO_TAG_SZ = 44, + MLX5DR_STE_SZ = 64, }; enum mlx5dr_rule_status { From patchwork Sun Oct 29 18:22:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory Etelson X-Patchwork-Id: 133612 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id BC56C43239; Sun, 29 Oct 2023 19:24:41 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9D57542686; Sun, 29 Oct 2023 19:23:57 +0100 (CET) Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2052.outbound.protection.outlook.com [40.107.94.52]) by mails.dpdk.org (Postfix) with ESMTP id 4E60041144 for ; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Oct 2023 18:23:53.2474 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 55a03d45-2855-4f07-1c0c-08dbd8ac34c0 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044EF.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV3PR12MB9268 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Ori Kam This commit adds calculate hash function support for mlx5 PMD. Signed-off-by: Ori Kam Acked-by: Dariusz Sosnowski --- drivers/net/mlx5/mlx5_flow.c | 32 ++++++++++++++++++++++++++++++++ drivers/net/mlx5/mlx5_flow.h | 8 ++++++++ drivers/net/mlx5/mlx5_flow_hw.c | 31 ++++++++++++++++++++++++++++++- 3 files changed, 70 insertions(+), 1 deletion(-) diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c index ad9a2f2273..819831cff8 100644 --- a/drivers/net/mlx5/mlx5_flow.c +++ b/drivers/net/mlx5/mlx5_flow.c @@ -1178,6 +1178,13 @@ mlx5_flow_async_action_list_handle_query_update(struct rte_eth_dev *dev, enum rte_flow_query_update_mode mode, void *user_data, struct rte_flow_error *error); +static int +mlx5_flow_calc_table_hash(struct rte_eth_dev *dev, + const struct rte_flow_template_table *table, + const struct rte_flow_item pattern[], + uint8_t pattern_template_index, + uint32_t *hash, struct rte_flow_error *error); + static const struct rte_flow_ops mlx5_flow_ops = { .validate = mlx5_flow_validate, .create = mlx5_flow_create, @@ -1231,6 +1238,7 @@ static const struct rte_flow_ops mlx5_flow_ops = { mlx5_flow_action_list_handle_query_update, .async_action_list_handle_query_update = mlx5_flow_async_action_list_handle_query_update, + .flow_calc_table_hash = mlx5_flow_calc_table_hash, }; /* Tunnel information. */ @@ -11058,6 +11066,30 @@ mlx5_flow_async_action_list_handle_query_update(struct rte_eth_dev *dev, } +static int +mlx5_flow_calc_table_hash(struct rte_eth_dev *dev, + const struct rte_flow_template_table *table, + const struct rte_flow_item pattern[], + uint8_t pattern_template_index, + uint32_t *hash, struct rte_flow_error *error) +{ + struct rte_flow_attr attr = { .transfer = 0 }; + enum mlx5_flow_drv_type drv_type = flow_get_drv_type(dev, &attr); + const struct mlx5_flow_driver_ops *fops; + + if (drv_type == MLX5_FLOW_TYPE_MIN || drv_type == MLX5_FLOW_TYPE_MAX) + return rte_flow_error_set(error, ENOTSUP, + RTE_FLOW_ERROR_TYPE_ACTION, + NULL, "invalid driver type"); + fops = flow_get_drv_ops(drv_type); + if (!fops || !fops->action_query_update) + return rte_flow_error_set(error, ENOTSUP, + RTE_FLOW_ERROR_TYPE_ACTION, + NULL, "no query_update handler"); + return fops->flow_calc_table_hash(dev, table, pattern, pattern_template_index, + hash, error); +} + /** * Destroy all indirect actions (shared RSS). * diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h index 81ec8fd7f1..db6f3ba6f5 100644 --- a/drivers/net/mlx5/mlx5_flow.h +++ b/drivers/net/mlx5/mlx5_flow.h @@ -2062,6 +2062,13 @@ typedef int const void **update, void **query, enum rte_flow_query_update_mode mode, void *user_data, struct rte_flow_error *error); +typedef int +(*mlx5_flow_calc_table_hash_t) + (struct rte_eth_dev *dev, + const struct rte_flow_template_table *table, + const struct rte_flow_item pattern[], + uint8_t pattern_template_index, + uint32_t *hash, struct rte_flow_error *error); struct mlx5_flow_driver_ops { mlx5_flow_validate_t validate; @@ -2133,6 +2140,7 @@ struct mlx5_flow_driver_ops { action_list_handle_query_update; mlx5_flow_async_action_list_handle_query_update_t async_action_list_handle_query_update; + mlx5_flow_calc_table_hash_t flow_calc_table_hash; }; /* mlx5_flow.c */ diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index cccf7de13f..ea43ebb78b 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -2773,7 +2773,7 @@ flow_hw_actions_construct(struct rte_eth_dev *dev, static const struct rte_flow_item * flow_hw_get_rule_items(struct rte_eth_dev *dev, - struct rte_flow_template_table *table, + const struct rte_flow_template_table *table, const struct rte_flow_item items[], uint8_t pattern_template_index, struct mlx5_hw_q_job *job) @@ -10144,6 +10144,34 @@ flow_hw_action_list_handle_query_update(struct rte_eth_dev *dev, update, query, mode, NULL, error); } +static int +flow_hw_calc_table_hash(struct rte_eth_dev *dev, + const struct rte_flow_template_table *table, + const struct rte_flow_item pattern[], + uint8_t pattern_template_index, + uint32_t *hash, struct rte_flow_error *error) +{ + const struct rte_flow_item *items; + /* Temp job to allow adding missing items */ + static struct rte_flow_item tmp_items[MLX5_HW_MAX_ITEMS]; + static struct mlx5_hw_q_job job = {.items = tmp_items}; + int res; + + items = flow_hw_get_rule_items(dev, table, pattern, + pattern_template_index, + &job); + res = mlx5dr_rule_hash_calculate(table->matcher, items, + pattern_template_index, + MLX5DR_RULE_HASH_CALC_MODE_RAW, + hash); + if (res) + return rte_flow_error_set(error, res, + RTE_FLOW_ERROR_TYPE_UNSPECIFIED, + NULL, + "hash could not be calculated"); + return 0; +} + const struct mlx5_flow_driver_ops mlx5_flow_hw_drv_ops = { .info_get = flow_hw_info_get, .configure = flow_hw_configure, @@ -10187,6 +10215,7 @@ const struct mlx5_flow_driver_ops mlx5_flow_hw_drv_ops = { .get_q_aged_flows = flow_hw_get_q_aged_flows, .item_create = flow_dv_item_create, .item_release = flow_dv_item_release, + .flow_calc_table_hash = flow_hw_calc_table_hash, }; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Oct 2023 18:23:58.4164 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e16c1eb0-49da-4a97-7200-08dbd8ac37d2 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002636E.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CYYPR12MB8921 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Ori Kam Due to mlx5dr internal logic calling the rule_create function must have items structure. This commit create such temp structure. Fixes: fa16fead9a68 ("net/mlx5/hws: support rule update after its creation") Cc: erezsh@nvidia.com Signed-off-by: Ori Kam Acked-by: Dariusz Sosnowski --- drivers/net/mlx5/mlx5_flow_hw.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index ea43ebb78b..2148f5a63a 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -2987,6 +2987,7 @@ flow_hw_async_flow_create_by_index(struct rte_eth_dev *dev, void *user_data, struct rte_flow_error *error) { + struct rte_flow_item items[] = {{.type = RTE_FLOW_ITEM_TYPE_END,}}; struct mlx5_priv *priv = dev->data->dev_private; struct mlx5dr_rule_attr rule_attr = { .queue_id = queue, @@ -3050,7 +3051,7 @@ flow_hw_async_flow_create_by_index(struct rte_eth_dev *dev, goto free; } ret = mlx5dr_rule_create(table->matcher, - 0, NULL, action_template_index, rule_acts, + 0, items, action_template_index, rule_acts, &rule_attr, (struct mlx5dr_rule *)flow->rule); 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Oct 2023 18:24:02.1054 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0fbc5dad-0926-416f-5934-08dbd8ac3a05 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002636D.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8710 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Ori Kam Add query for nic flow table support bit. Fixes: 5f44fb1958e5 ("common/mlx5: query capability of registers") Cc: bingz@nvidia.com Signed-off-by: Ori Kam Acked-by: Dariusz Sosnowski --- drivers/common/mlx5/mlx5_devx_cmds.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c index ff2d6d10b7..3afb2e9f80 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.c +++ b/drivers/common/mlx5/mlx5_devx_cmds.c @@ -1082,6 +1082,7 @@ mlx5_devx_cmd_query_hca_attr(void *ctx, attr->striding_rq = MLX5_GET(cmd_hca_cap, hcattr, striding_rq); attr->ext_stride_num_range = MLX5_GET(cmd_hca_cap, hcattr, ext_stride_num_range); + attr->nic_flow_table = MLX5_GET(cmd_hca_cap, hcattr, nic_flow_table); attr->max_flow_counter_15_0 = MLX5_GET(cmd_hca_cap, hcattr, max_flow_counter_15_0); attr->max_flow_counter_31_16 = MLX5_GET(cmd_hca_cap, hcattr, From patchwork Sun Oct 29 18:22:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory Etelson X-Patchwork-Id: 133617 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 41F9443239; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Oct 2023 18:24:05.1749 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0dd135e7-5243-487c-b6cf-08dbd8ac3bd9 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF00026369.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7185 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Ori Kam This commit adds the support for a additional registers that were added to the HW. Signed-off-by: Ori Kam Acked-by: Dariusz Sosnowski --- drivers/common/mlx5/mlx5_devx_cmds.c | 16 +++++++++---- drivers/common/mlx5/mlx5_devx_cmds.h | 2 +- drivers/common/mlx5/mlx5_prm.h | 36 ++++++++++++++++++++++++---- drivers/net/mlx5/mlx5.c | 4 ++-- drivers/net/mlx5/mlx5.h | 2 +- drivers/net/mlx5/mlx5_flow_dv.c | 4 ++++ drivers/net/mlx5/mlx5_flow_hw.c | 2 +- 7 files changed, 53 insertions(+), 13 deletions(-) diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c index 3afb2e9f80..4d8818924a 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.c +++ b/drivers/common/mlx5/mlx5_devx_cmds.c @@ -1229,7 +1229,7 @@ mlx5_devx_cmd_query_hca_attr(void *ctx, attr->modify_outer_ip_ecn = MLX5_GET (flow_table_nic_cap, hcattr, ft_header_modify_nic_receive.outer_ip_ecn); - attr->set_reg_c = 0xff; + attr->set_reg_c = 0xffff; if (attr->nic_flow_table) { #define GET_RX_REG_X_BITS \ MLX5_GET(flow_table_nic_cap, hcattr, \ @@ -1238,10 +1238,16 @@ mlx5_devx_cmd_query_hca_attr(void *ctx, MLX5_GET(flow_table_nic_cap, hcattr, \ ft_header_modify_nic_transmit.metadata_reg_c_x) - uint32_t tx_reg, rx_reg; + uint32_t tx_reg, rx_reg, reg_c_8_15; tx_reg = GET_TX_REG_X_BITS; + reg_c_8_15 = MLX5_GET(flow_table_nic_cap, hcattr, + ft_field_support_2_nic_transmit.metadata_reg_c_8_15); + tx_reg |= ((0xff & reg_c_8_15) << 8); rx_reg = GET_RX_REG_X_BITS; + reg_c_8_15 = MLX5_GET(flow_table_nic_cap, hcattr, + ft_field_support_2_nic_receive.metadata_reg_c_8_15); + rx_reg |= ((0xff & reg_c_8_15) << 8); attr->set_reg_c &= (rx_reg & tx_reg); #undef GET_RX_REG_X_BITS @@ -1371,7 +1377,7 @@ mlx5_devx_cmd_query_hca_attr(void *ctx, MLX5_GET(esw_cap, hcattr, esw_manager_vport_number); } if (attr->eswitch_manager) { - uint32_t esw_reg; + uint32_t esw_reg, reg_c_8_15; hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, MLX5_GET_HCA_CAP_OP_MOD_ESW_FLOW_TABLE | @@ -1380,7 +1386,9 @@ mlx5_devx_cmd_query_hca_attr(void *ctx, return rc; esw_reg = MLX5_GET(flow_table_esw_cap, hcattr, ft_header_modify_esw_fdb.metadata_reg_c_x); - attr->set_reg_c &= esw_reg; + reg_c_8_15 = MLX5_GET(flow_table_esw_cap, hcattr, + ft_field_support_2_esw_fdb.metadata_reg_c_8_15); + attr->set_reg_c &= ((0xff & reg_c_8_15) << 8) | esw_reg; } return 0; error: diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h index 11772431ae..7f23e925a5 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.h +++ b/drivers/common/mlx5/mlx5_devx_cmds.h @@ -301,7 +301,7 @@ struct mlx5_hca_attr { uint32_t cqe_compression_128:1; uint32_t multi_pkt_send_wqe:1; uint32_t enhanced_multi_pkt_send_wqe:1; - uint32_t set_reg_c:8; + uint32_t set_reg_c:16; uint32_t nic_flow_table:1; uint32_t modify_outer_ip_ecn:1; union { diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index 19c6d0282b..2b499666f8 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -840,6 +840,14 @@ enum mlx5_modification_field { MLX5_MODI_IN_MPLS_LABEL_3, MLX5_MODI_IN_MPLS_LABEL_4, MLX5_MODI_OUT_IPV6_NEXT_HDR = 0x4A, + MLX5_MODI_META_REG_C_8 = 0x8F, + MLX5_MODI_META_REG_C_9 = 0x90, + MLX5_MODI_META_REG_C_10 = 0x91, + MLX5_MODI_META_REG_C_11 = 0x92, + MLX5_MODI_META_REG_C_12 = 0x93, + MLX5_MODI_META_REG_C_13 = 0x94, + MLX5_MODI_META_REG_C_14 = 0x95, + MLX5_MODI_META_REG_C_15 = 0x96, MLX5_MODI_INVALID = INT_MAX, }; @@ -2227,8 +2235,22 @@ struct mlx5_ifc_ft_fields_support_2_bits { u8 inner_ipv4_checksum_ok[0x1]; u8 inner_l4_checksum_ok[0x1]; u8 outer_ipv4_checksum_ok[0x1]; - u8 outer_l4_checksum_ok[0x1]; - u8 reserved_at_20[0x60]; + u8 outer_l4_checksum_ok[0x1]; /* end of DW0 */ + u8 reserved_at_20[0x18]; + union { + struct { + u8 metadata_reg_c_15[0x1]; + u8 metadata_reg_c_14[0x1]; + u8 metadata_reg_c_13[0x1]; + u8 metadata_reg_c_12[0x1]; + u8 metadata_reg_c_11[0x1]; + u8 metadata_reg_c_10[0x1]; + u8 metadata_reg_c_9[0x1]; + u8 metadata_reg_c_8[0x1]; + }; + u8 metadata_reg_c_8_15[0x8]; + }; /* end of DW1 */ + u8 reserved_at_40[0x40]; }; struct mlx5_ifc_flow_table_nic_cap_bits { @@ -2250,7 +2272,10 @@ struct mlx5_ifc_flow_table_nic_cap_bits { ft_header_modify_nic_receive; struct mlx5_ifc_ft_fields_support_2_bits ft_field_support_2_nic_receive; - u8 reserved_at_1480[0x780]; + u8 reserved_at_1480[0x280]; + struct mlx5_ifc_ft_fields_support_2_bits + ft_field_support_2_nic_transmit; + u8 reserved_at_1780[0x480]; struct mlx5_ifc_ft_fields_support_bits ft_header_modify_nic_transmit; u8 reserved_at_2000[0x6000]; @@ -2259,7 +2284,10 @@ struct mlx5_ifc_flow_table_nic_cap_bits { struct mlx5_ifc_flow_table_esw_cap_bits { u8 reserved_at_0[0x800]; struct mlx5_ifc_ft_fields_support_bits ft_header_modify_esw_fdb; - u8 reserved_at_C00[0x7400]; + u8 reserved_at_C00[0x800]; + struct mlx5_ifc_ft_fields_support_2_bits + ft_field_support_2_esw_fdb; + u8 reserved_at_1480[0x6b80]; }; enum mlx5_ifc_cross_vhca_object_to_object_supported_types { diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c index 840c566162..cdb4eeb612 100644 --- a/drivers/net/mlx5/mlx5.c +++ b/drivers/net/mlx5/mlx5.c @@ -1604,8 +1604,8 @@ mlx5_init_hws_flow_tags_registers(struct mlx5_dev_ctx_shared *sh) { struct mlx5_dev_registers *reg = &sh->registers; uint32_t meta_mode = sh->config.dv_xmeta_en; - uint8_t masks = (uint8_t)sh->cdev->config.hca_attr.set_reg_c; - uint8_t unset = 0; + uint16_t masks = (uint16_t)sh->cdev->config.hca_attr.set_reg_c; + uint16_t unset = 0; uint32_t i, j; /* diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index a0dcd788b4..0289cbd04b 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -1373,7 +1373,7 @@ struct mlx5_hws_cnt_svc_mng { struct mlx5_hws_aso_mng aso_mng __rte_cache_aligned; }; -#define MLX5_FLOW_HW_TAGS_MAX 8 +#define MLX5_FLOW_HW_TAGS_MAX 12 struct mlx5_dev_registers { enum modify_reg aso_reg; diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index 9268a07c84..bdc8d0076a 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -970,6 +970,10 @@ static enum mlx5_modification_field reg_to_field[] = { [REG_C_5] = MLX5_MODI_META_REG_C_5, [REG_C_6] = MLX5_MODI_META_REG_C_6, [REG_C_7] = MLX5_MODI_META_REG_C_7, + [REG_C_8] = MLX5_MODI_META_REG_C_8, + [REG_C_9] = MLX5_MODI_META_REG_C_9, + [REG_C_10] = MLX5_MODI_META_REG_C_10, + [REG_C_11] = MLX5_MODI_META_REG_C_11, }; /** diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index 2148f5a63a..f2159e40fd 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -5615,7 +5615,7 @@ flow_hw_pattern_validate(struct rte_eth_dev *dev, { const struct rte_flow_item_tag *tag = (const struct rte_flow_item_tag *)items[i].spec; - uint8_t regcs = (uint8_t)priv->sh->cdev->config.hca_attr.set_reg_c; + uint16_t regcs = (uint8_t)priv->sh->cdev->config.hca_attr.set_reg_c; if (!((1 << (tag->index - REG_C_0)) & regcs)) return rte_flow_error_set(error, EINVAL, From patchwork Sun Oct 29 18:23:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory Etelson X-Patchwork-Id: 133616 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id AF14643239; Sun, 29 Oct 2023 19:25:09 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B98D0427E3; Sun, 29 Oct 2023 19:24:13 +0100 (CET) Received: from NAM02-BN1-obe.outbound.protection.outlook.com (mail-bn1nam02on2080.outbound.protection.outlook.com [40.107.212.80]) by mails.dpdk.org (Postfix) with ESMTP id 0497440E4A for ; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Oct 2023 18:24:07.1991 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 419820dc-b886-4ef4-97b5-08dbd8ac3d0e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002636D.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB7952 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Ori Kam This commit introduce validation for invalid tags Signed-off-by: Ori Kam Acked-by: Dariusz Sosnowski --- drivers/net/mlx5/mlx5_flow_hw.c | 30 +++++++++++++++++++++++++++--- 1 file changed, 27 insertions(+), 3 deletions(-) diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index f2159e40fd..2b1fc519fc 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -4049,7 +4049,8 @@ flow_hw_modify_field_is_used(const struct rte_flow_action_modify_field *action, } static int -flow_hw_validate_action_modify_field(const struct rte_flow_action *action, +flow_hw_validate_action_modify_field(struct rte_eth_dev *dev, + const struct rte_flow_action *action, const struct rte_flow_action *mask, struct rte_flow_error *error) { @@ -4118,6 +4119,22 @@ flow_hw_validate_action_modify_field(const struct rte_flow_action *action, if (ret) return ret; } + if ((action_conf->dst.field == RTE_FLOW_FIELD_TAG && + action_conf->dst.tag_index >= MLX5_FLOW_HW_TAGS_MAX && + action_conf->dst.tag_index != MLX5_LINEAR_HASH_TAG_INDEX) || + (action_conf->src.field == RTE_FLOW_FIELD_TAG && + action_conf->src.tag_index >= MLX5_FLOW_HW_TAGS_MAX && + action_conf->src.tag_index != MLX5_LINEAR_HASH_TAG_INDEX)) + return rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ACTION, action, + "tag index is out of range"); + if ((action_conf->dst.field == RTE_FLOW_FIELD_TAG && + flow_hw_get_reg_id(dev, RTE_FLOW_ITEM_TYPE_TAG, action_conf->dst.tag_index) == REG_NON) || + (action_conf->src.field == RTE_FLOW_FIELD_TAG && + flow_hw_get_reg_id(dev, RTE_FLOW_ITEM_TYPE_TAG, action_conf->src.tag_index) == REG_NON)) + return rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ACTION, action, + "tag index is out of range"); if (mask_conf->width != UINT32_MAX) return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, action, @@ -4728,7 +4745,7 @@ mlx5_flow_hw_actions_validate(struct rte_eth_dev *dev, action_flags |= MLX5_FLOW_ACTION_METER; break; case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD: - ret = flow_hw_validate_action_modify_field(action, mask, + ret = flow_hw_validate_action_modify_field(dev, action, mask, error); if (ret < 0) return ret; @@ -5596,7 +5613,14 @@ flow_hw_pattern_validate(struct rte_eth_dev *dev, if (tag == NULL) return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, - NULL, "Tag spec is NULL"); + NULL, + "Tag spec is NULL"); + if (tag->index >= MLX5_FLOW_HW_TAGS_MAX && + tag->index != MLX5_LINEAR_HASH_TAG_INDEX) + return rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_UNSPECIFIED, + NULL, + "Invalid tag index"); tag_idx = flow_hw_get_reg_id(dev, RTE_FLOW_ITEM_TYPE_TAG, tag->index); if (tag_idx == REG_NON) return rte_flow_error_set(error, EINVAL,