diff mbox series

[04/13] net/cnxk: add use nixtx offset for cn10kb

Message ID 20221011120135.45846-4-ndabilpuram@marvell.com (mailing list archive)
State Changes Requested, archived
Delegated to: Jerin Jacob
Headers
Series [01/13] common/cnxk: set MTU size on SDP based on SoC type |

Checks

Context Check Description
ci/checkpatch success coding style OK

Commit Message

Nithin Dabilpuram Oct. 11, 2022, 12:01 p.m. UTC 
  In outbound inline case, use NIX Tx offset instead of
NIX Tx address for CN103XX as per new instruction format.

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
---
 drivers/common/cnxk/roc_constants.h | 1 +
 drivers/event/cnxk/cn10k_worker.h   | 3 +++
 drivers/net/cnxk/cn10k_ethdev.c     | 6 ++++++
 drivers/net/cnxk/cn10k_ethdev.h     | 3 ++-
 drivers/net/cnxk/cn10k_ethdev_sec.c | 2 ++
 drivers/net/cnxk/cn10k_tx.h         | 4 ++--
 6 files changed, 16 insertions(+), 3 deletions(-)
diff mbox series

Patch

diff --git a/drivers/common/cnxk/roc_constants.h b/drivers/common/cnxk/roc_constants.h
index c693dde62e..0495965daa 100644
--- a/drivers/common/cnxk/roc_constants.h
+++ b/drivers/common/cnxk/roc_constants.h
@@ -12,6 +12,7 @@ 
 /* [CN10K, .) */
 #define ROC_LMT_LINE_SZ		    128
 #define ROC_NUM_LMT_LINES	    2048
+#define ROC_LMT_LINES_PER_STR_LOG2  4
 #define ROC_LMT_LINES_PER_CORE_LOG2 5
 #define ROC_LMT_LINE_SIZE_LOG2	    7
 #define ROC_LMT_BASE_PER_CORE_LOG2                                             \
diff --git a/drivers/event/cnxk/cn10k_worker.h b/drivers/event/cnxk/cn10k_worker.h
index 7a82dd352a..75a2ff244a 100644
--- a/drivers/event/cnxk/cn10k_worker.h
+++ b/drivers/event/cnxk/cn10k_worker.h
@@ -595,6 +595,9 @@  cn10k_sso_tx_one(struct cn10k_sso_hws *ws, struct rte_mbuf *m, uint64_t *cmd,
 		ws->gw_rdata = roc_sso_hws_head_wait(ws->base);
 
 	cn10k_sso_txq_fc_wait(txq);
+	if (flags & NIX_TX_OFFLOAD_SECURITY_F && sec)
+		cn10k_nix_sec_fc_wait_one(txq);
+
 	roc_lmt_submit_steorl(lmt_id, pa);
 
 	if (flags & NIX_TX_OFFLOAD_MBUF_NOFF_F) {
diff --git a/drivers/net/cnxk/cn10k_ethdev.c b/drivers/net/cnxk/cn10k_ethdev.c
index e8faeebe1f..cf1d9b164d 100644
--- a/drivers/net/cnxk/cn10k_ethdev.c
+++ b/drivers/net/cnxk/cn10k_ethdev.c
@@ -538,6 +538,9 @@  cn10k_nix_reassembly_capability_get(struct rte_eth_dev *eth_dev,
 	int rc = -ENOTSUP;
 	RTE_SET_USED(eth_dev);
 
+	if (!roc_nix_has_reass_support(&dev->nix))
+		return -ENOTSUP;
+
 	if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY) {
 		reassembly_capa->timeout_ms = 60 * 1000;
 		reassembly_capa->max_frags = 4;
@@ -565,6 +568,9 @@  cn10k_nix_reassembly_conf_set(struct rte_eth_dev *eth_dev,
 	struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
 	int rc = 0;
 
+	if (!roc_nix_has_reass_support(&dev->nix))
+		return -ENOTSUP;
+
 	if (!conf->flags) {
 		/* Clear offload flags on disable */
 		dev->rx_offload_flags &= ~NIX_RX_REAS_F;
diff --git a/drivers/net/cnxk/cn10k_ethdev.h b/drivers/net/cnxk/cn10k_ethdev.h
index d0a5b136e3..948c8348ad 100644
--- a/drivers/net/cnxk/cn10k_ethdev.h
+++ b/drivers/net/cnxk/cn10k_ethdev.h
@@ -75,7 +75,8 @@  struct cn10k_sec_sess_priv {
 			uint16_t partial_len : 10;
 			uint16_t chksum : 2;
 			uint16_t dec_ttl : 1;
-			uint16_t rsvd : 3;
+			uint16_t nixtx_off : 1;
+			uint16_t rsvd : 2;
 		};
 
 		uint64_t u64;
diff --git a/drivers/net/cnxk/cn10k_ethdev_sec.c b/drivers/net/cnxk/cn10k_ethdev_sec.c
index 6de4a284da..3ca707f038 100644
--- a/drivers/net/cnxk/cn10k_ethdev_sec.c
+++ b/drivers/net/cnxk/cn10k_ethdev_sec.c
@@ -798,6 +798,8 @@  cn10k_eth_sec_session_create(void *device,
 		sess_priv.chksum = (!ipsec->options.ip_csum_enable << 1 |
 				    !ipsec->options.l4_csum_enable);
 		sess_priv.dec_ttl = ipsec->options.dec_ttl;
+		if (roc_model_is_cn10kb_a0())
+			sess_priv.nixtx_off = 1;
 
 		/* Pointer from eth_sec -> outb_sa */
 		eth_sec->sa = outb_sa;
diff --git a/drivers/net/cnxk/cn10k_tx.h b/drivers/net/cnxk/cn10k_tx.h
index 492942de15..527b65022f 100644
--- a/drivers/net/cnxk/cn10k_tx.h
+++ b/drivers/net/cnxk/cn10k_tx.h
@@ -397,7 +397,7 @@  cn10k_nix_prep_sec_vec(struct rte_mbuf *m, uint64x2_t *cmd0, uint64x2_t *cmd1,
 		/* DLEN passed is excluding L2 HDR */
 		pkt_len -= l2_len;
 	}
-	w0 |= nixtx;
+	w0 |= sess_priv.nixtx_off ? ((((int64_t)nixtx - (int64_t)dptr) & 0xFFFFF) << 32) : nixtx;
 	/* CPT word 0 and 1 */
 	cmd01 = vdupq_n_u64(0);
 	cmd01 = vsetq_lane_u64(w0, cmd01, 0);
@@ -539,7 +539,7 @@  cn10k_nix_prep_sec(struct rte_mbuf *m, uint64_t *cmd, uintptr_t *nixtx_addr,
 		sg->seg1_size = pkt_len + dlen_adj;
 		pkt_len -= l2_len;
 	}
-	w0 |= nixtx;
+	w0 |= sess_priv.nixtx_off ? ((((int64_t)nixtx - (int64_t)dptr) & 0xFFFFF) << 32) : nixtx;
 	/* CPT word 0 and 1 */
 	cmd01 = vdupq_n_u64(0);
 	cmd01 = vsetq_lane_u64(w0, cmd01, 0);