From patchwork Tue Oct 11 12:01:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 117909 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B3956A0547; Tue, 11 Oct 2022 14:01:49 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9964842DBA; Tue, 11 Oct 2022 14:01:49 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id A72CA42D42 for ; Tue, 11 Oct 2022 14:01:48 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 29B9eJgG008912 for ; Tue, 11 Oct 2022 05:01:43 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=OR2jBpap/Y8Kt/qKqism7DwyWjJax3oskGnaTP1SKZ8=; b=ZfD1y2XJIESNL/xTdCuscDVeyWAB+/O/HGmB7/36P2wq2AOlKpSY6q/ZGnSTis73Vka8 4oOZELfffZ5+XTJwArg01ZeCDX5E/I/fIEPIjC6KErc1PKiXMhVGLnYnORbbi9j5YjF1 zOKXGjsAi+NAK76g7PmZnwNUmcn/HA60ozwyNQK3el8MBKdAukehAzittv+OtTt34MBt lFlpLKDrd01Al8FbxsJ3ifRjqb/s2jFAwCSGb0nwJxI/abmr9RqL073yOJntXo6T6LNJ 7tFo77O4/lsXEgF3BuRisvU3F/FekBIZyOqkiSPvxgZvbgH+GxWJaY2ZZeLB4WbS5f7a Eg== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3k40g4y26f-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 11 Oct 2022 05:01:42 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 11 Oct 2022 05:01:40 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 11 Oct 2022 05:01:40 -0700 Received: from localhost.localdomain (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 8957F3F7040; Tue, 11 Oct 2022 05:01:38 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , , Sathesh Edara Subject: [PATCH 01/13] common/cnxk: set MTU size on SDP based on SoC type Date: Tue, 11 Oct 2022 17:31:23 +0530 Message-ID: <20221011120135.45846-1-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: aszLtfhV8ZbstN5-JAFWpk7r17lgU91E X-Proofpoint-GUID: aszLtfhV8ZbstN5-JAFWpk7r17lgU91E X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-10-11_07,2022-10-11_02,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Sathesh Edara Set maximum frame size on SDP NIX side to 16KB for T93 A0-B0, F95N A0 and F95O A0 SOC type. Rest of the SoCs SDP NIX to 64KB. Signed-off-by: Sathesh Edara --- drivers/common/cnxk/hw/nix.h | 1 + drivers/common/cnxk/roc_errata.h | 8 ++++++++ drivers/common/cnxk/roc_model.h | 12 ++++++++++++ drivers/common/cnxk/roc_nix.c | 5 ++++- 4 files changed, 25 insertions(+), 1 deletion(-) diff --git a/drivers/common/cnxk/hw/nix.h b/drivers/common/cnxk/hw/nix.h index a5352644ca..425c335bf3 100644 --- a/drivers/common/cnxk/hw/nix.h +++ b/drivers/common/cnxk/hw/nix.h @@ -2118,6 +2118,7 @@ struct nix_lso_format { #define NIX_CN9K_MAX_HW_FRS 9212UL #define NIX_LBK_MAX_HW_FRS 65535UL #define NIX_SDP_MAX_HW_FRS 65535UL +#define NIX_SDP_16K_HW_FRS 16380UL #define NIX_RPM_MAX_HW_FRS 16380UL #define NIX_MIN_HW_FRS 60UL diff --git a/drivers/common/cnxk/roc_errata.h b/drivers/common/cnxk/roc_errata.h index d3b32f1786..a39796e894 100644 --- a/drivers/common/cnxk/roc_errata.h +++ b/drivers/common/cnxk/roc_errata.h @@ -90,4 +90,12 @@ roc_errata_nix_no_meta_aura(void) return roc_model_is_cn10ka_a0(); } +/* Errata IPBUNIXTX-35039 */ +static inline bool +roc_errata_nix_sdp_send_has_mtu_size_16k(void) +{ + return (roc_model_is_cnf95xxn_a0() || roc_model_is_cnf95xxo_a0() || + roc_model_is_cn96_a0() || roc_model_is_cn96_b0()); +} + #endif /* _ROC_ERRATA_H_ */ diff --git a/drivers/common/cnxk/roc_model.h b/drivers/common/cnxk/roc_model.h index 57a8af06fc..1985dd771d 100644 --- a/drivers/common/cnxk/roc_model.h +++ b/drivers/common/cnxk/roc_model.h @@ -140,6 +140,12 @@ roc_model_is_cn96_ax(void) return (roc_model->flag & ROC_MODEL_CN96xx_Ax); } +static inline uint64_t +roc_model_is_cn96_b0(void) +{ + return (roc_model->flag & ROC_MODEL_CN96xx_B0); +} + static inline uint64_t roc_model_is_cn96_cx(void) { @@ -170,6 +176,12 @@ roc_model_is_cnf95xxn_b0(void) return roc_model->flag & ROC_MODEL_CNF95xxN_B0; } +static inline uint64_t +roc_model_is_cnf95xxo_a0(void) +{ + return roc_model->flag & ROC_MODEL_CNF95xxO_A0; +} + static inline uint16_t roc_model_is_cn95xxn_a0(void) { diff --git a/drivers/common/cnxk/roc_nix.c b/drivers/common/cnxk/roc_nix.c index 4bb306b60e..8fd8ec8461 100644 --- a/drivers/common/cnxk/roc_nix.c +++ b/drivers/common/cnxk/roc_nix.c @@ -127,8 +127,11 @@ roc_nix_max_pkt_len(struct roc_nix *roc_nix) { struct nix *nix = roc_nix_to_nix_priv(roc_nix); - if (roc_nix_is_sdp(roc_nix)) + if (roc_nix_is_sdp(roc_nix)) { + if (roc_errata_nix_sdp_send_has_mtu_size_16k()) + return NIX_SDP_16K_HW_FRS; return NIX_SDP_MAX_HW_FRS; + } if (roc_model_is_cn9k()) return NIX_CN9K_MAX_HW_FRS; From patchwork Tue Oct 11 12:01:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 117921 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9E6AEA0545; Tue, 11 Oct 2022 14:03:55 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 7248842CCB; Tue, 11 Oct 2022 14:03:55 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id C5F0E42B7D for ; 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Tue, 11 Oct 2022 05:01:45 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 11 Oct 2022 05:01:43 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 11 Oct 2022 05:01:43 -0700 Received: from localhost.localdomain (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 5B2343F705A; Tue, 11 Oct 2022 05:01:41 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao , Ray Kinsella CC: , Subject: [PATCH 02/13] common/cnxk: add devargs for soft expiry poll frequency Date: Tue, 11 Oct 2022 17:31:24 +0530 Message-ID: <20221011120135.45846-2-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221011120135.45846-1-ndabilpuram@marvell.com> References: <20221011120135.45846-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: RLcJsHeRVAXpqEmgOG9BdVQp7TWhM3xb X-Proofpoint-GUID: RLcJsHeRVAXpqEmgOG9BdVQp7TWhM3xb X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-10-11_07,2022-10-11_02,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add support to override soft expiry poll frequency via devargs. Also provide helper API to indicate reassembly support on a chip and documentation for devargs that are already present. Signed-off-by: Nithin Dabilpuram --- doc/guides/nics/cnxk.rst | 39 +++++++++++++++++++++++++++ drivers/common/cnxk/roc_nix_inl.c | 7 +++++ drivers/common/cnxk/roc_nix_inl.h | 3 ++- drivers/common/cnxk/roc_nix_inl_dev.c | 4 +-- drivers/common/cnxk/version.map | 1 + drivers/net/cnxk/cnxk_ethdev_sec.c | 17 +++++++++--- 6 files changed, 65 insertions(+), 6 deletions(-) diff --git a/doc/guides/nics/cnxk.rst b/doc/guides/nics/cnxk.rst index a1e3a4a965..7da6cb3967 100644 --- a/doc/guides/nics/cnxk.rst +++ b/doc/guides/nics/cnxk.rst @@ -494,6 +494,45 @@ Runtime Config Options for inline device With the above configuration, application can enable inline IPsec processing for inbound SA with max SPI of 128 for traffic aggregated on inline device. +- ``Count of meta buffers for inline inbound IPsec second pass`` + + Number of meta buffers allocated for inline inbound IPsec second pass can + be specified by ``nb_meta_bufs`` ``devargs`` parameter. Default value is + computed runtime based on pkt mbuf pools created and in use. Number of meta + buffers should be at least equal to aggregated number of packet buffers of all + packet mbuf pools in use by Inline IPsec enabled ethernet devices. + + For example:: + + -a 0002:1d:00.0,nb_meta_bufs=1024 + + With the above configuration, PMD would enable inline IPsec processing + for inbound with 1024 meta buffers available for second pass. + +- ``Meta buffer size for inline inbound IPsec second pass`` + + Size of meta buffer allocated for inline inbound IPsec second pass can + be specified by ``meta_buf_sz`` ``devargs`` parameter. Default value is + computed runtime based on pkt mbuf pools created and in use. + + For example:: + + -a 0002:1d:00.0,meta_buf_sz=512 + + With the above configuration, PMD would allocate meta buffers of size 512 for + inline inbound IPsec processing second pass. + +- ``Inline Outbound soft expiry poll frequency in usec`` (default ``100``) + + Soft expiry poll frequency for Inline Outbound sessions can be specified by + ``soft_exp_poll_freq`` ``devargs`` parameter. + + For example:: + + -a 0002:1d:00.0,soft_exp_poll_freq=1000 + + With the above configuration, driver would poll for soft expiry events every + 1000 usec. Debugging Options ----------------- diff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c index cdf31b1f0c..213d71e684 100644 --- a/drivers/common/cnxk/roc_nix_inl.c +++ b/drivers/common/cnxk/roc_nix_inl.c @@ -480,6 +480,13 @@ nix_inl_rq_mask_cfg(struct roc_nix *roc_nix, bool enable) return mbox_process(mbox); } +bool +roc_nix_has_reass_support(struct roc_nix *nix) +{ + PLT_SET_USED(nix); + return !!roc_model_is_cn10ka(); +} + int roc_nix_inl_inb_init(struct roc_nix *roc_nix) { diff --git a/drivers/common/cnxk/roc_nix_inl.h b/drivers/common/cnxk/roc_nix_inl.h index 019cf6d28b..c537262819 100644 --- a/drivers/common/cnxk/roc_nix_inl.h +++ b/drivers/common/cnxk/roc_nix_inl.h @@ -183,7 +183,7 @@ struct roc_nix_inl_dev { uint16_t wqe_skip; uint8_t spb_drop_pc; uint8_t lpb_drop_pc; - bool set_soft_exp_poll; + uint32_t soft_exp_poll_freq; /* Polling disabled if 0 */ uint32_t nb_meta_bufs; uint32_t meta_buf_sz; /* End of input parameters */ @@ -229,6 +229,7 @@ int __roc_api roc_nix_inl_ts_pkind_set(struct roc_nix *roc_nix, bool ts_ena, bool inb_inl_dev); int __roc_api roc_nix_inl_rq_ena_dis(struct roc_nix *roc_nix, bool ena); int __roc_api roc_nix_inl_meta_aura_check(struct roc_nix_rq *rq); +bool __roc_api roc_nix_has_reass_support(struct roc_nix *nix); /* NIX Inline Outbound API */ int __roc_api roc_nix_inl_outb_init(struct roc_nix *roc_nix); diff --git a/drivers/common/cnxk/roc_nix_inl_dev.c b/drivers/common/cnxk/roc_nix_inl_dev.c index 4fe7b5180b..c3d94dd0da 100644 --- a/drivers/common/cnxk/roc_nix_inl_dev.c +++ b/drivers/common/cnxk/roc_nix_inl_dev.c @@ -789,7 +789,6 @@ nix_inl_outb_poll_thread_setup(struct nix_inl_dev *inl_dev) soft_exp_consumer_cnt = 0; soft_exp_poll_thread_exit = false; - inl_dev->soft_exp_poll_freq = 100; rc = plt_ctrl_thread_create(&inl_dev->soft_exp_poll_thread, "OUTB_SOFT_EXP_POLL_THREAD", NULL, nix_inl_outb_poll_thread, inl_dev); @@ -839,10 +838,11 @@ roc_nix_inl_dev_init(struct roc_nix_inl_dev *roc_inl_dev) inl_dev->wqe_skip = roc_inl_dev->wqe_skip; inl_dev->spb_drop_pc = NIX_AURA_DROP_PC_DFLT; inl_dev->lpb_drop_pc = NIX_AURA_DROP_PC_DFLT; - inl_dev->set_soft_exp_poll = roc_inl_dev->set_soft_exp_poll; + inl_dev->set_soft_exp_poll = !!roc_inl_dev->soft_exp_poll_freq; inl_dev->nb_rqs = inl_dev->is_multi_channel ? 1 : PLT_MAX_ETHPORTS; inl_dev->nb_meta_bufs = roc_inl_dev->nb_meta_bufs; inl_dev->meta_buf_sz = roc_inl_dev->meta_buf_sz; + inl_dev->soft_exp_poll_freq = roc_inl_dev->soft_exp_poll_freq; if (roc_inl_dev->spb_drop_pc) inl_dev->spb_drop_pc = roc_inl_dev->spb_drop_pc; diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 276fec3660..f08b6076e4 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -135,6 +135,7 @@ INTERNAL { roc_nix_get_pf_func; roc_nix_get_vf; roc_nix_get_vwqe_interval; + roc_nix_has_reass_support; roc_nix_inl_cb_register; roc_nix_inl_cb_unregister; roc_nix_inl_ctx_write; diff --git a/drivers/net/cnxk/cnxk_ethdev_sec.c b/drivers/net/cnxk/cnxk_ethdev_sec.c index 9304b1465d..8bec9acb54 100644 --- a/drivers/net/cnxk/cnxk_ethdev_sec.c +++ b/drivers/net/cnxk/cnxk_ethdev_sec.c @@ -12,6 +12,10 @@ #define CNXK_INL_CPT_CHANNEL "inl_cpt_channel" #define CNXK_NIX_INL_NB_META_BUFS "nb_meta_bufs" #define CNXK_NIX_INL_META_BUF_SZ "meta_buf_sz" +#define CNXK_NIX_SOFT_EXP_POLL_FREQ "soft_exp_poll_freq" + +/* Default soft expiry poll freq in usec */ +#define CNXK_NIX_SOFT_EXP_POLL_FREQ_DFLT 100 struct inl_cpt_channel { bool is_multi_channel; @@ -263,6 +267,7 @@ static int nix_inl_parse_devargs(struct rte_devargs *devargs, struct roc_nix_inl_dev *inl_dev) { + uint32_t soft_exp_poll_freq = CNXK_NIX_SOFT_EXP_POLL_FREQ_DFLT; uint32_t ipsec_in_max_spi = BIT(8) - 1; uint32_t ipsec_in_min_spi = 0; struct inl_cpt_channel cpt_channel; @@ -292,6 +297,8 @@ nix_inl_parse_devargs(struct rte_devargs *devargs, &nb_meta_bufs); rte_kvargs_process(kvlist, CNXK_NIX_INL_META_BUF_SZ, &parse_val_u32, &meta_buf_sz); + rte_kvargs_process(kvlist, CNXK_NIX_SOFT_EXP_POLL_FREQ, + &parse_val_u32, &soft_exp_poll_freq); rte_kvargs_free(kvlist); null_devargs: @@ -303,6 +310,7 @@ nix_inl_parse_devargs(struct rte_devargs *devargs, inl_dev->is_multi_channel = cpt_channel.is_multi_channel; inl_dev->nb_meta_bufs = nb_meta_bufs; inl_dev->meta_buf_sz = meta_buf_sz; + inl_dev->soft_exp_poll_freq = soft_exp_poll_freq; return 0; exit: return -EINVAL; @@ -390,7 +398,6 @@ cnxk_nix_inl_dev_probe(struct rte_pci_driver *pci_drv, wqe_skip = RTE_ALIGN_CEIL(sizeof(struct rte_mbuf), ROC_CACHE_LINE_SZ); wqe_skip = wqe_skip / ROC_CACHE_LINE_SZ; inl_dev->wqe_skip = wqe_skip; - inl_dev->set_soft_exp_poll = true; rc = roc_nix_inl_dev_init(inl_dev); if (rc) { plt_err("Failed to init nix inl device, rc=%d(%s)", rc, @@ -425,5 +432,9 @@ RTE_PMD_REGISTER_KMOD_DEP(cnxk_nix_inl, "vfio-pci"); RTE_PMD_REGISTER_PARAM_STRING(cnxk_nix_inl, CNXK_NIX_INL_SELFTEST "=1" - CNXK_NIX_INL_IPSEC_IN_MAX_SPI "=<1-65535>" - CNXK_INL_CPT_CHANNEL "=<1-4095>/<1-4095>"); + CNXK_NIX_INL_IPSEC_IN_MIN_SPI "=<1-U32_MAX>" + CNXK_NIX_INL_IPSEC_IN_MAX_SPI "=<1-U32_MAX>" + CNXK_INL_CPT_CHANNEL "=<1-4095>/<1-4095>" + CNXK_NIX_INL_NB_META_BUFS "=<1-U32_MAX>" + CNXK_NIX_INL_META_BUF_SZ "=<1-U32_MAX>" + CNXK_NIX_SOFT_EXP_POLL_FREQ "=<0-U32_MAX>"); From patchwork Tue Oct 11 12:01:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 117910 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9A1DAA0545; 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Tue, 11 Oct 2022 05:01:48 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 11 Oct 2022 05:01:46 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 11 Oct 2022 05:01:46 -0700 Received: from localhost.localdomain (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 202813F7040; Tue, 11 Oct 2022 05:01:43 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , , Subject: [PATCH 03/13] net/cnxk: fix later skip to include mbuf priv Date: Tue, 11 Oct 2022 17:31:25 +0530 Message-ID: <20221011120135.45846-3-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221011120135.45846-1-ndabilpuram@marvell.com> References: <20221011120135.45846-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: FclyulrGNngZApqFW869Mt1X_G4fRPVO X-Proofpoint-GUID: FclyulrGNngZApqFW869Mt1X_G4fRPVO X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-10-11_07,2022-10-11_02,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Fix later skip to include mbuf priv data as mbuf->buf_addr is populated based on calculation including per-mbuf priv area. Fixes: 706eeae60757 ("net/cnxk: add multi-segment Rx for CN10K") cc: stable@dpdk.org Signed-off-by: Nithin Dabilpuram --- drivers/net/cnxk/cn10k_rx.h | 4 +++- drivers/net/cnxk/cnxk_ethdev.c | 2 +- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/net/cnxk/cn10k_rx.h b/drivers/net/cnxk/cn10k_rx.h index 46488d442e..cf390a0361 100644 --- a/drivers/net/cnxk/cn10k_rx.h +++ b/drivers/net/cnxk/cn10k_rx.h @@ -682,6 +682,7 @@ nix_cqe_xtract_mseg(const union nix_rx_parse_u *rx, struct rte_mbuf *mbuf, uint64_t rearm, const uint16_t flags) { const rte_iova_t *iova_list; + uint16_t later_skip = 0; struct rte_mbuf *head; const rte_iova_t *eol; uint8_t nb_segs; @@ -720,10 +721,11 @@ nix_cqe_xtract_mseg(const union nix_rx_parse_u *rx, struct rte_mbuf *mbuf, nb_segs--; rearm = rearm & ~0xFFFF; + later_skip = (uintptr_t)mbuf->buf_addr - (uintptr_t)mbuf; head = mbuf; while (nb_segs) { - mbuf->next = ((struct rte_mbuf *)*iova_list) - 1; + mbuf->next = (struct rte_mbuf *)(*iova_list - later_skip); mbuf = mbuf->next; RTE_MEMPOOL_CHECK_COOKIES(mbuf->pool, (void **)&mbuf, 1, 1); diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c index 2cb48ba152..8fe996b2d9 100644 --- a/drivers/net/cnxk/cnxk_ethdev.c +++ b/drivers/net/cnxk/cnxk_ethdev.c @@ -620,7 +620,7 @@ cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid, first_skip += RTE_PKTMBUF_HEADROOM; first_skip += rte_pktmbuf_priv_size(mp); rq->first_skip = first_skip; - rq->later_skip = sizeof(struct rte_mbuf); + rq->later_skip = sizeof(struct rte_mbuf) + rte_pktmbuf_priv_size(mp); rq->lpb_size = mp->elt_size; if (roc_errata_nix_no_meta_aura()) rq->lpb_drop_ena = !(dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY); From patchwork Tue Oct 11 12:01:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 117911 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C9BE8A0545; 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Tue, 11 Oct 2022 05:01:51 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 11 Oct 2022 05:01:49 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 11 Oct 2022 05:01:49 -0700 Received: from localhost.localdomain (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id E62053F7055; Tue, 11 Oct 2022 05:01:46 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao , Pavan Nikhilesh , "Shijith Thotton" CC: , Subject: [PATCH 04/13] net/cnxk: add use nixtx offset for cn10kb Date: Tue, 11 Oct 2022 17:31:26 +0530 Message-ID: <20221011120135.45846-4-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221011120135.45846-1-ndabilpuram@marvell.com> References: <20221011120135.45846-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: gEnqNqbjHf1RfwlUSiRIn8NYqueE_XFJ X-Proofpoint-GUID: gEnqNqbjHf1RfwlUSiRIn8NYqueE_XFJ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-10-11_07,2022-10-11_02,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org In outbound inline case, use NIX Tx offset instead of NIX Tx address for CN103XX as per new instruction format. Signed-off-by: Nithin Dabilpuram --- drivers/common/cnxk/roc_constants.h | 1 + drivers/event/cnxk/cn10k_worker.h | 3 +++ drivers/net/cnxk/cn10k_ethdev.c | 6 ++++++ drivers/net/cnxk/cn10k_ethdev.h | 3 ++- drivers/net/cnxk/cn10k_ethdev_sec.c | 2 ++ drivers/net/cnxk/cn10k_tx.h | 4 ++-- 6 files changed, 16 insertions(+), 3 deletions(-) diff --git a/drivers/common/cnxk/roc_constants.h b/drivers/common/cnxk/roc_constants.h index c693dde62e..0495965daa 100644 --- a/drivers/common/cnxk/roc_constants.h +++ b/drivers/common/cnxk/roc_constants.h @@ -12,6 +12,7 @@ /* [CN10K, .) */ #define ROC_LMT_LINE_SZ 128 #define ROC_NUM_LMT_LINES 2048 +#define ROC_LMT_LINES_PER_STR_LOG2 4 #define ROC_LMT_LINES_PER_CORE_LOG2 5 #define ROC_LMT_LINE_SIZE_LOG2 7 #define ROC_LMT_BASE_PER_CORE_LOG2 \ diff --git a/drivers/event/cnxk/cn10k_worker.h b/drivers/event/cnxk/cn10k_worker.h index 7a82dd352a..75a2ff244a 100644 --- a/drivers/event/cnxk/cn10k_worker.h +++ b/drivers/event/cnxk/cn10k_worker.h @@ -595,6 +595,9 @@ cn10k_sso_tx_one(struct cn10k_sso_hws *ws, struct rte_mbuf *m, uint64_t *cmd, ws->gw_rdata = roc_sso_hws_head_wait(ws->base); cn10k_sso_txq_fc_wait(txq); + if (flags & NIX_TX_OFFLOAD_SECURITY_F && sec) + cn10k_nix_sec_fc_wait_one(txq); + roc_lmt_submit_steorl(lmt_id, pa); if (flags & NIX_TX_OFFLOAD_MBUF_NOFF_F) { diff --git a/drivers/net/cnxk/cn10k_ethdev.c b/drivers/net/cnxk/cn10k_ethdev.c index e8faeebe1f..cf1d9b164d 100644 --- a/drivers/net/cnxk/cn10k_ethdev.c +++ b/drivers/net/cnxk/cn10k_ethdev.c @@ -538,6 +538,9 @@ cn10k_nix_reassembly_capability_get(struct rte_eth_dev *eth_dev, int rc = -ENOTSUP; RTE_SET_USED(eth_dev); + if (!roc_nix_has_reass_support(&dev->nix)) + return -ENOTSUP; + if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY) { reassembly_capa->timeout_ms = 60 * 1000; reassembly_capa->max_frags = 4; @@ -565,6 +568,9 @@ cn10k_nix_reassembly_conf_set(struct rte_eth_dev *eth_dev, struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); int rc = 0; + if (!roc_nix_has_reass_support(&dev->nix)) + return -ENOTSUP; + if (!conf->flags) { /* Clear offload flags on disable */ dev->rx_offload_flags &= ~NIX_RX_REAS_F; diff --git a/drivers/net/cnxk/cn10k_ethdev.h b/drivers/net/cnxk/cn10k_ethdev.h index d0a5b136e3..948c8348ad 100644 --- a/drivers/net/cnxk/cn10k_ethdev.h +++ b/drivers/net/cnxk/cn10k_ethdev.h @@ -75,7 +75,8 @@ struct cn10k_sec_sess_priv { uint16_t partial_len : 10; uint16_t chksum : 2; uint16_t dec_ttl : 1; - uint16_t rsvd : 3; + uint16_t nixtx_off : 1; + uint16_t rsvd : 2; }; uint64_t u64; diff --git a/drivers/net/cnxk/cn10k_ethdev_sec.c b/drivers/net/cnxk/cn10k_ethdev_sec.c index 6de4a284da..3ca707f038 100644 --- a/drivers/net/cnxk/cn10k_ethdev_sec.c +++ b/drivers/net/cnxk/cn10k_ethdev_sec.c @@ -798,6 +798,8 @@ cn10k_eth_sec_session_create(void *device, sess_priv.chksum = (!ipsec->options.ip_csum_enable << 1 | !ipsec->options.l4_csum_enable); sess_priv.dec_ttl = ipsec->options.dec_ttl; + if (roc_model_is_cn10kb_a0()) + sess_priv.nixtx_off = 1; /* Pointer from eth_sec -> outb_sa */ eth_sec->sa = outb_sa; diff --git a/drivers/net/cnxk/cn10k_tx.h b/drivers/net/cnxk/cn10k_tx.h index 492942de15..527b65022f 100644 --- a/drivers/net/cnxk/cn10k_tx.h +++ b/drivers/net/cnxk/cn10k_tx.h @@ -397,7 +397,7 @@ cn10k_nix_prep_sec_vec(struct rte_mbuf *m, uint64x2_t *cmd0, uint64x2_t *cmd1, /* DLEN passed is excluding L2 HDR */ pkt_len -= l2_len; } - w0 |= nixtx; + w0 |= sess_priv.nixtx_off ? ((((int64_t)nixtx - (int64_t)dptr) & 0xFFFFF) << 32) : nixtx; /* CPT word 0 and 1 */ cmd01 = vdupq_n_u64(0); cmd01 = vsetq_lane_u64(w0, cmd01, 0); @@ -539,7 +539,7 @@ cn10k_nix_prep_sec(struct rte_mbuf *m, uint64_t *cmd, uintptr_t *nixtx_addr, sg->seg1_size = pkt_len + dlen_adj; pkt_len -= l2_len; } - w0 |= nixtx; + w0 |= sess_priv.nixtx_off ? ((((int64_t)nixtx - (int64_t)dptr) & 0xFFFFF) << 32) : nixtx; /* CPT word 0 and 1 */ cmd01 = vdupq_n_u64(0); cmd01 = vsetq_lane_u64(w0, cmd01, 0); From patchwork Tue Oct 11 12:01:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 117912 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 43FEAA0545; Tue, 11 Oct 2022 14:02:08 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 92EA142DC6; Tue, 11 Oct 2022 14:01:56 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id CC1A142DC0 for ; Tue, 11 Oct 2022 14:01:54 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 29B8OQA3030232 for ; Tue, 11 Oct 2022 05:01:54 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=Zsc24S5RVFmtiGdiLW0SE77B+10vXl3e7NZnG11bTV0=; b=C7j26cipjog7qIEi/y31RKa72Dq7nwCZ7yGmEz12bmcQi5wFNtCqENM4x+yJdQtPkD4E VCOOx/A4cG5x0I3DaTvpBicFmBZfD0e5XQKmsAsg5OfOE5my3jJ30IWhdiMhTC8moRXx uLqOU0wB13regr1bLrHLsFc6+EwwMk+2Gl/wXsZxZmjUKmDf7tFSBMDg/I75DVLXTTVg DpNpJdADs+i35m9vKi+iNG/7XO0NiYpoEd4MACU8BmfD+4Io5lJYclKHXCzbFSZq3uOX /0v54rLXdhq9u5ghHBL4U2zgx6K7BWkCU/GIa1B5nu7WY1flKUWmRbraL8oYHPZAFCFi Qw== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3k54xugq6f-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 11 Oct 2022 05:01:53 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 11 Oct 2022 05:01:51 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Tue, 11 Oct 2022 05:01:51 -0700 Received: from localhost.localdomain (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id E5C423F7040; Tue, 11 Oct 2022 05:01:49 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Subject: [PATCH 05/13] common/cnxk: fix RQ mask config for cn10kb chip Date: Tue, 11 Oct 2022 17:31:27 +0530 Message-ID: <20221011120135.45846-5-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221011120135.45846-1-ndabilpuram@marvell.com> References: <20221011120135.45846-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: bDaevpgWDF9ZPDhjUFdT2b9kMSwkI945 X-Proofpoint-ORIG-GUID: bDaevpgWDF9ZPDhjUFdT2b9kMSwkI945 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-10-11_07,2022-10-11_02,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org RQ mask config needs to enable SPB_ENA in order for Zero for being able to override it with Meta aura. Also fix flow control config to catch invalid rxchan config errors. Fixes: ddf955d3917e ("common/cnxk: support CPT second pass") Fixes: da57d4589a6f ("common/cnxk: support NIX flow control") Signed-off-by: Nithin Dabilpuram --- drivers/common/cnxk/roc_nix_fc.c | 4 ++- drivers/common/cnxk/roc_nix_inl.c | 43 +++++++++++++++++-------------- 2 files changed, 26 insertions(+), 21 deletions(-) diff --git a/drivers/common/cnxk/roc_nix_fc.c b/drivers/common/cnxk/roc_nix_fc.c index f4cfa11c0f..033e17a4bf 100644 --- a/drivers/common/cnxk/roc_nix_fc.c +++ b/drivers/common/cnxk/roc_nix_fc.c @@ -52,8 +52,10 @@ nix_fc_rxchan_bpid_set(struct roc_nix *roc_nix, bool enable) req->bpid_per_chan = true; rc = mbox_process_msg(mbox, (void *)&rsp); - if (rc || (req->chan_cnt != rsp->chan_cnt)) + if (rc || (req->chan_cnt != rsp->chan_cnt)) { + rc = -EIO; goto exit; + } nix->chan_cnt = rsp->chan_cnt; for (i = 0; i < rsp->chan_cnt; i++) diff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c index 213d71e684..0da097c9e9 100644 --- a/drivers/common/cnxk/roc_nix_inl.c +++ b/drivers/common/cnxk/roc_nix_inl.c @@ -454,27 +454,29 @@ nix_inl_rq_mask_cfg(struct roc_nix *roc_nix, bool enable) msk_req->rq_set.lpb_drop_ena = 0; msk_req->rq_set.spb_drop_ena = 0; msk_req->rq_set.xqe_drop_ena = 0; + msk_req->rq_set.spb_ena = 1; - msk_req->rq_mask.len_ol3_dis = ~(msk_req->rq_set.len_ol3_dis); - msk_req->rq_mask.len_ol4_dis = ~(msk_req->rq_set.len_ol4_dis); - msk_req->rq_mask.len_il3_dis = ~(msk_req->rq_set.len_il3_dis); + msk_req->rq_mask.len_ol3_dis = 0; + msk_req->rq_mask.len_ol4_dis = 0; + msk_req->rq_mask.len_il3_dis = 0; - msk_req->rq_mask.len_il4_dis = ~(msk_req->rq_set.len_il4_dis); - msk_req->rq_mask.csum_ol4_dis = ~(msk_req->rq_set.csum_ol4_dis); - msk_req->rq_mask.csum_il4_dis = ~(msk_req->rq_set.csum_il4_dis); + msk_req->rq_mask.len_il4_dis = 0; + msk_req->rq_mask.csum_ol4_dis = 0; + msk_req->rq_mask.csum_il4_dis = 0; - msk_req->rq_mask.lenerr_dis = ~(msk_req->rq_set.lenerr_dis); - msk_req->rq_mask.port_ol4_dis = ~(msk_req->rq_set.port_ol4_dis); - msk_req->rq_mask.port_il4_dis = ~(msk_req->rq_set.port_il4_dis); + msk_req->rq_mask.lenerr_dis = 0; + msk_req->rq_mask.port_ol4_dis = 0; + msk_req->rq_mask.port_il4_dis = 0; - msk_req->rq_mask.lpb_drop_ena = ~(msk_req->rq_set.lpb_drop_ena); - msk_req->rq_mask.spb_drop_ena = ~(msk_req->rq_set.spb_drop_ena); - msk_req->rq_mask.xqe_drop_ena = ~(msk_req->rq_set.xqe_drop_ena); + msk_req->rq_mask.lpb_drop_ena = 0; + msk_req->rq_mask.spb_drop_ena = 0; + msk_req->rq_mask.xqe_drop_ena = 0; + msk_req->rq_mask.spb_ena = 0; aura_handle = roc_npa_zero_aura_handle(); msk_req->ipsec_cfg1.spb_cpt_aura = roc_npa_aura_handle_to_aura(aura_handle); msk_req->ipsec_cfg1.rq_mask_enable = enable; - msk_req->ipsec_cfg1.spb_cpt_sizem1 = inl_cfg->buf_sz; + msk_req->ipsec_cfg1.spb_cpt_sizem1 = (inl_cfg->buf_sz >> 7) - 1; msk_req->ipsec_cfg1.spb_cpt_enable = enable; return mbox_process(mbox); @@ -544,13 +546,6 @@ roc_nix_inl_inb_init(struct roc_nix *roc_nix) idev->inl_cfg.refs++; } - if (roc_model_is_cn10kb_a0()) { - rc = nix_inl_rq_mask_cfg(roc_nix, true); - if (rc) { - plt_err("Failed to get rq mask rc=%d", rc); - return rc; - } - } nix->inl_inb_ena = true; return 0; } @@ -1043,6 +1038,14 @@ roc_nix_inl_rq_ena_dis(struct roc_nix *roc_nix, bool enable) if (!idev) return -EFAULT; + if (roc_model_is_cn10kb_a0()) { + rc = nix_inl_rq_mask_cfg(roc_nix, true); + if (rc) { + plt_err("Failed to get rq mask rc=%d", rc); + return rc; + } + } + if (nix->inb_inl_dev) { if (!inl_rq || !idev->nix_inl_dev) return -EFAULT; From patchwork Tue Oct 11 12:01:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 117913 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2A8EDA0545; Tue, 11 Oct 2022 14:02:17 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D55D342DD2; Tue, 11 Oct 2022 14:01:58 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 3AA5242DC9 for ; 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Tue, 11 Oct 2022 05:01:56 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 11 Oct 2022 05:01:54 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 11 Oct 2022 05:01:54 -0700 Received: from localhost.localdomain (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 728D43F7050; Tue, 11 Oct 2022 05:01:52 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Subject: [PATCH 06/13] common/cnxk: fix schedule weight update Date: Tue, 11 Oct 2022 17:31:28 +0530 Message-ID: <20221011120135.45846-6-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221011120135.45846-1-ndabilpuram@marvell.com> References: <20221011120135.45846-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: RloxdkB4qkdn4alNbf1OKyQbrEhqMFG2 X-Proofpoint-GUID: RloxdkB4qkdn4alNbf1OKyQbrEhqMFG2 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-10-11_07,2022-10-11_02,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Satha Rao Each TX schedule config mail box supports maximum 20 register updates. This patch will send node weight updates in multiple mailbox when TM created with more than 20 scheduler nodes. Fixes: 464c9f919321 ("common/cnxk: support NIX TM dynamic update") Cc: ndabilpuram@marvell.com Signed-off-by: Satha Rao --- drivers/common/cnxk/roc_nix_queue.c | 2 +- drivers/common/cnxk/roc_nix_tm_ops.c | 60 ++++++++++++++++++---------- 2 files changed, 41 insertions(+), 21 deletions(-) diff --git a/drivers/common/cnxk/roc_nix_queue.c b/drivers/common/cnxk/roc_nix_queue.c index 405d9a8274..7f001efbb0 100644 --- a/drivers/common/cnxk/roc_nix_queue.c +++ b/drivers/common/cnxk/roc_nix_queue.c @@ -810,7 +810,7 @@ sqb_pool_populate(struct roc_nix *roc_nix, struct roc_nix_sq *sq) nb_sqb_bufs += NIX_SQB_LIST_SPACE; /* Clamp up the SQB count */ nb_sqb_bufs = PLT_MIN(roc_nix->max_sqb_count, - PLT_MAX(NIX_DEF_SQB, nb_sqb_bufs)); + (uint16_t)PLT_MAX(NIX_DEF_SQB, nb_sqb_bufs)); sq->nb_sqb_bufs = nb_sqb_bufs; sq->sqes_per_sqb_log2 = (uint16_t)plt_log2_u32(sqes_per_sqb); diff --git a/drivers/common/cnxk/roc_nix_tm_ops.c b/drivers/common/cnxk/roc_nix_tm_ops.c index 7036495ad8..4bf7b1e104 100644 --- a/drivers/common/cnxk/roc_nix_tm_ops.c +++ b/drivers/common/cnxk/roc_nix_tm_ops.c @@ -891,19 +891,29 @@ roc_nix_tm_node_parent_update(struct roc_nix *roc_nix, uint32_t node_id, TAILQ_FOREACH(sibling, list, node) { if (sibling->parent != node->parent) continue; - k += nix_tm_sw_xoff_prep(sibling, true, &req->reg[k], - &req->regval[k]); + k += nix_tm_sw_xoff_prep(sibling, true, &req->reg[k], &req->regval[k]); + if (k >= MAX_REGS_PER_MBOX_MSG) { + req->num_regs = k; + rc = mbox_process(mbox); + if (rc) + return rc; + k = 0; + req = mbox_alloc_msg_nix_txschq_cfg(mbox); + req->lvl = node->hw_lvl; + } + } + + if (k) { + req->num_regs = k; + rc = mbox_process(mbox); + if (rc) + return rc; + /* Update new weight for current node */ + req = mbox_alloc_msg_nix_txschq_cfg(mbox); } - req->num_regs = k; - rc = mbox_process(mbox); - if (rc) - return rc; - /* Update new weight for current node */ - req = mbox_alloc_msg_nix_txschq_cfg(mbox); req->lvl = node->hw_lvl; - req->num_regs = - nix_tm_sched_reg_prep(nix, node, req->reg, req->regval); + req->num_regs = nix_tm_sched_reg_prep(nix, node, req->reg, req->regval); rc = mbox_process(mbox); if (rc) return rc; @@ -916,19 +926,29 @@ roc_nix_tm_node_parent_update(struct roc_nix *roc_nix, uint32_t node_id, TAILQ_FOREACH(sibling, list, node) { if (sibling->parent != node->parent) continue; - k += nix_tm_sw_xoff_prep(sibling, false, &req->reg[k], - &req->regval[k]); + k += nix_tm_sw_xoff_prep(sibling, false, &req->reg[k], &req->regval[k]); + if (k >= MAX_REGS_PER_MBOX_MSG) { + req->num_regs = k; + rc = mbox_process(mbox); + if (rc) + return rc; + k = 0; + req = mbox_alloc_msg_nix_txschq_cfg(mbox); + req->lvl = node->hw_lvl; + } + } + + if (k) { + req->num_regs = k; + rc = mbox_process(mbox); + if (rc) + return rc; + /* XON Parent node */ + req = mbox_alloc_msg_nix_txschq_cfg(mbox); } - req->num_regs = k; - rc = mbox_process(mbox); - if (rc) - return rc; - /* XON Parent node */ - req = mbox_alloc_msg_nix_txschq_cfg(mbox); req->lvl = node->parent->hw_lvl; - req->num_regs = nix_tm_sw_xoff_prep(node->parent, false, - req->reg, req->regval); + req->num_regs = nix_tm_sw_xoff_prep(node->parent, false, req->reg, req->regval); rc = mbox_process(mbox); if (rc) return rc; From patchwork Tue Oct 11 12:01:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 117914 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 19AE3A0545; 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Tue, 11 Oct 2022 05:01:59 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 11 Oct 2022 05:01:57 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Tue, 11 Oct 2022 05:01:57 -0700 Received: from localhost.localdomain (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 043AB3F705A; Tue, 11 Oct 2022 05:01:54 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Subject: [PATCH 07/13] common/cnxk: sync NIX HW info mbox structure with kernel Date: Tue, 11 Oct 2022 17:31:29 +0530 Message-ID: <20221011120135.45846-7-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221011120135.45846-1-ndabilpuram@marvell.com> References: <20221011120135.45846-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: GM2YjiS-U_cmXRjyA_eHh3tPwCs9FikU X-Proofpoint-GUID: GM2YjiS-U_cmXRjyA_eHh3tPwCs9FikU X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-10-11_07,2022-10-11_02,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Satha Rao Sync nix_hw_info structure with kernel. Maintain default RR_QUANTUM for VF TL2 same as kernel to make equal distribution among all VFs. Signed-off-by: Satha Rao --- drivers/common/cnxk/roc_mbox.h | 8 +++++- drivers/common/cnxk/roc_nix.c | 9 ++++++- drivers/common/cnxk/roc_nix.h | 1 + drivers/common/cnxk/roc_nix_tm.c | 10 ++++---- drivers/common/cnxk/roc_nix_tm_utils.c | 34 +++++++++++++++++++++----- 5 files changed, 49 insertions(+), 13 deletions(-) diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h index a47e6a8f3b..e8d4ae283d 100644 --- a/drivers/common/cnxk/roc_mbox.h +++ b/drivers/common/cnxk/roc_mbox.h @@ -1215,7 +1215,13 @@ struct nix_inline_ipsec_lf_cfg { struct nix_hw_info { struct mbox_msghdr hdr; uint16_t __io vwqe_delay; - uint16_t __io rsvd[15]; + uint16_t __io max_mtu; + uint16_t __io min_mtu; + uint32_t __io rpm_dwrr_mtu; + uint32_t __io sdp_dwrr_mtu; + uint32_t __io lbk_dwrr_mtu; + uint32_t __io rsvd32[1]; + uint64_t __io rsvd[15]; /* Add reserved fields for future expansion */ }; struct nix_bandprof_alloc_req { diff --git a/drivers/common/cnxk/roc_nix.c b/drivers/common/cnxk/roc_nix.c index 8fd8ec8461..2a320cc291 100644 --- a/drivers/common/cnxk/roc_nix.c +++ b/drivers/common/cnxk/roc_nix.c @@ -303,8 +303,15 @@ roc_nix_get_hw_info(struct roc_nix *roc_nix) mbox_alloc_msg_nix_get_hw_info(mbox); rc = mbox_process_msg(mbox, (void *)&hw_info); - if (rc == 0) + if (rc == 0) { nix->vwqe_interval = hw_info->vwqe_delay; + if (nix->lbk_link) + roc_nix->dwrr_mtu = hw_info->lbk_dwrr_mtu; + else if (nix->sdp_link) + roc_nix->dwrr_mtu = hw_info->sdp_dwrr_mtu; + else + roc_nix->dwrr_mtu = hw_info->rpm_dwrr_mtu; + } return rc; } diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h index 5c2a869eba..1eb1c9af55 100644 --- a/drivers/common/cnxk/roc_nix.h +++ b/drivers/common/cnxk/roc_nix.h @@ -422,6 +422,7 @@ struct roc_nix { uint32_t ipsec_in_min_spi; uint32_t ipsec_in_max_spi; uint32_t ipsec_out_max_sa; + uint32_t dwrr_mtu; bool ipsec_out_sso_pffunc; bool custom_sa_action; /* End of input parameters */ diff --git a/drivers/common/cnxk/roc_nix_tm.c b/drivers/common/cnxk/roc_nix_tm.c index 81fa6b1d93..86918990a2 100644 --- a/drivers/common/cnxk/roc_nix_tm.c +++ b/drivers/common/cnxk/roc_nix_tm.c @@ -256,10 +256,6 @@ nix_tm_node_add(struct roc_nix *roc_nix, struct nix_tm_node *node) if (node->weight > roc_nix_tm_max_sched_wt_get()) return NIX_ERR_TM_WEIGHT_EXCEED; - /* Maintain minimum weight */ - if (!node->weight) - node->weight = 1; - node->hw_lvl = nix_tm_lvl2nix(nix, lvl); node->rr_prio = 0xF; node->max_prio = UINT32_MAX; @@ -1358,7 +1354,11 @@ nix_tm_prepare_default_tree(struct roc_nix *roc_nix) node->id = nonleaf_id; node->parent_id = parent; node->priority = 0; - node->weight = NIX_TM_DFLT_RR_WT; + /* Default VF root RR_QUANTUM is in sync with kernel */ + if (lvl == ROC_TM_LVL_ROOT && !nix_tm_have_tl1_access(nix)) + node->weight = 0; + else + node->weight = NIX_TM_DFLT_RR_WT; node->shaper_profile_id = ROC_NIX_TM_SHAPER_PROFILE_NONE; node->lvl = lvl; node->tree = ROC_NIX_TM_DEFAULT; diff --git a/drivers/common/cnxk/roc_nix_tm_utils.c b/drivers/common/cnxk/roc_nix_tm_utils.c index 193f9df5ff..d33e793664 100644 --- a/drivers/common/cnxk/roc_nix_tm_utils.c +++ b/drivers/common/cnxk/roc_nix_tm_utils.c @@ -644,9 +644,25 @@ nix_tm_topology_reg_prep(struct nix *nix, struct nix_tm_node *node, return k; } +static inline int +nix_tm_default_rr_weight(struct nix *nix) +{ + struct roc_nix *roc_nix = nix_priv_to_roc_nix(nix); + uint32_t max_pktlen = roc_nix_max_pkt_len(roc_nix); + uint32_t weight; + + /* Reduce TX VTAG Insertions */ + max_pktlen -= 8; + weight = max_pktlen / roc_nix->dwrr_mtu; + if (max_pktlen % roc_nix->dwrr_mtu) + weight += 1; + + return weight; +} + uint8_t -nix_tm_sched_reg_prep(struct nix *nix, struct nix_tm_node *node, - volatile uint64_t *reg, volatile uint64_t *regval) +nix_tm_sched_reg_prep(struct nix *nix, struct nix_tm_node *node, volatile uint64_t *reg, + volatile uint64_t *regval) { uint64_t strict_prio = node->priority; uint32_t hw_lvl = node->hw_lvl; @@ -654,8 +670,14 @@ nix_tm_sched_reg_prep(struct nix *nix, struct nix_tm_node *node, uint64_t rr_quantum; uint8_t k = 0; - /* For CN9K, weight needs to be converted to quantum */ - rr_quantum = nix_tm_weight_to_rr_quantum(node->weight); + /* If minimum weight not provided, then by default RR_QUANTUM + * should be in sync with kernel, i.e., single MTU value + */ + if (!node->weight) + rr_quantum = nix_tm_default_rr_weight(nix); + else + /* For CN9K, weight needs to be converted to quantum */ + rr_quantum = nix_tm_weight_to_rr_quantum(node->weight); /* For children to root, strict prio is default if either * device root is TL2 or TL1 Static Priority is disabled. @@ -666,8 +688,8 @@ nix_tm_sched_reg_prep(struct nix *nix, struct nix_tm_node *node, plt_tm_dbg("Schedule config node %s(%u) lvl %u id %u, " "prio 0x%" PRIx64 ", rr_quantum/rr_wt 0x%" PRIx64 " (%p)", - nix_tm_hwlvl2str(node->hw_lvl), schq, node->lvl, node->id, - strict_prio, rr_quantum, node); + nix_tm_hwlvl2str(node->hw_lvl), schq, node->lvl, node->id, strict_prio, + rr_quantum, node); switch (hw_lvl) { case NIX_TXSCH_LVL_SMQ: From patchwork Tue Oct 11 12:01:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 117915 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id BA487A0545; Tue, 11 Oct 2022 14:02:30 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0FD9942DDB; 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Tue, 11 Oct 2022 05:02:03 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 11 Oct 2022 05:01:59 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Tue, 11 Oct 2022 05:01:59 -0700 Received: from localhost.localdomain (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 881013F7040; Tue, 11 Oct 2022 05:01:57 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Subject: [PATCH 08/13] common/cnxk: revert VF root weight Date: Tue, 11 Oct 2022 17:31:30 +0530 Message-ID: <20221011120135.45846-8-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221011120135.45846-1-ndabilpuram@marvell.com> References: <20221011120135.45846-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: rBWEIAH0WNR_JrwK1mpgJj0qnBsvPU1a X-Proofpoint-GUID: rBWEIAH0WNR_JrwK1mpgJj0qnBsvPU1a X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-10-11_07,2022-10-11_02,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Satha Rao With kernel RR_QUANTUM some of the DPDK perf test (ipsec reassembly) was failing, so reverting this change. Signed-off-by: Satha Rao --- drivers/common/cnxk/roc_nix_tm.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/drivers/common/cnxk/roc_nix_tm.c b/drivers/common/cnxk/roc_nix_tm.c index 86918990a2..be8da714cd 100644 --- a/drivers/common/cnxk/roc_nix_tm.c +++ b/drivers/common/cnxk/roc_nix_tm.c @@ -1354,11 +1354,7 @@ nix_tm_prepare_default_tree(struct roc_nix *roc_nix) node->id = nonleaf_id; node->parent_id = parent; node->priority = 0; - /* Default VF root RR_QUANTUM is in sync with kernel */ - if (lvl == ROC_TM_LVL_ROOT && !nix_tm_have_tl1_access(nix)) - node->weight = 0; - else - node->weight = NIX_TM_DFLT_RR_WT; + node->weight = NIX_TM_DFLT_RR_WT; node->shaper_profile_id = ROC_NIX_TM_SHAPER_PROFILE_NONE; node->lvl = lvl; node->tree = ROC_NIX_TM_DEFAULT; From patchwork Tue Oct 11 12:01:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 117916 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3887DA0545; Tue, 11 Oct 2022 14:02:37 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0268442DE0; Tue, 11 Oct 2022 14:02:07 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 00B3742DDA for ; Tue, 11 Oct 2022 14:02:04 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 29B8OJEu030159 for ; Tue, 11 Oct 2022 05:02:04 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=6g7GC0RsvZ35s3dbeA4n9hbJelNaKCDAormmkyQLDis=; b=JniQyzNM8wFinX/Gn4ChHPLB0cagK/T5/6dsZ8vVzFFd91SrV/illve2aZDCRw3qagD8 /dgWe3beSFXyrCyH3LKejedhucb0+E1mLlEqyxYJQCC0kZxTkIFwoEh8Q6EvLe0ZRb4z KgyRK4jWkJDMnZKDnaD/Vpv15XM9YUaZDFuLLAzabkKGRbLbzFGNhvkfoSCj0e4LFBL0 raIIe8n+8cDRcZDKYlCx6KSCfrwj4IZzYQhGufS9+D/Z7Cm33mg8iDN7B6v7wVMu4OSy WlrnwjUsRSCZI8rw2NjRHemel17wIjlMerSzx8Tj09Hylo9wHdSgEBCGE8H8VLgzoXCh gQ== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3k54xugqa4-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 11 Oct 2022 05:02:04 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 11 Oct 2022 05:02:02 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Tue, 11 Oct 2022 05:02:02 -0700 Received: from localhost.localdomain (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 1C97D3F7050; Tue, 11 Oct 2022 05:01:59 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Subject: [PATCH 09/13] common/cnxk: set hysteresis bit to one Date: Tue, 11 Oct 2022 17:31:31 +0530 Message-ID: <20221011120135.45846-9-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221011120135.45846-1-ndabilpuram@marvell.com> References: <20221011120135.45846-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: MZYGXwm0JhsQ1rbxYAn0NWg2rplAxxdS X-Proofpoint-ORIG-GUID: MZYGXwm0JhsQ1rbxYAn0NWg2rplAxxdS X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-10-11_07,2022-10-11_02,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Satha Rao Setting non zero FC_HYST_BITS to reduce mesh traffic on HW. Signed-off-by: Satha Rao --- drivers/common/cnxk/roc_nix_queue.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/common/cnxk/roc_nix_queue.c b/drivers/common/cnxk/roc_nix_queue.c index 7f001efbb0..040b9cc45b 100644 --- a/drivers/common/cnxk/roc_nix_queue.c +++ b/drivers/common/cnxk/roc_nix_queue.c @@ -834,7 +834,7 @@ sqb_pool_populate(struct roc_nix *roc_nix, struct roc_nix_sq *sq) else aura.fc_stype = 0x3; /* STSTP */ aura.fc_addr = (uint64_t)sq->fc; - aura.fc_hyst_bits = 0; /* Store count on all updates */ + aura.fc_hyst_bits = 1; /* Store count on all updates */ rc = roc_npa_pool_create(&sq->aura_handle, blk_sz, nb_sqb_bufs, &aura, &pool, 0); if (rc) From patchwork Tue Oct 11 12:01:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 117917 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A341DA0545; Tue, 11 Oct 2022 14:02:43 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id DB09B42DDA; Tue, 11 Oct 2022 14:02:11 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id B271142DCF for ; Tue, 11 Oct 2022 14:02:09 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 29B1Na46011947 for ; Tue, 11 Oct 2022 05:02:09 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=UOgsU1Cpp+KBBRqJGM9fPJmrGl+77m3z4msIxsf9YGE=; b=FYfkZuXVTXmmRcqyJ6bXC6r5hdluDxDPrPE2YVA7CDw6aEgiDk8i9ApZa262tNjnf18A 2j7ixVlJiWXMYIQVwCgHpn22t6RmjBnvouogcLNi7CcZHZAbGG/rggWyBT2EqMmrkHN7 P3EholMYecog/0XYsDESCwrIyCp/ehvKFzk7an6CHawjDjM9AvOvb1a2j1qXUTh+JZ7Q AJE73fvhOAc9C56F5060up0YkekoPukIaqJZ2fr8GxTzzEOYIigGqI96NgzXzdy1gLru QeVZ01tp5mFPtWElV/1DHvnWnXaQ1qxTPPfY9eUlYGW/SvzCqxwH1tU37UT8fuv0UbNh Vw== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3k40g4y2bq-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 11 Oct 2022 05:02:08 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 11 Oct 2022 05:02:04 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 11 Oct 2022 05:02:04 -0700 Received: from localhost.localdomain (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id A76D93F7060; Tue, 11 Oct 2022 05:02:02 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , , Vamsi Attunuru Subject: [PATCH 10/13] net/cnxk: handle SA soft packet and byte expiry events Date: Tue, 11 Oct 2022 17:31:32 +0530 Message-ID: <20221011120135.45846-10-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221011120135.45846-1-ndabilpuram@marvell.com> References: <20221011120135.45846-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: -4GAyULFO8lO26mm6Qmuc7P_9RUUOloR X-Proofpoint-GUID: -4GAyULFO8lO26mm6Qmuc7P_9RUUOloR X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-10-11_07,2022-10-11_02,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Vamsi Attunuru Handle SA soft packet and byte expiry event for Inline outbound SA. Signed-off-by: Nithin Dabilpuram --- drivers/net/cnxk/cn10k_ethdev_sec.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/net/cnxk/cn10k_ethdev_sec.c b/drivers/net/cnxk/cn10k_ethdev_sec.c index 3ca707f038..ce1b10d885 100644 --- a/drivers/net/cnxk/cn10k_ethdev_sec.c +++ b/drivers/net/cnxk/cn10k_ethdev_sec.c @@ -428,7 +428,12 @@ cn10k_eth_sec_sso_work_cb(uint64_t *gw, void *args, uint32_t soft_exp_event) sa = (struct roc_ot_ipsec_outb_sa *)args; priv = roc_nix_inl_ot_ipsec_outb_sa_sw_rsvd(sa); desc.metadata = (uint64_t)priv->userdata; - desc.subtype = RTE_ETH_EVENT_IPSEC_SA_TIME_EXPIRY; + if (sa->w2.s.life_unit == ROC_IE_OT_SA_LIFE_UNIT_PKTS) + desc.subtype = + RTE_ETH_EVENT_IPSEC_SA_PKT_EXPIRY; + else + desc.subtype = + RTE_ETH_EVENT_IPSEC_SA_BYTE_EXPIRY; eth_dev = &rte_eth_devices[soft_exp_event >> 8]; rte_eth_dev_callback_process(eth_dev, RTE_ETH_EVENT_IPSEC, &desc); From patchwork Tue Oct 11 12:01:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 117918 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id DE53EA0545; Tue, 11 Oct 2022 14:02:49 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id DF63342DE9; Tue, 11 Oct 2022 14:02:12 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 4A84042DCF for ; Tue, 11 Oct 2022 14:02:10 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 29BA3Alu015818 for ; Tue, 11 Oct 2022 05:02:09 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=kRgPsuCzmr2bBpO5yiW3xT6IJLWBke0V5BdVsHYL+UE=; b=OHgiatK+Y8h1PqsauybL8r7JioqNan5IXfx7UWfqZfEpdWXTRaza879Ow/EOxvj8PR4o kNgiIx4ofliPp+bbrToVr85lqA3BCHPBlI5bDLDrSWe5FaNQl81PpmBRLZvuoBKevLKt 0gW1VB1fNmkTDrHRuIjvdsmQopWytZgQSd2Yi0t+7q/sGU1evyQxzwxpxP3/WymMYmDk 8xJdwV5EQTYG8HIQrTbONh/yWnHgT6t+wEOBm/zxnQNshfOFMe3QMiqYoZOUB8hdjY7c 5Moz384IprpQO8e48EMAYM/H/Pps/HoxkTFftwSI4abrsKW89W+KZixv09X2GPBeS558 xw== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3k40g4y2bx-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 11 Oct 2022 05:02:09 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 11 Oct 2022 05:02:07 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 11 Oct 2022 05:02:07 -0700 Received: from localhost.localdomain (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 7AD953F7088; Tue, 11 Oct 2022 05:02:05 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Subject: [PATCH 11/13] common/cnxk: sync mailbox for channel and bpid map Date: Tue, 11 Oct 2022 17:31:33 +0530 Message-ID: <20221011120135.45846-11-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221011120135.45846-1-ndabilpuram@marvell.com> References: <20221011120135.45846-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: 0a_zD_65RXl3sOM_4sHbtVkohhrWShG9 X-Proofpoint-GUID: 0a_zD_65RXl3sOM_4sHbtVkohhrWShG9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-10-11_07,2022-10-11_02,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Sunil Kumar Kori As per recent change in Linux-5.4.x, mailbox is updated to configure mapping between channel and BPID. Due to mbox mismatch, PFC was broken. Patch syncs mailbox definition for the same. Also fixes the PFC configuration issues. Signed-off-by: Sunil Kumar Kori --- drivers/common/cnxk/roc_mbox.h | 6 +++--- drivers/common/cnxk/roc_nix.h | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h index e8d4ae283d..d47808e5ef 100644 --- a/drivers/common/cnxk/roc_mbox.h +++ b/drivers/common/cnxk/roc_mbox.h @@ -1164,10 +1164,10 @@ struct nix_bp_cfg_req { /* bpid_per_chan = 1 assigns separate bp id for each channel */ }; -/* PF can be mapped to either CGX or LBK interface, - * so maximum 64 channels are possible. +/* PF can be mapped to either CGX or LBK or SDP interface, + * so maximum 256 channels are possible. */ -#define NIX_MAX_CHAN 64 +#define NIX_MAX_CHAN 256 #define NIX_CGX_MAX_CHAN 16 #define NIX_LBK_MAX_CHAN 1 struct nix_bp_cfg_rsp { diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h index 1eb1c9af55..c50efefa80 100644 --- a/drivers/common/cnxk/roc_nix.h +++ b/drivers/common/cnxk/roc_nix.h @@ -432,7 +432,7 @@ struct roc_nix { bool rx_ptp_ena; uint16_t cints; -#define ROC_NIX_MEM_SZ (6 * 1024) +#define ROC_NIX_MEM_SZ (6 * 1056) uint8_t reserved[ROC_NIX_MEM_SZ] __plt_cache_aligned; } __plt_cache_aligned; From patchwork Tue Oct 11 12:01:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 117919 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id BEBC9A0545; Tue, 11 Oct 2022 14:02:58 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2B5DC42DE6; Tue, 11 Oct 2022 14:02:15 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id D0C9342DED for ; Tue, 11 Oct 2022 14:02:13 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 29B9q7YA000409 for ; Tue, 11 Oct 2022 05:02:13 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=ErfVdWd0QcuMJ+5oWmTstmxvTwtATQ9T3YiPa6G8WyA=; b=E9/PYQ+4ztIMeCAt86D7RDGy7bWzabaD8vkZmy8GoBYLN9AIb11kzBBz7AphQH6HhSRx DfwWWBrmAE2mni+A/MOzinezJ1OvtG0aItjVyQk3ycIbOJ/B4aS7U4MrOnQerG68zvLK Umf4T2W3mzMcfzPHI1kpg4xj67IznYdR4VvjP5ySxw4+hB8eNkTwRU/yuBxM4CoFSq3e tVbPVq9mSDQ0+wz1lhSKMmBRLx5kI89JlrHofA4C2ugbDnbteA7s+QdMWibN6OCwveN/ gLOkJLgNSM7647T4QpT+Cae/B7B82+uLRAfEV03RpEOiyiTDbfJxGERtZYzwVIKYvI8p RQ== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3k40g4y2da-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 11 Oct 2022 05:02:13 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 11 Oct 2022 05:02:10 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Tue, 11 Oct 2022 05:02:10 -0700 Received: from localhost.localdomain (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 05C4F3F7060; Tue, 11 Oct 2022 05:02:07 -0700 (PDT) From: Nithin Dabilpuram To: Pavan Nikhilesh , Shijith Thotton , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao CC: , , Vidya Sagar Velumuri Subject: [PATCH 12/13] net/cnxk: remove unnecessary dptr update Date: Tue, 11 Oct 2022 17:31:34 +0530 Message-ID: <20221011120135.45846-12-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221011120135.45846-1-ndabilpuram@marvell.com> References: <20221011120135.45846-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: 3VclvVMA2PT8UKzQuvVin_PyaJXBrfxR X-Proofpoint-GUID: 3VclvVMA2PT8UKzQuvVin_PyaJXBrfxR X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-10-11_07,2022-10-11_02,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Also remove ESN update from ucode command word 0 based on latest ucode. Signed-off-by: Nithin Dabilpuram Signed-off-by: Vidya Sagar Velumuri --- drivers/event/cnxk/cn9k_worker.h | 1 - drivers/net/cnxk/cn10k_tx.h | 4 ---- 2 files changed, 5 deletions(-) diff --git a/drivers/event/cnxk/cn9k_worker.h b/drivers/event/cnxk/cn9k_worker.h index 881861f348..4c3932da47 100644 --- a/drivers/event/cnxk/cn9k_worker.h +++ b/drivers/event/cnxk/cn9k_worker.h @@ -718,7 +718,6 @@ cn9k_sso_hws_xmit_sec_one(const struct cn9k_eth_txq *txq, uint64_t base, esn = outb_priv->esn; outb_priv->esn = esn + 1; - ucode_cmd[0] |= (esn >> 32) << 16; esn_lo = rte_cpu_to_be_32(esn & (BIT_ULL(32) - 1)); esn_hi = rte_cpu_to_be_32(esn >> 32); diff --git a/drivers/net/cnxk/cn10k_tx.h b/drivers/net/cnxk/cn10k_tx.h index 527b65022f..5b13f02095 100644 --- a/drivers/net/cnxk/cn10k_tx.h +++ b/drivers/net/cnxk/cn10k_tx.h @@ -422,8 +422,6 @@ cn10k_nix_prep_sec_vec(struct rte_mbuf *m, uint64x2_t *cmd0, uint64x2_t *cmd1, CNXK_ETHDEV_SEC_OUTB_EV_SUB << 20), cmd23, 0); cmd23 = vsetq_lane_u64((uintptr_t)m | 1, cmd23, 1); - dptr += l2_len; - /* Move to our line */ laddr = LMT_OFF(lbase, *lnum, *loff ? 64 : 0); @@ -564,8 +562,6 @@ cn10k_nix_prep_sec(struct rte_mbuf *m, uint64_t *cmd, uintptr_t *nixtx_addr, CNXK_ETHDEV_SEC_OUTB_EV_SUB << 20), cmd23, 0); cmd23 = vsetq_lane_u64((uintptr_t)m | 1, cmd23, 1); - dptr += l2_len; - /* Move to our line */ laddr = LMT_OFF(lbase, *lnum, *loff ? 64 : 0); From patchwork Tue Oct 11 12:01:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 117920 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7FEFAA0545; Tue, 11 Oct 2022 14:03:04 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3CA9842DED; Tue, 11 Oct 2022 14:02:17 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id C35CB42DF5 for ; Tue, 11 Oct 2022 14:02:15 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 29B8OQAI030232 for ; Tue, 11 Oct 2022 05:02:15 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=rS1WBoQh4isp7oDK3l/h2z+KgJed4miJKo6O5H3o9K4=; b=EX1f80nGKGqXQuR52Y/TMoefkUNcYgrzVu75UOF4Gmwr29Sv1zoosfzvASRa8qUWBncS Xe+Q87kwpzwGXHF2V9n0djavfQ4CNVGeBpF+YXGxjGVRIsRWhuMRIw18OmTT3GVI3U1/ G1w9Fl6ikRRGO9TNRDISUJuqHakJ7KDT31N1pGhGVOWD5mqXYSW/2lu082gl9KbF2FaY MsiC+lld1PxkKN9Z0Y2FDtIr0FldP0OaTbvkBta/uG8j9zgwjEbl3APaikROCS8uaQ/J ZKh1/sKQDSN2Y+Y+1xBnjFy0+YDK4emiRwRUPU/mNmVv/ai5mCNHLQlUdh9R9V2zTYCm Tg== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3k54xugqck-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 11 Oct 2022 05:02:14 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 11 Oct 2022 05:02:13 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Tue, 11 Oct 2022 05:02:13 -0700 Received: from localhost.localdomain (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 4494B3F706B; Tue, 11 Oct 2022 05:02:11 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Subject: [PATCH 13/13] net/cnxk: remove duplicate mempool debug checks Date: Tue, 11 Oct 2022 17:31:35 +0530 Message-ID: <20221011120135.45846-13-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221011120135.45846-1-ndabilpuram@marvell.com> References: <20221011120135.45846-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: yMdn3SQddczt0O4HKJL4wzQH_QhRNDg- X-Proofpoint-ORIG-GUID: yMdn3SQddczt0O4HKJL4wzQH_QhRNDg- X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-10-11_07,2022-10-11_02,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Remove duplicate mempool debug checks for mbufs received. Fixes: 592642c494b1 ("net/cnxk: align prefetches to CN10K cache model") Signed-off-by: Nithin Dabilpuram --- drivers/net/cnxk/cn10k_rx.h | 6 ------ 1 file changed, 6 deletions(-) diff --git a/drivers/net/cnxk/cn10k_rx.h b/drivers/net/cnxk/cn10k_rx.h index cf390a0361..4e22ceda02 100644 --- a/drivers/net/cnxk/cn10k_rx.h +++ b/drivers/net/cnxk/cn10k_rx.h @@ -1307,12 +1307,6 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts, ol_flags3 |= nix_rx_olflags_get(lookup_mem, cq3_w1); } - /* Mark mempool obj as "get" as it is alloc'ed by NIX */ - RTE_MEMPOOL_CHECK_COOKIES(mbuf0->pool, (void **)&mbuf0, 1, 1); - RTE_MEMPOOL_CHECK_COOKIES(mbuf1->pool, (void **)&mbuf1, 1, 1); - RTE_MEMPOOL_CHECK_COOKIES(mbuf2->pool, (void **)&mbuf2, 1, 1); - RTE_MEMPOOL_CHECK_COOKIES(mbuf3->pool, (void **)&mbuf3, 1, 1); - /* Translate meta to mbuf */ if (flags & NIX_RX_OFFLOAD_SECURITY_F) { uint64_t cq0_w5 = *CQE_PTR_OFF(cq0, 0, 40, flags);