diff mbox series

[11/13] common/cnxk: sync mailbox for channel and bpid map

Message ID 20221011120135.45846-11-ndabilpuram@marvell.com (mailing list archive)
State Changes Requested, archived
Delegated to: Jerin Jacob
Headers
Series [01/13] common/cnxk: set MTU size on SDP based on SoC type |

Checks

Context Check Description
ci/checkpatch success coding style OK

Commit Message

Nithin Dabilpuram Oct. 11, 2022, 12:01 p.m. UTC 
  From: Sunil Kumar Kori <skori@marvell.com>

As per recent change in Linux-5.4.x, mailbox is updated to configure
mapping between channel and BPID. Due to mbox mismatch, PFC was broken.
Patch syncs mailbox definition for the same. Also fixes the PFC
configuration issues.

Signed-off-by: Sunil Kumar Kori <skori@marvell.com>
---
 drivers/common/cnxk/roc_mbox.h | 6 +++---
 drivers/common/cnxk/roc_nix.h  | 2 +-
 2 files changed, 4 insertions(+), 4 deletions(-)
diff mbox series

Patch

diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h
index e8d4ae283d..d47808e5ef 100644
--- a/drivers/common/cnxk/roc_mbox.h
+++ b/drivers/common/cnxk/roc_mbox.h
@@ -1164,10 +1164,10 @@  struct nix_bp_cfg_req {
 	/* bpid_per_chan = 1 assigns separate bp id for each channel */
 };
 
-/* PF can be mapped to either CGX or LBK interface,
- * so maximum 64 channels are possible.
+/* PF can be mapped to either CGX or LBK or SDP interface,
+ * so maximum 256 channels are possible.
  */
-#define NIX_MAX_CHAN	 64
+#define NIX_MAX_CHAN	 256
 #define NIX_CGX_MAX_CHAN 16
 #define NIX_LBK_MAX_CHAN 1
 struct nix_bp_cfg_rsp {
diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h
index 1eb1c9af55..c50efefa80 100644
--- a/drivers/common/cnxk/roc_nix.h
+++ b/drivers/common/cnxk/roc_nix.h
@@ -432,7 +432,7 @@  struct roc_nix {
 	bool rx_ptp_ena;
 	uint16_t cints;
 
-#define ROC_NIX_MEM_SZ (6 * 1024)
+#define ROC_NIX_MEM_SZ (6 * 1056)
 	uint8_t reserved[ROC_NIX_MEM_SZ] __plt_cache_aligned;
 } __plt_cache_aligned;