diff mbox series

[v1,03/33] baseband/acc100: add default e value for FCW

Message ID	20220816055258.107564-4-hernan.vargas@intel.com (mailing list archive)
State	Superseded, archived
Delegated to:	akhil goyal
Headers	From: Hernan Vargas <hernan.vargas@intel.com> To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas <hernan.vargas@intel.com> Subject: [PATCH v1 03/33] baseband/acc100: add default e value for FCW Date: Mon, 15 Aug 2022 22:52:28 -0700 Message-Id: <20220816055258.107564-4-hernan.vargas@intel.com> In-Reply-To: <20220816055258.107564-1-hernan.vargas@intel.com> References: <20220816055258.107564-1-hernan.vargas@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: list Errors-To: dev-bounces@dpdk.org
Series	baseband/acc100: changes for 22.11 \| [v1,00/33] baseband/acc100: changes for 22.11 [v1,01/33] baseband/acc100: update dev close function [v1,02/33] baseband/acc100: quit queue setup for undef dev [v1,03/33] baseband/acc100: add default e value for FCW [v1,04/33] baseband/acc100: add LDPC encoder padding function [v1,05/33] baseband/acc100: add scatter-gather support [v1,06/33] baseband/acc100: add HARQ index helper function [v1,07/33] baseband/acc100: avoid mux for small inbound frames [v1,08/33] baseband/acc100: separate validation functions from debug [v1,09/33] baseband/acc100: add LDPC transport block support [v1,10/33] baseband/acc10x: limit cases for HARQ pruning [v1,11/33] baseband/acc100: update validate LDPC enc/dec [v1,12/33] baseband/acc100: add workaround for deRM corner cases [v1,13/33] baseband/acc100: enable vf2pf doorbell register [v1,14/33] baseband/acc100: add ring companion address [v1,15/33] baseband/acc100: configure PMON control registers [v1,16/33] baseband/acc100: configurable queue depth [v1,17/33] baseband/acc100: add queue stop operation [v1,18/33] basbeband/acc100: check turbo dec/enc input [v1,19/33] baseband/acc100: check for unlikely operation vals [v1,20/33] baseband/acc100: enforce additional check on FCW [v1,21/33] baseband/acc100: update uplink CB input length [v1,22/33] baseband/acc100: rename ldpc encode function arg [v1,23/33] baseband/acc100: update log messages [v1,24/33] baseband/acc100: allocate ring/queue mem when NULL [v1,25/33] baseband/acc100: store FCW from first CB descriptor [v1,26/33] baseband/acc100: remove input error check from enc [v1,27/33] baseband/acc100: make desc optimization optional [v1,28/33] baseband/acc100: update device info [v1,29/33] baseband/acc100: reduce input length for CRC24B [v1,30/33] baseband/acc100: initialize ring data value [v1,31/33] baseband/acc100: update debug print for LDPC FCW [v1,32/33] baseband/acc100: set device min alignment to 1 [v1,33/33] baseband/acc100: update meson file sdk dependency

Checks

Context	Check	Description
ci/checkpatch	success	coding style OK

Commit Message

Hernan Vargas Aug. 16, 2022, 5:52 a.m. UTC

  Update frame control word LDPC encoder fill function to take a default e
value as a parameter.

Signed-off-by: Hernan Vargas <hernan.vargas@intel.com>
---
 drivers/baseband/acc100/rte_acc100_pmd.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff mbox series

Patch

diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c
index b7daef3d84..a07692faa9 100644
--- a/drivers/baseband/acc100/rte_acc100_pmd.c
+++ b/drivers/baseband/acc100/rte_acc100_pmd.c
@@ -1271,7 +1271,7 @@  get_k0(uint16_t n_cb, uint16_t z_c, uint8_t bg, uint8_t rv_index)
 /* Fill in a frame control word for LDPC encoding. */
 static inline void
 acc100_fcw_le_fill(const struct rte_bbdev_enc_op *op,
-		struct acc100_fcw_le *fcw, int num_cb)
+		struct acc100_fcw_le *fcw, int num_cb, uint32_t default_e)
 {
 	fcw->qm = op->ldpc_enc.q_m;
 	fcw->nfiller = op->ldpc_enc.n_filler;
@@ -1280,7 +1280,7 @@  acc100_fcw_le_fill(const struct rte_bbdev_enc_op *op,
 	fcw->ncb = op->ldpc_enc.n_cb;
 	fcw->k0 = get_k0(fcw->ncb, fcw->Zc, op->ldpc_enc.basegraph,
 			op->ldpc_enc.rv_index);
-	fcw->rm_e = op->ldpc_enc.cb_params.e;
+	fcw->rm_e = (default_e == 0) ? op->ldpc_enc.cb_params.e : default_e;
 	fcw->crc_select = check_bit(op->ldpc_enc.op_flags,
 			RTE_BBDEV_LDPC_CRC_24B_ATTACH);
 	fcw->bypass_intlv = check_bit(op->ldpc_enc.op_flags,
@@ -2528,7 +2528,7 @@  enqueue_ldpc_enc_n_op_cb(struct acc100_queue *q, struct rte_bbdev_enc_op **ops,
 	uint16_t desc_idx = ((q->sw_ring_head + total_enqueued_cbs)
 			& q->sw_ring_wrap_mask);
 	desc = q->ring_addr + desc_idx;
-	acc100_fcw_le_fill(ops[0], &desc->req.fcw_le, num);
+	acc100_fcw_le_fill(ops[0], &desc->req.fcw_le, num, 0);
 
 	/** This could be done at polling */
 	acc100_header_init(&desc->req);
@@ -2590,7 +2590,7 @@  enqueue_ldpc_enc_one_op_cb(struct acc100_queue *q, struct rte_bbdev_enc_op *op,
 	uint16_t desc_idx = ((q->sw_ring_head + total_enqueued_cbs)
 			& q->sw_ring_wrap_mask);
 	desc = q->ring_addr + desc_idx;
-	acc100_fcw_le_fill(op, &desc->req.fcw_le, 1);
+	acc100_fcw_le_fill(op, &desc->req.fcw_le, 1, 0);
 
 	input = op->ldpc_enc.input.data;
 	output_head = output = op->ldpc_enc.output.data;