diff mbox series

[v1,21/33] baseband/acc100: update uplink CB input length

Message ID	20220816055258.107564-22-hernan.vargas@intel.com (mailing list archive)
State	Superseded, archived
Delegated to:	akhil goyal
Headers	From: Hernan Vargas <hernan.vargas@intel.com> To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas <hernan.vargas@intel.com> Subject: [PATCH v1 21/33] baseband/acc100: update uplink CB input length Date: Mon, 15 Aug 2022 22:52:46 -0700 Message-Id: <20220816055258.107564-22-hernan.vargas@intel.com> In-Reply-To: <20220816055258.107564-1-hernan.vargas@intel.com> References: <20220816055258.107564-1-hernan.vargas@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: list Errors-To: dev-bounces@dpdk.org
Series	baseband/acc100: changes for 22.11 \| [v1,00/33] baseband/acc100: changes for 22.11 [v1,01/33] baseband/acc100: update dev close function [v1,02/33] baseband/acc100: quit queue setup for undef dev [v1,03/33] baseband/acc100: add default e value for FCW [v1,04/33] baseband/acc100: add LDPC encoder padding function [v1,05/33] baseband/acc100: add scatter-gather support [v1,06/33] baseband/acc100: add HARQ index helper function [v1,07/33] baseband/acc100: avoid mux for small inbound frames [v1,08/33] baseband/acc100: separate validation functions from debug [v1,09/33] baseband/acc100: add LDPC transport block support [v1,10/33] baseband/acc10x: limit cases for HARQ pruning [v1,11/33] baseband/acc100: update validate LDPC enc/dec [v1,12/33] baseband/acc100: add workaround for deRM corner cases [v1,13/33] baseband/acc100: enable vf2pf doorbell register [v1,14/33] baseband/acc100: add ring companion address [v1,15/33] baseband/acc100: configure PMON control registers [v1,16/33] baseband/acc100: configurable queue depth [v1,17/33] baseband/acc100: add queue stop operation [v1,18/33] basbeband/acc100: check turbo dec/enc input [v1,19/33] baseband/acc100: check for unlikely operation vals [v1,20/33] baseband/acc100: enforce additional check on FCW [v1,21/33] baseband/acc100: update uplink CB input length [v1,22/33] baseband/acc100: rename ldpc encode function arg [v1,23/33] baseband/acc100: update log messages [v1,24/33] baseband/acc100: allocate ring/queue mem when NULL [v1,25/33] baseband/acc100: store FCW from first CB descriptor [v1,26/33] baseband/acc100: remove input error check from enc [v1,27/33] baseband/acc100: make desc optimization optional [v1,28/33] baseband/acc100: update device info [v1,29/33] baseband/acc100: reduce input length for CRC24B [v1,30/33] baseband/acc100: initialize ring data value [v1,31/33] baseband/acc100: update debug print for LDPC FCW [v1,32/33] baseband/acc100: set device min alignment to 1 [v1,33/33] baseband/acc100: update meson file sdk dependency

Checks

Context	Check	Description
ci/checkpatch	success	coding style OK

Commit Message

Hernan Vargas Aug. 16, 2022, 5:52 a.m. UTC

  Use the FCW E parameter for rate matching as the code block input
length.

Signed-off-by: Hernan Vargas <hernan.vargas@intel.com>
---
 drivers/baseband/acc100/rte_acc100_pmd.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff mbox series

Patch

diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c
index 0e91205c49..a404a06e55 100644
--- a/drivers/baseband/acc100/rte_acc100_pmd.c
+++ b/drivers/baseband/acc100/rte_acc100_pmd.c
@@ -2174,7 +2174,7 @@  acc100_dma_desc_ld_fill(struct rte_bbdev_dec_op *op,
 		crc24_overlap = 24;
 
 	/* Compute some LDPC BG lengths */
-	input_length = dec->cb_params.e;
+	input_length = fcw->rm_e;
 	if (check_bit(op->ldpc_dec.op_flags,
 			RTE_BBDEV_LDPC_LLR_COMPRESSION))
 		input_length = (input_length * 3 + 3) / 4;