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GET /api/patches/131654/?format=api
{ "id": 131654, "url": "http://patches.dpdk.org/api/patches/131654/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20230919182417.93374-2-hernan.vargas@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230919182417.93374-2-hernan.vargas@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230919182417.93374-2-hernan.vargas@intel.com", "date": "2023-09-19T18:24:17", "name": "[v1,1/1] baseband/acc: fix ACC100 HARQ input is alignment", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "36ab0547440482cf1be3786f961852235f2572dc", "submitter": { "id": 2659, "url": "http://patches.dpdk.org/api/people/2659/?format=api", "name": "Hernan Vargas", "email": "hernan.vargas@intel.com" }, "delegate": { "id": 2642, "url": "http://patches.dpdk.org/api/users/2642/?format=api", "username": "mcoquelin", "first_name": "Maxime", "last_name": "Coquelin", "email": "maxime.coquelin@redhat.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20230919182417.93374-2-hernan.vargas@intel.com/mbox/", "series": [ { "id": 29558, "url": "http://patches.dpdk.org/api/series/29558/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=29558", "date": "2023-09-19T18:24:16", "name": "baseband/acc: fix for 23.11", "version": 1, "mbox": "http://patches.dpdk.org/series/29558/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/131654/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/131654/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 4E6F54260D;\n\tTue, 19 Sep 2023 20:24:59 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 27F1F4069F;\n\tTue, 19 Sep 2023 20:24:54 +0200 (CEST)", "from mgamail.intel.com (mgamail.intel.com [192.55.52.43])\n by mails.dpdk.org (Postfix) with ESMTP id 70E2E40277;\n Tue, 19 Sep 2023 20:24:51 +0200 (CEST)", "from orsmga001.jf.intel.com ([10.7.209.18])\n by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 19 Sep 2023 11:24:49 -0700", "from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103])\n by orsmga001.jf.intel.com with ESMTP; 19 Sep 2023 11:24:49 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1695147891; x=1726683891;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=BGKqNvuRTEB1FWZFgVeaYMJBpqfv/rySAM8f8k300eg=;\n b=M1j6b+Ufes5QsMGe4Rttyd8gdeMD7pAD97dNE5EaEOXIOFGbJVUWEsKL\n 9TkjMLSeLOtV9I+X9i5j9WtjNZeVJ8tJVOsBGpz6+T/vvYvUVB8/F/tgb\n FMwWtw0rGUWizN5JRd6i13yn30mbagxfLFUbYbvb7EsmH43G29drjPboF\n Qg6+3dNCo9Nz587aBCMvxB8kyCtGViOhBI01hyVHZGBE63RvZGSoxVz1g\n h2z4dfNdskOLC6IXkiMSMjJDXGdCfTY5bZApFNFetuFitdGhpMscN7heo\n SyZo2f6unjI1AI1pNtGzlUTWHB+YxV/yAGGyJ1l3uduAchi2sMWdmo3Bm w==;", "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,10838\"; a=\"466336419\"", "E=Sophos;i=\"6.02,160,1688454000\"; d=\"scan'208\";a=\"466336419\"", "E=McAfee;i=\"6600,9927,10838\"; a=\"781396869\"", "E=Sophos;i=\"6.02,160,1688454000\"; d=\"scan'208\";a=\"781396869\"" ], "X-ExtLoop1": "1", "From": "Hernan Vargas <hernan.vargas@intel.com>", "To": "dev@dpdk.org, gakhil@marvell.com, trix@redhat.com,\n maxime.coquelin@redhat.com", "Cc": "nicolas.chautru@intel.com, qi.z.zhang@intel.com,\n Hernan Vargas <hernan.vargas@intel.com>, stable@dpdk.org", "Subject": "[PATCH v1 1/1] baseband/acc: fix ACC100 HARQ input is alignment", "Date": "Tue, 19 Sep 2023 11:24:17 -0700", "Message-Id": "<20230919182417.93374-2-hernan.vargas@intel.com>", "X-Mailer": "git-send-email 2.37.1", "In-Reply-To": "<20230919182417.93374-1-hernan.vargas@intel.com>", "References": "<20230919182417.93374-1-hernan.vargas@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Some constraints are imposed onto the ACC100 HARQ input size,\nbut that value is incorrectly aligned down when getting close to\nmax (Ncb-F) which is not required.\nThe wireless performance impact is negligeable but still causes a\nfew LLRs no to be combined at the very end of the circular buffer.\n\nFixes: 5802f36dd492 (\"baseband/acc100: enforce additional check on FCW\")\nCc: stable@dpdk.org\n\nSigned-off-by: Hernan Vargas <hernan.vargas@intel.com>\n---\n drivers/baseband/acc/rte_acc100_pmd.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)", "diff": "diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c\nindex 5362d39c302f..c736f3e4201c 100644\n--- a/drivers/baseband/acc/rte_acc100_pmd.c\n+++ b/drivers/baseband/acc/rte_acc100_pmd.c\n@@ -1218,7 +1218,7 @@ acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc_fcw_ld *fcw,\n \t\t\t\t- op->ldpc_dec.n_filler);\n \n \t\t/* Alignment on next 64B - Already enforced from HC output */\n-\t\tharq_in_length = RTE_ALIGN_FLOOR(harq_in_length, ACC_HARQ_ALIGN_64B);\n+\t\tharq_in_length = RTE_ALIGN_CEIL(harq_in_length, ACC_HARQ_ALIGN_64B);\n \n \t\t/* Stronger alignment requirement when in decompression mode */\n \t\tif (fcw->hcin_decomp_mode > 0)\n", "prefixes": [ "v1", "1/1" ] }