From patchwork Tue Sep 19 18:24:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 131654 X-Patchwork-Delegate: maxime.coquelin@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4E6F54260D; Tue, 19 Sep 2023 20:24:59 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 27F1F4069F; Tue, 19 Sep 2023 20:24:54 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.43]) by mails.dpdk.org (Postfix) with ESMTP id 70E2E40277; Tue, 19 Sep 2023 20:24:51 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1695147891; x=1726683891; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=BGKqNvuRTEB1FWZFgVeaYMJBpqfv/rySAM8f8k300eg=; b=M1j6b+Ufes5QsMGe4Rttyd8gdeMD7pAD97dNE5EaEOXIOFGbJVUWEsKL 9TkjMLSeLOtV9I+X9i5j9WtjNZeVJ8tJVOsBGpz6+T/vvYvUVB8/F/tgb FMwWtw0rGUWizN5JRd6i13yn30mbagxfLFUbYbvb7EsmH43G29drjPboF Qg6+3dNCo9Nz587aBCMvxB8kyCtGViOhBI01hyVHZGBE63RvZGSoxVz1g h2z4dfNdskOLC6IXkiMSMjJDXGdCfTY5bZApFNFetuFitdGhpMscN7heo SyZo2f6unjI1AI1pNtGzlUTWHB+YxV/yAGGyJ1l3uduAchi2sMWdmo3Bm w==; X-IronPort-AV: E=McAfee;i="6600,9927,10838"; a="466336419" X-IronPort-AV: E=Sophos;i="6.02,160,1688454000"; d="scan'208";a="466336419" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Sep 2023 11:24:49 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10838"; a="781396869" X-IronPort-AV: E=Sophos;i="6.02,160,1688454000"; d="scan'208";a="781396869" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by orsmga001.jf.intel.com with ESMTP; 19 Sep 2023 11:24:49 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas , stable@dpdk.org Subject: [PATCH v1 1/1] baseband/acc: fix ACC100 HARQ input is alignment Date: Tue, 19 Sep 2023 11:24:17 -0700 Message-Id: <20230919182417.93374-2-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20230919182417.93374-1-hernan.vargas@intel.com> References: <20230919182417.93374-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Some constraints are imposed onto the ACC100 HARQ input size, but that value is incorrectly aligned down when getting close to max (Ncb-F) which is not required. The wireless performance impact is negligeable but still causes a few LLRs no to be combined at the very end of the circular buffer. Fixes: 5802f36dd492 ("baseband/acc100: enforce additional check on FCW") Cc: stable@dpdk.org Signed-off-by: Hernan Vargas Reviewed-by: Maxime Coquelin --- drivers/baseband/acc/rte_acc100_pmd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c index 5362d39c302f..c736f3e4201c 100644 --- a/drivers/baseband/acc/rte_acc100_pmd.c +++ b/drivers/baseband/acc/rte_acc100_pmd.c @@ -1218,7 +1218,7 @@ acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc_fcw_ld *fcw, - op->ldpc_dec.n_filler); /* Alignment on next 64B - Already enforced from HC output */ - harq_in_length = RTE_ALIGN_FLOOR(harq_in_length, ACC_HARQ_ALIGN_64B); + harq_in_length = RTE_ALIGN_CEIL(harq_in_length, ACC_HARQ_ALIGN_64B); /* Stronger alignment requirement when in decompression mode */ if (fcw->hcin_decomp_mode > 0)