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GET /api/patches/103743/?format=api
{ "id": 103743, "url": "http://patches.dpdk.org/api/patches/103743/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20211104112644.17278-4-bingz@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20211104112644.17278-4-bingz@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20211104112644.17278-4-bingz@nvidia.com", "date": "2021-11-04T11:26:43", "name": "[3/4] net/mlx5: support querying delay drop status via ethtool", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "40d674301b16dfe2f6ff8d1e1f9f2bcf10416b17", "submitter": { "id": 1976, "url": "http://patches.dpdk.org/api/people/1976/?format=api", "name": "Bing Zhao", "email": "bingz@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20211104112644.17278-4-bingz@nvidia.com/mbox/", "series": [ { "id": 20307, "url": "http://patches.dpdk.org/api/series/20307/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=20307", "date": "2021-11-04T11:26:41", "name": "Add delay drop support for Rx queue", "version": 1, "mbox": "http://patches.dpdk.org/series/20307/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/103743/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/103743/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id A5AD6A0548;\n\tThu, 4 Nov 2021 12:27:28 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 812EC42701;\n\tThu, 4 Nov 2021 12:27:14 +0100 (CET)", "from NAM11-CO1-obe.outbound.protection.outlook.com\n (mail-co1nam11on2055.outbound.protection.outlook.com [40.107.220.55])\n by mails.dpdk.org (Postfix) with ESMTP id D7E72426FC\n for <dev@dpdk.org>; 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dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.112.34 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.112.34; helo=mail.nvidia.com;", "From": "Bing Zhao <bingz@nvidia.com>", "To": "<viacheslavo@nvidia.com>, <matan@nvidia.com>", "CC": "<dev@dpdk.org>, <rasland@nvidia.com>, <thomas@monjalon.net>,\n <orika@nvidia.com>", "Date": "Thu, 4 Nov 2021 13:26:43 +0200", "Message-ID": "<20211104112644.17278-4-bingz@nvidia.com>", "X-Mailer": "git-send-email 2.27.0", "In-Reply-To": "<20211104112644.17278-1-bingz@nvidia.com>", "References": "<20211104112644.17278-1-bingz@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.187.5]", "X-ClientProxiedBy": "HQMAIL101.nvidia.com (172.20.187.10) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "36c83fcc-ae64-4d05-331b-08d99f860a8e", "X-MS-TrafficTypeDiagnostic": "MW3PR12MB4393:", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-Microsoft-Antispam-PRVS": "\n <MW3PR12MB43937E7C0717ABAD45892AA3D08D9@MW3PR12MB4393.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:8882;", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n 7qk627OhiDC9yhb32YPpT5JR6zqDdmKRv2U9MBxvdz8KyATJIV+SP/pxxfkmrBR4UKyCEPPR/PIzF2PFqRoVPYt5tqLa5QpyMOR7sf6CAvbVrKLZ0cOc8OuAz5pTWxYsNE7VK718BqKVyWvqOe/op0H9GL3YEJIw8LhCcs8M6LBIUia/Et1ciZhJOb9g8IKzasvs25645hL4+mJwze5ncjFkoXD+pA8SuBSYsiSAP8wD9L68foH4kAmTZFsM/W0aynQI3xgBad8hYu20NIdyQEE2uamBtTu7wiBWIMsUG1jEQeS1ck0J1AQ0QuU+jk+tctlS2Xao1MLktggErLA00X3+FCfK92o/ymPre7PKIXqZe7NEpz/NDR9g19F5gsZ5DSw5Z05fK1yx4VylsGH1qhw5Qd4eO40gwloB3QW703Rl4uKkpVUj9/rJFIurooSyxwS1pL8dBuxuUqfvD6UHIGED9raKjrHLFcHPlqSSP8VZgiF+UUF1Siw5BzHgax29udT99FQscXiWkl8fxjCBpMXOB2YasXvS4E9wCifsNkjCHOZLnD2eqHJpmBHdwfCoqd2Cs2PPOULkWU8plg9d39rBa6EnzXkdQBtSSC/kP68FFUsaZrZbawYuWk95uvgn8wISgLMmyrT82KLElA8YVkipcgjvJa8AelQ/PP4RRFhjDjfN3FP3unt2UR02Q3yCDfScwaLAi0GAyHq9RwxmFw==", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(36840700001)(46966006)(5660300002)(26005)(2906002)(356005)(70206006)(6286002)(16526019)(8676002)(36860700001)(6636002)(55016002)(70586007)(508600001)(110136005)(107886003)(4326008)(186003)(7636003)(86362001)(1076003)(2616005)(426003)(316002)(54906003)(82310400003)(8936002)(7696005)(83380400001)(336012)(36756003)(47076005)(6666004);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "04 Nov 2021 11:27:09.8912 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 36c83fcc-ae64-4d05-331b-08d99f860a8e", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1NAM11FT052.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MW3PR12MB4393", "Subject": "[dpdk-dev] [PATCH 3/4] net/mlx5: support querying delay drop status\n via ethtool", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The delay drop is global per PF device and the kernel driver is\ntaking care of the initialization and rearming. By default, the\ntimeout value is set to activate the delay drop when the driver\nis loaded.\n\nA private flag \"dropless_rq\" is used to control the rearming. Only\nwhen it is on, the rearming will be handled once received a timeout\nevent. Or else, the delay drop will be deactived after the first\ntimeout and all the Rx queues won't have this feature.\n\nThe PMD is trying to query this flag and warn the application when\nsome queues are created with delay drop but the flag is off.\n\nSigned-off-by: Bing Zhao <bingz@nvidia.com>\n---\n drivers/net/mlx5/linux/mlx5_ethdev_os.c | 113 ++++++++++++++++++++++++\n drivers/net/mlx5/mlx5.h | 1 +\n drivers/net/mlx5/mlx5_trigger.c | 10 +++\n 3 files changed, 124 insertions(+)", "diff": "diff --git a/drivers/net/mlx5/linux/mlx5_ethdev_os.c b/drivers/net/mlx5/linux/mlx5_ethdev_os.c\nindex 9d0e491d0c..9255877dab 100644\n--- a/drivers/net/mlx5/linux/mlx5_ethdev_os.c\n+++ b/drivers/net/mlx5/linux/mlx5_ethdev_os.c\n@@ -1630,3 +1630,116 @@ mlx5_get_mac(struct rte_eth_dev *dev, uint8_t (*mac)[RTE_ETHER_ADDR_LEN])\n \tmemcpy(mac, request.ifr_hwaddr.sa_data, RTE_ETHER_ADDR_LEN);\n \treturn 0;\n }\n+\n+/*\n+ * Query dropless_rq private flag provided by ETHTOOL.\n+ *\n+ * @param dev\n+ * Pointer to Ethernet device.\n+ *\n+ * @return\n+ * 0 on success, negative errno value otherwise and rte_errno is set.\n+ */\n+int mlx5_get_flag_dropless_rq(struct rte_eth_dev *dev)\n+{\n+\tstruct {\n+\t\tstruct ethtool_sset_info hdr;\n+\t\tuint32_t buf[1];\n+\t} sset_info;\n+\tstruct ethtool_drvinfo drvinfo;\n+\tstruct ifreq ifr;\n+\tstruct ethtool_gstrings *strings = NULL;\n+\tstruct ethtool_value flags;\n+\tint32_t str_sz;\n+\tint32_t len;\n+\tint32_t i;\n+\tint ret;\n+\n+\tsset_info.hdr.cmd = ETHTOOL_GSSET_INFO;\n+\tsset_info.hdr.reserved = 0;\n+\tsset_info.hdr.sset_mask = 1ULL << ETH_SS_PRIV_FLAGS;\n+\tifr.ifr_data = (caddr_t)&sset_info;\n+\tret = mlx5_ifreq(dev, SIOCETHTOOL, &ifr);\n+\tif (!ret) {\n+\t\tconst uint32_t *sset_lengths = sset_info.hdr.data;\n+\n+\t\tlen = sset_info.hdr.sset_mask ? sset_lengths[0] : 0;\n+\t} else if (ret == -EOPNOTSUPP) {\n+\t\tdrvinfo.cmd = ETHTOOL_GDRVINFO;\n+\t\tifr.ifr_data = (caddr_t)&drvinfo;\n+\t\tret = mlx5_ifreq(dev, SIOCETHTOOL, &ifr);\n+\t\tif (ret) {\n+\t\t\tDRV_LOG(WARNING, \"port %u cannot get the driver info\",\n+\t\t\t\tdev->data->port_id);\n+\t\t\tgoto exit;\n+\t\t}\n+\t\tlen = *(uint32_t *)((char *)&drvinfo +\n+\t\t\toffsetof(struct ethtool_drvinfo, n_priv_flags));\n+\t} else {\n+\t\tDRV_LOG(WARNING, \"port %u cannot get the sset info\",\n+\t\t\tdev->data->port_id);\n+\t\tgoto exit;\n+\t}\n+\tif (!len) {\n+\t\tDRV_LOG(WARNING, \"port %u does not have private flag\",\n+\t\t\tdev->data->port_id);\n+\t\trte_errno = EOPNOTSUPP;\n+\t\tret = -rte_errno;\n+\t\tgoto exit;\n+\t} else if (len > 32) {\n+\t\tDRV_LOG(WARNING, \"port %u maximal private flags number is 32\",\n+\t\t\tdev->data->port_id);\n+\t\tlen = 32;\n+\t}\n+\tstr_sz = ETH_GSTRING_LEN * len;\n+\tstrings = (struct ethtool_gstrings *)\n+\t\t mlx5_malloc(0, str_sz + sizeof(struct ethtool_gstrings), 0,\n+\t\t\t SOCKET_ID_ANY);\n+\tif (!strings) {\n+\t\tDRV_LOG(WARNING, \"port %u unable to allocate memory for\"\n+\t\t\t\" private flags\", dev->data->port_id);\n+\t\trte_errno = ENOMEM;\n+\t\tret = -rte_errno;\n+\t\tgoto exit;\n+\t}\n+\tstrings->cmd = ETHTOOL_GSTRINGS;\n+\tstrings->string_set = ETH_SS_PRIV_FLAGS;\n+\tstrings->len = len;\n+\tifr.ifr_data = (caddr_t)strings;\n+\tret = mlx5_ifreq(dev, SIOCETHTOOL, &ifr);\n+\tif (ret) {\n+\t\tDRV_LOG(WARNING, \"port %u unable to get private flags strings\",\n+\t\t\tdev->data->port_id);\n+\t\tgoto exit;\n+\t}\n+\tfor (i = 0; i < len; i++) {\n+\t\tstrings->data[(i + 1) * ETH_GSTRING_LEN - 1] = 0;\n+\t\tif (!strcmp((const char *)strings->data + i * ETH_GSTRING_LEN,\n+\t\t\t \"dropless_rq\"))\n+\t\t\tbreak;\n+\t}\n+\tif (i == len) {\n+\t\tDRV_LOG(WARNING, \"port %u does not support dropless_rq\",\n+\t\t\tdev->data->port_id);\n+\t\trte_errno = EOPNOTSUPP;\n+\t\tret = -rte_errno;\n+\t\tgoto exit;\n+\t}\n+\tflags.cmd = ETHTOOL_GPFLAGS;\n+\tifr.ifr_data = (caddr_t)&flags;\n+\tret = mlx5_ifreq(dev, SIOCETHTOOL, &ifr);\n+\tif (ret) {\n+\t\tDRV_LOG(WARNING, \"port %u unable to get private flags status\",\n+\t\t\tdev->data->port_id);\n+\t\tgoto exit;\n+\t}\n+\tif (!(flags.data & (1U << i)))\n+\t\tDRV_LOG(WARNING, \"port %u dropless_rq flag is off, no rearming\",\n+\t\t\tdev->data->port_id);\n+\telse\n+\t\tDRV_LOG(DEBUG, \"port %u support dropless_rq with rearming\",\n+\t\t\tdev->data->port_id);\n+exit:\n+\tmlx5_free(strings);\n+\treturn ret;\n+}\ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex 8d32d55c9a..e0f40ce31a 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -1599,6 +1599,7 @@ int mlx5_os_read_dev_stat(struct mlx5_priv *priv,\n int mlx5_os_read_dev_counters(struct rte_eth_dev *dev, uint64_t *stats);\n int mlx5_os_get_stats_n(struct rte_eth_dev *dev);\n void mlx5_os_stats_init(struct rte_eth_dev *dev);\n+int mlx5_get_flag_dropless_rq(struct rte_eth_dev *dev);\n \n /* mlx5_mac.c */\n \ndiff --git a/drivers/net/mlx5/mlx5_trigger.c b/drivers/net/mlx5/mlx5_trigger.c\nindex ebeeae279e..2644855483 100644\n--- a/drivers/net/mlx5/mlx5_trigger.c\n+++ b/drivers/net/mlx5/mlx5_trigger.c\n@@ -1126,6 +1126,16 @@ mlx5_dev_start(struct rte_eth_dev *dev)\n \t\t\tdev->data->port_id, strerror(rte_errno));\n \t\tgoto error;\n \t}\n+\tif (priv->config.std_delay_drop || priv->config.hp_delay_drop) {\n+\t\tif (!priv->config.vf && !priv->config.sf &&\n+\t\t !priv->representor) {\n+\t\t\t(void)mlx5_get_flag_dropless_rq(dev);\n+\t\t} else {\n+\t\t\tDRV_LOG(INFO,\n+\t\t\t\t\"port %u doesn't support dropless_rq flag\",\n+\t\t\t\tdev->data->port_id);\n+\t\t}\n+\t}\n \tret = mlx5_rxq_start(dev);\n \tif (ret) {\n \t\tDRV_LOG(ERR, \"port %u Rx queue allocation failed: %s\",\n", "prefixes": [ "3/4" ] }