From patchwork Thu Nov 4 11:26:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bing Zhao X-Patchwork-Id: 103740 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B4D88A0548; Thu, 4 Nov 2021 12:27:08 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 7CAD041144; Thu, 4 Nov 2021 12:27:08 +0100 (CET) Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2073.outbound.protection.outlook.com [40.107.92.73]) by mails.dpdk.org (Postfix) with ESMTP id 6CCD340DFD for ; Thu, 4 Nov 2021 12:27:06 +0100 (CET) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=I1zl12JqeHYYWPPVBYqmNmdRMRy8AnwNIdP7ooVWBT/smM8zIdLtdKs4LUmy7wjDlNJ7L/5GQvaGV0evap21ajDbmyzYAoaPhaEWvXWMAf+v/4NPKRrU8IFODQs2glAo0D/wFoFI9AvosKTEgw1wzXLWhwBnCHyS/sn4Ggvbq1Ck1kQtEotdf53KwgflwIDDYO2//Uw3/rUzRDveYdmNfHc7/mYGUvyZQIFXEYgmvC0DRXJB7xKUo9F8sfWC/AR2KLUPgP0fT6btL6P5Bf+dkGVey1+2+ES1Fd6O7BNYE0hKdn14Oc3oWsPOE884GDdlr4uFBRC6pvK3bCMGGva5gw== ARC-Message-Signature: i=1; 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monjalon.net; dkim=none (message not signed) header.d=none;monjalon.net; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by CO1NAM11FT064.mail.protection.outlook.com (10.13.175.77) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4669.10 via Frontend Transport; Thu, 4 Nov 2021 11:27:04 +0000 Received: from nvidia.com (172.20.187.5) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 4 Nov 2021 11:27:01 +0000 From: Bing Zhao To: , CC: , , , Date: Thu, 4 Nov 2021 13:26:41 +0200 Message-ID: <20211104112644.17278-2-bingz@nvidia.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20211104112644.17278-1-bingz@nvidia.com> References: <20211104112644.17278-1-bingz@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.187.5] X-ClientProxiedBy: HQMAIL101.nvidia.com (172.20.187.10) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 8984a557-77b0-4023-55c5-08d99f860719 X-MS-TrafficTypeDiagnostic: MW3PR12MB4524: X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2958; 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CAT:NONE; SFS:(4636009)(46966006)(36840700001)(1076003)(2906002)(7636003)(54906003)(8676002)(356005)(70206006)(36756003)(6666004)(5660300002)(70586007)(6636002)(8936002)(82310400003)(16526019)(186003)(36860700001)(2616005)(107886003)(426003)(508600001)(6286002)(86362001)(55016002)(47076005)(7696005)(26005)(4326008)(316002)(110136005)(336012); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Nov 2021 11:27:04.2071 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8984a557-77b0-4023-55c5-08d99f860719 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT064.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW3PR12MB4524 Subject: [dpdk-dev] [PATCH 1/4] common/mlx5: support delay drop capabilities query X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The "rq_delay_drop" capability in the HCA_CAP is checked and saved in the output data structure for the future usage. Signed-off-by: Bing Zhao --- drivers/common/mlx5/mlx5_devx_cmds.c | 1 + drivers/common/mlx5/mlx5_devx_cmds.h | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c index 12c114a91b..eaf1dd5046 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.c +++ b/drivers/common/mlx5/mlx5_devx_cmds.c @@ -962,6 +962,7 @@ mlx5_devx_cmd_query_hca_attr(void *ctx, attr->ct_offload = !!(MLX5_GET64(cmd_hca_cap, hcattr, general_obj_types) & MLX5_GENERAL_OBJ_TYPES_CAP_CONN_TRACK_OFFLOAD); + attr->rq_delay_drop = MLX5_GET(cmd_hca_cap, hcattr, rq_delay_drop); if (attr->qos.sup) { hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP | diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h index 2326f1e968..25e2814ac0 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.h +++ b/drivers/common/mlx5/mlx5_devx_cmds.h @@ -176,6 +176,7 @@ struct mlx5_hca_attr { uint32_t swp_csum:1; uint32_t swp_lso:1; uint32_t lro_max_msg_sz_mode:2; + uint32_t rq_delay_drop:1; uint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS]; uint16_t lro_min_mss_size; uint32_t flex_parser_protocols; From patchwork Thu Nov 4 11:26:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bing Zhao X-Patchwork-Id: 103742 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9B673A0548; Thu, 4 Nov 2021 12:27:21 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9180F426DE; Thu, 4 Nov 2021 12:27:12 +0100 (CET) Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2068.outbound.protection.outlook.com [40.107.243.68]) by mails.dpdk.org (Postfix) with ESMTP id 9CAEC426FA for ; Thu, 4 Nov 2021 12:27:10 +0100 (CET) ARC-Seal: i=1; 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Thu, 4 Nov 2021 11:27:07 +0000 Received: from nvidia.com (172.20.187.5) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 4 Nov 2021 11:27:04 +0000 From: Bing Zhao To: , CC: , , , Date: Thu, 4 Nov 2021 13:26:42 +0200 Message-ID: <20211104112644.17278-3-bingz@nvidia.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20211104112644.17278-1-bingz@nvidia.com> References: <20211104112644.17278-1-bingz@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.187.5] X-ClientProxiedBy: HQMAIL101.nvidia.com (172.20.187.10) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 73121d1a-5a7f-4728-3fc4-08d99f8608f3 X-MS-TrafficTypeDiagnostic: MN2PR12MB4424: X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7691; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Nov 2021 11:27:07.3049 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 73121d1a-5a7f-4728-3fc4-08d99f8608f3 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT054.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4424 Subject: [dpdk-dev] [PATCH 2/4] net/mlx5: add support for Rx queue delay drop X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" For an Ethernet RQ, packets received when receive WQEs are exhausted are dropped. This behavior prevents slow or malicious software entities at the host from affecting the network. While for hairpin cases, even if there is no software involved during the packet forwarding from Rx to Tx side, some hiccup in the hardware or back pressure from Tx side may still cause the WQEs to be exhausted. In certain scenarios it may be preferred to configure the device to avoid such packet drops, assuming the posting of WQEs will resume shortly. To support this, a new devarg "delay_drop_en" is introduced, by default, the delay drop is enabled for hairpin Rx queues and disabled for standard Rx queues. This value is used as a bit mask: - bit 0: enablement of standard Rx queue - bit 1: enablement of hairpin Rx queue And this attribute will be applied to all Rx queues of a device. If the hardware capabilities do not support this delay drop, all the Rx queues will still be created without this attribute, and the devarg setting will be ignored. Signed-off-by: Bing Zhao --- drivers/net/mlx5/linux/mlx5_os.c | 11 +++++++++++ drivers/net/mlx5/mlx5.c | 7 +++++++ drivers/net/mlx5/mlx5.h | 9 +++++++++ drivers/net/mlx5/mlx5_devx.c | 5 +++++ drivers/net/mlx5/mlx5_rx.h | 1 + 5 files changed, 33 insertions(+) diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c index f51da8c3a3..def2cca3cd 100644 --- a/drivers/net/mlx5/linux/mlx5_os.c +++ b/drivers/net/mlx5/linux/mlx5_os.c @@ -1506,6 +1506,15 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, goto error; #endif } + if (config->std_delay_drop || config->hp_delay_drop) { + if (!config->hca_attr.rq_delay_drop) { + config->std_delay_drop = 0; + config->hp_delay_drop = 0; + DRV_LOG(WARNING, + "dev_port-%u: Rxq delay drop is not supported", + priv->dev_port); + } + } if (sh->devx) { uint32_t reg[MLX5_ST_SZ_DW(register_mtutc)]; @@ -2075,6 +2084,8 @@ mlx5_os_config_default(struct mlx5_dev_config *config) config->decap_en = 1; config->log_hp_size = MLX5_ARG_UNSET; config->allow_duplicate_pattern = 1; + config->std_delay_drop = 0; + config->hp_delay_drop = 1; } /** diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c index dc15688f21..80a6692b94 100644 --- a/drivers/net/mlx5/mlx5.c +++ b/drivers/net/mlx5/mlx5.c @@ -183,6 +183,9 @@ /* Device parameter to configure implicit registration of mempool memory. */ #define MLX5_MR_MEMPOOL_REG_EN "mr_mempool_reg_en" +/* Device parameter to configure the delay drop when creating Rxqs. */ +#define MLX5_DELAY_DROP_EN "delay_drop_en" + /* Shared memory between primary and secondary processes. */ struct mlx5_shared_data *mlx5_shared_data; @@ -2095,6 +2098,9 @@ mlx5_args_check(const char *key, const char *val, void *opaque) config->decap_en = !!tmp; } else if (strcmp(MLX5_ALLOW_DUPLICATE_PATTERN, key) == 0) { config->allow_duplicate_pattern = !!tmp; + } else if (strcmp(MLX5_DELAY_DROP_EN, key) == 0) { + config->std_delay_drop = tmp & MLX5_DELAY_DROP_STANDARD; + config->hp_delay_drop = tmp & MLX5_DELAY_DROP_HAIRPIN; } else { DRV_LOG(WARNING, "%s: unknown parameter", key); rte_errno = EINVAL; @@ -2157,6 +2163,7 @@ mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs) MLX5_DECAP_EN, MLX5_ALLOW_DUPLICATE_PATTERN, MLX5_MR_MEMPOOL_REG_EN, + MLX5_DELAY_DROP_EN, NULL, }; struct rte_kvargs *kvlist; diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index 74af88ec19..8d32d55c9a 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -99,6 +99,13 @@ enum mlx5_flow_type { MLX5_FLOW_TYPE_MAXI, }; +/* The mode of delay drop for Rx queues. */ +enum mlx5_delay_drop_mode { + MLX5_DELAY_DROP_NONE = 0, /* All disabled. */ + MLX5_DELAY_DROP_STANDARD = RTE_BIT32(0), /* Standard queues enable. */ + MLX5_DELAY_DROP_HAIRPIN = RTE_BIT32(1), /* Hairpin queues enable. */ +}; + /* Hlist and list callback context. */ struct mlx5_flow_cb_ctx { struct rte_eth_dev *dev; @@ -264,6 +271,8 @@ struct mlx5_dev_config { unsigned int dv_miss_info:1; /* restore packet after partial hw miss */ unsigned int allow_duplicate_pattern:1; /* Allow/Prevent the duplicate rules pattern. */ + unsigned int std_delay_drop:1; /* Enable standard Rxq delay drop. */ + unsigned int hp_delay_drop:1; /* Enable hairpin Rxq delay drop. */ struct { unsigned int enabled:1; /* Whether MPRQ is enabled. */ unsigned int stride_num_n; /* Number of strides. */ diff --git a/drivers/net/mlx5/mlx5_devx.c b/drivers/net/mlx5/mlx5_devx.c index 424f77be79..2e1d849eab 100644 --- a/drivers/net/mlx5/mlx5_devx.c +++ b/drivers/net/mlx5/mlx5_devx.c @@ -280,6 +280,7 @@ mlx5_rxq_create_devx_rq_resources(struct rte_eth_dev *dev, MLX5_WQ_END_PAD_MODE_NONE; rq_attr.wq_attr.pd = cdev->pdn; rq_attr.counter_set_id = priv->counter_set_id; + rq_attr.delay_drop_en = rxq_data->delay_drop; /* Create RQ using DevX API. */ return mlx5_devx_rq_create(cdev->ctx, &rxq_ctrl->obj->rq_obj, wqe_size, log_desc_n, &rq_attr, rxq_ctrl->socket); @@ -443,6 +444,8 @@ mlx5_rxq_obj_hairpin_new(struct rte_eth_dev *dev, uint16_t idx) attr.wq_attr.log_hairpin_data_sz - MLX5_HAIRPIN_QUEUE_STRIDE; attr.counter_set_id = priv->counter_set_id; + rxq_data->delay_drop = priv->config.hp_delay_drop; + attr.delay_drop_en = priv->config.hp_delay_drop; tmpl->rq = mlx5_devx_cmd_create_rq(priv->sh->cdev->ctx, &attr, rxq_ctrl->socket); if (!tmpl->rq) { @@ -503,6 +506,7 @@ mlx5_rxq_devx_obj_new(struct rte_eth_dev *dev, uint16_t idx) DRV_LOG(ERR, "Failed to create CQ."); goto error; } + rxq_data->delay_drop = priv->config.std_delay_drop; /* Create RQ using DevX API. */ ret = mlx5_rxq_create_devx_rq_resources(dev, rxq_data); if (ret) { @@ -921,6 +925,7 @@ mlx5_rxq_devx_obj_drop_create(struct rte_eth_dev *dev) rxq_ctrl->priv = priv; rxq_ctrl->obj = rxq; rxq_data = &rxq_ctrl->rxq; + rxq_data->delay_drop = 0; /* Create CQ using DevX API. */ ret = mlx5_rxq_create_devx_cq_resources(dev, rxq_data); if (ret != 0) { diff --git a/drivers/net/mlx5/mlx5_rx.h b/drivers/net/mlx5/mlx5_rx.h index 69b1263339..05807764b8 100644 --- a/drivers/net/mlx5/mlx5_rx.h +++ b/drivers/net/mlx5/mlx5_rx.h @@ -92,6 +92,7 @@ struct mlx5_rxq_data { unsigned int lro:1; /* Enable LRO. */ unsigned int dynf_meta:1; /* Dynamic metadata is configured. */ unsigned int mcqe_format:3; /* CQE compression format. */ + unsigned int delay_drop:1; /* Enable delay drop. */ volatile uint32_t *rq_db; volatile uint32_t *cq_db; uint16_t port_id; From patchwork Thu Nov 4 11:26:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bing Zhao X-Patchwork-Id: 103743 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A5AD6A0548; Thu, 4 Nov 2021 12:27:28 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 812EC42701; Thu, 4 Nov 2021 12:27:14 +0100 (CET) Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2055.outbound.protection.outlook.com [40.107.220.55]) by mails.dpdk.org (Postfix) with ESMTP id D7E72426FC for ; Thu, 4 Nov 2021 12:27:12 +0100 (CET) ARC-Seal: i=1; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Nov 2021 11:27:09.8912 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 36c83fcc-ae64-4d05-331b-08d99f860a8e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT052.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW3PR12MB4393 Subject: [dpdk-dev] [PATCH 3/4] net/mlx5: support querying delay drop status via ethtool X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The delay drop is global per PF device and the kernel driver is taking care of the initialization and rearming. By default, the timeout value is set to activate the delay drop when the driver is loaded. A private flag "dropless_rq" is used to control the rearming. Only when it is on, the rearming will be handled once received a timeout event. Or else, the delay drop will be deactived after the first timeout and all the Rx queues won't have this feature. The PMD is trying to query this flag and warn the application when some queues are created with delay drop but the flag is off. Signed-off-by: Bing Zhao --- drivers/net/mlx5/linux/mlx5_ethdev_os.c | 113 ++++++++++++++++++++++++ drivers/net/mlx5/mlx5.h | 1 + drivers/net/mlx5/mlx5_trigger.c | 10 +++ 3 files changed, 124 insertions(+) diff --git a/drivers/net/mlx5/linux/mlx5_ethdev_os.c b/drivers/net/mlx5/linux/mlx5_ethdev_os.c index 9d0e491d0c..9255877dab 100644 --- a/drivers/net/mlx5/linux/mlx5_ethdev_os.c +++ b/drivers/net/mlx5/linux/mlx5_ethdev_os.c @@ -1630,3 +1630,116 @@ mlx5_get_mac(struct rte_eth_dev *dev, uint8_t (*mac)[RTE_ETHER_ADDR_LEN]) memcpy(mac, request.ifr_hwaddr.sa_data, RTE_ETHER_ADDR_LEN); return 0; } + +/* + * Query dropless_rq private flag provided by ETHTOOL. + * + * @param dev + * Pointer to Ethernet device. + * + * @return + * 0 on success, negative errno value otherwise and rte_errno is set. + */ +int mlx5_get_flag_dropless_rq(struct rte_eth_dev *dev) +{ + struct { + struct ethtool_sset_info hdr; + uint32_t buf[1]; + } sset_info; + struct ethtool_drvinfo drvinfo; + struct ifreq ifr; + struct ethtool_gstrings *strings = NULL; + struct ethtool_value flags; + int32_t str_sz; + int32_t len; + int32_t i; + int ret; + + sset_info.hdr.cmd = ETHTOOL_GSSET_INFO; + sset_info.hdr.reserved = 0; + sset_info.hdr.sset_mask = 1ULL << ETH_SS_PRIV_FLAGS; + ifr.ifr_data = (caddr_t)&sset_info; + ret = mlx5_ifreq(dev, SIOCETHTOOL, &ifr); + if (!ret) { + const uint32_t *sset_lengths = sset_info.hdr.data; + + len = sset_info.hdr.sset_mask ? sset_lengths[0] : 0; + } else if (ret == -EOPNOTSUPP) { + drvinfo.cmd = ETHTOOL_GDRVINFO; + ifr.ifr_data = (caddr_t)&drvinfo; + ret = mlx5_ifreq(dev, SIOCETHTOOL, &ifr); + if (ret) { + DRV_LOG(WARNING, "port %u cannot get the driver info", + dev->data->port_id); + goto exit; + } + len = *(uint32_t *)((char *)&drvinfo + + offsetof(struct ethtool_drvinfo, n_priv_flags)); + } else { + DRV_LOG(WARNING, "port %u cannot get the sset info", + dev->data->port_id); + goto exit; + } + if (!len) { + DRV_LOG(WARNING, "port %u does not have private flag", + dev->data->port_id); + rte_errno = EOPNOTSUPP; + ret = -rte_errno; + goto exit; + } else if (len > 32) { + DRV_LOG(WARNING, "port %u maximal private flags number is 32", + dev->data->port_id); + len = 32; + } + str_sz = ETH_GSTRING_LEN * len; + strings = (struct ethtool_gstrings *) + mlx5_malloc(0, str_sz + sizeof(struct ethtool_gstrings), 0, + SOCKET_ID_ANY); + if (!strings) { + DRV_LOG(WARNING, "port %u unable to allocate memory for" + " private flags", dev->data->port_id); + rte_errno = ENOMEM; + ret = -rte_errno; + goto exit; + } + strings->cmd = ETHTOOL_GSTRINGS; + strings->string_set = ETH_SS_PRIV_FLAGS; + strings->len = len; + ifr.ifr_data = (caddr_t)strings; + ret = mlx5_ifreq(dev, SIOCETHTOOL, &ifr); + if (ret) { + DRV_LOG(WARNING, "port %u unable to get private flags strings", + dev->data->port_id); + goto exit; + } + for (i = 0; i < len; i++) { + strings->data[(i + 1) * ETH_GSTRING_LEN - 1] = 0; + if (!strcmp((const char *)strings->data + i * ETH_GSTRING_LEN, + "dropless_rq")) + break; + } + if (i == len) { + DRV_LOG(WARNING, "port %u does not support dropless_rq", + dev->data->port_id); + rte_errno = EOPNOTSUPP; + ret = -rte_errno; + goto exit; + } + flags.cmd = ETHTOOL_GPFLAGS; + ifr.ifr_data = (caddr_t)&flags; + ret = mlx5_ifreq(dev, SIOCETHTOOL, &ifr); + if (ret) { + DRV_LOG(WARNING, "port %u unable to get private flags status", + dev->data->port_id); + goto exit; + } + if (!(flags.data & (1U << i))) + DRV_LOG(WARNING, "port %u dropless_rq flag is off, no rearming", + dev->data->port_id); + else + DRV_LOG(DEBUG, "port %u support dropless_rq with rearming", + dev->data->port_id); +exit: + mlx5_free(strings); + return ret; +} diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index 8d32d55c9a..e0f40ce31a 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -1599,6 +1599,7 @@ int mlx5_os_read_dev_stat(struct mlx5_priv *priv, int mlx5_os_read_dev_counters(struct rte_eth_dev *dev, uint64_t *stats); int mlx5_os_get_stats_n(struct rte_eth_dev *dev); void mlx5_os_stats_init(struct rte_eth_dev *dev); +int mlx5_get_flag_dropless_rq(struct rte_eth_dev *dev); /* mlx5_mac.c */ diff --git a/drivers/net/mlx5/mlx5_trigger.c b/drivers/net/mlx5/mlx5_trigger.c index ebeeae279e..2644855483 100644 --- a/drivers/net/mlx5/mlx5_trigger.c +++ b/drivers/net/mlx5/mlx5_trigger.c @@ -1126,6 +1126,16 @@ mlx5_dev_start(struct rte_eth_dev *dev) dev->data->port_id, strerror(rte_errno)); goto error; } + if (priv->config.std_delay_drop || priv->config.hp_delay_drop) { + if (!priv->config.vf && !priv->config.sf && + !priv->representor) { + (void)mlx5_get_flag_dropless_rq(dev); + } else { + DRV_LOG(INFO, + "port %u doesn't support dropless_rq flag", + dev->data->port_id); + } + } ret = mlx5_rxq_start(dev); if (ret) { DRV_LOG(ERR, "port %u Rx queue allocation failed: %s", From patchwork Thu Nov 4 11:26:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bing Zhao X-Patchwork-Id: 103744 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7FF9AA0C41; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Nov 2021 11:27:13.5121 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ba311906-c987-470c-b197-08d99f860ca6 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT052.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR12MB1621 Subject: [dpdk-dev] [PATCH 4/4] doc: update the description for Rx delay drop X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The release note and new device parameter "delay_drop_en" for the delay drop feature in mlx5.rst are updated. Signed-off-by: Bing Zhao --- doc/guides/nics/mlx5.rst | 26 ++++++++++++++++++++++++++ doc/guides/rel_notes/release_21_11.rst | 1 + 2 files changed, 27 insertions(+) diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst index bb92520dff..2874a34cb6 100644 --- a/doc/guides/nics/mlx5.rst +++ b/doc/guides/nics/mlx5.rst @@ -1123,6 +1123,27 @@ Driver options By default, the PMD will set this value to 1. +- ``delay_drop_en`` parameter [int] + + Bitmask value for the Rx queue delay drop attribute. Bit 0 is used for standard + Rx queue and bit 1 is used for hairpin Rx queue. + By default, the delay drop will be enabled for all hairpin Rx queues (if any) + and disabled for all standard Rx queues. It will be ignored if the NIC does + not support the attribute. + A timeout value is set in the driver to control the waiting time before dropping + a packet when there is no WQE available on a delay drop Rx queue. Once the timer + is expired, the delay drop will be deactivated for all queues. To re-activeate it, + a rearming is needed and now it is part of the kernel driver. + + To enable / disable the delay drop rearming, the private flag ``dropless_rq`` can + be set and queried via ethtool: + + - ethtool --set-priv-flags dropless_rq on (/ off) + - ethtool --show-priv-flags + + The configuration flag is global per PF and can only be set on the PF, once it is on, + all the VFs', SFs' and representors' Rx queues will share the timer and rearming. + .. _mlx5_firmware_config: Firmware configuration @@ -1797,6 +1818,11 @@ Supported hardware offloads | | | | | rdma-core 35 | | | | | | ConnectX-6 Dx | +-----------------------+-----------------+-----------------+ + | Rxq Delay drop | | DPDK 21.11 | | DPDK 21.11 | + | | | OFED 5.5 | | OFED 5.5 | + | | | N/A | | N/A | + | | | ConnectX-5 | | ConnectX-5 | + +-----------------------+-----------------+-----------------+ .. table:: Minimal SW/HW versions for shared action offload :name: sact diff --git a/doc/guides/rel_notes/release_21_11.rst b/doc/guides/rel_notes/release_21_11.rst index 13d8330873..76d18aeb6b 100644 --- a/doc/guides/rel_notes/release_21_11.rst +++ b/doc/guides/rel_notes/release_21_11.rst @@ -191,6 +191,7 @@ New Features * Added implicit mempool registration to avoid data path hiccups (opt-out). * Added NIC offloads for the PMD on Windows (TSO, VLAN strip, CRC keep). * Added socket direct mode bonding support. + * Added delay drop support for Rx queue. * **Updated Solarflare network PMD.**