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GET /api/patches/95042/?format=api
{ "id": 95042, "url": "https://patches.dpdk.org/api/patches/95042/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210630070452.14055-3-getelson@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210630070452.14055-3-getelson@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210630070452.14055-3-getelson@nvidia.com", "date": "2021-06-30T07:04:51", "name": "[2/3] net/mlx5: add flow rule match for IPv4 IHL field", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "27f31751e8d12b55ed260c8c682bea6f21feb6ea", "submitter": { "id": 1882, "url": "https://patches.dpdk.org/api/people/1882/?format=api", "name": "Gregory Etelson", "email": "getelson@nvidia.com" }, "delegate": { "id": 3268, "url": "https://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210630070452.14055-3-getelson@nvidia.com/mbox/", "series": [ { "id": 17542, "url": "https://patches.dpdk.org/api/series/17542/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=17542", "date": "2021-06-30T07:04:49", "name": "net/mlx5: add flow rule match for IPv4 IHL field", "version": 1, "mbox": "https://patches.dpdk.org/series/17542/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/95042/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/95042/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", 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SFS:(4636009)(39860400002)(396003)(376002)(346002)(136003)(36840700001)(46966006)(83380400001)(7636003)(356005)(6666004)(54906003)(8936002)(82740400003)(5660300002)(478600001)(26005)(1076003)(36860700001)(55016002)(2616005)(186003)(7696005)(86362001)(6916009)(16526019)(316002)(6286002)(107886003)(36756003)(8676002)(426003)(47076005)(70586007)(70206006)(2906002)(36906005)(82310400003)(336012)(4326008);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "30 Jun 2021 07:05:17.8503 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 2f163ead-d77a-4ea1-6130-08d93b956aeb", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT040.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MN2PR12MB3309", "Subject": "[dpdk-dev] [PATCH 2/3] net/mlx5: add flow rule match for IPv4 IHL\n field", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Provide flow rules capability to match on IPv4 IHL field.\nMinimal HCA firmware version requiredto offload IPv4 IHL is\nxx_30_2000.\n\nSigned-off-by: Gregory Etelson <getelson@nvidia.com>\nAcked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>\n---\n drivers/net/mlx5/mlx5_flow_dv.c | 31 +++++++++++++++++++++++--------\n 1 file changed, 23 insertions(+), 8 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c\nindex c5d4b01e57..155f686ad1 100644\n--- a/drivers/net/mlx5/mlx5_flow_dv.c\n+++ b/drivers/net/mlx5/mlx5_flow_dv.c\n@@ -2451,19 +2451,19 @@ flow_dv_validate_item_gtp_psc(const struct rte_flow_item *item,\n * 0 on success, a negative errno value otherwise and rte_errno is set.\n */\n static int\n-flow_dv_validate_item_ipv4(const struct rte_flow_item *item,\n-\t\t\t uint64_t item_flags,\n-\t\t\t uint64_t last_item,\n-\t\t\t uint16_t ether_type,\n-\t\t\t struct rte_flow_error *error)\n+flow_dv_validate_item_ipv4(struct rte_eth_dev *dev,\n+\t\t\t const struct rte_flow_item *item,\n+\t\t\t uint64_t item_flags, uint64_t last_item,\n+\t\t\t uint16_t ether_type, struct rte_flow_error *error)\n {\n \tint ret;\n+\tstruct mlx5_priv *priv = dev->data->dev_private;\n \tconst struct rte_flow_item_ipv4 *spec = item->spec;\n \tconst struct rte_flow_item_ipv4 *last = item->last;\n \tconst struct rte_flow_item_ipv4 *mask = item->mask;\n \trte_be16_t fragment_offset_spec = 0;\n \trte_be16_t fragment_offset_last = 0;\n-\tconst struct rte_flow_item_ipv4 nic_ipv4_mask = {\n+\tstruct rte_flow_item_ipv4 nic_ipv4_mask = {\n \t\t.hdr = {\n \t\t\t.src_addr = RTE_BE32(0xffffffff),\n \t\t\t.dst_addr = RTE_BE32(0xffffffff),\n@@ -2474,6 +2474,17 @@ flow_dv_validate_item_ipv4(const struct rte_flow_item *item,\n \t\t},\n \t};\n \n+\tif (mask && (mask->hdr.version_ihl & RTE_IPV4_HDR_IHL_MASK)) {\n+\t\tint tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);\n+\t\tbool ihl_cap = !tunnel ? priv->config.hca_attr.outer_ipv4_ihl :\n+\t\t\t priv->config.hca_attr.inner_ipv4_ihl;\n+\t\tif (!ihl_cap)\n+\t\t\treturn rte_flow_error_set(error, ENOTSUP,\n+\t\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ITEM,\n+\t\t\t\t\t\t item,\n+\t\t\t\t\t\t \"IPV4 ihl offload not supported\");\n+\t\tnic_ipv4_mask.hdr.version_ihl = mask->hdr.version_ihl;\n+\t}\n \tret = mlx5_flow_validate_item_ipv4(item, item_flags, last_item,\n \t\t\t\t\t ether_type, &nic_ipv4_mask,\n \t\t\t\t\t MLX5_ITEM_RANGE_ACCEPTED, error);\n@@ -6771,7 +6782,7 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,\n \t\tcase RTE_FLOW_ITEM_TYPE_IPV4:\n \t\t\tmlx5_flow_tunnel_ip_check(items, next_protocol,\n \t\t\t\t\t\t &item_flags, &tunnel);\n-\t\t\tret = flow_dv_validate_item_ipv4(items, item_flags,\n+\t\t\tret = flow_dv_validate_item_ipv4(dev, items, item_flags,\n \t\t\t\t\t\t\t last_item, ether_type,\n \t\t\t\t\t\t\t error);\n \t\t\tif (ret < 0)\n@@ -8154,7 +8165,7 @@ flow_dv_translate_item_ipv4(void *matcher, void *key,\n \tvoid *headers_v;\n \tchar *l24_m;\n \tchar *l24_v;\n-\tuint8_t tos;\n+\tuint8_t tos, ihl_m, ihl_v;\n \n \tif (inner) {\n \t\theaders_m = MLX5_ADDR_OF(fte_match_param, matcher,\n@@ -8183,6 +8194,10 @@ flow_dv_translate_item_ipv4(void *matcher, void *key,\n \t*(uint32_t *)l24_m = ipv4_m->hdr.src_addr;\n \t*(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;\n \ttos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;\n+\tihl_m = ipv4_m->hdr.version_ihl & RTE_IPV4_HDR_IHL_MASK;\n+\tihl_v = ipv4_v->hdr.version_ihl & RTE_IPV4_HDR_IHL_MASK;\n+\tMLX5_SET(fte_match_set_lyr_2_4, headers_m, ipv4_ihl, ihl_m);\n+\tMLX5_SET(fte_match_set_lyr_2_4, headers_v, ipv4_ihl, ihl_m & ihl_v);\n \tMLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,\n \t\t ipv4_m->hdr.type_of_service);\n \tMLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);\n", "prefixes": [ "2/3" ] }