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GET /api/patches/94100/?format=api
{ "id": 94100, "url": "https://patches.dpdk.org/api/patches/94100/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210613000652.28191-6-ajit.khaparde@broadcom.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210613000652.28191-6-ajit.khaparde@broadcom.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210613000652.28191-6-ajit.khaparde@broadcom.com", "date": "2021-06-13T00:05:59", "name": "[v2,05/58] net/bnxt: update TRUFLOW resources", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "ef38e738c360315710611ebc555a7a15214a1e33", "submitter": { "id": 501, "url": "https://patches.dpdk.org/api/people/501/?format=api", "name": "Ajit Khaparde", "email": "ajit.khaparde@broadcom.com" }, "delegate": { "id": 1766, "url": "https://patches.dpdk.org/api/users/1766/?format=api", "username": "ajitkhaparde", "first_name": "Ajit", "last_name": "Khaparde", "email": "ajit.khaparde@broadcom.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210613000652.28191-6-ajit.khaparde@broadcom.com/mbox/", "series": [ { "id": 17305, "url": "https://patches.dpdk.org/api/series/17305/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=17305", "date": "2021-06-13T00:05:54", "name": "enhancements to host based flow table management", "version": 2, "mbox": "https://patches.dpdk.org/series/17305/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/94100/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/94100/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id CA7F5A0C41;\n\tSun, 13 Jun 2021 02:07:43 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 57B7B4113D;\n\tSun, 13 Jun 2021 02:07:08 +0200 (CEST)", "from mail-pl1-f179.google.com (mail-pl1-f179.google.com\n [209.85.214.179])\n by mails.dpdk.org (Postfix) with ESMTP id 7F89F41122\n for <dev@dpdk.org>; Sun, 13 Jun 2021 02:07:05 +0200 (CEST)", "by mail-pl1-f179.google.com with SMTP id v12so4675910plo.10\n for <dev@dpdk.org>; Sat, 12 Jun 2021 17:07:05 -0700 (PDT)", "from localhost.localdomain ([192.19.223.252])\n by smtp.gmail.com with ESMTPSA id gg22sm12774609pjb.17.2021.06.12.17.07.02\n (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128);\n Sat, 12 Jun 2021 17:07:03 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com;\n s=google;\n h=from:to:cc:subject:date:message-id:in-reply-to:references\n :mime-version; bh=QNZP3v5FxCEFZ78ZJCCjUwUeYvzBzlj2Ok6Kt7hzr2I=;\n b=J8NgVF+ZxtCros9y1p+Rs6Vy4rQz5s2YsTaMdt1yigu/Hf7fSHy0aibbfj4mJmIcGc\n S+2uTb2gbJHF09Ib6w+cxFNYYFXZg4FpRy4BB2GkHwlk1KGYUDspZpygv5kN3Oh9h5kt\n SmGq7+JgcvJ6H9HPfqQWuj9cxJDI4YWNq0mak=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20161025;\n h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n :references:mime-version;\n bh=QNZP3v5FxCEFZ78ZJCCjUwUeYvzBzlj2Ok6Kt7hzr2I=;\n b=QTJD5x7FzyxJa07l0bHCxJZeYwhGwgv8MAsGnNSQRbpWLK/xbl3j+yxGJFCrBISc8j\n lrW59JeCLnQGnMd5fIuHGzAIG5eEY2Mgwp0ar5gWnhZAFS7H8KXsGeXMMBtkFU0D6DO6\n uHrv2ja9VGqrM2SD+bvaNj61aI4CskRi4KkcqFKaqFx0VjICeuMX4YoM0hMlTJLXLj1i\n mn+Wzade7V3d3l2fY9phpWnBDYMFRrD7Z1Jj7cR1P28BLZCMw7vT/HIOTqZ8kAhO2H6B\n XRHeEXwsqwrHgipKzyz0/acCIBErXzT44DUm2yXYSfvExsRQbymMzdPdh6wo1m2yS2cT\n NACA==", "X-Gm-Message-State": "AOAM531SJncRBE0QfM1m7HUE5dLhpYV59nn7vOr14J1FOUDitS76UCCB\n wwN6zq3x9RLCoB7vD1hkqYxWz4CEp9iRUJ0Ng0wDW4LL02B7sRDZLpO0TsRpQYqT+HVtRPWno9q\n VzCtrZn/9EWBFHTotMkMhmnnVPKQEsAzIJXhM/aQUZNJgxiM0dvhkTA2xwoL30vY=", "X-Google-Smtp-Source": "\n ABdhPJw54l7alHJ/RHN6riApC72Ud7GxEEw0L0wKO2+/ePxbk5sobmZnhl8GVKxiRJVD8WH6OCiK8g==", "X-Received": "by 2002:a17:90a:fc8e:: with SMTP id\n ci14mr4963667pjb.163.1623542823866;\n Sat, 12 Jun 2021 17:07:03 -0700 (PDT)", "From": "Ajit Khaparde <ajit.khaparde@broadcom.com>", "To": "dev@dpdk.org", "Cc": "Farah Smith <farah.smith@broadcom.com>,\n Randy Schacher <stuart.schacher@broadcom.com>,\n Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>,\n Jay Ding <jay.ding@broadcom.com>,\n Peter Spreadborough <peter.spreadborough@broadcom.com>", "Date": "Sat, 12 Jun 2021 17:05:59 -0700", "Message-Id": "<20210613000652.28191-6-ajit.khaparde@broadcom.com>", "X-Mailer": "git-send-email 2.21.1 (Apple Git-122.3)", "In-Reply-To": "<20210613000652.28191-1-ajit.khaparde@broadcom.com>", "References": "<20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com>\n <20210613000652.28191-1-ajit.khaparde@broadcom.com>", "MIME-Version": "1.0", "Content-Type": "multipart/signed; protocol=\"application/pkcs7-signature\";\n micalg=sha-256; boundary=\"00000000000055591a05c49a8503\"", "X-Content-Filtered-By": "Mailman/MimeDel 2.1.29", "Subject": "[dpdk-dev] [PATCH v2 05/58] net/bnxt: update TRUFLOW resources", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Farah Smith <farah.smith@broadcom.com>\n\n- Remove unused tables from tf_tbl_type\n- Encode flow type into flow handle (internal or external)\n- Clean up Whitney resource tables\n- Clean up Truflow CLI open tables and update Thor resources\n- Add Thor SRAM and external pool types to core API\n- Remove unneeded Stingray table reference\n\nSigned-off-by: Farah Smith <farah.smith@broadcom.com>\nSigned-off-by: Randy Schacher <stuart.schacher@broadcom.com>\nSigned-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>\nReviewed-by: Jay Ding <jay.ding@broadcom.com>\nReviewed-by: Peter Spreadborough <peter.spreadborough@broadcom.com>\nReviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>\n---\n drivers/net/bnxt/tf_core/tf_core.c | 9 +-\n drivers/net/bnxt/tf_core/tf_core.h | 83 +++++----\n drivers/net/bnxt/tf_core/tf_device.c | 5 +-\n drivers/net/bnxt/tf_core/tf_device_p4.c | 105 ++++-------\n drivers/net/bnxt/tf_core/tf_device_p4.h | 175 ++++++++++--------\n drivers/net/bnxt/tf_core/tf_device_p45.h | 105 -----------\n drivers/net/bnxt/tf_core/tf_device_p58.c | 61 +++---\n drivers/net/bnxt/tf_core/tf_device_p58.h | 6 +\n drivers/net/bnxt/tf_core/tf_em_common.c | 2 +-\n drivers/net/bnxt/tf_core/tf_em_internal.c | 2 +-\n drivers/net/bnxt/tf_core/tf_ext_flow_handle.h | 15 +-\n drivers/net/bnxt/tf_core/tf_msg.c | 3 +-\n drivers/net/bnxt/tf_core/tf_rm.c | 14 +-\n drivers/net/bnxt/tf_core/tf_shadow_tbl.c | 2 -\n drivers/net/bnxt/tf_core/tf_util.c | 8 +-\n 15 files changed, 246 insertions(+), 349 deletions(-)\n delete mode 100644 drivers/net/bnxt/tf_core/tf_device_p45.h", "diff": "diff --git a/drivers/net/bnxt/tf_core/tf_core.c b/drivers/net/bnxt/tf_core/tf_core.c\nindex b1ce4e721c..ebe0fc34aa 100644\n--- a/drivers/net/bnxt/tf_core/tf_core.c\n+++ b/drivers/net/bnxt/tf_core/tf_core.c\n@@ -19,6 +19,7 @@\n #include \"rand.h\"\n #include \"tf_common.h\"\n #include \"hwrm_tf.h\"\n+#include \"tf_ext_flow_handle.h\"\n \n int\n tf_open_session(struct tf *tfp,\n@@ -251,6 +252,7 @@ int tf_delete_em_entry(struct tf *tfp,\n \tstruct tf_session *tfs;\n \tstruct tf_dev_info *dev;\n \tint rc;\n+\tunsigned int flag = 0;\n \n \tTF_CHECK_PARMS2(tfp, parms);\n \n@@ -274,12 +276,11 @@ int tf_delete_em_entry(struct tf *tfp,\n \t\treturn rc;\n \t}\n \n-\tif (parms->mem == TF_MEM_EXTERNAL)\n-\t\trc = dev->ops->tf_dev_delete_ext_em_entry(tfp, parms);\n-\telse if (parms->mem == TF_MEM_INTERNAL)\n+\tTF_GET_FLAG_FROM_FLOW_HANDLE(parms->flow_handle, flag);\n+\tif ((flag & TF_FLAGS_FLOW_HANDLE_INTERNAL))\n \t\trc = dev->ops->tf_dev_delete_int_em_entry(tfp, parms);\n \telse\n-\t\treturn -EINVAL;\n+\t\trc = dev->ops->tf_dev_delete_ext_em_entry(tfp, parms);\n \n \tif (rc) {\n \t\tTFP_DRV_LOG(ERR,\ndiff --git a/drivers/net/bnxt/tf_core/tf_core.h b/drivers/net/bnxt/tf_core/tf_core.h\nindex 5e458c58fb..4fe0590569 100644\n--- a/drivers/net/bnxt/tf_core/tf_core.h\n+++ b/drivers/net/bnxt/tf_core/tf_core.h\n@@ -158,34 +158,40 @@ enum tf_device_type {\n */\n enum tf_identifier_type {\n \t/**\n+\t * WH/SR/TH/SR2\n \t * The L2 Context is returned from the L2 Ctxt TCAM lookup\n \t * and can be used in WC TCAM or EM keys to virtualize further\n \t * lookups.\n \t */\n \tTF_IDENT_TYPE_L2_CTXT_HIGH,\n \t/**\n+\t * WH/SR/TH/SR2\n \t * The L2 Context is returned from the L2 Ctxt TCAM lookup\n \t * and can be used in WC TCAM or EM keys to virtualize further\n \t * lookups.\n \t */\n \tTF_IDENT_TYPE_L2_CTXT_LOW,\n \t/**\n+\t * WH/SR/TH/SR2\n \t * The WC profile func is returned from the L2 Ctxt TCAM lookup\n \t * to enable virtualization of the profile TCAM.\n \t */\n \tTF_IDENT_TYPE_PROF_FUNC,\n \t/**\n+\t * WH/SR/TH/SR2\n \t * The WC profile ID is included in the WC lookup key\n \t * to enable virtualization of the WC TCAM hardware.\n \t */\n \tTF_IDENT_TYPE_WC_PROF,\n \t/**\n+\t * WH/SR/TH/SR2\n \t * The EM profile ID is included in the EM lookup key\n \t * to enable virtualization of the EM hardware. (not required for SR2\n \t * as it has table scope)\n \t */\n \tTF_IDENT_TYPE_EM_PROF,\n \t/**\n+\t * TH/SR2\n \t * The L2 func is included in the ILT result and from recycling to\n \t * enable virtualization of further lookups.\n \t */\n@@ -203,59 +209,63 @@ enum tf_identifier_type {\n enum tf_tbl_type {\n \t/* Internal */\n \n-\t/** Wh+/SR Action Record */\n+\t/** Wh+/SR/TH Action Record */\n \tTF_TBL_TYPE_FULL_ACT_RECORD,\n-\t/** Wh+/SR/Th Multicast Groups */\n+\t/** TH Compact Action Record */\n+\tTF_TBL_TYPE_COMPACT_ACT_RECORD,\n+\t/** (Future) Multicast Groups */\n \tTF_TBL_TYPE_MCAST_GROUPS,\n-\t/** Wh+/SR Action Encap 8 Bytes */\n+\t/** Wh+/SR/TH Action Encap 8 Bytes */\n \tTF_TBL_TYPE_ACT_ENCAP_8B,\n-\t/** Wh+/SR Action Encap 16 Bytes */\n+\t/** Wh+/SR/TH Action Encap 16 Bytes */\n \tTF_TBL_TYPE_ACT_ENCAP_16B,\n-\t/** Action Encap 32 Bytes */\n+\t/** WH+/SR/TH Action Encap 32 Bytes */\n \tTF_TBL_TYPE_ACT_ENCAP_32B,\n-\t/** Wh+/SR Action Encap 64 Bytes */\n+\t/** Wh+/SR/TH Action Encap 64 Bytes */\n \tTF_TBL_TYPE_ACT_ENCAP_64B,\n-\t/** Action Source Properties SMAC */\n+\t/** WH+/SR/TH Action Source Properties SMAC */\n \tTF_TBL_TYPE_ACT_SP_SMAC,\n-\t/** Wh+/SR Action Source Properties SMAC IPv4 */\n+\t/** Wh+/SR/TH Action Source Properties SMAC IPv4 */\n \tTF_TBL_TYPE_ACT_SP_SMAC_IPV4,\n-\t/** Action Source Properties SMAC IPv6 */\n+\t/** WH+/SR/TH Action Source Properties SMAC IPv6 */\n \tTF_TBL_TYPE_ACT_SP_SMAC_IPV6,\n-\t/** Wh+/SR Action Statistics 64 Bits */\n+\t/** Wh+/SR/TH Action Statistics 64 Bits */\n \tTF_TBL_TYPE_ACT_STATS_64,\n-\t/** Wh+/SR Action Modify L4 Src Port */\n-\tTF_TBL_TYPE_ACT_MODIFY_SPORT,\n-\t/** Wh+/SR Action Modify L4 Dest Port */\n-\tTF_TBL_TYPE_ACT_MODIFY_DPORT,\n \t/** Wh+/SR Action Modify IPv4 Source */\n \tTF_TBL_TYPE_ACT_MODIFY_IPV4,\n-\t/** Meter Profiles */\n+\t/** TH 8B Modify Record */\n+\tTF_TBL_TYPE_ACT_MODIFY_8B,\n+\t/** TH 16B Modify Record */\n+\tTF_TBL_TYPE_ACT_MODIFY_16B,\n+\t/** TH 32B Modify Record */\n+\tTF_TBL_TYPE_ACT_MODIFY_32B,\n+\t/** TH 64B Modify Record */\n+\tTF_TBL_TYPE_ACT_MODIFY_64B,\n+\t/** (Future) Meter Profiles */\n \tTF_TBL_TYPE_METER_PROF,\n-\t/** Meter Instance */\n+\t/** (Future) Meter Instance */\n \tTF_TBL_TYPE_METER_INST,\n-\t/** Mirror Config */\n+\t/** Wh+/SR/Th Mirror Config */\n \tTF_TBL_TYPE_MIRROR_CONFIG,\n-\t/** UPAR */\n+\t/** (Future) UPAR */\n \tTF_TBL_TYPE_UPAR,\n-\t/** SR2 Epoch 0 table */\n+\t/** (Future) SR2 Epoch 0 table */\n \tTF_TBL_TYPE_EPOCH0,\n-\t/** SR2 Epoch 1 table */\n+\t/** (Future) SR2 Epoch 1 table */\n \tTF_TBL_TYPE_EPOCH1,\n-\t/** SR2 Metadata */\n+\t/** (Future) TH/SR2 Metadata */\n \tTF_TBL_TYPE_METADATA,\n-\t/** SR2 CT State */\n+\t/** (Future) TH/SR2 CT State */\n \tTF_TBL_TYPE_CT_STATE,\n-\t/** SR2 Range Profile */\n+\t/** (Future) TH/SR2 Range Profile */\n \tTF_TBL_TYPE_RANGE_PROF,\n-\t/** SR2 Range Entry */\n+\t/** (Future) SR2 Range Entry */\n \tTF_TBL_TYPE_RANGE_ENTRY,\n-\t/** SR2 LAG Entry */\n+\t/** (Future) SR2 LAG Entry */\n \tTF_TBL_TYPE_LAG,\n-\t/** SR2 VNIC/SVIF Table */\n-\tTF_TBL_TYPE_VNIC_SVIF,\n-\t/** Th/SR2 EM Flexible Key builder */\n+\t/** TH/SR2 EM Flexible Key builder */\n \tTF_TBL_TYPE_EM_FKB,\n-\t/** Th/SR2 WC Flexible Key builder */\n+\t/** TH/SR2 WC Flexible Key builder */\n \tTF_TBL_TYPE_WC_FKB,\n \n \t/* External */\n@@ -263,9 +273,18 @@ enum tf_tbl_type {\n \t/**\n \t * External table type - initially 1 poolsize entries.\n \t * All External table types are associated with a table\n-\t * scope. Internal types are not.\n+\t * scope. Internal types are not. Currently this is\n+\t * a pool of 64B entries.\n \t */\n \tTF_TBL_TYPE_EXT,\n+\t/* (Future) SR2 32B External EM Action 32B Pool */\n+\tTF_TBL_TYPE_EXT_32B,\n+\t/* (Future) SR2 64B External EM Action 64B Pool */\n+\tTF_TBL_TYPE_EXT_64B,\n+\t/* (Future) SR2 96B External EM Action 96B Pool */\n+\tTF_TBL_TYPE_EXT_96B,\n+\t/* (Future) SR2 128B External EM Action 128B Pool */\n+\tTF_TBL_TYPE_EXT_128B,\n \tTF_TBL_TYPE_MAX\n };\n \n@@ -1998,8 +2017,8 @@ enum tf_if_tbl_type {\n \tTF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR,\n \t/** SR2 Ingress lookup table */\n \tTF_IF_TBL_TYPE_ILT,\n-\t/** SR2 VNIC/SVIF Table */\n-\tTF_IF_TBL_TYPE_VNIC_SVIF,\n+\t/** SR2 VNIC/SVIF Properties Table */\n+\tTF_IF_TBL_TYPE_VSPT,\n \tTF_IF_TBL_TYPE_MAX\n };\n \ndiff --git a/drivers/net/bnxt/tf_core/tf_device.c b/drivers/net/bnxt/tf_core/tf_device.c\nindex d4c93439ec..d072b9877c 100644\n--- a/drivers/net/bnxt/tf_core/tf_device.c\n+++ b/drivers/net/bnxt/tf_core/tf_device.c\n@@ -153,11 +153,8 @@ tf_dev_bind_p4(struct tf *tfp,\n \t/*\n \t * EEM\n \t */\n-\tif (dev_handle->type == TF_DEVICE_TYPE_WH)\n-\t\tem_cfg.cfg = tf_em_ext_p4;\n-\telse\n-\t\tem_cfg.cfg = tf_em_ext_p45;\n \n+\tem_cfg.cfg = tf_em_ext_p4;\n \trsv_cnt = tf_dev_reservation_check(tfp,\n \t\t\t\t\t TF_EM_TBL_TYPE_MAX,\n \t\t\t\t\t em_cfg.cfg,\ndiff --git a/drivers/net/bnxt/tf_core/tf_device_p4.c b/drivers/net/bnxt/tf_core/tf_device_p4.c\nindex 6b28f6ce59..f6c8f5efd0 100644\n--- a/drivers/net/bnxt/tf_core/tf_device_p4.c\n+++ b/drivers/net/bnxt/tf_core/tf_device_p4.c\n@@ -19,76 +19,41 @@\n #define TF_DEV_P4_PF_MASK 0xfUL\n \n const char *tf_resource_str_p4[CFA_RESOURCE_TYPE_P4_LAST + 1] = {\n-\t/* CFA_RESOURCE_TYPE_P4_MCG */\n-\t\"mc_group\",\n-\t/* CFA_RESOURCE_TYPE_P4_ENCAP_8B */\n-\t\"encap_8 \",\n-\t/* CFA_RESOURCE_TYPE_P4_ENCAP_16B */\n-\t\"encap_16\",\n-\t/* CFA_RESOURCE_TYPE_P4_ENCAP_64B */\n-\t\"encap_64\",\n-\t/* CFA_RESOURCE_TYPE_P4_SP_MAC */\n-\t\"sp_mac \",\n-\t/* CFA_RESOURCE_TYPE_P4_SP_MAC_IPV4 */\n-\t\"sp_macv4\",\n-\t/* CFA_RESOURCE_TYPE_P4_SP_MAC_IPV6 */\n-\t\"sp_macv6\",\n-\t/* CFA_RESOURCE_TYPE_P4_COUNTER_64B */\n-\t\"ctr_64b \",\n-\t/* CFA_RESOURCE_TYPE_P4_NAT_PORT */\n-\t\"nat_port\",\n-\t/* CFA_RESOURCE_TYPE_P4_NAT_IPV4 */\n-\t\"nat_ipv4\",\n-\t/* CFA_RESOURCE_TYPE_P4_METER */\n-\t\"meter \",\n-\t/* CFA_RESOURCE_TYPE_P4_FLOW_STATE */\n-\t\"flow_st \",\n-\t/* CFA_RESOURCE_TYPE_P4_FULL_ACTION */\n-\t\"full_act\",\n-\t/* CFA_RESOURCE_TYPE_P4_FORMAT_0_ACTION */\n-\t\"fmt0_act\",\n-\t/* CFA_RESOURCE_TYPE_P4_EXT_FORMAT_0_ACTION */\n-\t\"ext0_act\",\n-\t/* CFA_RESOURCE_TYPE_P4_FORMAT_1_ACTION */\n-\t\"fmt1_act\",\n-\t/* CFA_RESOURCE_TYPE_P4_FORMAT_2_ACTION */\n-\t\"fmt2_act\",\n-\t/* CFA_RESOURCE_TYPE_P4_FORMAT_3_ACTION */\n-\t\"fmt3_act\",\n-\t/* CFA_RESOURCE_TYPE_P4_FORMAT_4_ACTION */\n-\t\"fmt4_act\",\n-\t/* CFA_RESOURCE_TYPE_P4_FORMAT_5_ACTION */\n-\t\"fmt5_act\",\n-\t/* CFA_RESOURCE_TYPE_P4_FORMAT_6_ACTION */\n-\t\"fmt6_act\",\n-\t/* CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_HIGH */\n-\t\"l2ctx_hi\",\n-\t/* CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_LOW */\n-\t\"l2ctx_lo\",\n-\t/* CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_HIGH */\n-\t\"l2ctr_hi\",\n-\t/* CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_LOW */\n-\t\"l2ctr_lo\",\n-\t/* CFA_RESOURCE_TYPE_P4_PROF_FUNC */\n-\t\"prf_func\",\n-\t/* CFA_RESOURCE_TYPE_P4_PROF_TCAM */\n-\t\"prf_tcam\",\n-\t/* CFA_RESOURCE_TYPE_P4_EM_PROF_ID */\n-\t\"em_prof \",\n-\t/* CFA_RESOURCE_TYPE_P4_EM_REC */\n-\t\"em_rec \",\n-\t/* CFA_RESOURCE_TYPE_P4_WC_TCAM_PROF_ID */\n-\t\"wc_prof \",\n-\t/* CFA_RESOURCE_TYPE_P4_WC_TCAM */\n-\t\"wc_tcam \",\n-\t/* CFA_RESOURCE_TYPE_P4_METER_PROF */\n-\t\"mtr_prof\",\n-\t/* CFA_RESOURCE_TYPE_P4_MIRROR */\n-\t\"mirror \",\n-\t/* CFA_RESOURCE_TYPE_P4_SP_TCAM */\n-\t\"sp_tcam \",\n-\t/* CFA_RESOURCE_TYPE_P4_TBL_SCOPE */\n-\t\"tb_scope\",\n+\t[CFA_RESOURCE_TYPE_P4_MCG] = \"mc_group\",\n+\t[CFA_RESOURCE_TYPE_P4_ENCAP_8B] = \"encap_8 \",\n+\t[CFA_RESOURCE_TYPE_P4_ENCAP_16B] = \"encap_16\",\n+\t[CFA_RESOURCE_TYPE_P4_ENCAP_64B] = \"encap_64\",\n+\t[CFA_RESOURCE_TYPE_P4_SP_MAC] =\t\"sp_mac \",\n+\t[CFA_RESOURCE_TYPE_P4_SP_MAC_IPV4] = \"sp_macv4\",\n+\t[CFA_RESOURCE_TYPE_P4_SP_MAC_IPV6] = \"sp_macv6\",\n+\t[CFA_RESOURCE_TYPE_P4_COUNTER_64B] = \"ctr_64b \",\n+\t[CFA_RESOURCE_TYPE_P4_NAT_PORT] = \"nat_port\",\n+\t[CFA_RESOURCE_TYPE_P4_NAT_IPV4] = \"nat_ipv4\",\n+\t[CFA_RESOURCE_TYPE_P4_METER] = \"meter \",\n+\t[CFA_RESOURCE_TYPE_P4_FLOW_STATE] = \"flow_st \",\n+\t[CFA_RESOURCE_TYPE_P4_FULL_ACTION] = \"full_act\",\n+\t[CFA_RESOURCE_TYPE_P4_FORMAT_0_ACTION] = \"fmt0_act\",\n+\t[CFA_RESOURCE_TYPE_P4_EXT_FORMAT_0_ACTION] = \"ext0_act\",\n+\t[CFA_RESOURCE_TYPE_P4_FORMAT_1_ACTION] = \"fmt1_act\",\n+\t[CFA_RESOURCE_TYPE_P4_FORMAT_2_ACTION] = \"fmt2_act\",\n+\t[CFA_RESOURCE_TYPE_P4_FORMAT_3_ACTION] = \"fmt3_act\",\n+\t[CFA_RESOURCE_TYPE_P4_FORMAT_4_ACTION] = \"fmt4_act\",\n+\t[CFA_RESOURCE_TYPE_P4_FORMAT_5_ACTION] = \"fmt5_act\",\n+\t[CFA_RESOURCE_TYPE_P4_FORMAT_6_ACTION] = \"fmt6_act\",\n+\t[CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_HIGH] = \"l2ctx_hi\",\n+\t[CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_LOW] = \"l2ctx_lo\",\n+\t[CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_HIGH] = \"l2ctr_hi\",\n+\t[CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_LOW] = \"l2ctr_lo\",\n+\t[CFA_RESOURCE_TYPE_P4_PROF_FUNC] = \"prf_func\",\n+\t[CFA_RESOURCE_TYPE_P4_PROF_TCAM] = \"prf_tcam\",\n+\t[CFA_RESOURCE_TYPE_P4_EM_PROF_ID] = \"em_prof \",\n+\t[CFA_RESOURCE_TYPE_P4_EM_REC] = \"em_rec \",\n+\t[CFA_RESOURCE_TYPE_P4_WC_TCAM_PROF_ID] = \"wc_prof \",\n+\t[CFA_RESOURCE_TYPE_P4_WC_TCAM] = \"wc_tcam \",\n+\t[CFA_RESOURCE_TYPE_P4_METER_PROF] = \"mtr_prof\",\n+\t[CFA_RESOURCE_TYPE_P4_MIRROR] = \"mirror \",\n+\t[CFA_RESOURCE_TYPE_P4_SP_TCAM] = \"sp_tcam \",\n+\t[CFA_RESOURCE_TYPE_P4_TBL_SCOPE] = \"tb_scope\",\n };\n \n /**\ndiff --git a/drivers/net/bnxt/tf_core/tf_device_p4.h b/drivers/net/bnxt/tf_core/tf_device_p4.h\nindex bfad02a0b8..ee283ce29d 100644\n--- a/drivers/net/bnxt/tf_core/tf_device_p4.h\n+++ b/drivers/net/bnxt/tf_core/tf_device_p4.h\n@@ -13,98 +13,123 @@\n #include \"tf_global_cfg.h\"\n \n struct tf_rm_element_cfg tf_ident_p4[TF_IDENT_TYPE_MAX] = {\n-\t{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_HIGH },\n-\t{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_LOW },\n-\t{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_PROF_FUNC },\n-\t{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_WC_TCAM_PROF_ID },\n-\t{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_EM_PROF_ID },\n-\t/* CFA_RESOURCE_TYPE_P4_L2_FUNC */\n-\t{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID }\n+\t[TF_IDENT_TYPE_L2_CTXT_HIGH] = {\n+\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_HIGH\n+\t},\n+\t[TF_IDENT_TYPE_L2_CTXT_LOW] = {\n+\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_LOW\n+\t},\n+\t[TF_IDENT_TYPE_PROF_FUNC] = {\n+\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_PROF_FUNC\n+\t},\n+\t[TF_IDENT_TYPE_WC_PROF] = {\n+\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_WC_TCAM_PROF_ID\n+\t},\n+\t[TF_IDENT_TYPE_EM_PROF] = {\n+\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_EM_PROF_ID\n+\t},\n };\n \n struct tf_rm_element_cfg tf_tcam_p4[TF_TCAM_TBL_TYPE_MAX] = {\n-\t{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_HIGH },\n-\t{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_LOW },\n-\t{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_PROF_TCAM },\n-\t{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_WC_TCAM },\n-\t{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_TCAM },\n-\t/* CFA_RESOURCE_TYPE_P4_CT_RULE_TCAM */\n-\t{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },\n-\t/* CFA_RESOURCE_TYPE_P4_VEB_TCAM */\n-\t{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID }\n+\t[TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH] = {\n+\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_HIGH\n+\t},\n+\t[TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW] = {\n+\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_LOW\n+\t},\n+\t[TF_TCAM_TBL_TYPE_PROF_TCAM] = {\n+\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_PROF_TCAM\n+\t},\n+\t[TF_TCAM_TBL_TYPE_WC_TCAM] = {\n+\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_WC_TCAM\n+\t},\n+\t[TF_TCAM_TBL_TYPE_SP_TCAM] = {\n+\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_TCAM\n+\t},\n };\n \n struct tf_rm_element_cfg tf_tbl_p4[TF_TBL_TYPE_MAX] = {\n-\t{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_FULL_ACTION },\n-\t{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MCG },\n-\t{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_8B },\n-\t{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_16B },\n-\t/* CFA_RESOURCE_TYPE_P4_ENCAP_32B */\n-\t{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },\n-\t{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_64B },\n-\t{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC },\n-\t{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV4 },\n-\t{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV6 },\n-\t{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_COUNTER_64B },\n-\t{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_NAT_PORT },\n-\t{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_NAT_PORT },\n-\t{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_NAT_IPV4 },\n-\t{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER_PROF },\n-\t{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER },\n-\t{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MIRROR },\n-\t/* CFA_RESOURCE_TYPE_P4_UPAR */\n-\t{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },\n-\t/* CFA_RESOURCE_TYPE_P4_EPOC */\n-\t{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },\n-\t/* CFA_RESOURCE_TYPE_P4_METADATA */\n-\t{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },\n-\t/* CFA_RESOURCE_TYPE_P4_CT_STATE */\n-\t{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },\n-\t/* CFA_RESOURCE_TYPE_P4_RANGE_PROF */\n-\t{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },\n-\t/* CFA_RESOURCE_TYPE_P4_RANGE_ENTRY */\n-\t{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },\n-\t/* CFA_RESOURCE_TYPE_P4_LAG */\n-\t{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },\n-\t/* CFA_RESOURCE_TYPE_P4_VNIC_SVIF */\n-\t{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },\n-\t/* CFA_RESOURCE_TYPE_P4_EM_FBK */\n-\t{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },\n-\t/* CFA_RESOURCE_TYPE_P4_WC_FKB */\n-\t{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },\n-\t/* CFA_RESOURCE_TYPE_P4_EXT */\n-\t{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID }\n-};\n+\t[TF_TBL_TYPE_FULL_ACT_RECORD] = {\n+\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_FULL_ACTION\n+\t},\n+\t[TF_TBL_TYPE_MCAST_GROUPS] = {\n+\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MCG\n+\t},\n+\t[TF_TBL_TYPE_ACT_ENCAP_8B] = {\n+\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_8B\n+\t},\n+\t[TF_TBL_TYPE_ACT_ENCAP_16B] = {\n+\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_16B\n+\t},\n+\t[TF_TBL_TYPE_ACT_ENCAP_64B] = {\n+\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_64B\n+\t},\n+\t[TF_TBL_TYPE_ACT_SP_SMAC] = {\n+\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC\n+\t},\n+\t[TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = {\n+\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV4\n+\t},\n+\t[TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = {\n+\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV6\n+\t},\n+\t[TF_TBL_TYPE_ACT_STATS_64] = {\n+\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_COUNTER_64B\n+\t},\n+\t[TF_TBL_TYPE_ACT_MODIFY_IPV4] = {\n+\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_NAT_IPV4\n+\t},\n+\t[TF_TBL_TYPE_METER_PROF] = {\n+\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER_PROF\n+\t},\n+\t[TF_TBL_TYPE_METER_INST] = {\n+\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER\n+\t},\n+\t[TF_TBL_TYPE_MIRROR_CONFIG] = {\n+\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MIRROR\n+\t},\n \n-struct tf_rm_element_cfg tf_em_ext_p4[TF_EM_TBL_TYPE_MAX] = {\n-\t/* CFA_RESOURCE_TYPE_P4_EM_REC */\n-\t{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },\n-\t{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_TBL_SCOPE },\n };\n \n-struct tf_rm_element_cfg tf_em_ext_p45[TF_EM_TBL_TYPE_MAX] = {\n-\t/* CFA_RESOURCE_TYPE_P4_EM_REC */\n-\t{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },\n-\t{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_TBL_SCOPE },\n+struct tf_rm_element_cfg tf_em_ext_p4[TF_EM_TBL_TYPE_MAX] = {\n+\t[TF_EM_TBL_TYPE_TBL_SCOPE] = {\n+\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_TBL_SCOPE\n+\t},\n };\n \n struct tf_rm_element_cfg tf_em_int_p4[TF_EM_TBL_TYPE_MAX] = {\n-\t{ TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_EM_REC },\n-\t/* CFA_RESOURCE_TYPE_P4_TBL_SCOPE */\n-\t{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },\n+\t[TF_EM_TBL_TYPE_EM_RECORD] = {\n+\t\tTF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_EM_REC\n+\t},\n };\n \n+/* Note that hcapi_types from this table are from hcapi_cfa_p4.h\n+ * These are not CFA resource types because they are not allocated\n+ * CFA resources - they are identifiers for the interface tables\n+ * shared between the firmware and the host. It may make sense to\n+ * move these types to cfa_resource_types.h.\n+ */\n struct tf_if_tbl_cfg tf_if_tbl_p4[TF_IF_TBL_TYPE_MAX] = {\n-\t{ TF_IF_TBL_CFG, CFA_P4_TBL_PROF_SPIF_DFLT_L2CTXT },\n-\t{ TF_IF_TBL_CFG, CFA_P4_TBL_PROF_PARIF_DFLT_ACT_REC_PTR },\n-\t{ TF_IF_TBL_CFG, CFA_P4_TBL_PROF_PARIF_ERR_ACT_REC_PTR },\n-\t{ TF_IF_TBL_CFG, CFA_P4_TBL_LKUP_PARIF_DFLT_ACT_REC_PTR },\n-\t{ TF_IF_TBL_CFG_NULL, CFA_IF_TBL_TYPE_INVALID },\n-\t{ TF_IF_TBL_CFG_NULL, CFA_IF_TBL_TYPE_INVALID }\n+\t[TF_IF_TBL_TYPE_PROF_SPIF_DFLT_L2_CTXT] = {\n+\t\tTF_IF_TBL_CFG, CFA_P4_TBL_PROF_SPIF_DFLT_L2CTXT\n+\t},\n+\t[TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR] = {\n+\t\tTF_IF_TBL_CFG, CFA_P4_TBL_PROF_PARIF_DFLT_ACT_REC_PTR\n+\t},\n+\t[TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR] = {\n+\t\tTF_IF_TBL_CFG, CFA_P4_TBL_PROF_PARIF_ERR_ACT_REC_PTR\n+\t},\n+\t[TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR] = {\n+\t\tTF_IF_TBL_CFG, CFA_P4_TBL_LKUP_PARIF_DFLT_ACT_REC_PTR\n+\t},\n };\n \n struct tf_global_cfg_cfg tf_global_cfg_p4[TF_GLOBAL_CFG_TYPE_MAX] = {\n-\t{ TF_GLOBAL_CFG_CFG_HCAPI, TF_TUNNEL_ENCAP },\n-\t{ TF_GLOBAL_CFG_CFG_HCAPI, TF_ACTION_BLOCK },\n+\t[TF_TUNNEL_ENCAP] = {\n+\t\tTF_GLOBAL_CFG_CFG_HCAPI, TF_TUNNEL_ENCAP\n+\t},\n+\t[TF_ACTION_BLOCK] = {\n+\t\tTF_GLOBAL_CFG_CFG_HCAPI, TF_ACTION_BLOCK\n+\t},\n };\n #endif /* _TF_DEVICE_P4_H_ */\ndiff --git a/drivers/net/bnxt/tf_core/tf_device_p45.h b/drivers/net/bnxt/tf_core/tf_device_p45.h\ndeleted file mode 100644\nindex 13e04c63fc..0000000000\n--- a/drivers/net/bnxt/tf_core/tf_device_p45.h\n+++ /dev/null\n@@ -1,105 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(c) 2019-2021 Broadcom\n- * All rights reserved.\n- */\n-\n-#ifndef _TF_DEVICE_P45_H_\n-#define _TF_DEVICE_P45_H_\n-\n-#include <cfa_resource_types.h>\n-\n-#include \"tf_core.h\"\n-#include \"tf_rm.h\"\n-#include \"tf_if_tbl.h\"\n-#include \"tf_global_cfg.h\"\n-\n-struct tf_rm_element_cfg tf_ident_p4[TF_IDENT_TYPE_MAX] = {\n-\t{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_L2_CTXT_REMAP_HIGH },\n-\t{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_L2_CTXT_REMAP_LOW },\n-\t{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_PROF_FUNC },\n-\t{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_WC_TCAM_PROF_ID },\n-\t{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_EM_PROF_ID },\n-\t/* CFA_RESOURCE_TYPE_P45_L2_FUNC */\n-\t{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID }\n-};\n-\n-struct tf_rm_element_cfg tf_tcam_p4[TF_TCAM_TBL_TYPE_MAX] = {\n-\t{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_L2_CTXT_TCAM_HIGH },\n-\t{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_L2_CTXT_TCAM_LOW },\n-\t{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_PROF_TCAM },\n-\t{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_WC_TCAM },\n-\t{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_SP_TCAM },\n-\t/* CFA_RESOURCE_TYPE_P45_CT_RULE_TCAM */\n-\t{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },\n-\t/* CFA_RESOURCE_TYPE_P45_VEB_TCAM */\n-\t{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID }\n-};\n-\n-struct tf_rm_element_cfg tf_tbl_p4[TF_TBL_TYPE_MAX] = {\n-\t{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_FULL_ACTION },\n-\t{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_MCG },\n-\t{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_ENCAP_8B },\n-\t{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_ENCAP_16B },\n-\t/* CFA_RESOURCE_TYPE_P45_ENCAP_32B */\n-\t{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },\n-\t{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_ENCAP_64B },\n-\t{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_SP_MAC },\n-\t{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_SP_MAC_IPV4 },\n-\t{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_SP_MAC_IPV6 },\n-\t{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_COUNTER_64B },\n-\t{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_NAT_PORT },\n-\t{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_NAT_PORT },\n-\t{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_NAT_IPV4 },\n-\t{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_METER_PROF },\n-\t{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_METER },\n-\t{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_MIRROR },\n-\t/* CFA_RESOURCE_TYPE_P45_UPAR */\n-\t{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },\n-\t/* CFA_RESOURCE_TYPE_P45_EPOC */\n-\t{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },\n-\t/* CFA_RESOURCE_TYPE_P45_METADATA */\n-\t{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },\n-\t/* CFA_RESOURCE_TYPE_P45_CT_STATE */\n-\t{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },\n-\t/* CFA_RESOURCE_TYPE_P45_RANGE_PROF */\n-\t{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },\n-\t/* CFA_RESOURCE_TYPE_P45_RANGE_ENTRY */\n-\t{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },\n-\t/* CFA_RESOURCE_TYPE_P45_LAG */\n-\t{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },\n-\t/* CFA_RESOURCE_TYPE_P45_VNIC_SVIF */\n-\t{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },\n-\t/* CFA_RESOURCE_TYPE_P45_EM_FBK */\n-\t{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },\n-\t/* CFA_RESOURCE_TYPE_P45_WC_FKB */\n-\t{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },\n-\t/* CFA_RESOURCE_TYPE_P45_EXT */\n-\t{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID }\n-};\n-\n-struct tf_rm_element_cfg tf_em_ext_p4[TF_EM_TBL_TYPE_MAX] = {\n-\t/* CFA_RESOURCE_TYPE_P45_EM_REC */\n-\t{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },\n-\t{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_TBL_SCOPE },\n-};\n-\n-struct tf_rm_element_cfg tf_em_int_p4[TF_EM_TBL_TYPE_MAX] = {\n-\t{ TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P45_EM_REC },\n-\t/* CFA_RESOURCE_TYPE_P45_TBL_SCOPE */\n-\t{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },\n-};\n-\n-struct tf_if_tbl_cfg tf_if_tbl_p4[TF_IF_TBL_TYPE_MAX] = {\n-\t{ TF_IF_TBL_CFG, CFA_P4_TBL_PROF_SPIF_DFLT_L2CTXT },\n-\t{ TF_IF_TBL_CFG, CFA_P4_TBL_PROF_PARIF_DFLT_ACT_REC_PTR },\n-\t{ TF_IF_TBL_CFG, CFA_P4_TBL_PROF_PARIF_ERR_ACT_REC_PTR },\n-\t{ TF_IF_TBL_CFG, CFA_P4_TBL_LKUP_PARIF_DFLT_ACT_REC_PTR },\n-\t{ TF_IF_TBL_CFG_NULL, CFA_IF_TBL_TYPE_INVALID },\n-\t{ TF_IF_TBL_CFG_NULL, CFA_IF_TBL_TYPE_INVALID }\n-};\n-\n-struct tf_global_cfg_cfg tf_global_cfg_p4[TF_GLOBAL_CFG_TYPE_MAX] = {\n-\t{ TF_GLOBAL_CFG_CFG_HCAPI, TF_TUNNEL_ENCAP },\n-\t{ TF_GLOBAL_CFG_CFG_HCAPI, TF_ACTION_BLOCK },\n-};\n-#endif /* _TF_DEVICE_P45_H_ */\ndiff --git a/drivers/net/bnxt/tf_core/tf_device_p58.c b/drivers/net/bnxt/tf_core/tf_device_p58.c\nindex b4530f8762..7dd806000c 100644\n--- a/drivers/net/bnxt/tf_core/tf_device_p58.c\n+++ b/drivers/net/bnxt/tf_core/tf_device_p58.c\n@@ -18,47 +18,28 @@\n #define TF_DEV_P58_PARIF_MAX 16\n #define TF_DEV_P58_PF_MASK 0xfUL\n \n+/* For print alignment, make all entries 8 chars in this table */\n const char *tf_resource_str_p58[CFA_RESOURCE_TYPE_P58_LAST + 1] = {\n-\t/* CFA_RESOURCE_TYPE_P58_METER */\n-\t\"meter \",\n-\t/* CFA_RESOURCE_TYPE_P58_SRAM_BANK_0 */\n-\t\"sram_bk0\",\n-\t/* CFA_RESOURCE_TYPE_P58_SRAM_BANK_1 */\n-\t\"sram_bk1\",\n-\t/* CFA_RESOURCE_TYPE_P58_SRAM_BANK_2 */\n-\t\"sram_bk2\",\n-\t/* CFA_RESOURCE_TYPE_P58_SRAM_BANK_3 */\n-\t\"sram_bk3\",\n-\t/* CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_HIGH */\n-\t\"l2ctx_hi\",\n-\t/* CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_LOW */\n-\t\"l2ctx_lo\",\n-\t/* CFA_RESOURCE_TYPE_P58_L2_CTXT_REMAP_HIGH */\n-\t\"l2ctr_hi\",\n-\t/* CFA_RESOURCE_TYPE_P58_L2_CTXT_REMAP_LOW */\n-\t\"l2ctr_lo\",\n-\t/* CFA_RESOURCE_TYPE_P58_PROF_FUNC */\n-\t\"prf_func\",\n-\t/* CFA_RESOURCE_TYPE_P58_PROF_TCAM */\n-\t\"prf_tcam\",\n-\t/* CFA_RESOURCE_TYPE_P58_EM_PROF_ID */\n-\t\"em_prof \",\n-\t/* CFA_RESOURCE_TYPE_P58_WC_TCAM_PROF_ID */\n-\t\"wc_prof \",\n-\t/* CFA_RESOURCE_TYPE_P58_EM_REC */\n-\t\"em_rec \",\n-\t/* CFA_RESOURCE_TYPE_P58_WC_TCAM */\n-\t\"wc_tcam \",\n-\t/* CFA_RESOURCE_TYPE_P58_METER_PROF */\n-\t\"mtr_prof\",\n-\t/* CFA_RESOURCE_TYPE_P58_MIRROR */\n-\t\"mirror \",\n-\t/* CFA_RESOURCE_TYPE_P58_EM_FKB */\n-\t\"em_fkb \",\n-\t/* CFA_RESOURCE_TYPE_P58_WC_FKB */\n-\t\"wc_fkb \",\n-\t/* CFA_RESOURCE_TYPE_P58_VEB_TCAM */\n-\t\"veb \",\n+\t[CFA_RESOURCE_TYPE_P58_METER] = \"meter \",\n+\t[CFA_RESOURCE_TYPE_P58_SRAM_BANK_0] = \"sram_bk0\",\n+\t[CFA_RESOURCE_TYPE_P58_SRAM_BANK_1] = \"sram_bk1\",\n+\t[CFA_RESOURCE_TYPE_P58_SRAM_BANK_2] = \"sram_bk2\",\n+\t[CFA_RESOURCE_TYPE_P58_SRAM_BANK_3] = \"sram_bk3\",\n+\t[CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_HIGH] = \"l2ctx_hi\",\n+\t[CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_LOW] = \"l2ctx_lo\",\n+\t[CFA_RESOURCE_TYPE_P58_L2_CTXT_REMAP_HIGH] = \"l2ctr_hi\",\n+\t[CFA_RESOURCE_TYPE_P58_L2_CTXT_REMAP_LOW] = \"l2ctr_lo\",\n+\t[CFA_RESOURCE_TYPE_P58_PROF_FUNC] = \"prf_func\",\n+\t[CFA_RESOURCE_TYPE_P58_PROF_TCAM] = \"prf_tcam\",\n+\t[CFA_RESOURCE_TYPE_P58_EM_PROF_ID] = \"em_prof \",\n+\t[CFA_RESOURCE_TYPE_P58_WC_TCAM_PROF_ID] = \"wc_prof \",\n+\t[CFA_RESOURCE_TYPE_P58_EM_REC] = \"em_rec \",\n+\t[CFA_RESOURCE_TYPE_P58_WC_TCAM] = \"wc_tcam \",\n+\t[CFA_RESOURCE_TYPE_P58_METER_PROF] = \"mtr_prof\",\n+\t[CFA_RESOURCE_TYPE_P58_MIRROR] = \"mirror \",\n+\t[CFA_RESOURCE_TYPE_P58_EM_FKB] = \"em_fkb \",\n+\t[CFA_RESOURCE_TYPE_P58_WC_FKB] = \"wc_fkb \",\n+\t[CFA_RESOURCE_TYPE_P58_VEB_TCAM] = \"veb \",\n };\n \n /**\ndiff --git a/drivers/net/bnxt/tf_core/tf_device_p58.h b/drivers/net/bnxt/tf_core/tf_device_p58.h\nindex 3d6e3240bf..de7bb1cd76 100644\n--- a/drivers/net/bnxt/tf_core/tf_device_p58.h\n+++ b/drivers/net/bnxt/tf_core/tf_device_p58.h\n@@ -49,6 +49,12 @@ struct tf_rm_element_cfg tf_tcam_p58[TF_TCAM_TBL_TYPE_MAX] = {\n };\n \n struct tf_rm_element_cfg tf_tbl_p58[TF_TBL_TYPE_MAX] = {\n+\t[TF_TBL_TYPE_EM_FKB] = {\n+\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_EM_FKB\n+\t},\n+\t[TF_TBL_TYPE_WC_FKB] = {\n+\t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_WC_FKB\n+\t},\n \t[TF_TBL_TYPE_METER_PROF] = {\n \t\tTF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER_PROF\n \t},\ndiff --git a/drivers/net/bnxt/tf_core/tf_em_common.c b/drivers/net/bnxt/tf_core/tf_em_common.c\nindex ddc6b3c4dd..6cd6086685 100644\n--- a/drivers/net/bnxt/tf_core/tf_em_common.c\n+++ b/drivers/net/bnxt/tf_core/tf_em_common.c\n@@ -777,7 +777,7 @@ tf_insert_eem_entry(struct tf_tbl_scope_cb *tbl_scope_cb,\n \tTF_SET_FIELDS_IN_FLOW_HANDLE(parms->flow_handle,\n \t\t\t\t 0,\n \t\t\t\t 0,\n-\t\t\t\t 0,\n+\t\t\t\t TF_FLAGS_FLOW_HANDLE_EXTERNAL,\n \t\t\t\t index,\n \t\t\t\t 0,\n \t\t\t\t table_type);\ndiff --git a/drivers/net/bnxt/tf_core/tf_em_internal.c b/drivers/net/bnxt/tf_core/tf_em_internal.c\nindex 62ccd7b78f..bdffd801b3 100644\n--- a/drivers/net/bnxt/tf_core/tf_em_internal.c\n+++ b/drivers/net/bnxt/tf_core/tf_em_internal.c\n@@ -203,7 +203,7 @@ tf_em_insert_int_entry(struct tf *tfp,\n \tTF_SET_FIELDS_IN_FLOW_HANDLE(parms->flow_handle,\n \t\t\t\t (uint32_t)num_of_entries,\n \t\t\t\t 0,\n-\t\t\t\t 0,\n+\t\t\t\t TF_FLAGS_FLOW_HANDLE_INTERNAL,\n \t\t\t\t rptr_index,\n \t\t\t\t rptr_entry,\n \t\t\t\t 0);\ndiff --git a/drivers/net/bnxt/tf_core/tf_ext_flow_handle.h b/drivers/net/bnxt/tf_core/tf_ext_flow_handle.h\nindex 9eb5aeb771..bf6dbcd238 100644\n--- a/drivers/net/bnxt/tf_core/tf_ext_flow_handle.h\n+++ b/drivers/net/bnxt/tf_core/tf_ext_flow_handle.h\n@@ -19,6 +19,9 @@\n #define TF_HASH_TYPE_FLOW_HANDLE_MASK\t\t0x0000000100000000ULL\n #define TF_HASH_TYPE_FLOW_HANDLE_SFT\t\t32\n \n+#define TF_FLAGS_FLOW_HANDLE_INTERNAL\t\t0x2\n+#define TF_FLAGS_FLOW_HANDLE_EXTERNAL\t\t0x0\n+\n #define TF_FLOW_HANDLE_MASK (TF_NUM_KEY_ENTRIES_FLOW_HANDLE_MASK |\t\\\n \t\t\t\tTF_FLOW_TYPE_FLOW_HANDLE_MASK |\t\t\\\n \t\t\t\tTF_FLAGS_FLOW_HANDLE_MASK |\t\t\\\n@@ -92,15 +95,23 @@ do {\t\t\t\t\t\t\t\t\t\\\n \n #define TF_GET_NUM_KEY_ENTRIES_FROM_FLOW_HANDLE(flow_handle,\t\t\\\n \t\t\t\t\t num_key_entries)\t\t\\\n+do {\t\t\t\t\t\t\t\t\t\\\n \t(num_key_entries =\t\t\t\t\t\t\\\n \t\t(((flow_handle) & TF_NUM_KEY_ENTRIES_FLOW_HANDLE_MASK) >> \\\n-\t\t TF_NUM_KEY_ENTRIES_FLOW_HANDLE_SFT))\t\t\\\n+\t\t TF_NUM_KEY_ENTRIES_FLOW_HANDLE_SFT));\t\t\\\n+} while (0)\n \n #define TF_GET_ENTRY_NUM_FROM_FLOW_HANDLE(flow_handle,\t\t\\\n \t\t\t\t\t entry_num)\t\t\\\n+do {\t\t\t\t\t\t\t\t\t\\\n \t(entry_num =\t\t\t\t\t\t\\\n \t\t(((flow_handle) & TF_ENTRY_NUM_FLOW_HANDLE_MASK) >> \\\n-\t\t TF_ENTRY_NUM_FLOW_HANDLE_SFT))\t\t\\\n+\t\t TF_ENTRY_NUM_FLOW_HANDLE_SFT));\t\t\\\n+} while (0)\n+\n+#define TF_GET_FLAG_FROM_FLOW_HANDLE(flow_handle, flag)\t\t\\\n+\t(flag =\t(((flow_handle) & TF_FLAGS_FLOW_HANDLE_MASK) >>\\\n+\t\t TF_FLAGS_FLOW_HANDLE_SFT))\n \n /*\n * 32 bit Flow ID handlers\ndiff --git a/drivers/net/bnxt/tf_core/tf_msg.c b/drivers/net/bnxt/tf_core/tf_msg.c\nindex 1007211363..be30d4a09f 100644\n--- a/drivers/net/bnxt/tf_core/tf_msg.c\n+++ b/drivers/net/bnxt/tf_core/tf_msg.c\n@@ -415,7 +415,6 @@ tf_msg_session_resc_qcaps(struct tf *tfp,\n \n \t/* Post process the response */\n \tdata = (struct tf_rm_resc_req_entry *)qcaps_buf.va_addr;\n-\n \tfor (i = 0; i < size; i++) {\n \t\tquery[i].type = tfp_le_to_cpu_32(data[i].type);\n \t\tquery[i].min = tfp_le_to_cpu_16(data[i].min);\n@@ -1462,7 +1461,7 @@ tf_msg_set_global_cfg(struct tf *tfp,\n \t/* Only set mask if pointer is provided\n \t */\n \tif (params->config_mask) {\n-\t\ttfp_memcpy(req.data + params->config_sz_in_bytes,\n+\t\ttfp_memcpy(req.mask,\n \t\t\t params->config_mask,\n \t\t\t params->config_sz_in_bytes);\n \t}\ndiff --git a/drivers/net/bnxt/tf_core/tf_rm.c b/drivers/net/bnxt/tf_core/tf_rm.c\nindex 2c08fb80fe..19de6e4c63 100644\n--- a/drivers/net/bnxt/tf_core/tf_rm.c\n+++ b/drivers/net/bnxt/tf_core/tf_rm.c\n@@ -486,14 +486,20 @@ tf_rm_create_db(struct tf *tfp,\n \t\t\t\treq[j].max = parms->alloc_cnt[i];\n \t\t\t\tj++;\n \t\t\t} else {\n+\t\t\t\tconst char *type_str;\n+\t\t\t\tuint16_t hcapi_type = parms->cfg[i].hcapi_type;\n+\n+\t\t\t\tdev->ops->tf_dev_get_resource_str(tfp,\n+\t\t\t\t\t\t\t\t hcapi_type,\n+\t\t\t\t\t\t\t\t &type_str);\n \t\t\t\tTFP_DRV_LOG(ERR,\n-\t\t\t\t\t \"%s: Resource failure, type:%d\\n\",\n-\t\t\t\t\t tf_dir_2_str(parms->dir),\n-\t\t\t\t\t parms->cfg[i].hcapi_type);\n+\t\t\t\t\t\"%s: Resource failure, type:%d:%s\\n\",\n+\t\t\t\t\ttf_dir_2_str(parms->dir),\n+\t\t\t\t\thcapi_type, type_str);\n \t\t\t\tTFP_DRV_LOG(ERR,\n \t\t\t\t\t\"req:%d, avail:%d\\n\",\n \t\t\t\t\tparms->alloc_cnt[i],\n-\t\t\t\t\tquery[parms->cfg[i].hcapi_type].max);\n+\t\t\t\t\tquery[hcapi_type].max);\n \t\t\t\treturn -EINVAL;\n \t\t\t}\n \t\t}\ndiff --git a/drivers/net/bnxt/tf_core/tf_shadow_tbl.c b/drivers/net/bnxt/tf_core/tf_shadow_tbl.c\nindex 014e4f3c83..396ebdb0a9 100644\n--- a/drivers/net/bnxt/tf_core/tf_shadow_tbl.c\n+++ b/drivers/net/bnxt/tf_core/tf_shadow_tbl.c\n@@ -177,8 +177,6 @@ static int tf_shadow_tbl_is_searchable(enum tf_tbl_type type)\n \tcase TF_TBL_TYPE_ACT_SP_SMAC_IPV4:\n \tcase TF_TBL_TYPE_ACT_SP_SMAC_IPV6:\n \tcase TF_TBL_TYPE_ACT_MODIFY_IPV4:\n-\tcase TF_TBL_TYPE_ACT_MODIFY_SPORT:\n-\tcase TF_TBL_TYPE_ACT_MODIFY_DPORT:\n \t\trc = 1;\n \t\tbreak;\n \tdefault:\ndiff --git a/drivers/net/bnxt/tf_core/tf_util.c b/drivers/net/bnxt/tf_core/tf_util.c\nindex ca37df5102..74c8f26204 100644\n--- a/drivers/net/bnxt/tf_core/tf_util.c\n+++ b/drivers/net/bnxt/tf_core/tf_util.c\n@@ -88,12 +88,8 @@ tf_tbl_type_2_str(enum tf_tbl_type tbl_type)\n \t\treturn \"Source Properties SMAC IPv6\";\n \tcase TF_TBL_TYPE_ACT_STATS_64:\n \t\treturn \"Stats 64B\";\n-\tcase TF_TBL_TYPE_ACT_MODIFY_SPORT:\n-\t\treturn \"NAT Source Port\";\n-\tcase TF_TBL_TYPE_ACT_MODIFY_DPORT:\n-\t\treturn \"NAT Destination Port\";\n \tcase TF_TBL_TYPE_ACT_MODIFY_IPV4:\n-\t\treturn \"NAT IPv4\";\n+\t\treturn \"Modify IPv4\";\n \tcase TF_TBL_TYPE_METER_PROF:\n \t\treturn \"Meter Profile\";\n \tcase TF_TBL_TYPE_METER_INST:\n@@ -116,8 +112,6 @@ tf_tbl_type_2_str(enum tf_tbl_type tbl_type)\n \t\treturn \"Range\";\n \tcase TF_TBL_TYPE_LAG:\n \t\treturn \"Link Aggregation\";\n-\tcase TF_TBL_TYPE_VNIC_SVIF:\n-\t\treturn \"VNIC SVIF\";\n \tcase TF_TBL_TYPE_EM_FKB:\n \t\treturn \"EM Flexible Key Builder\";\n \tcase TF_TBL_TYPE_WC_FKB:\n", "prefixes": [ "v2", "05/58" ] }