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GET /api/patches/117463/?format=api
{ "id": 117463, "url": "https://patches.dpdk.org/api/patches/117463/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20221006150325.660-4-valex@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20221006150325.660-4-valex@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20221006150325.660-4-valex@nvidia.com", "date": "2022-10-06T15:03:09", "name": "[v2,03/19] net/mlx5: add hardware steering item translation function", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "257553ad80a1bdd027ab9a60c8f7c6f528dfa886", "submitter": { "id": 2858, "url": "https://patches.dpdk.org/api/people/2858/?format=api", "name": "Alex Vesker", "email": "valex@nvidia.com" }, "delegate": { "id": 3268, "url": "https://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20221006150325.660-4-valex@nvidia.com/mbox/", "series": [ { "id": 25012, "url": "https://patches.dpdk.org/api/series/25012/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=25012", "date": "2022-10-06T15:03:06", "name": "net/mlx5: Add HW steering low level support", "version": 2, "mbox": "https://patches.dpdk.org/series/25012/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/117463/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/117463/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id A1277A00C2;\n\tThu, 6 Oct 2022 17:04:08 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id BF63C42C9E;\n\tThu, 6 Oct 2022 17:04:07 +0200 (CEST)", "from NAM10-DM6-obe.outbound.protection.outlook.com\n (mail-dm6nam10on2050.outbound.protection.outlook.com [40.107.93.50])\n by mails.dpdk.org (Postfix) with ESMTP id 884C842C9D\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Alex Vesker <valex@nvidia.com>", "To": "<valex@nvidia.com>, <viacheslavo@nvidia.com>, <thomas@monjalon.net>,\n <suanmingm@nvidia.com>, Matan Azrad <matan@nvidia.com>", "CC": "<dev@dpdk.org>, <orika@nvidia.com>", "Subject": "[v2 03/19] net/mlx5: add hardware steering item translation function", "Date": "Thu, 6 Oct 2022 18:03:09 +0300", "Message-ID": "<20221006150325.660-4-valex@nvidia.com>", "X-Mailer": "git-send-email 2.18.1", "In-Reply-To": "<20221006150325.660-1-valex@nvidia.com>", "References": "<20220922190345.394-1-valex@nvidia.com>\n <20221006150325.660-1-valex@nvidia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.35]", "X-ClientProxiedBy": "rnnvmail202.nvidia.com (10.129.68.7) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BN8NAM11FT014:EE_|DM4PR12MB5104:EE_", "X-MS-Office365-Filtering-Correlation-Id": "ac6e2be9-97e1-47f5-24d4-08daa7ac028a", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n ccVlAYcMYNdnICxJbJjhYJO3Cj8CySibHit7ocHCukut1Hbd1+zg9A0ElL5hQJusgtVqERSDOQFP5Q2twBhpw7qRm5HBvRv1wF3MdbvWKlhl+R4ZK1MCCLkd5Cuky2t8N9FFL6D2+6ECz+7/ioN1HhEpnYa6iHSLqdk060oFSXwKu/IMcsk+3jnAJXDHcOCbZY9BKzrHCY8eQjFBXtq9rjNoCVZdcoPLVIyWoykZAQ9aruAIximHXTFsws+5F41mNcaLZPougHUOnIPycCKNJeHF6dMG1VxbVrWYUh5SUJAMYshRPhXZL78XwBtPDYbgPrpVIIxQi0ELfyS5vGP4ejVS4NbC5haaXP4k/BC4YcQT7i+eyquuggndeojk8scFt62fQCFMScHzUp159XbaC96+sq05ND1qv3f23m1EzGKWUrxgAbMzsN9fRPeBgXz2KCYE+gYOjMiTuOGpcp0yhqp4/iZFcEkgUmBcpTIPXkHE8Dw+FAvSVQ4HJXoef43W+NkHviNcg+G/RQ8S7o5POCC6oUP3FIE4u6c1L2PBe6BGq0izuoghSUZMiJQsMqO/0K/QWmjDhSktaOes/nl52zgKL9dwhpNNQlzHrA76W983p6Wj4TFcbeQ9sTfOpnsJFbYVfW4OTNzjESAcdelWvmCAU90pKW/BfFONMOo4XQu6S7tnNCxPn9+MbKR8EQj1T0Ro6g8mkqlr/0Z6S/qwQta5FUV8GMBahfIkD28WZ7EUevfHccGdlWDwwgdkI/BOztOQoR79BrxKghh8jyR37w==", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; 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This commit provides shared item tranlsation code for hardware\nsteering root table flows.\n\nSigned-off-by: Suanming Mou <suanmingm@nvidia.com>\n---\n drivers/net/mlx5/mlx5_flow.h | 17 ++++++\n drivers/net/mlx5/mlx5_flow_dv.c | 93 +++++++++++++++++++++++++++++++++\n 2 files changed, 110 insertions(+)", "diff": "diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h\nindex 2ebb8496f2..86a08074dc 100644\n--- a/drivers/net/mlx5/mlx5_flow.h\n+++ b/drivers/net/mlx5/mlx5_flow.h\n@@ -1006,6 +1006,18 @@ flow_items_to_tunnel(const struct rte_flow_item items[])\n \treturn items[0].spec;\n }\n \n+/* HW steering flow attributes. */\n+struct mlx5_flow_attr {\n+\tuint32_t port_id; /* Port index. */\n+\tuint32_t group; /* Flow group. */\n+\tuint32_t priority; /* Original Priority. */\n+\t/* rss level, used by priority adjustment. */\n+\tuint32_t rss_level;\n+\t/* Action flags, used by priority adjustment. */\n+\tuint32_t act_flags;\n+\tuint32_t tbl_type; /* Flow table type. */\n+};\n+\n /* Flow structure. */\n struct rte_flow {\n \tuint32_t dev_handles;\n@@ -2122,4 +2134,9 @@ int mlx5_flow_get_item_vport_id(struct rte_eth_dev *dev,\n \t\t\t\tbool *all_ports,\n \t\t\t\tstruct rte_flow_error *error);\n \n+int flow_dv_translate_items_hws(const struct rte_flow_item *items,\n+\t\t\t\tstruct mlx5_flow_attr *attr, void *key,\n+\t\t\t\tuint32_t key_type, uint64_t *item_flags,\n+\t\t\t\tuint8_t *match_criteria,\n+\t\t\t\tstruct rte_flow_error *error);\n #endif /* RTE_PMD_MLX5_FLOW_H_ */\ndiff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c\nindex a2704f0b98..a4c59f3762 100644\n--- a/drivers/net/mlx5/mlx5_flow_dv.c\n+++ b/drivers/net/mlx5/mlx5_flow_dv.c\n@@ -13229,6 +13229,99 @@ flow_dv_translate_items(struct rte_eth_dev *dev,\n \treturn 0;\n }\n \n+/**\n+ * Fill the HW steering flow with DV spec.\n+ *\n+ * @param[in] items\n+ * Pointer to the list of items.\n+ * @param[in] attr\n+ * Pointer to the flow attributes.\n+ * @param[in] key\n+ * Pointer to the flow matcher key.\n+ * @param[in] key_type\n+ * Key type.\n+ * @param[in, out] item_flags\n+ * Pointer to the flow item flags.\n+ * @param[out] error\n+ * Pointer to the error structure.\n+ *\n+ * @return\n+ * 0 on success, a negative errno value otherwise and rte_errno is set.\n+ */\n+int\n+flow_dv_translate_items_hws(const struct rte_flow_item *items,\n+\t\t\t struct mlx5_flow_attr *attr, void *key,\n+\t\t\t uint32_t key_type, uint64_t *item_flags,\n+\t\t\t uint8_t *match_criteria,\n+\t\t\t struct rte_flow_error *error)\n+{\n+\tstruct mlx5_flow_rss_desc rss_desc = { .level = attr->rss_level };\n+\tstruct rte_flow_attr rattr = {\n+\t\t.group = attr->group,\n+\t\t.priority = attr->priority,\n+\t\t.ingress = !!(attr->tbl_type == MLX5DR_TABLE_TYPE_NIC_RX),\n+\t\t.egress = !!(attr->tbl_type == MLX5DR_TABLE_TYPE_NIC_TX),\n+\t\t.transfer = !!(attr->tbl_type == MLX5DR_TABLE_TYPE_FDB),\n+\t};\n+\tstruct mlx5_dv_matcher_workspace wks = {\n+\t\t.action_flags = attr->act_flags,\n+\t\t.item_flags = item_flags ? *item_flags : 0,\n+\t\t.external = 0,\n+\t\t.next_protocol = 0xff,\n+\t\t.attr = &rattr,\n+\t\t.rss_desc = &rss_desc,\n+\t};\n+\tint ret;\n+\n+\tfor (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {\n+\t\tif (!mlx5_flow_os_item_supported(items->type))\n+\t\t\treturn rte_flow_error_set(error, ENOTSUP,\n+\t\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ITEM,\n+\t\t\t\t\t\t NULL, \"item not supported\");\n+\t\tret = flow_dv_translate_items(&rte_eth_devices[attr->port_id],\n+\t\t\titems, &wks, key, key_type, NULL);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t}\n+\tif (wks.item_flags & MLX5_FLOW_LAYER_VXLAN_GPE) {\n+\t\tflow_dv_translate_item_vxlan_gpe(key,\n+\t\t\t\t\t\t wks.tunnel_item,\n+\t\t\t\t\t\t wks.item_flags,\n+\t\t\t\t\t\t key_type);\n+\t} else if (wks.item_flags & MLX5_FLOW_LAYER_GENEVE) {\n+\t\tflow_dv_translate_item_geneve(key,\n+\t\t\t\t\t wks.tunnel_item,\n+\t\t\t\t\t wks.item_flags,\n+\t\t\t\t\t key_type);\n+\t} else if (wks.item_flags & MLX5_FLOW_LAYER_GRE) {\n+\t\tif (wks.tunnel_item->type == RTE_FLOW_ITEM_TYPE_GRE) {\n+\t\t\tflow_dv_translate_item_gre(key,\n+\t\t\t\t\t\t wks.tunnel_item,\n+\t\t\t\t\t\t wks.item_flags,\n+\t\t\t\t\t\t key_type);\n+\t\t} else if (wks.tunnel_item->type == RTE_FLOW_ITEM_TYPE_GRE_OPTION) {\n+\t\t\tflow_dv_translate_item_gre_option(key,\n+\t\t\t\t\t\t\t wks.tunnel_item,\n+\t\t\t\t\t\t\t wks.gre_item,\n+\t\t\t\t\t\t\t wks.item_flags,\n+\t\t\t\t\t\t\t key_type);\n+\t\t} else if (wks.tunnel_item->type == RTE_FLOW_ITEM_TYPE_NVGRE) {\n+\t\t\tflow_dv_translate_item_nvgre(key,\n+\t\t\t\t\t\t wks.tunnel_item,\n+\t\t\t\t\t\t wks.item_flags,\n+\t\t\t\t\t\t key_type);\n+\t\t} else {\n+\t\t\tMLX5_ASSERT(false);\n+\t\t}\n+\t}\n+\n+\tif (match_criteria)\n+\t\t*match_criteria = flow_dv_matcher_enable(key);\n+\tif (item_flags)\n+\t\t*item_flags = wks.item_flags;\n+\treturn 0;\n+}\n+\n /**\n * Fill the SW steering flow with DV spec.\n *\n", "prefixes": [ "v2", "03/19" ] }