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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by BN8NAM11FT014.mail.protection.outlook.com (10.13.177.142) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5709.10 via Frontend Transport; Thu, 6 Oct 2022 15:04:04 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.26; Thu, 6 Oct 2022 08:03:51 -0700 Received: from nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Thu, 6 Oct 2022 08:03:48 -0700 From: Alex Vesker To: , , , , Matan Azrad CC: , Subject: [v2 03/19] net/mlx5: add hardware steering item translation function Date: Thu, 6 Oct 2022 18:03:09 +0300 Message-ID: <20221006150325.660-4-valex@nvidia.com> X-Mailer: git-send-email 2.18.1 In-Reply-To: <20221006150325.660-1-valex@nvidia.com> References: <20220922190345.394-1-valex@nvidia.com> <20221006150325.660-1-valex@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT014:EE_|DM4PR12MB5104:EE_ X-MS-Office365-Filtering-Correlation-Id: ac6e2be9-97e1-47f5-24d4-08daa7ac028a X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Oct 2022 15:04:04.2824 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ac6e2be9-97e1-47f5-24d4-08daa7ac028a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT014.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5104 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Suanming Mou As hardware steering root table flows still work under FW steering mode. This commit provides shared item tranlsation code for hardware steering root table flows. Signed-off-by: Suanming Mou --- drivers/net/mlx5/mlx5_flow.h | 17 ++++++ drivers/net/mlx5/mlx5_flow_dv.c | 93 +++++++++++++++++++++++++++++++++ 2 files changed, 110 insertions(+) diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h index 2ebb8496f2..86a08074dc 100644 --- a/drivers/net/mlx5/mlx5_flow.h +++ b/drivers/net/mlx5/mlx5_flow.h @@ -1006,6 +1006,18 @@ flow_items_to_tunnel(const struct rte_flow_item items[]) return items[0].spec; } +/* HW steering flow attributes. */ +struct mlx5_flow_attr { + uint32_t port_id; /* Port index. */ + uint32_t group; /* Flow group. */ + uint32_t priority; /* Original Priority. */ + /* rss level, used by priority adjustment. */ + uint32_t rss_level; + /* Action flags, used by priority adjustment. */ + uint32_t act_flags; + uint32_t tbl_type; /* Flow table type. */ +}; + /* Flow structure. */ struct rte_flow { uint32_t dev_handles; @@ -2122,4 +2134,9 @@ int mlx5_flow_get_item_vport_id(struct rte_eth_dev *dev, bool *all_ports, struct rte_flow_error *error); +int flow_dv_translate_items_hws(const struct rte_flow_item *items, + struct mlx5_flow_attr *attr, void *key, + uint32_t key_type, uint64_t *item_flags, + uint8_t *match_criteria, + struct rte_flow_error *error); #endif /* RTE_PMD_MLX5_FLOW_H_ */ diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index a2704f0b98..a4c59f3762 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -13229,6 +13229,99 @@ flow_dv_translate_items(struct rte_eth_dev *dev, return 0; } +/** + * Fill the HW steering flow with DV spec. + * + * @param[in] items + * Pointer to the list of items. + * @param[in] attr + * Pointer to the flow attributes. + * @param[in] key + * Pointer to the flow matcher key. + * @param[in] key_type + * Key type. + * @param[in, out] item_flags + * Pointer to the flow item flags. + * @param[out] error + * Pointer to the error structure. + * + * @return + * 0 on success, a negative errno value otherwise and rte_errno is set. + */ +int +flow_dv_translate_items_hws(const struct rte_flow_item *items, + struct mlx5_flow_attr *attr, void *key, + uint32_t key_type, uint64_t *item_flags, + uint8_t *match_criteria, + struct rte_flow_error *error) +{ + struct mlx5_flow_rss_desc rss_desc = { .level = attr->rss_level }; + struct rte_flow_attr rattr = { + .group = attr->group, + .priority = attr->priority, + .ingress = !!(attr->tbl_type == MLX5DR_TABLE_TYPE_NIC_RX), + .egress = !!(attr->tbl_type == MLX5DR_TABLE_TYPE_NIC_TX), + .transfer = !!(attr->tbl_type == MLX5DR_TABLE_TYPE_FDB), + }; + struct mlx5_dv_matcher_workspace wks = { + .action_flags = attr->act_flags, + .item_flags = item_flags ? *item_flags : 0, + .external = 0, + .next_protocol = 0xff, + .attr = &rattr, + .rss_desc = &rss_desc, + }; + int ret; + + for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) { + if (!mlx5_flow_os_item_supported(items->type)) + return rte_flow_error_set(error, ENOTSUP, + RTE_FLOW_ERROR_TYPE_ITEM, + NULL, "item not supported"); + ret = flow_dv_translate_items(&rte_eth_devices[attr->port_id], + items, &wks, key, key_type, NULL); + if (ret) + return ret; + } + if (wks.item_flags & MLX5_FLOW_LAYER_VXLAN_GPE) { + flow_dv_translate_item_vxlan_gpe(key, + wks.tunnel_item, + wks.item_flags, + key_type); + } else if (wks.item_flags & MLX5_FLOW_LAYER_GENEVE) { + flow_dv_translate_item_geneve(key, + wks.tunnel_item, + wks.item_flags, + key_type); + } else if (wks.item_flags & MLX5_FLOW_LAYER_GRE) { + if (wks.tunnel_item->type == RTE_FLOW_ITEM_TYPE_GRE) { + flow_dv_translate_item_gre(key, + wks.tunnel_item, + wks.item_flags, + key_type); + } else if (wks.tunnel_item->type == RTE_FLOW_ITEM_TYPE_GRE_OPTION) { + flow_dv_translate_item_gre_option(key, + wks.tunnel_item, + wks.gre_item, + wks.item_flags, + key_type); + } else if (wks.tunnel_item->type == RTE_FLOW_ITEM_TYPE_NVGRE) { + flow_dv_translate_item_nvgre(key, + wks.tunnel_item, + wks.item_flags, + key_type); + } else { + MLX5_ASSERT(false); + } + } + + if (match_criteria) + *match_criteria = flow_dv_matcher_enable(key); + if (item_flags) + *item_flags = wks.item_flags; + return 0; +} + /** * Fill the SW steering flow with DV spec. *