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GET /api/patches/117453/?format=api
{ "id": 117453, "url": "https://patches.dpdk.org/api/patches/117453/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20221006110105.2986966-6-dsosnowski@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20221006110105.2986966-6-dsosnowski@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20221006110105.2986966-6-dsosnowski@nvidia.com", "date": "2022-10-06T11:01:02", "name": "[v2,5/8] net/mlx5: allow hairpin Rx queue in locked memory", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "7be706e0afe4e7b35a973742ec9748337aa71b90", "submitter": { "id": 2386, "url": "https://patches.dpdk.org/api/people/2386/?format=api", "name": "Dariusz Sosnowski", "email": "dsosnowski@nvidia.com" }, "delegate": { "id": 1, "url": "https://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20221006110105.2986966-6-dsosnowski@nvidia.com/mbox/", "series": [ { "id": 25009, "url": "https://patches.dpdk.org/api/series/25009/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=25009", "date": "2022-10-06T11:00:57", "name": "ethdev: introduce hairpin memory capabilities", "version": 2, "mbox": "https://patches.dpdk.org/series/25009/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/117453/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/117453/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id A274BA00C2;\n\tThu, 6 Oct 2022 13:02:40 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id CD74042C25;\n\tThu, 6 Oct 2022 13:02:14 +0200 (CEST)", "from NAM11-DM6-obe.outbound.protection.outlook.com\n (mail-dm6nam11on2087.outbound.protection.outlook.com [40.107.223.87])\n by mails.dpdk.org (Postfix) with ESMTP id 9241042C19\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Dariusz Sosnowski <dsosnowski@nvidia.com>", "To": "Matan Azrad <matan@nvidia.com>, Viacheslav Ovsiienko\n <viacheslavo@nvidia.com>", "CC": "<dev@dpdk.org>", "Subject": "[PATCH v2 5/8] net/mlx5: allow hairpin Rx queue in locked memory", "Date": "Thu, 6 Oct 2022 11:01:02 +0000", "Message-ID": "<20221006110105.2986966-6-dsosnowski@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20221006110105.2986966-1-dsosnowski@nvidia.com>", "References": "<20221006110105.2986966-1-dsosnowski@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.35]", "X-ClientProxiedBy": "rnnvmail202.nvidia.com (10.129.68.7) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BN8NAM11FT020:EE_|PH7PR12MB6563:EE_", "X-MS-Office365-Filtering-Correlation-Id": "626df5c5-52fe-4b15-c5dc-08daa78a381d", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n jwf+r/dJV4wVEOb9QpBro8XYiETigUCmc06sCVxrkOoFUeG6DcOyVJAEoeOlXirtO9mQjgaL+6zsRB3j9jKuqSnY9hx7OPfGwCpaZy8m+CxaKbf5CpS62hK4RAZzsQDffuoREzRECBLbXD6IamsDzFqS4SxUmkjSKrlUVemrWLm/eaTXIbCoVa7UwEs04hhILBNNIJ0xmFGmebpJqvYrnRGtAu3ZmHhpqcLmn6xAWQWLMHp3PoIDTzTL6cfeFtc0bYDJb85cyn6X5imx4T0z42pihea09bc4PkISk/o2mj0IKM920TS/OhldoyF7eVZJsZnjfeGFKqzm2YE9thkFb/erUUSDn5n7m7GSU3HUrSXPFeOsBcjKfPBc4v2IB0u9o2yjUyKedDJFOb+otamUP6DwNaNfSPsjx+cCr+B5EQ7IU0jTifBL4qMCJzfUWQDL3enHZQdi+Nn/NNw7slLkIrT14UhGjwwHITV5m5QLMXRwVc6odp5F6yl4WaevelKkkTIdUu2870J1nmCET7HBo4Q56vh4ihk9Tw0Pw9A7TRYxlosggS301AFKlAI+ltaRm76PpLVbQLRqn/vlaV0lHuAiqPg0dgg7GQoqGEtHl+rkgxAkOgUgxDdm0iNXC1mlqSYZHnuMeJ69ZfC+eG/SpMkLRZTvJo17HQiMNxYaX72Vte9nhzgbP0LeATQZE+CcfTZBLxzqgRteqlHYsVeigN/6tkmnXvMDbvVA+TXXZoE2dZ+DEHrq/3BjG5s+OqhobO5JIu3IRVQlPXLlbzAilw==", "X-Forefront-Antispam-Report": "CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE;\n SFS:(13230022)(4636009)(136003)(39860400002)(346002)(396003)(376002)(451199015)(36840700001)(46966006)(40470700004)(40480700001)(1076003)(2616005)(2906002)(186003)(82310400005)(16526019)(356005)(316002)(70206006)(36756003)(6666004)(40460700003)(70586007)(6636002)(4326008)(478600001)(8676002)(55016003)(86362001)(110136005)(41300700001)(6286002)(336012)(7696005)(8936002)(5660300002)(26005)(47076005)(83380400001)(82740400003)(36860700001)(7636003)(426003);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "06 Oct 2022 11:02:11.3116 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 626df5c5-52fe-4b15-c5dc-08daa78a381d", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT020.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "PH7PR12MB6563", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "This patch adds a capability to place hairpin Rx queue in locked device\nmemory. This capability is equivalent to storing hairpin RQ's data\nbuffers in locked internal device memory.\n\nHairpin Rx queue creation is extended with requesting that RQ is\nallocated in locked internal device memory. If allocation fails and\nforce_memory hairpin configuration is set, then hairpin queue creation\n(and, as a result, device start) fails. If force_memory is unset, then\nPMD will fallback to allocating memory for hairpin RQ in unlocked\ninternal device memory.\n\nTo allow such allocation, the user must set HAIRPIN_DATA_BUFFER_LOCK\nflag in FW using mlxconfig tool.\n\nSigned-off-by: Dariusz Sosnowski <dsosnowski@nvidia.com>\nAcked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>\n---\n doc/guides/platform/mlx5.rst | 5 ++++\n drivers/net/mlx5/mlx5_devx.c | 51 ++++++++++++++++++++++++++++------\n drivers/net/mlx5/mlx5_ethdev.c | 2 ++\n 3 files changed, 49 insertions(+), 9 deletions(-)", "diff": "diff --git a/doc/guides/platform/mlx5.rst b/doc/guides/platform/mlx5.rst\nindex 46b394c4ee..3cc1dd29e2 100644\n--- a/doc/guides/platform/mlx5.rst\n+++ b/doc/guides/platform/mlx5.rst\n@@ -555,6 +555,11 @@ Below are some firmware configurations listed.\n \n REAL_TIME_CLOCK_ENABLE=1\n \n+- allow locking hairpin RQ data buffer in device memory::\n+\n+ HAIRPIN_DATA_BUFFER_LOCK=1\n+ MEMIC_SIZE_LIMIT=0\n+\n \n .. _mlx5_common_driver_options:\n \ndiff --git a/drivers/net/mlx5/mlx5_devx.c b/drivers/net/mlx5/mlx5_devx.c\nindex c61c34bd99..fe303a73bb 100644\n--- a/drivers/net/mlx5/mlx5_devx.c\n+++ b/drivers/net/mlx5/mlx5_devx.c\n@@ -468,14 +468,16 @@ mlx5_rxq_obj_hairpin_new(struct mlx5_rxq_priv *rxq)\n {\n \tuint16_t idx = rxq->idx;\n \tstruct mlx5_priv *priv = rxq->priv;\n+\tstruct mlx5_hca_attr *hca_attr __rte_unused = &priv->sh->cdev->config.hca_attr;\n \tstruct mlx5_rxq_ctrl *rxq_ctrl = rxq->ctrl;\n-\tstruct mlx5_devx_create_rq_attr attr = { 0 };\n+\tstruct mlx5_devx_create_rq_attr unlocked_attr = { 0 };\n+\tstruct mlx5_devx_create_rq_attr locked_attr = { 0 };\n \tstruct mlx5_rxq_obj *tmpl = rxq_ctrl->obj;\n \tuint32_t max_wq_data;\n \n \tMLX5_ASSERT(rxq != NULL && rxq->ctrl != NULL && tmpl != NULL);\n \ttmpl->rxq_ctrl = rxq_ctrl;\n-\tattr.hairpin = 1;\n+\tunlocked_attr.hairpin = 1;\n \tmax_wq_data =\n \t\tpriv->sh->cdev->config.hca_attr.log_max_hairpin_wq_data_sz;\n \t/* Jumbo frames > 9KB should be supported, and more packets. */\n@@ -487,20 +489,50 @@ mlx5_rxq_obj_hairpin_new(struct mlx5_rxq_priv *rxq)\n \t\t\trte_errno = ERANGE;\n \t\t\treturn -rte_errno;\n \t\t}\n-\t\tattr.wq_attr.log_hairpin_data_sz = priv->config.log_hp_size;\n+\t\tunlocked_attr.wq_attr.log_hairpin_data_sz = priv->config.log_hp_size;\n \t} else {\n-\t\tattr.wq_attr.log_hairpin_data_sz =\n+\t\tunlocked_attr.wq_attr.log_hairpin_data_sz =\n \t\t\t\t(max_wq_data < MLX5_HAIRPIN_JUMBO_LOG_SIZE) ?\n \t\t\t\t max_wq_data : MLX5_HAIRPIN_JUMBO_LOG_SIZE;\n \t}\n \t/* Set the packets number to the maximum value for performance. */\n-\tattr.wq_attr.log_hairpin_num_packets =\n-\t\t\tattr.wq_attr.log_hairpin_data_sz -\n+\tunlocked_attr.wq_attr.log_hairpin_num_packets =\n+\t\t\tunlocked_attr.wq_attr.log_hairpin_data_sz -\n \t\t\tMLX5_HAIRPIN_QUEUE_STRIDE;\n-\tattr.counter_set_id = priv->counter_set_id;\n+\tunlocked_attr.counter_set_id = priv->counter_set_id;\n \trxq_ctrl->rxq.delay_drop = priv->config.hp_delay_drop;\n-\tattr.delay_drop_en = priv->config.hp_delay_drop;\n-\ttmpl->rq = mlx5_devx_cmd_create_rq(priv->sh->cdev->ctx, &attr,\n+\tunlocked_attr.delay_drop_en = priv->config.hp_delay_drop;\n+\tunlocked_attr.hairpin_data_buffer_type =\n+\t\t\tMLX5_RQC_HAIRPIN_DATA_BUFFER_TYPE_UNLOCKED_INTERNAL_BUFFER;\n+\tif (rxq->hairpin_conf.use_locked_device_memory) {\n+\t\t/*\n+\t\t * It is assumed that configuration is verified against capabilities\n+\t\t * during queue setup.\n+\t\t */\n+\t\tMLX5_ASSERT(hca_attr->hairpin_data_buffer_locked);\n+\t\trte_memcpy(&locked_attr, &unlocked_attr, sizeof(locked_attr));\n+\t\tlocked_attr.hairpin_data_buffer_type =\n+\t\t\t\tMLX5_RQC_HAIRPIN_DATA_BUFFER_TYPE_LOCKED_INTERNAL_BUFFER;\n+\t\ttmpl->rq = mlx5_devx_cmd_create_rq(priv->sh->cdev->ctx, &locked_attr,\n+\t\t\t\t\t\t rxq_ctrl->socket);\n+\t\tif (!tmpl->rq && rxq->hairpin_conf.force_memory) {\n+\t\t\tDRV_LOG(ERR, \"Port %u Rx hairpin queue %u can't create RQ object\"\n+\t\t\t\t \" with locked memory buffer\",\n+\t\t\t\t priv->dev_data->port_id, idx);\n+\t\t\treturn -rte_errno;\n+\t\t} else if (!tmpl->rq && !rxq->hairpin_conf.force_memory) {\n+\t\t\tDRV_LOG(WARNING, \"Port %u Rx hairpin queue %u can't create RQ object\"\n+\t\t\t\t\t \" with locked memory buffer. Falling back to unlocked\"\n+\t\t\t\t\t \" device memory.\",\n+\t\t\t\t\t priv->dev_data->port_id, idx);\n+\t\t\trte_errno = 0;\n+\t\t\tgoto create_rq_unlocked;\n+\t\t}\n+\t\tgoto create_rq_set_state;\n+\t}\n+\n+create_rq_unlocked:\n+\ttmpl->rq = mlx5_devx_cmd_create_rq(priv->sh->cdev->ctx, &unlocked_attr,\n \t\t\t\t\t rxq_ctrl->socket);\n \tif (!tmpl->rq) {\n \t\tDRV_LOG(ERR,\n@@ -509,6 +541,7 @@ mlx5_rxq_obj_hairpin_new(struct mlx5_rxq_priv *rxq)\n \t\trte_errno = errno;\n \t\treturn -rte_errno;\n \t}\n+create_rq_set_state:\n \tpriv->dev_data->rx_queue_state[idx] = RTE_ETH_QUEUE_STATE_HAIRPIN;\n \treturn 0;\n }\ndiff --git a/drivers/net/mlx5/mlx5_ethdev.c b/drivers/net/mlx5/mlx5_ethdev.c\nindex c59005ea2b..4a85415ff3 100644\n--- a/drivers/net/mlx5/mlx5_ethdev.c\n+++ b/drivers/net/mlx5/mlx5_ethdev.c\n@@ -740,6 +740,8 @@ mlx5_hairpin_cap_get(struct rte_eth_dev *dev, struct rte_eth_hairpin_cap *cap)\n \tcap->max_tx_2_rx = 1;\n \tcap->max_nb_desc = 8192;\n \thca_attr = &priv->sh->cdev->config.hca_attr;\n+\tcap->rx_cap.locked_device_memory = hca_attr->hairpin_data_buffer_locked;\n+\tcap->rx_cap.rte_memory = 0;\n \tcap->tx_cap.locked_device_memory = 0;\n \tcap->tx_cap.rte_memory = hca_attr->hairpin_sq_wq_in_host_mem;\n \treturn 0;\n", "prefixes": [ "v2", "5/8" ] }