From patchwork Thu Oct 6 11:00:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dariusz Sosnowski X-Patchwork-Id: 117449 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 73A97A00C2; Thu, 6 Oct 2022 13:02:09 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 562C442C0A; Thu, 6 Oct 2022 13:02:05 +0200 (CEST) Received: from NAM11-BN8-obe.outbound.protection.outlook.com (mail-bn8nam11on2041.outbound.protection.outlook.com [40.107.236.41]) by mails.dpdk.org (Postfix) with ESMTP id 518FA42BF0 for ; Thu, 6 Oct 2022 13:02:03 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=mdTplIKfEDpASufUtQLeLsFnp5LdIplq5TMDZpnZz35+S8IhPx3ck7wadRfrLW/Fj0aQV85LBkv9hjogWjmVj2oO5oFrpWFat4lmzXCH9IktJP77EMZwK7edVEzlGIlTlBXup/t+mk30jEE/aTrvDcFeCtPfn/xgwXvqHOu79RaXhOeOSsORqxEPiwupr19dGC7B0H3OdzJ4cFH7G9CnMJnnKHGD8NmSMjWIWNTSVI3Bi0Egjxu9NaJAQ11KwIQ8UEku2R55+PcSJ2CNLUrP91tT305e8TP+4vdThfyOTxDtosZuitvNghRYsUZGTp34Y0cvqC7G7xI+h2OfvJ8WgA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=bn/MyawROKwK8H7CmCJ0ZtXf076IgfX5kKhbnYTtaq0=; b=XZUqYA4qCu5ArrKXHLfSLf68otuNu7XwKzvyyPIGWff8QK9a6c4SOPNboOuSSrimJTRcPDDMS2YfhsoyC4A637rDjtiSDFS+l5a8f6fLY6C7wIcPq9J83qK7torjz4JS40HrBFXzUEcVYJYOF+lIlex1u44Png7onPtMjxBM2leBkmh7O2nRrpKf/0fs1nRBHlm5CsFNGHzDplWvoeLLQZ0oWTNUZwCRdZuU37OIO4MUiA18nnUw6U9tRI3L/lg0w6YDN9AD2Ypm8ewTPMGMBwoe5tOwwPk9XCqRtvQw6qnG5Le8SusNLbh03iD1zLsZYNxeOpFY30SHjlj13IYkbg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=monjalon.net smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=bn/MyawROKwK8H7CmCJ0ZtXf076IgfX5kKhbnYTtaq0=; b=tpxuKY91F1tooCbISACA5Kwr6dZb1OgTWFOrpjQIRxpVw5Oyu8pjPtDbn2McwO69rYHI6tvS0HFcamRxDYVLiiUWcwkejvI8nPUFiXSc352ivj7l7iYu2V9jxdYVwSGK3Eo3N6xrsPVhqvWABK5iKk6AovCvtusm+EnLI9O2C4toZqmWha6tIr01FcahAgaiy/2LFGX2Nt9D47PLCCZFCZiPB44SxwEVDatVYH+zOnx3u+7GZuQzrfaCkTV3GgnZzyfvC8d/eRMd/QP+xYQ/urGm/rOdMSRvyAjr8GIx5U8PlyZVlNWemSrql7wVfJbHjZB8oDbQ52/3OLxsnkkaiA== Received: from BN1PR13CA0002.namprd13.prod.outlook.com (2603:10b6:408:e2::7) by BY5PR12MB4871.namprd12.prod.outlook.com (2603:10b6:a03:1d1::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5676.23; Thu, 6 Oct 2022 11:02:01 +0000 Received: from BN8NAM11FT011.eop-nam11.prod.protection.outlook.com (2603:10b6:408:e2:cafe::ca) by BN1PR13CA0002.outlook.office365.com (2603:10b6:408:e2::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5709.12 via Frontend Transport; Thu, 6 Oct 2022 11:02:01 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by BN8NAM11FT011.mail.protection.outlook.com (10.13.176.140) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5709.10 via Frontend Transport; Thu, 6 Oct 2022 11:02:01 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.26; Thu, 6 Oct 2022 04:01:50 -0700 Received: from nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Thu, 6 Oct 2022 04:01:48 -0700 From: Dariusz Sosnowski To: Thomas Monjalon , Ferruh Yigit , Andrew Rybchenko CC: Subject: [PATCH v2 1/8] ethdev: introduce hairpin memory capabilities Date: Thu, 6 Oct 2022 11:00:58 +0000 Message-ID: <20221006110105.2986966-2-dsosnowski@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221006110105.2986966-1-dsosnowski@nvidia.com> References: <20221006110105.2986966-1-dsosnowski@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT011:EE_|BY5PR12MB4871:EE_ X-MS-Office365-Filtering-Correlation-Id: adc2a582-1e92-4f6d-ec90-08daa78a31f8 X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 0SG4v7UN0zTfdiMVYrKZa5AYaVAz/UwsWP6Mj8FEGV2TsEA7guek9UklchJ/ij4o4sr5s6bo/0vxiOuxdzzQC4A0ZdK86VR0GV2zNtjuSE8yJomh3os3/0AjJ5T/J4NTkv8LEz9BaWpvrkmZEl/34Ou5Uuy4NB60tJM2Yr2o6VZUGwKEXau4gCH/bxBtcwpC2JxXPJTWUT14JSdCutYyM5BpvNJ2Wb+b9J0Nkl6tf71dS3bDWUZiuv5+TpZRrb9xbqG0agydcYWaKC8v3igkCarMjZaYdz/aq48XGBcdGqYl0QEaPdwdQqOZKmL14Wr/YC7hac2glKXGN0280q64h7ngTtiAwo3naZ4Yi6yKkPCKG0xkILFMC7x0YZinnvtFSx570lp3O5VZc0wvx42CyKM1Nj5Z/jrHDOPUh4LVHzgkRhZxtZl8VRvSEP0fjtVF1YYlXOvO9Z7ZIWn3AO6bjyRjkNhjrXYoGNwCYhR5/ottzAbFgxQKgsl3+gJFWj9tm5H/Ct6HZW/JmTj49jj5UNDvafZiljhU8XKkI6FYno8OpZt1cWSqnviop7BF4K+yjp1KqbxfxpiP1D1KXJx81acdeXNj9JUV/pr8KMBByIbVYiTxM3IwFjQ0J0Nke5WjLpk/99I+txs7v68evXo2G2BtPj4fL5cBPz8rEO3y65sVtjqfQ8QPx8u1HQUXLqpme5Z/Ua5cr6D5yia7E09Ms/Yrau46L9fPZeCfSfhkjTFwDF8gfdbFavye9EaG10hkKKB+e+prVJjbFSmDniEAQQ== X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230022)(4636009)(136003)(346002)(39860400002)(376002)(396003)(451199015)(36840700001)(46966006)(40470700004)(1076003)(186003)(2616005)(16526019)(356005)(2906002)(82310400005)(316002)(70206006)(6666004)(40460700003)(70586007)(4326008)(110136005)(8676002)(55016003)(86362001)(478600001)(41300700001)(5660300002)(6286002)(26005)(336012)(426003)(7636003)(8936002)(7696005)(40480700001)(47076005)(36756003)(82740400003)(83380400001)(36860700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Oct 2022 11:02:01.0037 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: adc2a582-1e92-4f6d-ec90-08daa78a31f8 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT011.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4871 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Before this patch, implementation details and configuration of hairpin queues were decided internally by the PMD. Applications had no control over the configuration of Rx and Tx hairpin queues, despite number of descriptors, explicit Tx flow mode and disabling automatic binding. This patch addresses that by adding: - Hairpin queue capabilities reported by PMDs. - New configuration options for Rx and Tx hairpin queues. Main goal of this patch is to allow applications to provide configuration hints regarding placement of hairpin queues. These hints specify whether buffers of hairpin queues should be placed in host memory or in dedicated device memory. Different memory options may have different performance characteristics and hairpin configuration should be fine-tuned to the specific application and use case. This patch introduces new hairpin queue configuration options through rte_eth_hairpin_conf struct, allowing to tune Rx and Tx hairpin queues memory configuration. Hairpin configuration is extended with the following fields: - use_locked_device_memory - If set, PMD will use specialized on-device memory to store RX or TX hairpin queue data. - use_rte_memory - If set, PMD will use DPDK-managed memory to store RX or TX hairpin queue data. - force_memory - If set, PMD will be forced to use provided memory settings. If no appropriate resources are available, then device start will fail. If unset and no resources are available, PMD will fallback to using default type of resource for given queue. If application chooses to use PMD default memory configuration, all of these flags should remain unset. Hairpin capabilities are also extended, to allow verification of support of given hairpin memory configurations. Struct rte_eth_hairpin_cap is extended with two additional fields of type rte_eth_hairpin_queue_cap: - rx_cap - memory capabilities of hairpin RX queues. - tx_cap - memory capabilities of hairpin TX queues. Struct rte_eth_hairpin_queue_cap exposes whether given queue type supports use_locked_device_memory and use_rte_memory flags. Signed-off-by: Dariusz Sosnowski --- doc/guides/rel_notes/release_22_11.rst | 10 ++++ lib/ethdev/rte_ethdev.c | 44 +++++++++++++++++ lib/ethdev/rte_ethdev.h | 68 +++++++++++++++++++++++++- 3 files changed, 120 insertions(+), 2 deletions(-) diff --git a/doc/guides/rel_notes/release_22_11.rst b/doc/guides/rel_notes/release_22_11.rst index ac67e7e710..e5c48c6b18 100644 --- a/doc/guides/rel_notes/release_22_11.rst +++ b/doc/guides/rel_notes/release_22_11.rst @@ -66,6 +66,16 @@ New Features Added new function ``rte_flow_async_action_handle_query()``, to query the action asynchronously. +* **Added hairpin memory configurations options in ethdev API.** + + Added new configuration flags for hairpin queues in ``rte_eth_hairpin_conf``: + + * ``use_locked_device_memory`` + * ``use_rte_memory`` + * ``force_memory`` + + Each flag has a corresponding capability flag in ``rte_eth_hairpin_queue_cap`` struct. + * **Updated Intel iavf driver.** * Added flow subscription support. diff --git a/lib/ethdev/rte_ethdev.c b/lib/ethdev/rte_ethdev.c index 2821770e2d..bece83eb91 100644 --- a/lib/ethdev/rte_ethdev.c +++ b/lib/ethdev/rte_ethdev.c @@ -1961,6 +1961,28 @@ rte_eth_rx_hairpin_queue_setup(uint16_t port_id, uint16_t rx_queue_id, conf->peer_count, cap.max_rx_2_tx); return -EINVAL; } + if (conf->use_locked_device_memory && !cap.rx_cap.locked_device_memory) { + RTE_ETHDEV_LOG(ERR, + "Attempt to use locked device memory for Rx queue, which is not supported"); + return -EINVAL; + } + if (conf->use_rte_memory && !cap.rx_cap.rte_memory) { + RTE_ETHDEV_LOG(ERR, + "Attempt to use DPDK memory for Rx queue, which is not supported"); + return -EINVAL; + } + if (conf->use_locked_device_memory && conf->use_rte_memory) { + RTE_ETHDEV_LOG(ERR, + "Attempt to use mutually exclusive memory settings for Rx queue"); + return -EINVAL; + } + if (conf->force_memory && + !conf->use_locked_device_memory && + !conf->use_rte_memory) { + RTE_ETHDEV_LOG(ERR, + "Attempt to force Rx queue memory settings, but none is set"); + return -EINVAL; + } if (conf->peer_count == 0) { RTE_ETHDEV_LOG(ERR, "Invalid value for number of peers for Rx queue(=%u), should be: > 0", @@ -2128,6 +2150,28 @@ rte_eth_tx_hairpin_queue_setup(uint16_t port_id, uint16_t tx_queue_id, conf->peer_count, cap.max_tx_2_rx); return -EINVAL; } + if (conf->use_locked_device_memory && !cap.tx_cap.locked_device_memory) { + RTE_ETHDEV_LOG(ERR, + "Attempt to use locked device memory for Tx queue, which is not supported"); + return -EINVAL; + } + if (conf->use_rte_memory && !cap.tx_cap.rte_memory) { + RTE_ETHDEV_LOG(ERR, + "Attempt to use DPDK memory for Tx queue, which is not supported"); + return -EINVAL; + } + if (conf->use_locked_device_memory && conf->use_rte_memory) { + RTE_ETHDEV_LOG(ERR, + "Attempt to use mutually exclusive memory settings for Tx queue"); + return -EINVAL; + } + if (conf->force_memory && + !conf->use_locked_device_memory && + !conf->use_rte_memory) { + RTE_ETHDEV_LOG(ERR, + "Attempt to force Tx queue memory settings, but none is set"); + return -EINVAL; + } if (conf->peer_count == 0) { RTE_ETHDEV_LOG(ERR, "Invalid value for number of peers for Tx queue(=%u), should be: > 0", diff --git a/lib/ethdev/rte_ethdev.h b/lib/ethdev/rte_ethdev.h index a21f58b9cd..eab931d3b2 100644 --- a/lib/ethdev/rte_ethdev.h +++ b/lib/ethdev/rte_ethdev.h @@ -1092,6 +1092,28 @@ struct rte_eth_txconf { void *reserved_ptrs[2]; /**< Reserved for future fields */ }; +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * A structure used to return the Tx or Rx hairpin queue capabilities that are supported. + */ +struct rte_eth_hairpin_queue_cap { + /** + * When set, PMD supports placing descriptors and/or data buffers + * in dedicated device memory. + */ + uint32_t locked_device_memory:1; + + /** + * When set, PMD supports placing descriptors and/or data buffers + * in host memory managed by DPDK. + */ + uint32_t rte_memory:1; + + uint32_t reserved:30; /**< Reserved for future fields */ +}; + /** * @warning * @b EXPERIMENTAL: this API may change, or be removed, without prior notice @@ -1106,6 +1128,8 @@ struct rte_eth_hairpin_cap { /** Max number of Tx queues to be connected to one Rx queue. */ uint16_t max_tx_2_rx; uint16_t max_nb_desc; /**< The max num of descriptors. */ + struct rte_eth_hairpin_queue_cap rx_cap; /**< Rx hairpin queue capabilities. */ + struct rte_eth_hairpin_queue_cap tx_cap; /**< Tx hairpin queue capabilities. */ }; #define RTE_ETH_MAX_HAIRPIN_PEERS 32 @@ -1149,11 +1173,51 @@ struct rte_eth_hairpin_conf { * function after all the queues are set up properly and the ports are * started. Also, the hairpin unbind function should be called * accordingly before stopping a port that with hairpin configured. - * - When clear, the PMD will try to enable the hairpin with the queues + * - When cleared, the PMD will try to enable the hairpin with the queues * configured automatically during port start. */ uint32_t manual_bind:1; - uint32_t reserved:14; /**< Reserved bits. */ + + /** + * Use locked device memory as a backing storage. + * + * - When set, PMD will attempt place descriptors and/or data buffers + * in dedicated device memory. + * - When cleared, PMD will use default memory type as a backing storage. + * Please refer to PMD documentation for details. + * + * API user should check if PMD supports this configuration flag using + * @see rte_eth_dev_hairpin_capability_get. + */ + uint32_t use_locked_device_memory:1; + + /** + * Use DPDK memory as backing storage. + * + * - When set, PMD will attempt place descriptors and/or data buffers + * in host memory managed by DPDK. + * - When cleared, PMD will use default memory type as a backing storage. + * Please refer to PMD documentation for details. + * + * API user should check if PMD supports this configuration flag using + * @see rte_eth_dev_hairpin_capability_get. + */ + uint32_t use_rte_memory:1; + + /** + * Force usage of hairpin memory configuration. + * + * - When set, PMD will attempt to use specified memory settings. + * If resource allocation fails, then hairpin queue allocation + * will result in an error. + * - When clear, PMD will attempt to use specified memory settings. + * If resource allocation fails, then PMD will retry + * allocation with default configuration. + */ + uint32_t force_memory:1; + + uint32_t reserved:11; /**< Reserved bits. */ + struct rte_eth_hairpin_peer peers[RTE_ETH_MAX_HAIRPIN_PEERS]; }; From patchwork Thu Oct 6 11:00:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dariusz Sosnowski X-Patchwork-Id: 117450 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 52B23A00C2; Thu, 6 Oct 2022 13:02:18 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 7C33442C09; Thu, 6 Oct 2022 13:02:09 +0200 (CEST) Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2047.outbound.protection.outlook.com [40.107.220.47]) by mails.dpdk.org (Postfix) with ESMTP id F1F0942B70 for ; Thu, 6 Oct 2022 13:02:07 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=H8Y605A9OkEeeCg/kzBtuLeF97jUWudkzjMnejx++n4qoTwiixzjsfTfgzot2KwCNTaM24t+U6eAYHo8/x/PRuEFiU57+/mxMEzbs/q45spNrcQvYXnEiB9pDTycWjgo69dXdFCny1lIva8DLEkv3vr/H9cr3pFQNvOvVmuc6M07mcpQSPaFWvQmj6pTon/OlR24MB4gP4FbN80NGcwdgUOV8dhSUMC90qjejPcN5pGrfsmS6e9bgXdXhD/6ZWwv8Hnpgjznze7Vti4dx8qDXDjM7ZKTvaVhehcCzAr5IzC6q6nEi5WlYKyfXC1LR/vFhfuInOsQQwY7PPG0u3F74g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=89I2iS9IgrjmNUYpYX8WUXBc4kdf4p8OUOLnHkMS5t8=; b=dDYoL2TsVtQfxaM7QG0nfcKXs6XIHzNcl+MsaleEF3PCPFhw6VZ579k4gkDWHgEaYmcFa9oGG0DaD4YPB9LiPFLaJsVy44uu+HBb7MzFfB00UPsohJuKVtKFesPmAPoYxoJhTvnq7LbQDJ55+PKtltaJ4irR76F58pZwffQY4w0IFzhUQS2UNlyErUn7Bkm0rCwRpb0f4uSly3x1LMJ2RCJ+s4iOSsfVoBMxhNeZuLiEhrSIOEAnZLcO9fl0uzgHB1xKvw4ubepOX7rZTO1hK3B+lqpjp9tAArrW5vKsNu4+AaRBEUwqBU5ihizDHcWUY3VoWAd9QEa8lDnOm57b0w== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=temperror (sender ip is 216.228.117.160) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=temperror action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=89I2iS9IgrjmNUYpYX8WUXBc4kdf4p8OUOLnHkMS5t8=; b=U3Nm2neU1oYmfXWQ2b1XCh9s31Ggj4ibbZYWJl9cFIOxfV6DZ4hQR1mOhwEdBOBhg4dse1C70dCvV4zlbBp0A2xHLzh1DtQl+Rwi0XkNYIUgz7yY9XXJ6uGSnth1zYkopaDtcxMoD2P5jXD6bN58OG0hVCqbZcwzjwkp+8ELn6hdDCUyssT09I0KTKMxVqykB7piCn0i7XaO9yTwuBRGqHGDCMrhtUMUzNdBLRqhvbwTS+jHrwRyQJjypv2PLvnENyT+xgU6e5F/BDG78cwvuc15RDq7E8mtlQBqk8NzF1moz8M+3GOBc/fIO4ULQh2eDNgoh3gghdfOf1Q6gJU4aQ== Received: from BN0PR04CA0193.namprd04.prod.outlook.com (2603:10b6:408:e9::18) by BL3PR12MB6427.namprd12.prod.outlook.com (2603:10b6:208:3b6::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5676.32; Thu, 6 Oct 2022 11:02:05 +0000 Received: from BN8NAM11FT020.eop-nam11.prod.protection.outlook.com (2603:10b6:408:e9:cafe::fc) by BN0PR04CA0193.outlook.office365.com (2603:10b6:408:e9::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5676.23 via Frontend Transport; Thu, 6 Oct 2022 11:02:05 +0000 X-MS-Exchange-Authentication-Results: spf=temperror (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=temperror action=none header.from=nvidia.com; Received-SPF: TempError (protection.outlook.com: error in processing during lookup of nvidia.com: DNS Timeout) Received: from mail.nvidia.com (216.228.117.160) by BN8NAM11FT020.mail.protection.outlook.com (10.13.176.223) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5709.10 via Frontend Transport; Thu, 6 Oct 2022 11:02:03 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.26; Thu, 6 Oct 2022 04:01:52 -0700 Received: from nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Thu, 6 Oct 2022 04:01:51 -0700 From: Dariusz Sosnowski To: Matan Azrad , Viacheslav Ovsiienko CC: Subject: [PATCH v2 2/8] common/mlx5: add hairpin SQ buffer type capabilities Date: Thu, 6 Oct 2022 11:00:59 +0000 Message-ID: <20221006110105.2986966-3-dsosnowski@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221006110105.2986966-1-dsosnowski@nvidia.com> References: <20221006110105.2986966-1-dsosnowski@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT020:EE_|BL3PR12MB6427:EE_ X-MS-Office365-Filtering-Correlation-Id: 104b228e-b882-40cc-2d24-08daa78a33aa X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 90+ximccAqoVezRcIGtV039Cdfiy3OGZONGbddoVSXshURUvFSPlZAze6I3Nj0FulGrTbY1DLVy5KO2XOqVSaron59vILwKp+tnwwuDlhExm58udO7CBUdYsEU23eMXm/+gF2dY8Z8ksejpYDi/hCf7UQdjHLN3FHHJe+CB1zEFautlvYpLc9dURYwSmPS8COJFAz6bJcIaShc1n6cBiOevCHKNMYSgvW9zh+XTsFKyBoQrQxXY4QTAIv7wI5C/2BWUy8yFG0BpyQTiY1NdF9ixykMWKyye3AT9jYKYIZj2dAcApemTEeZ/AjXZ36s+47N263N/LPICA7mMp2MYfGeg8leUAMi+RHtVQz1qSxoQBHnq6tbCF+uWhwPB2v62Kg1MS0ayMoJN9Cm+HtK5WkQonw3F59NymFMsYNMcLL92ps9uHeuGi3EgcENiclJPY1WzkXp+CfZ/SLsFMiIZRffc+h1nAeeGVNsk8SyyTLsjZEYtqAConMYbcyL3j8pFGCrcvmafnGLHj6iIsYrPC7Xcfsf/V1EagV4QknCDEXY4SIEOWk+dQznQiEbSxGdv2HlP1Jwl7F6MJvg0Hi8OqDtvyt3U7ciZnfJnYhXkwVffQJ+tAvkjD+IrQpOWekg5sOlggDVba9IeIvFYKO39vHeEMGLmt5P86GHRKPZ97kKoN+60Nwqu8K6G2wy7B4pRdb7NZPayi1jB34iCPhJVzNYf1rDTYWbtZAmMpUzJg33M6d8Xr+EzchKqi4RLW3F+fSgbeuJamr5wvV/OouCzXag== X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230022)(4636009)(39860400002)(396003)(376002)(136003)(346002)(451199015)(36840700001)(46966006)(40470700004)(16526019)(426003)(336012)(7636003)(47076005)(356005)(1076003)(83380400001)(186003)(86362001)(63350400001)(82740400003)(82310400005)(36860700001)(70206006)(41300700001)(8936002)(5660300002)(110136005)(4326008)(316002)(6636002)(70586007)(7696005)(40480700001)(8676002)(55016003)(6286002)(2906002)(26005)(40460700003)(2616005)(478600001)(63370400001)(36756003); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Oct 2022 11:02:03.8431 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 104b228e-b882-40cc-2d24-08daa78a33aa X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT020.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL3PR12MB6427 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch extends HCA_CAP and SQ Context structs available in PRM. This fields allow checking if NIC supports storing hairpin SQ's WQ buffer in host memory and configuring such memory placement. HCA capabilities are extended with the following fields: - hairpin_sq_wq_in_host_mem - If set, then NIC supports using host memory as a backing storage for hairpin SQ's WQ buffer. - hairpin_sq_wqe_bb_size - Indicates the required size of SQ WQE basic block. SQ Context is extended with hairpin_wq_buffer_type which informs NIC where SQ's WQ buffer will be stored. This field can take the following values: - MLX5_SQC_HAIRPIN_WQ_BUFFER_TYPE_INTERNAL_BUFFER - WQ buffer will be stored in unlocked device memory. - MLX5_SQC_HAIRPIN_WQ_BUFFER_TYPE_HOST_MEMORY - WQ buffer will be stored in host memory. Buffer is provided by PMD. Signed-off-by: Dariusz Sosnowski Acked-by: Viacheslav Ovsiienko --- drivers/common/mlx5/mlx5_devx_cmds.c | 5 +++++ drivers/common/mlx5/mlx5_devx_cmds.h | 3 +++ drivers/common/mlx5/mlx5_prm.h | 15 +++++++++++++-- 3 files changed, 21 insertions(+), 2 deletions(-) diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c index fb33023138..a1e8179568 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.c +++ b/drivers/common/mlx5/mlx5_devx_cmds.c @@ -989,6 +989,10 @@ mlx5_devx_cmd_query_hca_attr(void *ctx, } attr->log_min_stride_wqe_sz = MLX5_GET(cmd_hca_cap_2, hcattr, log_min_stride_wqe_sz); + attr->hairpin_sq_wqe_bb_size = MLX5_GET(cmd_hca_cap_2, hcattr, + hairpin_sq_wqe_bb_size); + attr->hairpin_sq_wq_in_host_mem = MLX5_GET(cmd_hca_cap_2, hcattr, + hairpin_sq_wq_in_host_mem); } if (attr->log_min_stride_wqe_sz == 0) attr->log_min_stride_wqe_sz = MLX5_MPRQ_LOG_MIN_STRIDE_WQE_SIZE; @@ -1706,6 +1710,7 @@ mlx5_devx_cmd_create_sq(void *ctx, MLX5_SET(sqc, sq_ctx, hairpin, sq_attr->hairpin); MLX5_SET(sqc, sq_ctx, non_wire, sq_attr->non_wire); MLX5_SET(sqc, sq_ctx, static_sq_wq, sq_attr->static_sq_wq); + MLX5_SET(sqc, sq_ctx, hairpin_wq_buffer_type, sq_attr->hairpin_wq_buffer_type); MLX5_SET(sqc, sq_ctx, user_index, sq_attr->user_index); MLX5_SET(sqc, sq_ctx, cqn, sq_attr->cqn); MLX5_SET(sqc, sq_ctx, packet_pacing_rate_limit_index, diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h index af6053a788..9ac2d75df4 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.h +++ b/drivers/common/mlx5/mlx5_devx_cmds.h @@ -191,6 +191,8 @@ struct mlx5_hca_attr { uint32_t log_max_hairpin_queues:5; uint32_t log_max_hairpin_wq_data_sz:5; uint32_t log_max_hairpin_num_packets:5; + uint32_t hairpin_sq_wqe_bb_size:4; + uint32_t hairpin_sq_wq_in_host_mem:1; uint32_t vhca_id:16; uint32_t relaxed_ordering_write:1; uint32_t relaxed_ordering_read:1; @@ -407,6 +409,7 @@ struct mlx5_devx_create_sq_attr { uint32_t non_wire:1; uint32_t static_sq_wq:1; uint32_t ts_format:2; + uint32_t hairpin_wq_buffer_type:3; uint32_t user_index:24; uint32_t cqn:24; uint32_t packet_pacing_rate_limit_index:16; diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index 4346279c81..04d35ca845 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -2020,7 +2020,11 @@ struct mlx5_ifc_cmd_hca_cap_2_bits { u8 reserved_at_d8[0x3]; u8 log_max_conn_track_offload[0x5]; u8 reserved_at_e0[0x20]; /* End of DW7. */ - u8 reserved_at_100[0x700]; + u8 reserved_at_100[0x60]; + u8 reserved_at_160[0x3]; + u8 hairpin_sq_wqe_bb_size[0x5]; + u8 hairpin_sq_wq_in_host_mem[0x1]; + u8 reserved_at_169[0x697]; }; struct mlx5_ifc_esw_cap_bits { @@ -2673,6 +2677,11 @@ enum { MLX5_SQC_STATE_ERR = 0x3, }; +enum { + MLX5_SQC_HAIRPIN_WQ_BUFFER_TYPE_INTERNAL_BUFFER = 0x0, + MLX5_SQC_HAIRPIN_WQ_BUFFER_TYPE_HOST_MEMORY = 0x1, +}; + struct mlx5_ifc_sqc_bits { u8 rlky[0x1]; u8 cd_master[0x1]; @@ -2686,7 +2695,9 @@ struct mlx5_ifc_sqc_bits { u8 hairpin[0x1]; u8 non_wire[0x1]; u8 static_sq_wq[0x1]; - u8 reserved_at_11[0x9]; + u8 reserved_at_11[0x4]; + u8 hairpin_wq_buffer_type[0x3]; + u8 reserved_at_18[0x2]; u8 ts_format[0x02]; u8 reserved_at_1c[0x4]; u8 reserved_at_20[0x8]; From patchwork Thu Oct 6 11:01:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dariusz Sosnowski X-Patchwork-Id: 117451 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 718DCA00C2; Thu, 6 Oct 2022 13:02:24 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 7396F42C11; Thu, 6 Oct 2022 13:02:11 +0200 (CEST) Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2061.outbound.protection.outlook.com [40.107.223.61]) by mails.dpdk.org (Postfix) with ESMTP id 4682E42C11 for ; Thu, 6 Oct 2022 13:02:10 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=PQ1D6rtcuqeOMmJ0jjXD8ZTDnpExBrR6jbD9UEDyxsD4t8ni3MSCL8hhfbx+QrML1UiIXO+270KAI6lh848z7dglItMUlumli0JQX9IMmXh8WvmljXopGEW0a/YqWby3/WjlAMQQMp79NHKmoGAbJCATevazmvuLJQr0EtnYlYTs2zdbDUC7rmYecIKlkszq8das/sX5xIgGLNWf09OZkyoxXJe2T8H6rTv2Hi0zcTRdeOLkh1mT9oOK+FCrowftbfhY8Xv8mzcb/iHLvDmkfsJENPrbgiv6N9o1f9Hn9fZwuCsF3e14Wpcypin1IT2RfAE0LAmvYP6RV0cg0VT5Cg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=OZ+DO+gmAr5KDH02vPQCSuYdZBiu00MfWbjeD33mTBM=; b=TiXoYPvSgsaNVIHqyW7UuQcdBS0S8TKhpGan+sATz9knZUrp3uLaeQQNjgjFfTu0DYe9gwzm2swxatEPqHJDZP4KjG416q9xgMcvqIGVMQJrc5HsNvMAuY/I/78JqX2j7KIhJJAHBGkPkweNnFLWgnapOYFdosHCCXisPz1COF8eQTyu/YYcDXmYGsfUmyvqCyuBwBej+9YgW+YEInx3N8tk8G4VSZYHXFC+fq37aLpoOMEtIY6AwVkd8U1hKLTyVLLRG+qgM1Amuc6oES4s4SJLkc+d1SQitcn6aQRMqYOnMjv8AbSGPuvpF7bYZQDfiLq4tmPv8aLLPTL1eSj0wg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=OZ+DO+gmAr5KDH02vPQCSuYdZBiu00MfWbjeD33mTBM=; b=Nd+2xkwRh48PUJLwqo6oSFS7OqumXm1a/jjlj0YyujmnXsib0VOVy5VvaJN6qM+e6qnO6vM42XaUh0vFbsdQYOn+LCEeKsPRGLTQgih6nnCaUs8+VVczCflAHyQFsODVKI0vY2KO61PHOnrsa8o76ZVs9XL75fx9MceFdvrRGwDHqkQ0ido1BxH53Iyak4FnJEHTP47GAwiSb0o07FDNvv/5WyH8fReuQ9WBpJHl87xtV6X08x1bCeXBnRfX0PBQcDgK7DISH/JjbQM4xktF8/fQXH7Bv/99wPDq32WzuW6uUR7Lt50AWt1Goj8e3U+6MSd2ZMXdsw66+vhVJMiXjw== Received: from DS7PR03CA0017.namprd03.prod.outlook.com (2603:10b6:5:3b8::22) by BL3PR12MB6473.namprd12.prod.outlook.com (2603:10b6:208:3b9::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5654.20; Thu, 6 Oct 2022 11:02:08 +0000 Received: from DM6NAM11FT024.eop-nam11.prod.protection.outlook.com (2603:10b6:5:3b8:cafe::3a) by DS7PR03CA0017.outlook.office365.com (2603:10b6:5:3b8::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5676.26 via Frontend Transport; Thu, 6 Oct 2022 11:02:08 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by DM6NAM11FT024.mail.protection.outlook.com (10.13.172.159) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5709.10 via Frontend Transport; Thu, 6 Oct 2022 11:02:07 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.26; Thu, 6 Oct 2022 04:01:55 -0700 Received: from nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Thu, 6 Oct 2022 04:01:53 -0700 From: Dariusz Sosnowski To: Matan Azrad , Viacheslav Ovsiienko CC: Subject: [PATCH v2 3/8] common/mlx5: add hairpin RQ buffer type capabilities Date: Thu, 6 Oct 2022 11:01:00 +0000 Message-ID: <20221006110105.2986966-4-dsosnowski@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221006110105.2986966-1-dsosnowski@nvidia.com> References: <20221006110105.2986966-1-dsosnowski@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT024:EE_|BL3PR12MB6473:EE_ X-MS-Office365-Filtering-Correlation-Id: e1270f39-6215-4938-9160-08daa78a3619 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: PTwRUHVQMz+qv7ILmNuYbkrb3hOvCFNdl3zu9UquqsKRwCmyRFgfswCQh7iGbaBnQnAJJqDgNmQLAkJVPljVosI6r4TZd2G+c5INnfcRMFT8HTn+xaAE2c76qzm1f7tj9wMKEnCQ4Hu1sADA6ORQZERQOHSNNsv+SsGSuiT0ER2jI8udccQ6X0p11p+HK4TzBTH3NknqFfA6UEeLfpmmjBGIu3n28+KQ6MDvPKs6FBOxgp1HkZHP0bLJ0UuexcNdi1nj+TD+nX/ZS5c/STBukJXUsx86h/anqctfRT2lmJcYpU5EemKbxYCM37h69DiZJ3ro2XWy5wQQAqaWaa1UgnWW7ft5qYVifhB2xKiFeLQJ58qcx7PHW6v1gC8M3iJDWCGzJEviCi8uII37/aiNbv1rF/vFR3zj+j1kGFtKnKEOkExvmjJzUOl23iRVb6XcFnhQYmxDrqFlS4B+K9rU7ZJ95QEAJjyB/1kC7tHcDXPVXfDKbjs2a3Fe5m9r1EhvnwUGgkgsoz/GynIXN9RXU7davjjA/nZRgAZ9w0o3U5ouaTLmWHufW6w5+qytADf/K/b6cZlcfypJcL0miaYY+/Xm3fs+Ra64LfUWiTg6KC/9z1+8OCuAEQu3C3QioCWV4fzMK0k/p0iMqf7ZhLMeybYCj/PTnRx+TDQ4wzutrE+zfTrJSknQwnfRoDgqcPZ67lwdNHXU1BZN3NRAWQzE45HQck+HZfit4s/52Q9mu1B9xH5ZfwmOkmS+NRVGv//WszU8TVfcEOUS+YI5vQDSkQ== X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230022)(4636009)(346002)(376002)(39860400002)(396003)(136003)(451199015)(40470700004)(36840700001)(46966006)(1076003)(36756003)(55016003)(82310400005)(40480700001)(40460700003)(110136005)(83380400001)(2616005)(426003)(70206006)(47076005)(16526019)(41300700001)(6666004)(8676002)(2906002)(478600001)(186003)(7696005)(8936002)(6286002)(86362001)(5660300002)(336012)(356005)(36860700001)(82740400003)(26005)(4326008)(70586007)(6636002)(316002)(7636003); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Oct 2022 11:02:07.9598 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e1270f39-6215-4938-9160-08daa78a3619 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT024.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL3PR12MB6473 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch adds new HCA capability related to hairpin RQs. This new capability, hairpin_data_buffer_locked, indicates whether HCA supports locking data buffer of hairpin RQ in ICMC (Interconnect Context Memory Cache). Struct used to define RQ configuration (RQ context) is extended with hairpin_data_buffer_type field, which configures data buffer for hairpin RQ. It can take the following values: - MLX5_RQC_HAIRPIN_DATA_BUFFER_TYPE_UNLOCKED_INTERNAL_BUFFER - hairpin RQ's data buffer is stored in unlocked memory in ICMC. - MLX5_RQC_HAIRPIN_DATA_BUFFER_TYPE_LOCKED_INTERNAL_BUFFER - hairpin RQ's data buffer is stored in locked memory in ICMC. Signed-off-by: Dariusz Sosnowski Acked-by: Viacheslav Ovsiienko --- drivers/common/mlx5/mlx5_devx_cmds.c | 3 +++ drivers/common/mlx5/mlx5_devx_cmds.h | 2 ++ drivers/common/mlx5/mlx5_prm.h | 12 ++++++++++-- 3 files changed, 15 insertions(+), 2 deletions(-) diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c index a1e8179568..76f0b6724f 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.c +++ b/drivers/common/mlx5/mlx5_devx_cmds.c @@ -993,6 +993,8 @@ mlx5_devx_cmd_query_hca_attr(void *ctx, hairpin_sq_wqe_bb_size); attr->hairpin_sq_wq_in_host_mem = MLX5_GET(cmd_hca_cap_2, hcattr, hairpin_sq_wq_in_host_mem); + attr->hairpin_data_buffer_locked = MLX5_GET(cmd_hca_cap_2, hcattr, + hairpin_data_buffer_locked); } if (attr->log_min_stride_wqe_sz == 0) attr->log_min_stride_wqe_sz = MLX5_MPRQ_LOG_MIN_STRIDE_WQE_SIZE; @@ -1293,6 +1295,7 @@ mlx5_devx_cmd_create_rq(void *ctx, MLX5_SET(rqc, rq_ctx, state, rq_attr->state); MLX5_SET(rqc, rq_ctx, flush_in_error_en, rq_attr->flush_in_error_en); MLX5_SET(rqc, rq_ctx, hairpin, rq_attr->hairpin); + MLX5_SET(rqc, rq_ctx, hairpin_data_buffer_type, rq_attr->hairpin_data_buffer_type); MLX5_SET(rqc, rq_ctx, user_index, rq_attr->user_index); MLX5_SET(rqc, rq_ctx, cqn, rq_attr->cqn); MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id); diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h index 9ac2d75df4..cceaf3411d 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.h +++ b/drivers/common/mlx5/mlx5_devx_cmds.h @@ -193,6 +193,7 @@ struct mlx5_hca_attr { uint32_t log_max_hairpin_num_packets:5; uint32_t hairpin_sq_wqe_bb_size:4; uint32_t hairpin_sq_wq_in_host_mem:1; + uint32_t hairpin_data_buffer_locked:1; uint32_t vhca_id:16; uint32_t relaxed_ordering_write:1; uint32_t relaxed_ordering_read:1; @@ -313,6 +314,7 @@ struct mlx5_devx_create_rq_attr { uint32_t state:4; uint32_t flush_in_error_en:1; uint32_t hairpin:1; + uint32_t hairpin_data_buffer_type:3; uint32_t ts_format:2; uint32_t user_index:24; uint32_t cqn:24; diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index 04d35ca845..9c1c93f916 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -2024,7 +2024,8 @@ struct mlx5_ifc_cmd_hca_cap_2_bits { u8 reserved_at_160[0x3]; u8 hairpin_sq_wqe_bb_size[0x5]; u8 hairpin_sq_wq_in_host_mem[0x1]; - u8 reserved_at_169[0x697]; + u8 hairpin_data_buffer_locked[0x1]; + u8 reserved_at_16a[0x696]; }; struct mlx5_ifc_esw_cap_bits { @@ -2304,7 +2305,9 @@ struct mlx5_ifc_rqc_bits { u8 reserved_at_c[0x1]; u8 flush_in_error_en[0x1]; u8 hairpin[0x1]; - u8 reserved_at_f[0xB]; + u8 reserved_at_f[0x6]; + u8 hairpin_data_buffer_type[0x3]; + u8 reserved_at_a8[0x2]; u8 ts_format[0x02]; u8 reserved_at_1c[0x4]; u8 reserved_at_20[0x8]; @@ -2813,6 +2816,11 @@ enum { MLX5_CQE_SIZE_128B = 0x1, }; +enum { + MLX5_RQC_HAIRPIN_DATA_BUFFER_TYPE_UNLOCKED_INTERNAL_BUFFER = 0x0, + MLX5_RQC_HAIRPIN_DATA_BUFFER_TYPE_LOCKED_INTERNAL_BUFFER = 0x1, +}; + struct mlx5_ifc_cqc_bits { u8 status[0x4]; u8 as_notify[0x1]; From patchwork Thu Oct 6 11:01:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dariusz Sosnowski X-Patchwork-Id: 117452 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 69F5DA00C2; Thu, 6 Oct 2022 13:02:31 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9DE7042C1C; Thu, 6 Oct 2022 13:02:13 +0200 (CEST) Received: from NAM02-BN1-obe.outbound.protection.outlook.com (mail-bn1nam07on2043.outbound.protection.outlook.com [40.107.212.43]) by mails.dpdk.org (Postfix) with ESMTP id 0947F42C19 for ; Thu, 6 Oct 2022 13:02:12 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=hg25p/hOJ5WQPg9XVuwRvZHsBJhme8qGSpKDnP8sXKhmjbJdoMVTnyvtMsMmAMbd+kgLufSHqmpti/4EAz7W0ECRcA/bzFC/K42DKaivIKeOnhZ5UzFb1qlX6hLPoHQ6dAuLOh29d5qbFC69ez3cyY/mtkVrjXFC0JDrRSin1GrNxA3xlSPfR294f2qODM5796Rrvgo4PGivHGU/M1OHVCReAvw9j0DSjlieXjkFopWvmuDlTGZInh9lFPAE6zAPw4ec9t1wfK5lY7gpeTu4/NZqpbLJTJr2rSmBVDrGjXsyk5xlNnUxxe7ER6nI0oXUCl/IdvTe4abGKXzjBy1lBw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=VxgWJ9RFsEW+BQWTPqoiyrs+5qt5GV3VBC8bb2b3lkk=; b=h82yUz4qNzHLMG8JOFGshHhbtKDD7X7R0k3K30NTC368FVNART1R/hqxAOJrGDKRtIaVql4zAMyQiNtsZksJXXhVWojcvJL7ApFaRKj+AXZkP6AA/pzZ3QM2UURiCjOQEXzMAnCxXebTyhCJQBMU1nqoKZaKL49HTGVrUvil0WMhc5ayuMhrl3xW1ukTNfLXBlc4UWfox9TbS1EBdA3OzSHoMBgFRvxUG5h+DJ82VwNDxfUQ+QDj1yEw/77qJpkcsy5kU9MyVoFUx3zovT7dbfe6r/lCRK7z3Blhcdxew90GQcUX9W8L9Z+0qZjhHdaVL+wFZF/GzyYqkkMxDcZZsg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=VxgWJ9RFsEW+BQWTPqoiyrs+5qt5GV3VBC8bb2b3lkk=; b=kK+Ktx5KaZ5weFFgP67bL5A+dxcYAmMdyMNvh84TDLtwVn/lAXivExMwDsAom7NIVnQo0uwDSB9jRYC/C6WZwae8Tco0xX21pkzIGvIGsm3frumt2Ita8QkLi/0LntEvjfXFU7ObuuKSrxGC7c+b8PtN5YWqVIgI57Hwd1IUzXRwh4bFsfT9NMjuItdd0L5cVNt+jX+OHXCufmOWlc0u8ureeZc91zwKlcikh0kXKtAVGjsLrN/oD1QALBJ3ZchECzUYqcWWKar9GB6/6V0OooFFX94M8pYH6As8ikGFkws3DqzRHQXibvgN98xeSvWoQt0xZgl+z+ABebXuYC7/0A== Received: from DS7PR03CA0021.namprd03.prod.outlook.com (2603:10b6:5:3b8::26) by PH8PR12MB7230.namprd12.prod.outlook.com (2603:10b6:510:226::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5676.18; Thu, 6 Oct 2022 11:02:10 +0000 Received: from DM6NAM11FT024.eop-nam11.prod.protection.outlook.com (2603:10b6:5:3b8:cafe::4b) by DS7PR03CA0021.outlook.office365.com (2603:10b6:5:3b8::26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5676.23 via Frontend Transport; Thu, 6 Oct 2022 11:02:10 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by DM6NAM11FT024.mail.protection.outlook.com (10.13.172.159) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5709.10 via Frontend Transport; Thu, 6 Oct 2022 11:02:09 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.26; Thu, 6 Oct 2022 04:01:57 -0700 Received: from nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Thu, 6 Oct 2022 04:01:56 -0700 From: Dariusz Sosnowski To: Matan Azrad , Viacheslav Ovsiienko CC: Subject: [PATCH v2 4/8] net/mlx5: allow hairpin Tx queue in RTE memory Date: Thu, 6 Oct 2022 11:01:01 +0000 Message-ID: <20221006110105.2986966-5-dsosnowski@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221006110105.2986966-1-dsosnowski@nvidia.com> References: <20221006110105.2986966-1-dsosnowski@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT024:EE_|PH8PR12MB7230:EE_ X-MS-Office365-Filtering-Correlation-Id: cb0d6539-f850-4148-cd9d-08daa78a373e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: X3AtAdyToGV8++qWYE8ILgYDXIgOPTFVh9IQsDwGlEyCBqu3GDRjsi04R9RlYJlt14k9b56NP56MUT6Yk75/B08hS90NNHuxjOELj0QIunN9J4aMMKDuCSmEf7zxuHrgV4FjtMCpgEykWOGtsQ0xG6/3gfIyti6vXMMsxhLYhJtGW+Uz817d6LvGE3M2cD3AJvHX2skjJnBR4UCBx6QbiCw2LKnJx32ukHc/J7GFjTKn9vXQUGvQ6j4OiiD5t1m31olQ+BYo6feHbkCYsvUjd5IZzZ5MRz9PeNkey70FkEbmoaLKKGTWGiiDMAFJbzOCfzRv5R+U/gxp496HAbMHk/7OQVHLWciNJk1zT7m3DgcsM6WlAim2b6Rd76rbhk2z/AqAIVubqgL4c4NKXCkdu2vkKl+zPFnBKlhRCPuRh33jNeTfKuLo3cCYrWA/6HyQ4L/dKnhOTSEahnolz1E9abX05Ged/59fofHqOAQND6/u49J64wxDIC5XT1aNmm9UNrtkJJVf+usV+w1xOrkWKyi63ptUT7RHqVArGk5AVNqVKbJ8k1MirI43yxwJHoKuZbY79USuWpAPJ4f/2hh+pNedkELNisUvkcAjcf9E2oH9ICIoMkTX1FQmX8hPEOlrmpUcHNwOTdBsqP8NBhI3SuNG3Xf3w2jBVEPjp+wT6sjMt11wG38eQycUyaBQeyCmljhLvSiDt1ecb8Dq+GfrofXhCDp+j6jHugF0RWeCnqTps37WKYsPTEGpFO1JgegugQISiiZsiwMLJqY8TYKrVg== X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230022)(4636009)(396003)(376002)(39860400002)(136003)(346002)(451199015)(36840700001)(40470700004)(46966006)(5660300002)(41300700001)(186003)(47076005)(316002)(6666004)(16526019)(110136005)(356005)(6636002)(8676002)(86362001)(2906002)(70586007)(70206006)(55016003)(1076003)(336012)(40460700003)(7636003)(82740400003)(82310400005)(8936002)(36756003)(83380400001)(478600001)(4326008)(2616005)(426003)(6286002)(7696005)(26005)(40480700001)(36860700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Oct 2022 11:02:09.8816 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cb0d6539-f850-4148-cd9d-08daa78a373e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT024.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB7230 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch adds a capability to place hairpin Tx queue in host memory managed by DPDK. This capability is equivalent to storing hairpin SQ's WQ buffer in host memory. Hairpin Tx queue creation is extended with allocating a memory buffer of proper size (calculated from required number of packets and WQE BB size advertised in HCA capabilities). force_memory flag of hairpin queue configuration is also supported. If it is set and: - allocation of memory buffer fails, - or hairpin SQ creation fails, then device start will fail. If it is unset, PMD will fallback to creating the hairpin SQ with WQ buffer located in unlocked device memory. Signed-off-by: Dariusz Sosnowski Acked-by: Viacheslav Ovsiienko --- drivers/net/mlx5/mlx5.h | 2 + drivers/net/mlx5/mlx5_devx.c | 119 ++++++++++++++++++++++++++++++--- drivers/net/mlx5/mlx5_ethdev.c | 4 ++ 3 files changed, 116 insertions(+), 9 deletions(-) diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index 95ecbea39e..3c9e6bad53 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -1386,6 +1386,8 @@ struct mlx5_txq_obj { struct mlx5_devx_obj *sq; /* DevX object for Sx queue. */ struct mlx5_devx_obj *tis; /* The TIS object. */ + void *umem_buf_wq_buffer; + void *umem_obj_wq_buffer; }; struct { struct rte_eth_dev *dev; diff --git a/drivers/net/mlx5/mlx5_devx.c b/drivers/net/mlx5/mlx5_devx.c index 943aa8ef57..c61c34bd99 100644 --- a/drivers/net/mlx5/mlx5_devx.c +++ b/drivers/net/mlx5/mlx5_devx.c @@ -1185,18 +1185,23 @@ static int mlx5_txq_obj_hairpin_new(struct rte_eth_dev *dev, uint16_t idx) { struct mlx5_priv *priv = dev->data->dev_private; + struct mlx5_hca_attr *hca_attr = &priv->sh->cdev->config.hca_attr; struct mlx5_txq_data *txq_data = (*priv->txqs)[idx]; struct mlx5_txq_ctrl *txq_ctrl = container_of(txq_data, struct mlx5_txq_ctrl, txq); - struct mlx5_devx_create_sq_attr attr = { 0 }; + struct mlx5_devx_create_sq_attr dev_mem_attr = { 0 }; + struct mlx5_devx_create_sq_attr host_mem_attr = { 0 }; struct mlx5_txq_obj *tmpl = txq_ctrl->obj; + void *umem_buf = NULL; + void *umem_obj = NULL; uint32_t max_wq_data; MLX5_ASSERT(txq_data); MLX5_ASSERT(tmpl); tmpl->txq_ctrl = txq_ctrl; - attr.hairpin = 1; - attr.tis_lst_sz = 1; + dev_mem_attr.hairpin = 1; + dev_mem_attr.tis_lst_sz = 1; + dev_mem_attr.tis_num = mlx5_get_txq_tis_num(dev, idx); max_wq_data = priv->sh->cdev->config.hca_attr.log_max_hairpin_wq_data_sz; /* Jumbo frames > 9KB should be supported, and more packets. */ @@ -1208,19 +1213,103 @@ mlx5_txq_obj_hairpin_new(struct rte_eth_dev *dev, uint16_t idx) rte_errno = ERANGE; return -rte_errno; } - attr.wq_attr.log_hairpin_data_sz = priv->config.log_hp_size; + dev_mem_attr.wq_attr.log_hairpin_data_sz = priv->config.log_hp_size; } else { - attr.wq_attr.log_hairpin_data_sz = + dev_mem_attr.wq_attr.log_hairpin_data_sz = (max_wq_data < MLX5_HAIRPIN_JUMBO_LOG_SIZE) ? max_wq_data : MLX5_HAIRPIN_JUMBO_LOG_SIZE; } /* Set the packets number to the maximum value for performance. */ - attr.wq_attr.log_hairpin_num_packets = - attr.wq_attr.log_hairpin_data_sz - + dev_mem_attr.wq_attr.log_hairpin_num_packets = + dev_mem_attr.wq_attr.log_hairpin_data_sz - MLX5_HAIRPIN_QUEUE_STRIDE; + dev_mem_attr.hairpin_wq_buffer_type = MLX5_SQC_HAIRPIN_WQ_BUFFER_TYPE_INTERNAL_BUFFER; + if (txq_ctrl->hairpin_conf.use_rte_memory) { + uint32_t umem_size; + uint32_t umem_dbrec; + size_t alignment = MLX5_WQE_BUF_ALIGNMENT; - attr.tis_num = mlx5_get_txq_tis_num(dev, idx); - tmpl->sq = mlx5_devx_cmd_create_sq(priv->sh->cdev->ctx, &attr); + if (alignment == (size_t)-1) { + DRV_LOG(ERR, "Failed to get WQE buf alignment."); + rte_errno = ENOMEM; + return -rte_errno; + } + /* + * It is assumed that configuration is verified against capabilities + * during queue setup. + */ + MLX5_ASSERT(hca_attr->hairpin_sq_wq_in_host_mem); + MLX5_ASSERT(hca_attr->hairpin_sq_wqe_bb_size > 0); + rte_memcpy(&host_mem_attr, &dev_mem_attr, sizeof(host_mem_attr)); + umem_size = MLX5_WQE_SIZE * + RTE_BIT32(host_mem_attr.wq_attr.log_hairpin_num_packets); + umem_dbrec = RTE_ALIGN(umem_size, MLX5_DBR_SIZE); + umem_size += MLX5_DBR_SIZE; + umem_buf = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, umem_size, + alignment, priv->sh->numa_node); + if (umem_buf == NULL && txq_ctrl->hairpin_conf.force_memory) { + DRV_LOG(ERR, "Failed to allocate memory for hairpin TX queue"); + rte_errno = ENOMEM; + return -rte_errno; + } else if (umem_buf == NULL && !txq_ctrl->hairpin_conf.force_memory) { + DRV_LOG(WARNING, "Failed to allocate memory for hairpin TX queue." + " Falling back to TX queue located on the device."); + goto create_sq_on_device; + } + umem_obj = mlx5_os_umem_reg(priv->sh->cdev->ctx, + (void *)(uintptr_t)umem_buf, + umem_size, + IBV_ACCESS_LOCAL_WRITE); + if (umem_obj == NULL && txq_ctrl->hairpin_conf.force_memory) { + DRV_LOG(ERR, "Failed to register UMEM for hairpin TX queue"); + mlx5_free(umem_buf); + return -rte_errno; + } else if (umem_obj == NULL && !txq_ctrl->hairpin_conf.force_memory) { + DRV_LOG(WARNING, "Failed to register UMEM for hairpin TX queue." + " Falling back to TX queue located on the device."); + rte_errno = 0; + mlx5_free(umem_buf); + goto create_sq_on_device; + } + host_mem_attr.wq_attr.wq_type = MLX5_WQ_TYPE_CYCLIC; + host_mem_attr.wq_attr.wq_umem_valid = 1; + host_mem_attr.wq_attr.wq_umem_id = mlx5_os_get_umem_id(umem_obj); + host_mem_attr.wq_attr.wq_umem_offset = 0; + host_mem_attr.wq_attr.dbr_umem_valid = 1; + host_mem_attr.wq_attr.dbr_umem_id = host_mem_attr.wq_attr.wq_umem_id; + host_mem_attr.wq_attr.dbr_addr = umem_dbrec; + host_mem_attr.wq_attr.log_wq_stride = rte_log2_u32(MLX5_WQE_SIZE); + host_mem_attr.wq_attr.log_wq_sz = + host_mem_attr.wq_attr.log_hairpin_num_packets * + hca_attr->hairpin_sq_wqe_bb_size; + host_mem_attr.wq_attr.log_wq_pg_sz = MLX5_LOG_PAGE_SIZE; + host_mem_attr.hairpin_wq_buffer_type = MLX5_SQC_HAIRPIN_WQ_BUFFER_TYPE_HOST_MEMORY; + tmpl->sq = mlx5_devx_cmd_create_sq(priv->sh->cdev->ctx, &host_mem_attr); + if (!tmpl->sq && txq_ctrl->hairpin_conf.force_memory) { + DRV_LOG(ERR, + "Port %u tx hairpin queue %u can't create SQ object.", + dev->data->port_id, idx); + claim_zero(mlx5_os_umem_dereg(umem_obj)); + mlx5_free(umem_buf); + return -rte_errno; + } else if (!tmpl->sq && !txq_ctrl->hairpin_conf.force_memory) { + DRV_LOG(WARNING, + "Port %u tx hairpin queue %u failed to allocate SQ object" + " using host memory. Falling back to TX queue located" + " on the device", + dev->data->port_id, idx); + rte_errno = 0; + claim_zero(mlx5_os_umem_dereg(umem_obj)); + mlx5_free(umem_buf); + goto create_sq_on_device; + } + tmpl->umem_buf_wq_buffer = umem_buf; + tmpl->umem_obj_wq_buffer = umem_obj; + return 0; + } + +create_sq_on_device: + tmpl->sq = mlx5_devx_cmd_create_sq(priv->sh->cdev->ctx, &dev_mem_attr); if (!tmpl->sq) { DRV_LOG(ERR, "Port %u tx hairpin queue %u can't create SQ object.", @@ -1452,8 +1541,20 @@ mlx5_txq_devx_obj_release(struct mlx5_txq_obj *txq_obj) { MLX5_ASSERT(txq_obj); if (txq_obj->txq_ctrl->is_hairpin) { + if (txq_obj->sq) { + claim_zero(mlx5_devx_cmd_destroy(txq_obj->sq)); + txq_obj->sq = NULL; + } if (txq_obj->tis) claim_zero(mlx5_devx_cmd_destroy(txq_obj->tis)); + if (txq_obj->umem_obj_wq_buffer) { + claim_zero(mlx5_os_umem_dereg(txq_obj->umem_obj_wq_buffer)); + txq_obj->umem_obj_wq_buffer = NULL; + } + if (txq_obj->umem_buf_wq_buffer) { + mlx5_free(txq_obj->umem_buf_wq_buffer); + txq_obj->umem_buf_wq_buffer = NULL; + } #if defined(HAVE_MLX5DV_DEVX_UAR_OFFSET) || !defined(HAVE_INFINIBAND_VERBS_H) } else { mlx5_txq_release_devx_resources(txq_obj); diff --git a/drivers/net/mlx5/mlx5_ethdev.c b/drivers/net/mlx5/mlx5_ethdev.c index a5c7ca8c52..c59005ea2b 100644 --- a/drivers/net/mlx5/mlx5_ethdev.c +++ b/drivers/net/mlx5/mlx5_ethdev.c @@ -729,6 +729,7 @@ int mlx5_hairpin_cap_get(struct rte_eth_dev *dev, struct rte_eth_hairpin_cap *cap) { struct mlx5_priv *priv = dev->data->dev_private; + struct mlx5_hca_attr *hca_attr; if (!mlx5_devx_obj_ops_en(priv->sh)) { rte_errno = ENOTSUP; @@ -738,5 +739,8 @@ mlx5_hairpin_cap_get(struct rte_eth_dev *dev, struct rte_eth_hairpin_cap *cap) cap->max_rx_2_tx = 1; cap->max_tx_2_rx = 1; cap->max_nb_desc = 8192; + hca_attr = &priv->sh->cdev->config.hca_attr; + cap->tx_cap.locked_device_memory = 0; + cap->tx_cap.rte_memory = hca_attr->hairpin_sq_wq_in_host_mem; return 0; } From patchwork Thu Oct 6 11:01:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dariusz Sosnowski X-Patchwork-Id: 117453 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A274BA00C2; Thu, 6 Oct 2022 13:02:40 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id CD74042C25; Thu, 6 Oct 2022 13:02:14 +0200 (CEST) Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2087.outbound.protection.outlook.com [40.107.223.87]) by mails.dpdk.org (Postfix) with ESMTP id 9241042C19 for ; Thu, 6 Oct 2022 13:02:13 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=TDrfTEIsv5Ot06b86Q+X5j8qTixqs15iMco5UGCPUHloAeFF5ttz//isodd3m5n7an2cAKdljpAGvRvCinfk/DRYDNH4a/pF79qiIz8oIkghsmFk4X5utRq/Z7qkFx4PPKqqGhStTIkOH85WV78UdEwolinkQyGpGPTYW50SlMji5h6zaVD4ky/5I7FXaP0OBUjmY9l6l6OAOxN0uWdZtK9PGFg2dne+FzPY3wpBaeDPXZMLcj0dCby5wtttbIraDnaM1B7oC6bnhsVWcCNQ8lmgU6eAWb1pcgMOZboYLHT0V2HnXloDDhXxjtyWA0Nkmc0tLm2QLTH32gzoro6wPA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=RqwpN8Yx1IGFGyUJZRnRIdRwe60PUBr1xh4glNPlknM=; b=lXgsdH/M/OYwyf7m2DlEy6YVEGICsM0qBzFZM1VtfF9TmiNmooZrSUd0JrtHMedSEQZG+gthAC0880xeTER7IA/CM+3n37XDJrAmgTJ4Soc3P1KlW2h34I8kCqWogY5QuDWH1JXD1u3jRcETB+poHIc7MFlswL8Yk8z3xJKowgAuWSgu1ntQ89zvfmQ8Q+nGkApF6NTIqo6KjvcFGWr0hwGohhLhxQybRS62SEgkLJUQO2P88jeaYctofDqOqFLN1mflop5ydqPsGXxqnvllzS+HvnVqR7qcy76s0vOBbHsOwfAgfRg0riTFvhx25hmYhjNG0VJ5pNv22ee2FQB7Ag== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=RqwpN8Yx1IGFGyUJZRnRIdRwe60PUBr1xh4glNPlknM=; b=ukTLoEKqDGujt4oU6Ts3bP2hL9QJUspAEpPsH6LkpZPMm0k1K9e9GvXelIn39NqOfun2cjWb1Ak/K3Eh8ZfSUZRT56nYK8/qQQ3EW6sRcV47lhmT9OSEYiehRlULq0LmkBASGjG0QVsGbMu6mESGeryVTXxWJBYfS/5rQDSAMUZS2rwbj05wCFxxkc57Q0iZN3n7VOstR0Sr9JehSkAsGYBWiHdqOUce6KS2AEuLUVGnixO5FDW49rO3bzNsLVo4ivNngxEDZGEPfCaT6+UIfgqAetp2tukJABPb3gJsHuMjr+SA7hv7Qb+gCJSHHmNvmjyrzCHLNpequtdM7JopHw== Received: from BN0PR04CA0198.namprd04.prod.outlook.com (2603:10b6:408:e9::23) by PH7PR12MB6563.namprd12.prod.outlook.com (2603:10b6:510:211::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5676.31; Thu, 6 Oct 2022 11:02:11 +0000 Received: from BN8NAM11FT020.eop-nam11.prod.protection.outlook.com (2603:10b6:408:e9:cafe::3) by BN0PR04CA0198.outlook.office365.com (2603:10b6:408:e9::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5676.23 via Frontend Transport; Thu, 6 Oct 2022 11:02:11 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by BN8NAM11FT020.mail.protection.outlook.com (10.13.176.223) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5709.10 via Frontend Transport; Thu, 6 Oct 2022 11:02:11 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.26; Thu, 6 Oct 2022 04:02:00 -0700 Received: from nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Thu, 6 Oct 2022 04:01:58 -0700 From: Dariusz Sosnowski To: Matan Azrad , Viacheslav Ovsiienko CC: Subject: [PATCH v2 5/8] net/mlx5: allow hairpin Rx queue in locked memory Date: Thu, 6 Oct 2022 11:01:02 +0000 Message-ID: <20221006110105.2986966-6-dsosnowski@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221006110105.2986966-1-dsosnowski@nvidia.com> References: <20221006110105.2986966-1-dsosnowski@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT020:EE_|PH7PR12MB6563:EE_ X-MS-Office365-Filtering-Correlation-Id: 626df5c5-52fe-4b15-c5dc-08daa78a381d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: jwf+r/dJV4wVEOb9QpBro8XYiETigUCmc06sCVxrkOoFUeG6DcOyVJAEoeOlXirtO9mQjgaL+6zsRB3j9jKuqSnY9hx7OPfGwCpaZy8m+CxaKbf5CpS62hK4RAZzsQDffuoREzRECBLbXD6IamsDzFqS4SxUmkjSKrlUVemrWLm/eaTXIbCoVa7UwEs04hhILBNNIJ0xmFGmebpJqvYrnRGtAu3ZmHhpqcLmn6xAWQWLMHp3PoIDTzTL6cfeFtc0bYDJb85cyn6X5imx4T0z42pihea09bc4PkISk/o2mj0IKM920TS/OhldoyF7eVZJsZnjfeGFKqzm2YE9thkFb/erUUSDn5n7m7GSU3HUrSXPFeOsBcjKfPBc4v2IB0u9o2yjUyKedDJFOb+otamUP6DwNaNfSPsjx+cCr+B5EQ7IU0jTifBL4qMCJzfUWQDL3enHZQdi+Nn/NNw7slLkIrT14UhGjwwHITV5m5QLMXRwVc6odp5F6yl4WaevelKkkTIdUu2870J1nmCET7HBo4Q56vh4ihk9Tw0Pw9A7TRYxlosggS301AFKlAI+ltaRm76PpLVbQLRqn/vlaV0lHuAiqPg0dgg7GQoqGEtHl+rkgxAkOgUgxDdm0iNXC1mlqSYZHnuMeJ69ZfC+eG/SpMkLRZTvJo17HQiMNxYaX72Vte9nhzgbP0LeATQZE+CcfTZBLxzqgRteqlHYsVeigN/6tkmnXvMDbvVA+TXXZoE2dZ+DEHrq/3BjG5s+OqhobO5JIu3IRVQlPXLlbzAilw== X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230022)(4636009)(136003)(39860400002)(346002)(396003)(376002)(451199015)(36840700001)(46966006)(40470700004)(40480700001)(1076003)(2616005)(2906002)(186003)(82310400005)(16526019)(356005)(316002)(70206006)(36756003)(6666004)(40460700003)(70586007)(6636002)(4326008)(478600001)(8676002)(55016003)(86362001)(110136005)(41300700001)(6286002)(336012)(7696005)(8936002)(5660300002)(26005)(47076005)(83380400001)(82740400003)(36860700001)(7636003)(426003); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Oct 2022 11:02:11.3116 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 626df5c5-52fe-4b15-c5dc-08daa78a381d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT020.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6563 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch adds a capability to place hairpin Rx queue in locked device memory. This capability is equivalent to storing hairpin RQ's data buffers in locked internal device memory. Hairpin Rx queue creation is extended with requesting that RQ is allocated in locked internal device memory. If allocation fails and force_memory hairpin configuration is set, then hairpin queue creation (and, as a result, device start) fails. If force_memory is unset, then PMD will fallback to allocating memory for hairpin RQ in unlocked internal device memory. To allow such allocation, the user must set HAIRPIN_DATA_BUFFER_LOCK flag in FW using mlxconfig tool. Signed-off-by: Dariusz Sosnowski Acked-by: Viacheslav Ovsiienko --- doc/guides/platform/mlx5.rst | 5 ++++ drivers/net/mlx5/mlx5_devx.c | 51 ++++++++++++++++++++++++++++------ drivers/net/mlx5/mlx5_ethdev.c | 2 ++ 3 files changed, 49 insertions(+), 9 deletions(-) diff --git a/doc/guides/platform/mlx5.rst b/doc/guides/platform/mlx5.rst index 46b394c4ee..3cc1dd29e2 100644 --- a/doc/guides/platform/mlx5.rst +++ b/doc/guides/platform/mlx5.rst @@ -555,6 +555,11 @@ Below are some firmware configurations listed. REAL_TIME_CLOCK_ENABLE=1 +- allow locking hairpin RQ data buffer in device memory:: + + HAIRPIN_DATA_BUFFER_LOCK=1 + MEMIC_SIZE_LIMIT=0 + .. _mlx5_common_driver_options: diff --git a/drivers/net/mlx5/mlx5_devx.c b/drivers/net/mlx5/mlx5_devx.c index c61c34bd99..fe303a73bb 100644 --- a/drivers/net/mlx5/mlx5_devx.c +++ b/drivers/net/mlx5/mlx5_devx.c @@ -468,14 +468,16 @@ mlx5_rxq_obj_hairpin_new(struct mlx5_rxq_priv *rxq) { uint16_t idx = rxq->idx; struct mlx5_priv *priv = rxq->priv; + struct mlx5_hca_attr *hca_attr __rte_unused = &priv->sh->cdev->config.hca_attr; struct mlx5_rxq_ctrl *rxq_ctrl = rxq->ctrl; - struct mlx5_devx_create_rq_attr attr = { 0 }; + struct mlx5_devx_create_rq_attr unlocked_attr = { 0 }; + struct mlx5_devx_create_rq_attr locked_attr = { 0 }; struct mlx5_rxq_obj *tmpl = rxq_ctrl->obj; uint32_t max_wq_data; MLX5_ASSERT(rxq != NULL && rxq->ctrl != NULL && tmpl != NULL); tmpl->rxq_ctrl = rxq_ctrl; - attr.hairpin = 1; + unlocked_attr.hairpin = 1; max_wq_data = priv->sh->cdev->config.hca_attr.log_max_hairpin_wq_data_sz; /* Jumbo frames > 9KB should be supported, and more packets. */ @@ -487,20 +489,50 @@ mlx5_rxq_obj_hairpin_new(struct mlx5_rxq_priv *rxq) rte_errno = ERANGE; return -rte_errno; } - attr.wq_attr.log_hairpin_data_sz = priv->config.log_hp_size; + unlocked_attr.wq_attr.log_hairpin_data_sz = priv->config.log_hp_size; } else { - attr.wq_attr.log_hairpin_data_sz = + unlocked_attr.wq_attr.log_hairpin_data_sz = (max_wq_data < MLX5_HAIRPIN_JUMBO_LOG_SIZE) ? max_wq_data : MLX5_HAIRPIN_JUMBO_LOG_SIZE; } /* Set the packets number to the maximum value for performance. */ - attr.wq_attr.log_hairpin_num_packets = - attr.wq_attr.log_hairpin_data_sz - + unlocked_attr.wq_attr.log_hairpin_num_packets = + unlocked_attr.wq_attr.log_hairpin_data_sz - MLX5_HAIRPIN_QUEUE_STRIDE; - attr.counter_set_id = priv->counter_set_id; + unlocked_attr.counter_set_id = priv->counter_set_id; rxq_ctrl->rxq.delay_drop = priv->config.hp_delay_drop; - attr.delay_drop_en = priv->config.hp_delay_drop; - tmpl->rq = mlx5_devx_cmd_create_rq(priv->sh->cdev->ctx, &attr, + unlocked_attr.delay_drop_en = priv->config.hp_delay_drop; + unlocked_attr.hairpin_data_buffer_type = + MLX5_RQC_HAIRPIN_DATA_BUFFER_TYPE_UNLOCKED_INTERNAL_BUFFER; + if (rxq->hairpin_conf.use_locked_device_memory) { + /* + * It is assumed that configuration is verified against capabilities + * during queue setup. + */ + MLX5_ASSERT(hca_attr->hairpin_data_buffer_locked); + rte_memcpy(&locked_attr, &unlocked_attr, sizeof(locked_attr)); + locked_attr.hairpin_data_buffer_type = + MLX5_RQC_HAIRPIN_DATA_BUFFER_TYPE_LOCKED_INTERNAL_BUFFER; + tmpl->rq = mlx5_devx_cmd_create_rq(priv->sh->cdev->ctx, &locked_attr, + rxq_ctrl->socket); + if (!tmpl->rq && rxq->hairpin_conf.force_memory) { + DRV_LOG(ERR, "Port %u Rx hairpin queue %u can't create RQ object" + " with locked memory buffer", + priv->dev_data->port_id, idx); + return -rte_errno; + } else if (!tmpl->rq && !rxq->hairpin_conf.force_memory) { + DRV_LOG(WARNING, "Port %u Rx hairpin queue %u can't create RQ object" + " with locked memory buffer. Falling back to unlocked" + " device memory.", + priv->dev_data->port_id, idx); + rte_errno = 0; + goto create_rq_unlocked; + } + goto create_rq_set_state; + } + +create_rq_unlocked: + tmpl->rq = mlx5_devx_cmd_create_rq(priv->sh->cdev->ctx, &unlocked_attr, rxq_ctrl->socket); if (!tmpl->rq) { DRV_LOG(ERR, @@ -509,6 +541,7 @@ mlx5_rxq_obj_hairpin_new(struct mlx5_rxq_priv *rxq) rte_errno = errno; return -rte_errno; } +create_rq_set_state: priv->dev_data->rx_queue_state[idx] = RTE_ETH_QUEUE_STATE_HAIRPIN; return 0; } diff --git a/drivers/net/mlx5/mlx5_ethdev.c b/drivers/net/mlx5/mlx5_ethdev.c index c59005ea2b..4a85415ff3 100644 --- a/drivers/net/mlx5/mlx5_ethdev.c +++ b/drivers/net/mlx5/mlx5_ethdev.c @@ -740,6 +740,8 @@ mlx5_hairpin_cap_get(struct rte_eth_dev *dev, struct rte_eth_hairpin_cap *cap) cap->max_tx_2_rx = 1; cap->max_nb_desc = 8192; hca_attr = &priv->sh->cdev->config.hca_attr; + cap->rx_cap.locked_device_memory = hca_attr->hairpin_data_buffer_locked; + cap->rx_cap.rte_memory = 0; cap->tx_cap.locked_device_memory = 0; cap->tx_cap.rte_memory = hca_attr->hairpin_sq_wq_in_host_mem; return 0; From patchwork Thu Oct 6 11:01:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dariusz Sosnowski X-Patchwork-Id: 117454 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 064CFA00C2; Thu, 6 Oct 2022 13:02:47 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1DB4242C1B; Thu, 6 Oct 2022 13:02:22 +0200 (CEST) Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2054.outbound.protection.outlook.com [40.107.244.54]) by mails.dpdk.org (Postfix) with ESMTP id 1AD5442C17 for ; Thu, 6 Oct 2022 13:02:20 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=COghkzNDyNZNuFvGEtSpNJuSTAftK93j1GJHyIEPblOGchnEHx5uOTs8/UfVyOONcVLbz4ikt3Z7N30RRSZjDZknZyyqdLwFng1qTtQ4a9DRRUNgEu884sfx8ZgFEzNgDzSLwK1YIX/CdoKyPxTxdOWagl6Sck8CSoLbKPlrzKDsaiOZbFc0083MMH7qgSjfEy7iCvRnEFqwNz7qTEWt49NuBEughKDXIGKwpwF2fjU7VPZ5GrggUbouCKtvWMHUNpo224IqpTVIhag+8SidYtY7ws1onqxZQmMwMSm3Cp9wV6Rnh6BwsQQ7DLIXwDDHMifd0w7nN7vql8dWD5Co4A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=+u4rBjgUF8FJiGunBf5Y+6C7BtvT3WRbs+eXXqOhLd8=; b=aj5y9t4zQ9REqbkYtG/KSm7CCpzNGdCrnObWweoBWRIgwS7m9BOrZyTYKOg4CRnyEg3gh3hQyrYlFyXlpztJQ7i2SJ7OSrB7G4M0GVTNR1JRxIyc61MYI/+Mmay6ZC4qQkl8FWCaqmfqbSPILJb20yPUW9MGJ1ceEwncArYIe+nxj4uZcPfQZW/lGFNZxHThyePfqQrDzGVfTv7a26XNCH2fdY7Ae2X6lgOTBbavkfUVIM08/JQ3p7bo43lDalV6SpWDx6ZDJA+kHXwstLTdWBtTEcxpFmnlsg+X/WZhc5o067NFTw6mGIe1OYWdp54UaDihEWBb5d10fqhseLFOww== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=+u4rBjgUF8FJiGunBf5Y+6C7BtvT3WRbs+eXXqOhLd8=; b=X826KAxuRHJOosXWKF81uljceDDvzTUvcjLLPTdFVfSI2aC48tpFr7uplyabfwb/QLZjx2OmtgEM59pyZYNmwDEnkMpj5Lp1GsyZhWoGiGe+mv6Y12eMl+YUmO++Fcc5SXSe0OMUqRdO7mmMkNEBheOWy26BVkmAacU3HJ0FmE2B6A+3UOoxPi/AZMmwVDF45325Q8pNDAcOJHZ13wRUeg0LVHKa9VUO0Kl+6O0F3FnMd+xMxbgylCEJfAaMU99Ll9MKuh3MfydqAr9rZElQkIdL885uQiQ7/1DWerw3AWGHWpvOUl8rSe9o4YqETv4iqFgfGtCSmbSpFdcwU6mQ2w== Received: from BN0PR04CA0193.namprd04.prod.outlook.com (2603:10b6:408:e9::18) by SN7PR12MB6689.namprd12.prod.outlook.com (2603:10b6:806:273::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5676.20; Thu, 6 Oct 2022 11:02:18 +0000 Received: from BN8NAM11FT020.eop-nam11.prod.protection.outlook.com (2603:10b6:408:e9:cafe::31) by BN0PR04CA0193.outlook.office365.com (2603:10b6:408:e9::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5676.23 via Frontend Transport; Thu, 6 Oct 2022 11:02:18 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by BN8NAM11FT020.mail.protection.outlook.com (10.13.176.223) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5709.10 via Frontend Transport; Thu, 6 Oct 2022 11:02:17 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.26; Thu, 6 Oct 2022 04:02:04 -0700 Received: from nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Thu, 6 Oct 2022 04:02:02 -0700 From: Dariusz Sosnowski To: Matan Azrad , Viacheslav Ovsiienko CC: Subject: [PATCH v2 6/8] doc: add notes for hairpin to mlx5 documentation Date: Thu, 6 Oct 2022 11:01:03 +0000 Message-ID: <20221006110105.2986966-7-dsosnowski@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221006110105.2986966-1-dsosnowski@nvidia.com> References: <20221006110105.2986966-1-dsosnowski@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT020:EE_|SN7PR12MB6689:EE_ X-MS-Office365-Filtering-Correlation-Id: a924439b-a36e-455b-a0d1-08daa78a3c10 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: /+LUd9RefP+E5jOmjHgXVHwbhyFuWV1+PeqVdxFyQse9kYh1qcj7vQrOypYU6SMbAwELnQ11AxOnR2dUjezz9MEicy9yvGYwJZVbXLoeBzernq+2o/3y7wyFR7ZhGdx0fmPb6O8bYRY+YStRnzQZpYomm4zeipDZf6u1/UDetWBKAgoahqh3q3DnNRg4B4IrwsuKGfflVPkc7LkT4MVklLUlNq9fxWu7ZVuvsepuNw1c+r3VltuWFQPAnb7rX8FoXiw/oa/UrhkmX46nGl82KrgEXC9ueUdLvRi9yN/vEtcmQhQuVG9QUuHqT4A1Ymjasx8EdtTyQahHY5vBLee2BtERGOCoooo3TrnRKVOWUkDkw7UwHAo4e5ISmwjzO8TvcmMypOijtgDxbD4dsqizNPOpKK1aZC2yM0iXSHLvTzbqHi7VRLXJA/GnOPOVswGk/e1Q8jUDaKdPap6CXKxfA+4NizVzfa7jlfVY3+xJHj4Yc2TXcIUgfiB5A9ViAPpc38pi70EzYa4zav2PLNbzB0QxZ0m8Q+K344WkDIeQQWV16ka5lWjV4anRo2xILdpfpp6NAYKzEKhE8CBPq1OnnZ0fi4rXdFYl39WTgyPyxlzlZLSKmi8kpiN/he27VVxF2+/ny1qvLM4xAKtwAE4kZTcTuBs2431Ts7uVIYQiR/lai2UiDhkk0KjOC4CJGDxkqUSfVsbrDdjULCuBH7EzXz9/ADOEQ7O58N4ES8cljv/N2wr0cgLakZKlUWEgtk3oh5j1sHI4NLsgBib0QN3j5A== X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230022)(4636009)(346002)(136003)(39860400002)(376002)(396003)(451199015)(36840700001)(46966006)(40470700004)(16526019)(186003)(40460700003)(2616005)(86362001)(1076003)(7636003)(6636002)(7696005)(110136005)(5660300002)(41300700001)(316002)(356005)(6286002)(478600001)(36756003)(70206006)(4326008)(70586007)(26005)(8676002)(82310400005)(55016003)(40480700001)(36860700001)(8936002)(47076005)(82740400003)(426003)(83380400001)(336012)(2906002); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Oct 2022 11:02:17.9363 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a924439b-a36e-455b-a0d1-08daa78a3c10 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT020.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB6689 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch extends mlx5 PMD documentation with more information regarding hairpin support. The following is added to mlx5 PMD documentation: - description of the default behavior of hairpin queues, - description of use_locked_device_memory effect on hairpin queue configuration, - description of use_rte_memory effect on hairpin queue configuration, - DPDK and OFED requirements for new memory options for hairpin. Signed-off-by: Dariusz Sosnowski Acked-by: Viacheslav Ovsiienko --- doc/guides/nics/mlx5.rst | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst index 3d4ee31f8d..997cb19ba2 100644 --- a/doc/guides/nics/mlx5.rst +++ b/doc/guides/nics/mlx5.rst @@ -1517,6 +1517,43 @@ behavior as librte_net_mlx4:: > port config all rss all > port start all +Notes for hairpin +----------------- + +NVIDIA Connect-X and BlueField devices support specifying memory +placement for hairpin Rx and Tx queues. This feature requires OFED 5.8. + +By default, data buffers and packet descriptors for hairpin queues are placed +in device memory which is shared with other resources (e.g. flow rules). + +Starting with DPDK 22.11 and OFED 5.8 applications are allowed to: + +#. Place data buffers and Rx packet descriptors in dedicated device memory. + Application can request that configuration through ``use_locked_device_memory`` + configuration option. + + Placing data buffers and Rx packet descriptors in dedicated device memory + can decrease latency on hairpinned traffic, since traffic processing + for the hairpin queue will not be memory starved. + + However, reserving device memory for hairpin Rx queues may decrease throughput + under heavy load, since less resources will be available on device. + + This option is supported only for Rx hairpin queues. + +#. Place Tx packet descriptors in host memory. + Application can request that configuration through ``use_rte_memory`` + configuration option. + + Placing Tx packet descritors in host memory can increase traffic throughput. + This results in more resources available on the device for other purposes, + which reduces memory contention on device. + Side effect of this option is visible increase in latency, since each packet + incurs additional PCI transactions. + + This option is supported only for Tx hairpin queues. + + Usage example ------------- From patchwork Thu Oct 6 11:01:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dariusz Sosnowski X-Patchwork-Id: 117455 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8A0D2A00C2; Thu, 6 Oct 2022 13:02:53 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2C4DD42C2A; Thu, 6 Oct 2022 13:02:27 +0200 (CEST) Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2040.outbound.protection.outlook.com [40.107.94.40]) by mails.dpdk.org (Postfix) with ESMTP id 80A2A42C29 for ; Thu, 6 Oct 2022 13:02:25 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=J8sC3TIZ+d3zHxKRgE/DvdKG3qD9PDEeJrNS/51UT1v8X65ahYby8zLM4TSHbmIf2VkujG4u0Q0QV554c9NGnn4nYqWzjCho2hO3kRKFQ0nfaI8BT1Izmcliq4fJKJN45uOFTbfeAiNGe+1j3ICp4o4ShFKJ8BxSiiRMLJxrX4tU9rT5IvyeRU3SACIz5qswxkKCpv95ckY1WcOioishd2NdANjd/pPFRgStNvACdtkefN/88/byO30vN04kVKQcdOnbWoHRLji4cdoyKYlxI1eyNNYZRsoykIG0T/P/JXpilchXlfTovzQcjZqVBMHGhztoi9rb3eAXLNewb+MNZw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Nqa6e73nlLKek/zoPRxKR44O9u+smjikRMB8IIS2kFM=; b=Qx1vpITrR6KsFuAlv38xnq9GbboGPz8n2PIvdm8z68MYMjxZL78dTFA2nM3tXYU3E2B9Q2s2aoXf3WIjemz6rQ43ro3SizLMT9KnvGHR8ybxUOipzM4edgAqUci0EYEbC4pih9o3HTvwxTMv70cClvyBYxhQgEB+G0mGZu7PqfOj8bREHBh6gMIRz35p8jReGhLfjqxOja+WlsdOTF7LLiSdTy5Xve15aWv7K7AYvZf+HGuztov2mCSzqhptuYK34do1E62sp74/TUco+8xLkHaOLkJvQ9FWlZZbeK3i3FU9kcXkO5G6yz8bho2ttCYL8eSVebLg70OyjqOTwPRoVw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=intel.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Nqa6e73nlLKek/zoPRxKR44O9u+smjikRMB8IIS2kFM=; b=Aq+rvI9wxCz2WNTne7E6JGwnfG6BZEzmYNbwrvv+HNrynrcslK49aKJujObEnXNVW6sGt1OadrMSbi8G+MJlOkQ8vfQN2QoHtwOzIoHamdPdSVCXQubRV5BC81yLPijMtBFzA25C6JNyNCp30399CjeCO3u6iM6hN9RV7bzZd6xb0inxqzhqHEtirAK6i23XTnmW0pjebjYKWJAdeq1z3SppUHc4+CRQkLGnXFb8AHaS88iNXuSO2oCgNb31OOOW7wsiqDamgikPbOgCIHi3c5WDLjhhtahsioL8eu2Zecs7zNXcsd7QKa7zxKWPwxC5VECb8fiZ4DrDK3zuDbZ80g== Received: from BN0PR03CA0005.namprd03.prod.outlook.com (2603:10b6:408:e6::10) by LV2PR12MB5967.namprd12.prod.outlook.com (2603:10b6:408:170::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5676.28; Thu, 6 Oct 2022 11:02:23 +0000 Received: from BN8NAM11FT079.eop-nam11.prod.protection.outlook.com (2603:10b6:408:e6:cafe::ed) by BN0PR03CA0005.outlook.office365.com (2603:10b6:408:e6::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5676.23 via Frontend Transport; Thu, 6 Oct 2022 11:02:23 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by BN8NAM11FT079.mail.protection.outlook.com (10.13.177.61) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5709.10 via Frontend Transport; Thu, 6 Oct 2022 11:02:23 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.26; Thu, 6 Oct 2022 04:02:06 -0700 Received: from nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Thu, 6 Oct 2022 04:02:05 -0700 From: Dariusz Sosnowski To: Aman Singh , Yuying Zhang CC: Subject: [PATCH v2 7/8] app/testpmd: add hairpin queues memory modes Date: Thu, 6 Oct 2022 11:01:04 +0000 Message-ID: <20221006110105.2986966-8-dsosnowski@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221006110105.2986966-1-dsosnowski@nvidia.com> References: <20221006110105.2986966-1-dsosnowski@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT079:EE_|LV2PR12MB5967:EE_ X-MS-Office365-Filtering-Correlation-Id: a7847205-e7d8-47b2-8296-08daa78a3f4e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 63XGb6otXnSsOkGkzEdTnUNwJAp2g1VDw4hltHQJ9odwE7GVAkoiwrlQl90TNri3uw/abd5mrLwxaRePOhm3111zV9U6fxm9e/1CDC+QYlV8TTgopk4iBq7M7yBLvucJK7py9ILC6L0uQJoXLyocg4agieYDMqEOTPNd39ZlOD4Rkns0ey8Cnfo0aiHLpdbEluYCKl+65i2dAObG9nRDcUzmgDEhGzA2QuXynzuGIg1JxZc0U/YuHFtgIdt7ESL3auOM+YmCDpdbtLGaJM4ef+ah/MqsyshsYLYNUXiCCiRwucbwqqoMCyUrpeewxyOJMp6twSRkNNNbdJMnn/alrvu0Nb4+vUwoZxK9fucs4/blBItFoT+iOIrLbaCIBRm3iZFS8FSyD6yQJDC6l98kLC1yAEIRzWmqISapbf08Eyg5Pcp8jMk4nm1I3QOnrc8Yypmi3LtsLTNEyEH8paayXneqY5JAM5g7+o2/9vtWqlAa5gwy8jtAUAmBayQTNeecYg/aeQ6WHQDaeE3TXuOqChdxZXvoTltD0mBnIPEYxfWjKNJhX4odE0vMSSnqNcH40ibapYZB3KcvDDYO6c6TOOjCCka10eELe5r5X2dY+dqeEt3KcCS+l5K74QsZpE1F69ArwmjsZoMON1s0LlapeFI3USVK0OH7KJ3v2E1qzYCf7LqkEhXqfRkEq8CkYDwz+5qk7D3G5LKcfCkRJk7J/8fSY3iPWTJ7Kf26dF7QThc1zTjOqBgdsMm6mKDbfeFsO3PpmPL2QTjq639D6dAZDhpQnsseBqI4fqVo/T45904= X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230022)(4636009)(346002)(396003)(376002)(136003)(39860400002)(451199015)(46966006)(36840700001)(40470700004)(2906002)(8936002)(70206006)(316002)(36756003)(8676002)(478600001)(41300700001)(86362001)(70586007)(4326008)(5660300002)(110136005)(36860700001)(55016003)(16526019)(83380400001)(356005)(26005)(2616005)(1076003)(47076005)(6286002)(40460700003)(186003)(336012)(7636003)(82740400003)(7696005)(40480700001)(426003)(82310400005)(309714004); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Oct 2022 11:02:23.3750 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a7847205-e7d8-47b2-8296-08daa78a3f4e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT079.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5967 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch extends hairpin-mode command line option of test-pmd application with an ability to configure whether Rx/Tx hairpin queue should use locked device memory or RTE memory. For purposes of this configurations the following bits of 32 bit hairpin-mode are reserved: - Bit 8 - If set, then force_memory flag will be set for hairpin RX queue. - Bit 9 - If set, then force_memory flag will be set for hairpin TX queue. - Bits 12-15 - Memory options for hairpin Rx queue: - Bit 12 - If set, then use_locked_device_memory will be set. - Bit 13 - If set, then use_rte_memory will be set. - Bit 14 - Reserved for future use. - Bit 15 - Reserved for future use. - Bits 16-19 - Memory options for hairpin Tx queue: - Bit 16 - If set, then use_locked_device_memory will be set. - Bit 17 - If set, then use_rte_memory will be set. - Bit 18 - Reserved for future use. - Bit 19 - Reserved for future use. Signed-off-by: Dariusz Sosnowski --- app/test-pmd/parameters.c | 2 +- app/test-pmd/testpmd.c | 24 +++++++++++++++++++++++- app/test-pmd/testpmd.h | 2 +- doc/guides/testpmd_app_ug/run_app.rst | 10 ++++++++-- 4 files changed, 33 insertions(+), 5 deletions(-) diff --git a/app/test-pmd/parameters.c b/app/test-pmd/parameters.c index 1024b5419c..14752f9571 100644 --- a/app/test-pmd/parameters.c +++ b/app/test-pmd/parameters.c @@ -1085,7 +1085,7 @@ launch_args_parse(int argc, char** argv) if (errno != 0 || end == optarg) rte_exit(EXIT_FAILURE, "hairpin mode invalid\n"); else - hairpin_mode = (uint16_t)n; + hairpin_mode = (uint32_t)n; } if (!strcmp(lgopts[opt_idx].name, "burst")) { n = atoi(optarg); diff --git a/app/test-pmd/testpmd.c b/app/test-pmd/testpmd.c index 39ee3d331d..bb1c901742 100644 --- a/app/test-pmd/testpmd.c +++ b/app/test-pmd/testpmd.c @@ -409,7 +409,7 @@ bool setup_on_probe_event = true; uint8_t clear_ptypes = true; /* Hairpin ports configuration mode. */ -uint16_t hairpin_mode; +uint32_t hairpin_mode; /* Pretty printing of ethdev events */ static const char * const eth_event_desc[] = { @@ -2519,6 +2519,16 @@ port_is_started(portid_t port_id) return 1; } +#define HAIRPIN_MODE_RX_FORCE_MEMORY RTE_BIT32(8) +#define HAIRPIN_MODE_TX_FORCE_MEMORY RTE_BIT32(9) + +#define HAIRPIN_MODE_RX_LOCKED_MEMORY RTE_BIT32(12) +#define HAIRPIN_MODE_RX_RTE_MEMORY RTE_BIT32(13) + +#define HAIRPIN_MODE_TX_LOCKED_MEMORY RTE_BIT32(16) +#define HAIRPIN_MODE_TX_RTE_MEMORY RTE_BIT32(17) + + /* Configure the Rx and Tx hairpin queues for the selected port. */ static int setup_hairpin_queues(portid_t pi, portid_t p_pi, uint16_t cnt_pi) @@ -2534,6 +2544,12 @@ setup_hairpin_queues(portid_t pi, portid_t p_pi, uint16_t cnt_pi) uint16_t peer_tx_port = pi; uint32_t manual = 1; uint32_t tx_exp = hairpin_mode & 0x10; + uint32_t rx_force_memory = hairpin_mode & HAIRPIN_MODE_RX_FORCE_MEMORY; + uint32_t rx_locked_memory = hairpin_mode & HAIRPIN_MODE_RX_LOCKED_MEMORY; + uint32_t rx_rte_memory = hairpin_mode & HAIRPIN_MODE_RX_RTE_MEMORY; + uint32_t tx_force_memory = hairpin_mode & HAIRPIN_MODE_TX_FORCE_MEMORY; + uint32_t tx_locked_memory = hairpin_mode & HAIRPIN_MODE_TX_LOCKED_MEMORY; + uint32_t tx_rte_memory = hairpin_mode & HAIRPIN_MODE_TX_RTE_MEMORY; if (!(hairpin_mode & 0xf)) { peer_rx_port = pi; @@ -2573,6 +2589,9 @@ setup_hairpin_queues(portid_t pi, portid_t p_pi, uint16_t cnt_pi) hairpin_conf.peers[0].queue = i + nb_rxq; hairpin_conf.manual_bind = !!manual; hairpin_conf.tx_explicit = !!tx_exp; + hairpin_conf.force_memory = !!tx_force_memory; + hairpin_conf.use_locked_device_memory = !!tx_locked_memory; + hairpin_conf.use_rte_memory = !!tx_rte_memory; diag = rte_eth_tx_hairpin_queue_setup (pi, qi, nb_txd, &hairpin_conf); i++; @@ -2596,6 +2615,9 @@ setup_hairpin_queues(portid_t pi, portid_t p_pi, uint16_t cnt_pi) hairpin_conf.peers[0].queue = i + nb_txq; hairpin_conf.manual_bind = !!manual; hairpin_conf.tx_explicit = !!tx_exp; + hairpin_conf.force_memory = !!rx_force_memory; + hairpin_conf.use_locked_device_memory = !!rx_locked_memory; + hairpin_conf.use_rte_memory = !!rx_rte_memory; diag = rte_eth_rx_hairpin_queue_setup (pi, qi, nb_rxd, &hairpin_conf); i++; diff --git a/app/test-pmd/testpmd.h b/app/test-pmd/testpmd.h index 627a42ce3b..2244c25e97 100644 --- a/app/test-pmd/testpmd.h +++ b/app/test-pmd/testpmd.h @@ -562,7 +562,7 @@ extern uint16_t stats_period; extern struct rte_eth_xstat_name *xstats_display; extern unsigned int xstats_display_num; -extern uint16_t hairpin_mode; +extern uint32_t hairpin_mode; #ifdef RTE_LIB_LATENCYSTATS extern uint8_t latencystats_enabled; diff --git a/doc/guides/testpmd_app_ug/run_app.rst b/doc/guides/testpmd_app_ug/run_app.rst index 8b41b960c8..abc3ec10a0 100644 --- a/doc/guides/testpmd_app_ug/run_app.rst +++ b/doc/guides/testpmd_app_ug/run_app.rst @@ -529,10 +529,16 @@ The command line options are: Enable display of RX and TX burst stats. -* ``--hairpin-mode=0xXX`` +* ``--hairpin-mode=0xXXXX`` - Set the hairpin port mode with bitmask, only valid when hairpin queues number is set:: + Set the hairpin port configuration with bitmask, only valid when hairpin queues number is set:: + bit 18 - hairpin TX queues will use RTE memory + bit 16 - hairpin TX queues will use locked device memory + bit 13 - hairpin RX queues will use RTE memory + bit 12 - hairpin RX queues will use locked device memory + bit 9 - force memory settings of hairpin TX queue + bit 8 - force memory settings of hairpin RX queue bit 4 - explicit Tx flow rule bit 1 - two hairpin ports paired bit 0 - two hairpin ports loop From patchwork Thu Oct 6 11:01:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dariusz Sosnowski X-Patchwork-Id: 117456 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E6A65A00C2; Thu, 6 Oct 2022 13:03:01 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9B78542C35; Thu, 6 Oct 2022 13:02:29 +0200 (CEST) Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2059.outbound.protection.outlook.com [40.107.92.59]) by mails.dpdk.org (Postfix) with ESMTP id EBA8942C29 for ; Thu, 6 Oct 2022 13:02:26 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=HUrfaE6phxExuG7ouUviL++HImrzc4B4w/dH+Y3s7o/ES01/4QoxssdfbjGeB6ldrnPErsTcQHXugB1FA2fDLFcnIBftT6C+Dot1PMJt+55pFZRG8RvPmc+p4ZsoILVBavx68Fhs3uGSfH2LsBGas91vxp7WRz5g52mKgGj3EWOpcStmCUjKOIqtkIKg+YuJDP21+1juoDBPsPnkOh6vv/IP3kYEMa8DrYg1AE4qBhNPixVK2b5C2D8naqlFUokQjG2K4SMH7f9ueEHgPczF9Z3UmAgA2PYFyaV8PH9O5FTkSNC7zJT7XnoQ467NKwI1j32sszo6kwsxxql4MC7HPw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=cs+71IgRq+KCaj0cU+c08916hQk0hszfWRWdfq0v4p8=; b=fHYB31xgq2MvgpDmcBqsp831M3IUNcBYFHGs2nkdDr9+OXvrbvDZjn8HXQyMxClD91DIh12HY2km19q+T8SaVsd67gecANAkNRWXekxpBcpfTfMgQ8euuucVZ0iAM5McWMursyzbaPhv30uFGQx41i/TDPxRVJ5+6UI1BEStzok6B3m6rNV4z+FMJq9rAhG99sxPCvoNbofeN5QZrXByES5lCzYHvdJB2toVMGmr47dPI99S0pb7Ode2CR7rMrRvD+Uuo2KUT50D6hbTZ2lkXAievQL/wnQEGcXUECc/uQRO01qYj2tUc5Pb5u4YOWYqthhiiUoPB1SurcMn4EG0Dg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=cs+71IgRq+KCaj0cU+c08916hQk0hszfWRWdfq0v4p8=; b=bY9wfAVkRSEhIo1E1rgE8Je/5ERRFUiGzKzEUkn4ZvRZwDiVBg6++xBj2xXGI3O8lCdn9QqWkXZ0QdONGexWeR0wnQ+yicwYRW/nteSma+/A6LRCarw3x1GZl4L1YD1bqoYjOJDdeRRRsJm3HNW8XeG/unXvGZt2xcQbCAdVVvYHf0pSNBiO9VU/Y+yHiUEEtmhXImJeEhKFYrK4emI3ul/CC7HAXql1SdXPn+m3S6yyk+3BC48gpjdox+UFjJOu6dsPVv2NfRm22s75sOIRO9jvw/uBOLTmIopatK5ntCj8x2RA92LW7LRyclUO4rB0fQYHnYeH6AThZztVB2kdkg== Received: from BN1PR12CA0002.namprd12.prod.outlook.com (2603:10b6:408:e1::7) by SA1PR12MB6679.namprd12.prod.outlook.com (2603:10b6:806:252::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5654.26; Thu, 6 Oct 2022 11:02:25 +0000 Received: from BN8NAM11FT071.eop-nam11.prod.protection.outlook.com (2603:10b6:408:e1:cafe::3) by BN1PR12CA0002.outlook.office365.com (2603:10b6:408:e1::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5676.29 via Frontend Transport; Thu, 6 Oct 2022 11:02:25 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by BN8NAM11FT071.mail.protection.outlook.com (10.13.177.92) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5709.10 via Frontend Transport; Thu, 6 Oct 2022 11:02:25 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.26; Thu, 6 Oct 2022 04:02:09 -0700 Received: from nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Thu, 6 Oct 2022 04:02:08 -0700 From: Dariusz Sosnowski To: Wisam Jaddo CC: Subject: [PATCH v2 8/8] app/flow-perf: add hairpin queue memory config Date: Thu, 6 Oct 2022 11:01:05 +0000 Message-ID: <20221006110105.2986966-9-dsosnowski@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221006110105.2986966-1-dsosnowski@nvidia.com> References: <20221006110105.2986966-1-dsosnowski@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT071:EE_|SA1PR12MB6679:EE_ X-MS-Office365-Filtering-Correlation-Id: d0d1633a-4c0a-4027-68f0-08daa78a404c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: HhWy8zYlv4Vs27I9pY9gEF8S62YlB7IGO2sMTQPj0q9NjCJ6ArKuC5K2LuRn3P3kNHGQeQFpjMjV2E7Eg+jLQuzUdP68K5PuSyOtR61OO93P+SVDZMHE/RoXVIQ9ME+G0lxmmafly5NGeAhl86cLbtrkehuF8b5jI0Cd+YbJSCxV9EPyyp+OEEyLVohtQcZzhL7eExUeREEhT1Yz+pYZ9/wJFYh5/4J7CL/VnpQMcyQ6SSNkuK91ggx6wexxPFjNVRnZAsqrGEnFzuLZIWOO6aBx15P3RU3fu+j6w2wno+YgZlT1Cw24N0apNSKElF9hZ7E2LjnukdmBsjv5Yiy/svXlQgtV3KmniwG5ZLkSJMfJ+xiguoq6Be/QM1pDDIb5v0m9+gkjE9nFzmcR2lJWs5a1FYxJ7rNdV7xYYbeOh/07S2NSMEZDbZo9gAyMMZWfNjkxdJmifa1lQOqlAZ4IQmx8SOxj2Ada8dZ/o7b6VCbx+XsDZ6/OQ1df6JfcsSgSGqLKbghLm14a5DpMRJbKh5j3bgQ9xfNOqWdIoqIviq8/0TbsQSu1TX3NQGzba0OuGM3PXjfGB20oI/U12Zc9hAlSY1jR+I/rFYlVbLKDjOFtdQpuLuown8shmMBOZfj6sQZ7yhJLjw4m9tDHmAyi+Xz9roai4OB4nYwqubxZB1q1TSf54Sr9698xCnhu2JfRF/kwCbuZR5YeXzqepFpLBGqEkITzl6nHNldH823TIJl822WIZEVfClYWL8JrmNfTjjV5dvwbLWr6lSIO7Z48hA== X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230022)(4636009)(39860400002)(136003)(396003)(376002)(346002)(451199015)(46966006)(40470700004)(36840700001)(186003)(82310400005)(1076003)(82740400003)(16526019)(336012)(2616005)(6862004)(7696005)(8936002)(7636003)(55016003)(36860700001)(40460700003)(70206006)(26005)(426003)(40480700001)(47076005)(478600001)(6666004)(6286002)(70586007)(4326008)(2906002)(41300700001)(316002)(8676002)(37006003)(83380400001)(356005)(36756003)(5660300002)(86362001)(6636002); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Oct 2022 11:02:25.0234 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d0d1633a-4c0a-4027-68f0-08daa78a404c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT071.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB6679 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch adds the hairpin-conf command line parameter to flow-perf application. hairpin-conf parameter takes a hexadecimal bitmask with bits having the following meaning: - Bit 0 - Force memory settings of hairpin RX queue. - Bit 1 - Force memory settings of hairpin TX queue. - Bit 4 - Use locked device memory for hairpin RX queue. - Bit 5 - Use RTE memory for hairpin RX queue. - Bit 8 - Use locked device memory for hairpin TX queue. - Bit 9 - Use RTE memory for hairpin TX queue. Signed-off-by: Dariusz Sosnowski Acked-by: Wisam Jaddo --- app/test-flow-perf/main.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/app/test-flow-perf/main.c b/app/test-flow-perf/main.c index f375097028..4a9206803a 100644 --- a/app/test-flow-perf/main.c +++ b/app/test-flow-perf/main.c @@ -46,6 +46,15 @@ #define DEFAULT_RULES_BATCH 100000 #define DEFAULT_GROUP 0 +#define HAIRPIN_RX_CONF_FORCE_MEMORY (0x0001) +#define HAIRPIN_TX_CONF_FORCE_MEMORY (0x0002) + +#define HAIRPIN_RX_CONF_LOCKED_MEMORY (0x0010) +#define HAIRPIN_RX_CONF_RTE_MEMORY (0x0020) + +#define HAIRPIN_TX_CONF_LOCKED_MEMORY (0x0100) +#define HAIRPIN_TX_CONF_RTE_MEMORY (0x0200) + struct rte_flow *flow; static uint8_t flow_group; @@ -61,6 +70,7 @@ static uint32_t policy_id[MAX_PORTS]; static uint8_t items_idx, actions_idx, attrs_idx; static uint64_t ports_mask; +static uint64_t hairpin_conf_mask; static uint16_t dst_ports[RTE_MAX_ETHPORTS]; static volatile bool force_quit; static bool dump_iterations; @@ -482,6 +492,7 @@ usage(char *progname) printf(" --enable-fwd: To enable packets forwarding" " after insertion\n"); printf(" --portmask=N: hexadecimal bitmask of ports used\n"); + printf(" --hairpin-conf=0xXXXX: hexadecimal bitmask of hairpin queue configuration\n"); printf(" --random-priority=N,S: use random priority levels " "from 0 to (N - 1) for flows " "and S as seed for pseudo-random number generator\n"); @@ -629,6 +640,7 @@ static void args_parse(int argc, char **argv) { uint64_t pm, seed; + uint64_t hp_conf; char **argvopt; uint32_t prio; char *token; @@ -648,6 +660,7 @@ args_parse(int argc, char **argv) { "enable-fwd", 0, 0, 0 }, { "unique-data", 0, 0, 0 }, { "portmask", 1, 0, 0 }, + { "hairpin-conf", 1, 0, 0 }, { "cores", 1, 0, 0 }, { "random-priority", 1, 0, 0 }, { "meter-profile-alg", 1, 0, 0 }, @@ -880,6 +893,13 @@ args_parse(int argc, char **argv) rte_exit(EXIT_FAILURE, "Invalid fwd port mask\n"); ports_mask = pm; } + if (strcmp(lgopts[opt_idx].name, "hairpin-conf") == 0) { + end = NULL; + hp_conf = strtoull(optarg, &end, 16); + if ((optarg[0] == '\0') || (end == NULL) || (*end != '\0')) + rte_exit(EXIT_FAILURE, "Invalid hairpin config mask\n"); + hairpin_conf_mask = hp_conf; + } if (strcmp(lgopts[opt_idx].name, "port-id") == 0) { uint16_t port_idx = 0; @@ -2035,6 +2055,12 @@ init_port(void) hairpin_conf.peers[0].port = port_id; hairpin_conf.peers[0].queue = std_queue + tx_queues_count; + hairpin_conf.use_locked_device_memory = + !!(hairpin_conf_mask & HAIRPIN_RX_CONF_LOCKED_MEMORY); + hairpin_conf.use_rte_memory = + !!(hairpin_conf_mask & HAIRPIN_RX_CONF_RTE_MEMORY); + hairpin_conf.force_memory = + !!(hairpin_conf_mask & HAIRPIN_RX_CONF_FORCE_MEMORY); ret = rte_eth_rx_hairpin_queue_setup( port_id, hairpin_queue, rxd_count, &hairpin_conf); @@ -2050,6 +2076,12 @@ init_port(void) hairpin_conf.peers[0].port = port_id; hairpin_conf.peers[0].queue = std_queue + rx_queues_count; + hairpin_conf.use_locked_device_memory = + !!(hairpin_conf_mask & HAIRPIN_TX_CONF_LOCKED_MEMORY); + hairpin_conf.use_rte_memory = + !!(hairpin_conf_mask & HAIRPIN_TX_CONF_RTE_MEMORY); + hairpin_conf.force_memory = + !!(hairpin_conf_mask & HAIRPIN_TX_CONF_FORCE_MEMORY); ret = rte_eth_tx_hairpin_queue_setup( port_id, hairpin_queue, txd_count, &hairpin_conf);