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GET /api/patches/117452/?format=api
{ "id": 117452, "url": "https://patches.dpdk.org/api/patches/117452/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20221006110105.2986966-5-dsosnowski@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20221006110105.2986966-5-dsosnowski@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20221006110105.2986966-5-dsosnowski@nvidia.com", "date": "2022-10-06T11:01:01", "name": "[v2,4/8] net/mlx5: allow hairpin Tx queue in RTE memory", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "c6822a1d297ccede2953b10922d4f077420cf8ef", "submitter": { "id": 2386, "url": "https://patches.dpdk.org/api/people/2386/?format=api", "name": "Dariusz Sosnowski", "email": "dsosnowski@nvidia.com" }, "delegate": { "id": 1, "url": "https://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20221006110105.2986966-5-dsosnowski@nvidia.com/mbox/", "series": [ { "id": 25009, "url": "https://patches.dpdk.org/api/series/25009/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=25009", "date": "2022-10-06T11:00:57", "name": "ethdev: introduce hairpin memory capabilities", "version": 2, "mbox": "https://patches.dpdk.org/series/25009/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/117452/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/117452/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 69F5DA00C2;\n\tThu, 6 Oct 2022 13:02:31 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 9DE7042C1C;\n\tThu, 6 Oct 2022 13:02:13 +0200 (CEST)", "from NAM02-BN1-obe.outbound.protection.outlook.com\n (mail-bn1nam07on2043.outbound.protection.outlook.com [40.107.212.43])\n by mails.dpdk.org (Postfix) with ESMTP id 0947F42C19\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Dariusz Sosnowski <dsosnowski@nvidia.com>", "To": "Matan Azrad <matan@nvidia.com>, Viacheslav Ovsiienko\n <viacheslavo@nvidia.com>", "CC": "<dev@dpdk.org>", "Subject": "[PATCH v2 4/8] net/mlx5: allow hairpin Tx queue in RTE memory", "Date": "Thu, 6 Oct 2022 11:01:01 +0000", "Message-ID": "<20221006110105.2986966-5-dsosnowski@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20221006110105.2986966-1-dsosnowski@nvidia.com>", "References": "<20221006110105.2986966-1-dsosnowski@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.35]", "X-ClientProxiedBy": "rnnvmail202.nvidia.com (10.129.68.7) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "DM6NAM11FT024:EE_|PH8PR12MB7230:EE_", "X-MS-Office365-Filtering-Correlation-Id": "cb0d6539-f850-4148-cd9d-08daa78a373e", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n X3AtAdyToGV8++qWYE8ILgYDXIgOPTFVh9IQsDwGlEyCBqu3GDRjsi04R9RlYJlt14k9b56NP56MUT6Yk75/B08hS90NNHuxjOELj0QIunN9J4aMMKDuCSmEf7zxuHrgV4FjtMCpgEykWOGtsQ0xG6/3gfIyti6vXMMsxhLYhJtGW+Uz817d6LvGE3M2cD3AJvHX2skjJnBR4UCBx6QbiCw2LKnJx32ukHc/J7GFjTKn9vXQUGvQ6j4OiiD5t1m31olQ+BYo6feHbkCYsvUjd5IZzZ5MRz9PeNkey70FkEbmoaLKKGTWGiiDMAFJbzOCfzRv5R+U/gxp496HAbMHk/7OQVHLWciNJk1zT7m3DgcsM6WlAim2b6Rd76rbhk2z/AqAIVubqgL4c4NKXCkdu2vkKl+zPFnBKlhRCPuRh33jNeTfKuLo3cCYrWA/6HyQ4L/dKnhOTSEahnolz1E9abX05Ged/59fofHqOAQND6/u49J64wxDIC5XT1aNmm9UNrtkJJVf+usV+w1xOrkWKyi63ptUT7RHqVArGk5AVNqVKbJ8k1MirI43yxwJHoKuZbY79USuWpAPJ4f/2hh+pNedkELNisUvkcAjcf9E2oH9ICIoMkTX1FQmX8hPEOlrmpUcHNwOTdBsqP8NBhI3SuNG3Xf3w2jBVEPjp+wT6sjMt11wG38eQycUyaBQeyCmljhLvSiDt1ecb8Dq+GfrofXhCDp+j6jHugF0RWeCnqTps37WKYsPTEGpFO1JgegugQISiiZsiwMLJqY8TYKrVg==", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE;\n SFS:(13230022)(4636009)(396003)(376002)(39860400002)(136003)(346002)(451199015)(36840700001)(40470700004)(46966006)(5660300002)(41300700001)(186003)(47076005)(316002)(6666004)(16526019)(110136005)(356005)(6636002)(8676002)(86362001)(2906002)(70586007)(70206006)(55016003)(1076003)(336012)(40460700003)(7636003)(82740400003)(82310400005)(8936002)(36756003)(83380400001)(478600001)(4326008)(2616005)(426003)(6286002)(7696005)(26005)(40480700001)(36860700001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "06 Oct 2022 11:02:09.8816 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n cb0d6539-f850-4148-cd9d-08daa78a373e", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT024.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "PH8PR12MB7230", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "This patch adds a capability to place hairpin Tx queue in host memory\nmanaged by DPDK. This capability is equivalent to storing hairpin SQ's\nWQ buffer in host memory.\n\nHairpin Tx queue creation is extended with allocating a memory buffer of\nproper size (calculated from required number of packets and WQE BB size\nadvertised in HCA capabilities).\n\nforce_memory flag of hairpin queue configuration is also supported.\nIf it is set and:\n\n- allocation of memory buffer fails,\n- or hairpin SQ creation fails,\n\nthen device start will fail. If it is unset, PMD will fallback to\ncreating the hairpin SQ with WQ buffer located in unlocked device\nmemory.\n\nSigned-off-by: Dariusz Sosnowski <dsosnowski@nvidia.com>\nAcked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>\n---\n drivers/net/mlx5/mlx5.h | 2 +\n drivers/net/mlx5/mlx5_devx.c | 119 ++++++++++++++++++++++++++++++---\n drivers/net/mlx5/mlx5_ethdev.c | 4 ++\n 3 files changed, 116 insertions(+), 9 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex 95ecbea39e..3c9e6bad53 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -1386,6 +1386,8 @@ struct mlx5_txq_obj {\n \t\t\tstruct mlx5_devx_obj *sq;\n \t\t\t/* DevX object for Sx queue. */\n \t\t\tstruct mlx5_devx_obj *tis; /* The TIS object. */\n+\t\t\tvoid *umem_buf_wq_buffer;\n+\t\t\tvoid *umem_obj_wq_buffer;\n \t\t};\n \t\tstruct {\n \t\t\tstruct rte_eth_dev *dev;\ndiff --git a/drivers/net/mlx5/mlx5_devx.c b/drivers/net/mlx5/mlx5_devx.c\nindex 943aa8ef57..c61c34bd99 100644\n--- a/drivers/net/mlx5/mlx5_devx.c\n+++ b/drivers/net/mlx5/mlx5_devx.c\n@@ -1185,18 +1185,23 @@ static int\n mlx5_txq_obj_hairpin_new(struct rte_eth_dev *dev, uint16_t idx)\n {\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n+\tstruct mlx5_hca_attr *hca_attr = &priv->sh->cdev->config.hca_attr;\n \tstruct mlx5_txq_data *txq_data = (*priv->txqs)[idx];\n \tstruct mlx5_txq_ctrl *txq_ctrl =\n \t\tcontainer_of(txq_data, struct mlx5_txq_ctrl, txq);\n-\tstruct mlx5_devx_create_sq_attr attr = { 0 };\n+\tstruct mlx5_devx_create_sq_attr dev_mem_attr = { 0 };\n+\tstruct mlx5_devx_create_sq_attr host_mem_attr = { 0 };\n \tstruct mlx5_txq_obj *tmpl = txq_ctrl->obj;\n+\tvoid *umem_buf = NULL;\n+\tvoid *umem_obj = NULL;\n \tuint32_t max_wq_data;\n \n \tMLX5_ASSERT(txq_data);\n \tMLX5_ASSERT(tmpl);\n \ttmpl->txq_ctrl = txq_ctrl;\n-\tattr.hairpin = 1;\n-\tattr.tis_lst_sz = 1;\n+\tdev_mem_attr.hairpin = 1;\n+\tdev_mem_attr.tis_lst_sz = 1;\n+\tdev_mem_attr.tis_num = mlx5_get_txq_tis_num(dev, idx);\n \tmax_wq_data =\n \t\tpriv->sh->cdev->config.hca_attr.log_max_hairpin_wq_data_sz;\n \t/* Jumbo frames > 9KB should be supported, and more packets. */\n@@ -1208,19 +1213,103 @@ mlx5_txq_obj_hairpin_new(struct rte_eth_dev *dev, uint16_t idx)\n \t\t\trte_errno = ERANGE;\n \t\t\treturn -rte_errno;\n \t\t}\n-\t\tattr.wq_attr.log_hairpin_data_sz = priv->config.log_hp_size;\n+\t\tdev_mem_attr.wq_attr.log_hairpin_data_sz = priv->config.log_hp_size;\n \t} else {\n-\t\tattr.wq_attr.log_hairpin_data_sz =\n+\t\tdev_mem_attr.wq_attr.log_hairpin_data_sz =\n \t\t\t\t(max_wq_data < MLX5_HAIRPIN_JUMBO_LOG_SIZE) ?\n \t\t\t\t max_wq_data : MLX5_HAIRPIN_JUMBO_LOG_SIZE;\n \t}\n \t/* Set the packets number to the maximum value for performance. */\n-\tattr.wq_attr.log_hairpin_num_packets =\n-\t\t\tattr.wq_attr.log_hairpin_data_sz -\n+\tdev_mem_attr.wq_attr.log_hairpin_num_packets =\n+\t\t\tdev_mem_attr.wq_attr.log_hairpin_data_sz -\n \t\t\tMLX5_HAIRPIN_QUEUE_STRIDE;\n+\tdev_mem_attr.hairpin_wq_buffer_type = MLX5_SQC_HAIRPIN_WQ_BUFFER_TYPE_INTERNAL_BUFFER;\n+\tif (txq_ctrl->hairpin_conf.use_rte_memory) {\n+\t\tuint32_t umem_size;\n+\t\tuint32_t umem_dbrec;\n+\t\tsize_t alignment = MLX5_WQE_BUF_ALIGNMENT;\n \n-\tattr.tis_num = mlx5_get_txq_tis_num(dev, idx);\n-\ttmpl->sq = mlx5_devx_cmd_create_sq(priv->sh->cdev->ctx, &attr);\n+\t\tif (alignment == (size_t)-1) {\n+\t\t\tDRV_LOG(ERR, \"Failed to get WQE buf alignment.\");\n+\t\t\trte_errno = ENOMEM;\n+\t\t\treturn -rte_errno;\n+\t\t}\n+\t\t/*\n+\t\t * It is assumed that configuration is verified against capabilities\n+\t\t * during queue setup.\n+\t\t */\n+\t\tMLX5_ASSERT(hca_attr->hairpin_sq_wq_in_host_mem);\n+\t\tMLX5_ASSERT(hca_attr->hairpin_sq_wqe_bb_size > 0);\n+\t\trte_memcpy(&host_mem_attr, &dev_mem_attr, sizeof(host_mem_attr));\n+\t\tumem_size = MLX5_WQE_SIZE *\n+\t\t\tRTE_BIT32(host_mem_attr.wq_attr.log_hairpin_num_packets);\n+\t\tumem_dbrec = RTE_ALIGN(umem_size, MLX5_DBR_SIZE);\n+\t\tumem_size += MLX5_DBR_SIZE;\n+\t\tumem_buf = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, umem_size,\n+\t\t\t\t alignment, priv->sh->numa_node);\n+\t\tif (umem_buf == NULL && txq_ctrl->hairpin_conf.force_memory) {\n+\t\t\tDRV_LOG(ERR, \"Failed to allocate memory for hairpin TX queue\");\n+\t\t\trte_errno = ENOMEM;\n+\t\t\treturn -rte_errno;\n+\t\t} else if (umem_buf == NULL && !txq_ctrl->hairpin_conf.force_memory) {\n+\t\t\tDRV_LOG(WARNING, \"Failed to allocate memory for hairpin TX queue.\"\n+\t\t\t\t\t \" Falling back to TX queue located on the device.\");\n+\t\t\tgoto create_sq_on_device;\n+\t\t}\n+\t\tumem_obj = mlx5_os_umem_reg(priv->sh->cdev->ctx,\n+\t\t\t\t\t (void *)(uintptr_t)umem_buf,\n+\t\t\t\t\t umem_size,\n+\t\t\t\t\t IBV_ACCESS_LOCAL_WRITE);\n+\t\tif (umem_obj == NULL && txq_ctrl->hairpin_conf.force_memory) {\n+\t\t\tDRV_LOG(ERR, \"Failed to register UMEM for hairpin TX queue\");\n+\t\t\tmlx5_free(umem_buf);\n+\t\t\treturn -rte_errno;\n+\t\t} else if (umem_obj == NULL && !txq_ctrl->hairpin_conf.force_memory) {\n+\t\t\tDRV_LOG(WARNING, \"Failed to register UMEM for hairpin TX queue.\"\n+\t\t\t\t\t \" Falling back to TX queue located on the device.\");\n+\t\t\trte_errno = 0;\n+\t\t\tmlx5_free(umem_buf);\n+\t\t\tgoto create_sq_on_device;\n+\t\t}\n+\t\thost_mem_attr.wq_attr.wq_type = MLX5_WQ_TYPE_CYCLIC;\n+\t\thost_mem_attr.wq_attr.wq_umem_valid = 1;\n+\t\thost_mem_attr.wq_attr.wq_umem_id = mlx5_os_get_umem_id(umem_obj);\n+\t\thost_mem_attr.wq_attr.wq_umem_offset = 0;\n+\t\thost_mem_attr.wq_attr.dbr_umem_valid = 1;\n+\t\thost_mem_attr.wq_attr.dbr_umem_id = host_mem_attr.wq_attr.wq_umem_id;\n+\t\thost_mem_attr.wq_attr.dbr_addr = umem_dbrec;\n+\t\thost_mem_attr.wq_attr.log_wq_stride = rte_log2_u32(MLX5_WQE_SIZE);\n+\t\thost_mem_attr.wq_attr.log_wq_sz =\n+\t\t\t\thost_mem_attr.wq_attr.log_hairpin_num_packets *\n+\t\t\t\thca_attr->hairpin_sq_wqe_bb_size;\n+\t\thost_mem_attr.wq_attr.log_wq_pg_sz = MLX5_LOG_PAGE_SIZE;\n+\t\thost_mem_attr.hairpin_wq_buffer_type = MLX5_SQC_HAIRPIN_WQ_BUFFER_TYPE_HOST_MEMORY;\n+\t\ttmpl->sq = mlx5_devx_cmd_create_sq(priv->sh->cdev->ctx, &host_mem_attr);\n+\t\tif (!tmpl->sq && txq_ctrl->hairpin_conf.force_memory) {\n+\t\t\tDRV_LOG(ERR,\n+\t\t\t\t\"Port %u tx hairpin queue %u can't create SQ object.\",\n+\t\t\t\tdev->data->port_id, idx);\n+\t\t\tclaim_zero(mlx5_os_umem_dereg(umem_obj));\n+\t\t\tmlx5_free(umem_buf);\n+\t\t\treturn -rte_errno;\n+\t\t} else if (!tmpl->sq && !txq_ctrl->hairpin_conf.force_memory) {\n+\t\t\tDRV_LOG(WARNING,\n+\t\t\t\t\"Port %u tx hairpin queue %u failed to allocate SQ object\"\n+\t\t\t\t\" using host memory. Falling back to TX queue located\"\n+\t\t\t\t\" on the device\",\n+\t\t\t\tdev->data->port_id, idx);\n+\t\t\trte_errno = 0;\n+\t\t\tclaim_zero(mlx5_os_umem_dereg(umem_obj));\n+\t\t\tmlx5_free(umem_buf);\n+\t\t\tgoto create_sq_on_device;\n+\t\t}\n+\t\ttmpl->umem_buf_wq_buffer = umem_buf;\n+\t\ttmpl->umem_obj_wq_buffer = umem_obj;\n+\t\treturn 0;\n+\t}\n+\n+create_sq_on_device:\n+\ttmpl->sq = mlx5_devx_cmd_create_sq(priv->sh->cdev->ctx, &dev_mem_attr);\n \tif (!tmpl->sq) {\n \t\tDRV_LOG(ERR,\n \t\t\t\"Port %u tx hairpin queue %u can't create SQ object.\",\n@@ -1452,8 +1541,20 @@ mlx5_txq_devx_obj_release(struct mlx5_txq_obj *txq_obj)\n {\n \tMLX5_ASSERT(txq_obj);\n \tif (txq_obj->txq_ctrl->is_hairpin) {\n+\t\tif (txq_obj->sq) {\n+\t\t\tclaim_zero(mlx5_devx_cmd_destroy(txq_obj->sq));\n+\t\t\ttxq_obj->sq = NULL;\n+\t\t}\n \t\tif (txq_obj->tis)\n \t\t\tclaim_zero(mlx5_devx_cmd_destroy(txq_obj->tis));\n+\t\tif (txq_obj->umem_obj_wq_buffer) {\n+\t\t\tclaim_zero(mlx5_os_umem_dereg(txq_obj->umem_obj_wq_buffer));\n+\t\t\ttxq_obj->umem_obj_wq_buffer = NULL;\n+\t\t}\n+\t\tif (txq_obj->umem_buf_wq_buffer) {\n+\t\t\tmlx5_free(txq_obj->umem_buf_wq_buffer);\n+\t\t\ttxq_obj->umem_buf_wq_buffer = NULL;\n+\t\t}\n #if defined(HAVE_MLX5DV_DEVX_UAR_OFFSET) || !defined(HAVE_INFINIBAND_VERBS_H)\n \t} else {\n \t\tmlx5_txq_release_devx_resources(txq_obj);\ndiff --git a/drivers/net/mlx5/mlx5_ethdev.c b/drivers/net/mlx5/mlx5_ethdev.c\nindex a5c7ca8c52..c59005ea2b 100644\n--- a/drivers/net/mlx5/mlx5_ethdev.c\n+++ b/drivers/net/mlx5/mlx5_ethdev.c\n@@ -729,6 +729,7 @@ int\n mlx5_hairpin_cap_get(struct rte_eth_dev *dev, struct rte_eth_hairpin_cap *cap)\n {\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n+\tstruct mlx5_hca_attr *hca_attr;\n \n \tif (!mlx5_devx_obj_ops_en(priv->sh)) {\n \t\trte_errno = ENOTSUP;\n@@ -738,5 +739,8 @@ mlx5_hairpin_cap_get(struct rte_eth_dev *dev, struct rte_eth_hairpin_cap *cap)\n \tcap->max_rx_2_tx = 1;\n \tcap->max_tx_2_rx = 1;\n \tcap->max_nb_desc = 8192;\n+\thca_attr = &priv->sh->cdev->config.hca_attr;\n+\tcap->tx_cap.locked_device_memory = 0;\n+\tcap->tx_cap.rte_memory = hca_attr->hairpin_sq_wq_in_host_mem;\n \treturn 0;\n }\n", "prefixes": [ "v2", "4/8" ] }