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GET /api/patches/117450/?format=api
{ "id": 117450, "url": "https://patches.dpdk.org/api/patches/117450/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20221006110105.2986966-3-dsosnowski@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20221006110105.2986966-3-dsosnowski@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20221006110105.2986966-3-dsosnowski@nvidia.com", "date": "2022-10-06T11:00:59", "name": "[v2,2/8] common/mlx5: add hairpin SQ buffer type capabilities", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "5be7fa9f91af4d23ba77298e32ca1b3c808b58bf", "submitter": { "id": 2386, "url": "https://patches.dpdk.org/api/people/2386/?format=api", "name": "Dariusz Sosnowski", "email": "dsosnowski@nvidia.com" }, "delegate": { "id": 1, "url": "https://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20221006110105.2986966-3-dsosnowski@nvidia.com/mbox/", "series": [ { "id": 25009, "url": "https://patches.dpdk.org/api/series/25009/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=25009", "date": "2022-10-06T11:00:57", "name": "ethdev: introduce hairpin memory capabilities", "version": 2, "mbox": "https://patches.dpdk.org/series/25009/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/117450/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/117450/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 52B23A00C2;\n\tThu, 6 Oct 2022 13:02:18 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 7C33442C09;\n\tThu, 6 Oct 2022 13:02:09 +0200 (CEST)", "from NAM11-CO1-obe.outbound.protection.outlook.com\n (mail-co1nam11on2047.outbound.protection.outlook.com [40.107.220.47])\n by mails.dpdk.org (Postfix) with ESMTP id F1F0942B70\n for <dev@dpdk.org>; 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mx.microsoft.com 1; spf=temperror (sender ip\n is 216.228.117.160) smtp.rcpttodomain=dpdk.org\n smtp.mailfrom=nvidia.com;\n dmarc=temperror action=none header.from=nvidia.com; dkim=none (message not\n signed); arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=89I2iS9IgrjmNUYpYX8WUXBc4kdf4p8OUOLnHkMS5t8=;\n b=U3Nm2neU1oYmfXWQ2b1XCh9s31Ggj4ibbZYWJl9cFIOxfV6DZ4hQR1mOhwEdBOBhg4dse1C70dCvV4zlbBp0A2xHLzh1DtQl+Rwi0XkNYIUgz7yY9XXJ6uGSnth1zYkopaDtcxMoD2P5jXD6bN58OG0hVCqbZcwzjwkp+8ELn6hdDCUyssT09I0KTKMxVqykB7piCn0i7XaO9yTwuBRGqHGDCMrhtUMUzNdBLRqhvbwTS+jHrwRyQJjypv2PLvnENyT+xgU6e5F/BDG78cwvuc15RDq7E8mtlQBqk8NzF1moz8M+3GOBc/fIO4ULQh2eDNgoh3gghdfOf1Q6gJU4aQ==", "X-MS-Exchange-Authentication-Results": "spf=temperror (sender IP is\n 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed)\n header.d=none;dmarc=temperror action=none header.from=nvidia.com;", "Received-SPF": "TempError (protection.outlook.com: error in processing during\n lookup of nvidia.com: DNS Timeout)", "From": "Dariusz Sosnowski <dsosnowski@nvidia.com>", "To": "Matan Azrad <matan@nvidia.com>, Viacheslav Ovsiienko\n <viacheslavo@nvidia.com>", "CC": "<dev@dpdk.org>", "Subject": "[PATCH v2 2/8] common/mlx5: add hairpin SQ buffer type capabilities", "Date": "Thu, 6 Oct 2022 11:00:59 +0000", "Message-ID": "<20221006110105.2986966-3-dsosnowski@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20221006110105.2986966-1-dsosnowski@nvidia.com>", "References": "<20221006110105.2986966-1-dsosnowski@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.35]", "X-ClientProxiedBy": "rnnvmail202.nvidia.com (10.129.68.7) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BN8NAM11FT020:EE_|BL3PR12MB6427:EE_", "X-MS-Office365-Filtering-Correlation-Id": "104b228e-b882-40cc-2d24-08daa78a33aa", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n 90+ximccAqoVezRcIGtV039Cdfiy3OGZONGbddoVSXshURUvFSPlZAze6I3Nj0FulGrTbY1DLVy5KO2XOqVSaron59vILwKp+tnwwuDlhExm58udO7CBUdYsEU23eMXm/+gF2dY8Z8ksejpYDi/hCf7UQdjHLN3FHHJe+CB1zEFautlvYpLc9dURYwSmPS8COJFAz6bJcIaShc1n6cBiOevCHKNMYSgvW9zh+XTsFKyBoQrQxXY4QTAIv7wI5C/2BWUy8yFG0BpyQTiY1NdF9ixykMWKyye3AT9jYKYIZj2dAcApemTEeZ/AjXZ36s+47N263N/LPICA7mMp2MYfGeg8leUAMi+RHtVQz1qSxoQBHnq6tbCF+uWhwPB2v62Kg1MS0ayMoJN9Cm+HtK5WkQonw3F59NymFMsYNMcLL92ps9uHeuGi3EgcENiclJPY1WzkXp+CfZ/SLsFMiIZRffc+h1nAeeGVNsk8SyyTLsjZEYtqAConMYbcyL3j8pFGCrcvmafnGLHj6iIsYrPC7Xcfsf/V1EagV4QknCDEXY4SIEOWk+dQznQiEbSxGdv2HlP1Jwl7F6MJvg0Hi8OqDtvyt3U7ciZnfJnYhXkwVffQJ+tAvkjD+IrQpOWekg5sOlggDVba9IeIvFYKO39vHeEMGLmt5P86GHRKPZ97kKoN+60Nwqu8K6G2wy7B4pRdb7NZPayi1jB34iCPhJVzNYf1rDTYWbtZAmMpUzJg33M6d8Xr+EzchKqi4RLW3F+fSgbeuJamr5wvV/OouCzXag==", "X-Forefront-Antispam-Report": "CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE;\n SFS:(13230022)(4636009)(39860400002)(396003)(376002)(136003)(346002)(451199015)(36840700001)(46966006)(40470700004)(16526019)(426003)(336012)(7636003)(47076005)(356005)(1076003)(83380400001)(186003)(86362001)(63350400001)(82740400003)(82310400005)(36860700001)(70206006)(41300700001)(8936002)(5660300002)(110136005)(4326008)(316002)(6636002)(70586007)(7696005)(40480700001)(8676002)(55016003)(6286002)(2906002)(26005)(40460700003)(2616005)(478600001)(63370400001)(36756003);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "06 Oct 2022 11:02:03.8431 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 104b228e-b882-40cc-2d24-08daa78a33aa", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT020.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BL3PR12MB6427", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "This patch extends HCA_CAP and SQ Context structs available in PRM. This\nfields allow checking if NIC supports storing hairpin SQ's WQ buffer in\nhost memory and configuring such memory placement.\n\nHCA capabilities are extended with the following fields:\n\n- hairpin_sq_wq_in_host_mem - If set, then NIC supports using host\nmemory as a backing storage for hairpin SQ's WQ buffer.\n- hairpin_sq_wqe_bb_size - Indicates the required size of SQ WQE basic\nblock.\n\nSQ Context is extended with hairpin_wq_buffer_type which informs\nNIC where SQ's WQ buffer will be stored. This field can take the\nfollowing values:\n\n- MLX5_SQC_HAIRPIN_WQ_BUFFER_TYPE_INTERNAL_BUFFER - WQ buffer will be\n stored in unlocked device memory.\n- MLX5_SQC_HAIRPIN_WQ_BUFFER_TYPE_HOST_MEMORY - WQ buffer will be stored\n in host memory. Buffer is provided by PMD.\n\nSigned-off-by: Dariusz Sosnowski <dsosnowski@nvidia.com>\nAcked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>\n---\n drivers/common/mlx5/mlx5_devx_cmds.c | 5 +++++\n drivers/common/mlx5/mlx5_devx_cmds.h | 3 +++\n drivers/common/mlx5/mlx5_prm.h | 15 +++++++++++++--\n 3 files changed, 21 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c\nindex fb33023138..a1e8179568 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.c\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.c\n@@ -989,6 +989,10 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,\n \t\t}\n \t\tattr->log_min_stride_wqe_sz = MLX5_GET(cmd_hca_cap_2, hcattr,\n \t\t\t\t\t\t log_min_stride_wqe_sz);\n+\t\tattr->hairpin_sq_wqe_bb_size = MLX5_GET(cmd_hca_cap_2, hcattr,\n+\t\t\t\t\t\t\thairpin_sq_wqe_bb_size);\n+\t\tattr->hairpin_sq_wq_in_host_mem = MLX5_GET(cmd_hca_cap_2, hcattr,\n+\t\t\t\t\t\t\t hairpin_sq_wq_in_host_mem);\n \t}\n \tif (attr->log_min_stride_wqe_sz == 0)\n \t\tattr->log_min_stride_wqe_sz = MLX5_MPRQ_LOG_MIN_STRIDE_WQE_SIZE;\n@@ -1706,6 +1710,7 @@ mlx5_devx_cmd_create_sq(void *ctx,\n \tMLX5_SET(sqc, sq_ctx, hairpin, sq_attr->hairpin);\n \tMLX5_SET(sqc, sq_ctx, non_wire, sq_attr->non_wire);\n \tMLX5_SET(sqc, sq_ctx, static_sq_wq, sq_attr->static_sq_wq);\n+\tMLX5_SET(sqc, sq_ctx, hairpin_wq_buffer_type, sq_attr->hairpin_wq_buffer_type);\n \tMLX5_SET(sqc, sq_ctx, user_index, sq_attr->user_index);\n \tMLX5_SET(sqc, sq_ctx, cqn, sq_attr->cqn);\n \tMLX5_SET(sqc, sq_ctx, packet_pacing_rate_limit_index,\ndiff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h\nindex af6053a788..9ac2d75df4 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.h\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.h\n@@ -191,6 +191,8 @@ struct mlx5_hca_attr {\n \tuint32_t log_max_hairpin_queues:5;\n \tuint32_t log_max_hairpin_wq_data_sz:5;\n \tuint32_t log_max_hairpin_num_packets:5;\n+\tuint32_t hairpin_sq_wqe_bb_size:4;\n+\tuint32_t hairpin_sq_wq_in_host_mem:1;\n \tuint32_t vhca_id:16;\n \tuint32_t relaxed_ordering_write:1;\n \tuint32_t relaxed_ordering_read:1;\n@@ -407,6 +409,7 @@ struct mlx5_devx_create_sq_attr {\n \tuint32_t non_wire:1;\n \tuint32_t static_sq_wq:1;\n \tuint32_t ts_format:2;\n+\tuint32_t hairpin_wq_buffer_type:3;\n \tuint32_t user_index:24;\n \tuint32_t cqn:24;\n \tuint32_t packet_pacing_rate_limit_index:16;\ndiff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex 4346279c81..04d35ca845 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -2020,7 +2020,11 @@ struct mlx5_ifc_cmd_hca_cap_2_bits {\n \tu8 reserved_at_d8[0x3];\n \tu8 log_max_conn_track_offload[0x5];\n \tu8 reserved_at_e0[0x20]; /* End of DW7. */\n-\tu8 reserved_at_100[0x700];\n+\tu8 reserved_at_100[0x60];\n+\tu8 reserved_at_160[0x3];\n+\tu8 hairpin_sq_wqe_bb_size[0x5];\n+\tu8 hairpin_sq_wq_in_host_mem[0x1];\n+\tu8 reserved_at_169[0x697];\n };\n \n struct mlx5_ifc_esw_cap_bits {\n@@ -2673,6 +2677,11 @@ enum {\n \tMLX5_SQC_STATE_ERR = 0x3,\n };\n \n+enum {\n+\tMLX5_SQC_HAIRPIN_WQ_BUFFER_TYPE_INTERNAL_BUFFER = 0x0,\n+\tMLX5_SQC_HAIRPIN_WQ_BUFFER_TYPE_HOST_MEMORY = 0x1,\n+};\n+\n struct mlx5_ifc_sqc_bits {\n \tu8 rlky[0x1];\n \tu8 cd_master[0x1];\n@@ -2686,7 +2695,9 @@ struct mlx5_ifc_sqc_bits {\n \tu8 hairpin[0x1];\n \tu8 non_wire[0x1];\n \tu8 static_sq_wq[0x1];\n-\tu8 reserved_at_11[0x9];\n+\tu8 reserved_at_11[0x4];\n+\tu8 hairpin_wq_buffer_type[0x3];\n+\tu8 reserved_at_18[0x2];\n \tu8 ts_format[0x02];\n \tu8 reserved_at_1c[0x4];\n \tu8 reserved_at_20[0x8];\n", "prefixes": [ "v2", "2/8" ] }