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{ "id": 117448, "url": "https://patches.dpdk.org/api/covers/117448/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/cover/20221006110105.2986966-1-dsosnowski@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20221006110105.2986966-1-dsosnowski@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20221006110105.2986966-1-dsosnowski@nvidia.com", "date": "2022-10-06T11:00:57", "name": "[v2,0/8] ethdev: introduce hairpin memory capabilities", "submitter": { "id": 2386, "url": "https://patches.dpdk.org/api/people/2386/?format=api", "name": "Dariusz Sosnowski", "email": "dsosnowski@nvidia.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/cover/20221006110105.2986966-1-dsosnowski@nvidia.com/mbox/", "series": [ { "id": 25009, "url": "https://patches.dpdk.org/api/series/25009/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=25009", "date": "2022-10-06T11:00:57", "name": "ethdev: introduce hairpin memory capabilities", "version": 2, "mbox": "https://patches.dpdk.org/series/25009/mbox/" } ], "comments": "https://patches.dpdk.org/api/covers/117448/comments/", "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id C13E7A00C2;\n\tThu, 6 Oct 2022 13:02:04 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 7599B42BF0;\n\tThu, 6 Oct 2022 13:02:04 +0200 (CEST)", "from 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<dsosnowski@nvidia.com>", "To": "Thomas Monjalon <thomas@monjalon.net>, Ferruh Yigit\n <ferruh.yigit@xilinx.com>, Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>", "CC": "<dev@dpdk.org>, Viacheslav Ovsiienko <viacheslavo@nvidia.com>, Matan Azrad\n <matan@nvidia.com>, Ori Kam <orika@nvidia.com>, Wisam Jaddo\n <wisamm@nvidia.com>, Aman Singh <aman.deep.singh@intel.com>, Yuying Zhang\n <yuying.zhang@intel.com>", "Subject": "[PATCH v2 0/8] ethdev: introduce hairpin memory capabilities", "Date": "Thu, 6 Oct 2022 11:00:57 +0000", "Message-ID": "<20221006110105.2986966-1-dsosnowski@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20220919163731.1540454-1-dsosnowski@nvidia.com>", "References": "", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.35]", "X-ClientProxiedBy": "rnnvmail202.nvidia.com (10.129.68.7) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", 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H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE;\n SFS:(13230022)(4636009)(136003)(396003)(376002)(346002)(39860400002)(451199015)(36840700001)(40470700004)(46966006)(36756003)(86362001)(110136005)(36860700001)(336012)(16526019)(1076003)(186003)(2616005)(356005)(7636003)(82740400003)(47076005)(426003)(6286002)(26005)(7696005)(966005)(478600001)(316002)(6666004)(54906003)(70586007)(8676002)(4326008)(70206006)(8936002)(82310400005)(5660300002)(2906002)(83380400001)(40460700003)(40480700001)(55016003)(41300700001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "06 Oct 2022 11:02:00.1383 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 244079b8-7a7f-4ab5-7dc6-08daa78a3172", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT037.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MW4PR12MB7142", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "The hairpin queues are used to transmit packets received on the wire, back to the wire.\nHow hairpin queues are implemented and configured is decided internally by the PMD and\napplications have no control over the configuration of Rx and Tx hairpin queues.\nThis patchset addresses that by:\n\n- Extending hairpin queue capabilities reported by PMDs.\n- Exposing new configuration options for Rx and Tx hairpin queues.\n\nMain goal of this patchset is to allow applications to provide configuration hints\nregarding memory placement of hairpin queues.\nThese hints specify whether buffers of hairpin queues should be placed in host memory\nor in dedicated device memory.\n\nFor example, in context of NVIDIA Connect-X and BlueField devices,\nthis distinction is important for several reasons:\n\n- By default, data buffers and packet descriptors are placed in device memory region\n which is shared with other resources (e.g. flow rules).\n This results in memory contention on the device,\n which may lead to degraded performance under heavy load.\n- Placing hairpin queues in dedicated device memory can decrease latency of hairpinned traffic,\n since hairpin queue processing will not be memory starved by other operations.\n Side effect of this memory configuration is that it leaves less memory for other resources,\n possibly causing memory contention in non-hairpin traffic.\n- Placing hairpin queues in host memory can increase throughput of hairpinned\n traffic at the cost of increasing latency.\n Each packet processed by hairpin queues will incur additional PCI transactions (increase in latency),\n but memory contention on the device is avoided.\n\nDepending on the workload and whether throughput or latency has a higher priority for developers,\nit would be beneficial if developers could choose the best hairpin configuration for their use case.\n\nTo address that, this patchset adds the following configuration options (in rte_eth_hairpin_conf struct):\n\n- use_locked_device_memory - If set, PMD will allocate specialized on-device memory for the queue.\n- use_rte_memory - If set, PMD will use DPDK-managed memory for the queue.\n- force_memory - If set, PMD will be forced to use provided memory configuration.\n If no appropriate resources are available, the queue allocation will fail.\n If unset and no appropriate resources are available, PMD will fallback to its default behavior.\n\nImplementing support for these flags is optional and applications should be allowed to not set any of these new flags.\nThis will result in default memory configuration provided by the PMD.\nApplication developers should consult the PMD documentation in that case.\n\nThese changes were originally proposed in http://patches.dpdk.org/project/dpdk/patch/20220811120530.191683-1-dsosnowski@nvidia.com/.\n\nDariusz Sosnowski (8):\n ethdev: introduce hairpin memory capabilities\n common/mlx5: add hairpin SQ buffer type capabilities\n common/mlx5: add hairpin RQ buffer type capabilities\n net/mlx5: allow hairpin Tx queue in RTE memory\n net/mlx5: allow hairpin Rx queue in locked memory\n doc: add notes for hairpin to mlx5 documentation\n app/testpmd: add hairpin queues memory modes\n app/flow-perf: add hairpin queue memory config\n\n app/test-flow-perf/main.c | 32 +++++\n app/test-pmd/parameters.c | 2 +-\n app/test-pmd/testpmd.c | 24 +++-\n app/test-pmd/testpmd.h | 2 +-\n doc/guides/nics/mlx5.rst | 37 ++++++\n doc/guides/platform/mlx5.rst | 5 +\n doc/guides/rel_notes/release_22_11.rst | 10 ++\n doc/guides/testpmd_app_ug/run_app.rst | 10 +-\n drivers/common/mlx5/mlx5_devx_cmds.c | 8 ++\n drivers/common/mlx5/mlx5_devx_cmds.h | 5 +\n drivers/common/mlx5/mlx5_prm.h | 25 +++-\n drivers/net/mlx5/mlx5.h | 2 +\n drivers/net/mlx5/mlx5_devx.c | 170 ++++++++++++++++++++++---\n drivers/net/mlx5/mlx5_ethdev.c | 6 +\n lib/ethdev/rte_ethdev.c | 44 +++++++\n lib/ethdev/rte_ethdev.h | 68 +++++++++-\n 16 files changed, 422 insertions(+), 28 deletions(-)" }