diff mbox series

crypto/mlx5: add max segment assert

Message ID 20240301124246.1216467-1-suanmingm@nvidia.com (mailing list archive)
State Accepted, archived
Delegated to: akhil goyal
Headers
Series crypto/mlx5: add max segment assert |

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/Intel-compilation success Compilation OK
ci/intel-Testing success Testing PASS
ci/github-robot: build success github build: passed
ci/intel-Functional success Functional PASS
ci/iol-mellanox-Performance success Performance Testing PASS
ci/iol-abi-testing success Testing PASS
ci/iol-unit-arm64-testing success Testing PASS
ci/iol-compile-amd64-testing success Testing PASS
ci/iol-compile-arm64-testing success Testing PASS
ci/iol-unit-amd64-testing success Testing PASS
ci/iol-intel-Functional success Functional Testing PASS
ci/iol-intel-Performance success Performance Testing PASS
ci/loongarch-compilation success Compilation OK
ci/loongarch-unit-testing success Unit Testing PASS
ci/iol-broadcom-Performance success Performance Testing PASS
ci/iol-broadcom-Functional success Functional Testing PASS
ci/iol-sample-apps-testing success Testing PASS

Commit Message

Suanming Mou March 1, 2024, 12:42 p.m. UTC 
  Currently, for multi-segment mbuf, before crypto WQE an extra
UMR WQE will be introduced to build the contiguous memory space.
Crypto WQE uses that contiguous memory space key as input.

This commit adds assert for maximum supported segments in debug
mode in case the segments exceed UMR's limitation.

Signed-off-by: Suanming Mou <suanmingm@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
---
 drivers/crypto/mlx5/mlx5_crypto_gcm.c | 6 ++++++
 1 file changed, 6 insertions(+)

Comments

Patrick Robb March 1, 2024, 4:09 p.m. UTC | #1 
The Community Lab had an infra failure this morning and some patches
including yours were affected with false failures. The issue is now
resolved and we are rerunning the tests in question for all patches
submitted today.

On Fri, Mar 1, 2024 at 7:43 AM Suanming Mou <suanmingm@nvidia.com> wrote:

> Currently, for multi-segment mbuf, before crypto WQE an extra
> UMR WQE will be introduced to build the contiguous memory space.
> Crypto WQE uses that contiguous memory space key as input.
>
> This commit adds assert for maximum supported segments in debug
> mode in case the segments exceed UMR's limitation.
>
> Signed-off-by: Suanming Mou <suanmingm@nvidia.com>
> Acked-by: Matan Azrad <matan@nvidia.com>
> ---
>  drivers/crypto/mlx5/mlx5_crypto_gcm.c | 6 ++++++
>  1 file changed, 6 insertions(+)
>
> diff --git a/drivers/crypto/mlx5/mlx5_crypto_gcm.c
> b/drivers/crypto/mlx5/mlx5_crypto_gcm.c
> index 8b9953b46d..fc6ade6711 100644
> --- a/drivers/crypto/mlx5/mlx5_crypto_gcm.c
> +++ b/drivers/crypto/mlx5/mlx5_crypto_gcm.c
> @@ -441,6 +441,9 @@ mlx5_crypto_gcm_get_op_info(struct mlx5_crypto_qp *qp,
>         op_info->digest = NULL;
>         op_info->src_addr = aad_addr;
>         if (op->sym->m_dst && op->sym->m_dst != m_src) {
> +               /* Add 2 for AAD and digest. */
> +               MLX5_ASSERT((uint32_t)(m_dst->nb_segs + m_src->nb_segs +
> 2) <
> +                           qp->priv->max_klm_num);
>                 op_info->is_oop = true;
>                 m_dst = op->sym->m_dst;
>                 dst_addr = rte_pktmbuf_mtod_offset(m_dst, void *,
> op->sym->aead.data.offset);
> @@ -457,6 +460,9 @@ mlx5_crypto_gcm_get_op_info(struct mlx5_crypto_qp *qp,
>                         op_info->need_umr = true;
>                         return;
>                 }
> +       } else {
> +               /* Add 2 for AAD and digest. */
> +               MLX5_ASSERT((uint32_t)(m_src->nb_segs) + 2 <
> qp->priv->max_klm_num);
>         }
>         if (m_src->nb_segs > 1) {
>                 op_info->need_umr = true;
> --
> 2.34.1
>
>
Akhil Goyal March 4, 2024, 10:01 a.m. UTC | #2 
> Currently, for multi-segment mbuf, before crypto WQE an extra
> UMR WQE will be introduced to build the contiguous memory space.
> Crypto WQE uses that contiguous memory space key as input.
> 
> This commit adds assert for maximum supported segments in debug
> mode in case the segments exceed UMR's limitation.
> 
> Signed-off-by: Suanming Mou <suanmingm@nvidia.com>
> Acked-by: Matan Azrad <matan@nvidia.com>
Applied to dpdk-next-crypto
Thanks.
diff mbox series

Patch

diff --git a/drivers/crypto/mlx5/mlx5_crypto_gcm.c b/drivers/crypto/mlx5/mlx5_crypto_gcm.c
index 8b9953b46d..fc6ade6711 100644
--- a/drivers/crypto/mlx5/mlx5_crypto_gcm.c
+++ b/drivers/crypto/mlx5/mlx5_crypto_gcm.c
@@ -441,6 +441,9 @@  mlx5_crypto_gcm_get_op_info(struct mlx5_crypto_qp *qp,
 	op_info->digest = NULL;
 	op_info->src_addr = aad_addr;
 	if (op->sym->m_dst && op->sym->m_dst != m_src) {
+		/* Add 2 for AAD and digest. */
+		MLX5_ASSERT((uint32_t)(m_dst->nb_segs + m_src->nb_segs + 2) <
+			    qp->priv->max_klm_num);
 		op_info->is_oop = true;
 		m_dst = op->sym->m_dst;
 		dst_addr = rte_pktmbuf_mtod_offset(m_dst, void *, op->sym->aead.data.offset);
@@ -457,6 +460,9 @@  mlx5_crypto_gcm_get_op_info(struct mlx5_crypto_qp *qp,
 			op_info->need_umr = true;
 			return;
 		}
+	} else {
+		/* Add 2 for AAD and digest. */
+		MLX5_ASSERT((uint32_t)(m_src->nb_segs) + 2 < qp->priv->max_klm_num);
 	}
 	if (m_src->nb_segs > 1) {
 		op_info->need_umr = true;