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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by SN1PEPF0002BA4F.mail.protection.outlook.com (10.167.242.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7362.11 via Frontend Transport; Fri, 1 Mar 2024 12:43:15 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Fri, 1 Mar 2024 04:43:00 -0800 Received: from nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Fri, 1 Mar 2024 04:42:59 -0800 From: Suanming Mou To: Matan Azrad CC: Subject: [PATCH] crypto/mlx5: add max segment assert Date: Fri, 1 Mar 2024 20:42:45 +0800 Message-ID: <20240301124246.1216467-1-suanmingm@nvidia.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002BA4F:EE_|MN0PR12MB6128:EE_ X-MS-Office365-Filtering-Correlation-Id: abe040e0-1bad-4584-784f-08dc39ed29f1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Mar 2024 12:43:15.2084 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: abe040e0-1bad-4584-784f-08dc39ed29f1 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002BA4F.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB6128 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Currently, for multi-segment mbuf, before crypto WQE an extra UMR WQE will be introduced to build the contiguous memory space. Crypto WQE uses that contiguous memory space key as input. This commit adds assert for maximum supported segments in debug mode in case the segments exceed UMR's limitation. Signed-off-by: Suanming Mou Acked-by: Matan Azrad --- drivers/crypto/mlx5/mlx5_crypto_gcm.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/crypto/mlx5/mlx5_crypto_gcm.c b/drivers/crypto/mlx5/mlx5_crypto_gcm.c index 8b9953b46d..fc6ade6711 100644 --- a/drivers/crypto/mlx5/mlx5_crypto_gcm.c +++ b/drivers/crypto/mlx5/mlx5_crypto_gcm.c @@ -441,6 +441,9 @@ mlx5_crypto_gcm_get_op_info(struct mlx5_crypto_qp *qp, op_info->digest = NULL; op_info->src_addr = aad_addr; if (op->sym->m_dst && op->sym->m_dst != m_src) { + /* Add 2 for AAD and digest. */ + MLX5_ASSERT((uint32_t)(m_dst->nb_segs + m_src->nb_segs + 2) < + qp->priv->max_klm_num); op_info->is_oop = true; m_dst = op->sym->m_dst; dst_addr = rte_pktmbuf_mtod_offset(m_dst, void *, op->sym->aead.data.offset); @@ -457,6 +460,9 @@ mlx5_crypto_gcm_get_op_info(struct mlx5_crypto_qp *qp, op_info->need_umr = true; return; } + } else { + /* Add 2 for AAD and digest. */ + MLX5_ASSERT((uint32_t)(m_src->nb_segs) + 2 < qp->priv->max_klm_num); } if (m_src->nb_segs > 1) { op_info->need_umr = true;