[v8,0/9] add rte flow support for cpfl

Message ID 20230927125416.2308974-1-yuying.zhang@intel.com (mailing list archive)
Headers
Series add rte flow support for cpfl |

Message

Zhang, Yuying Sept. 27, 2023, 12:54 p.m. UTC
  From: Yuying Zhang <yuying.zhang@intel.com>

This patchset add rte flow support for cpfl driver.
It depends on the following patch set:
http://patchwork.dpdk.org/project/dpdk/cover/20230912173039.1612287-1-beilei.xing@intel.com/

Wenjing Qiao (2):
  net/cpfl: add json parser for rte flow pattern rules
  net/cpfl: build action mapping rules from JSON

Yuying Zhang (7):
  net/cpfl: set up rte flow skeleton
  net/cpfl: set up control path
  net/cpfl: add FXP low level implementation
  net/cpfl: add fxp rule module
  net/cpfl: add fxp flow engine
  net/cpfl: add flow support for representor
  net/cpfl: add support of to represented port action
---
v8:
* fix compile issues
* refine document and separate patch with different features
v7:
* refine commit log
* fix compile issues

v6:
* use existed jansson instead of json-c library.
* refine "add FXP low level implementation"

V5:
* Add input validation for some functions.

 doc/guides/nics/cpfl.rst                |   52 +
 doc/guides/rel_notes/release_23_11.rst  |    1 +
 drivers/net/cpfl/cpfl_actions.h         |  858 +++++++++++
 drivers/net/cpfl/cpfl_controlq.c        |  801 ++++++++++
 drivers/net/cpfl/cpfl_controlq.h        |   75 +
 drivers/net/cpfl/cpfl_ethdev.c          |  392 ++++-
 drivers/net/cpfl/cpfl_ethdev.h          |  128 ++
 drivers/net/cpfl/cpfl_flow.c            |  339 +++++
 drivers/net/cpfl/cpfl_flow.h            |   85 ++
 drivers/net/cpfl/cpfl_flow_engine_fxp.c |  667 ++++++++
 drivers/net/cpfl/cpfl_flow_parser.c     | 1839 +++++++++++++++++++++++
 drivers/net/cpfl/cpfl_flow_parser.h     |  267 ++++
 drivers/net/cpfl/cpfl_fxp_rule.c        |  296 ++++
 drivers/net/cpfl/cpfl_fxp_rule.h        |   68 +
 drivers/net/cpfl/cpfl_representor.c     |   29 +
 drivers/net/cpfl/cpfl_rules.c           |  127 ++
 drivers/net/cpfl/cpfl_rules.h           |  306 ++++
 drivers/net/cpfl/cpfl_vchnl.c           |  144 ++
 drivers/net/cpfl/meson.build            |   12 +
 19 files changed, 6485 insertions(+), 1 deletion(-)
 create mode 100644 drivers/net/cpfl/cpfl_actions.h
 create mode 100644 drivers/net/cpfl/cpfl_controlq.c
 create mode 100644 drivers/net/cpfl/cpfl_controlq.h
 create mode 100644 drivers/net/cpfl/cpfl_flow.c
 create mode 100644 drivers/net/cpfl/cpfl_flow.h
 create mode 100644 drivers/net/cpfl/cpfl_flow_engine_fxp.c
 create mode 100644 drivers/net/cpfl/cpfl_flow_parser.c
 create mode 100644 drivers/net/cpfl/cpfl_flow_parser.h
 create mode 100644 drivers/net/cpfl/cpfl_fxp_rule.c
 create mode 100644 drivers/net/cpfl/cpfl_fxp_rule.h
 create mode 100644 drivers/net/cpfl/cpfl_rules.c
 create mode 100644 drivers/net/cpfl/cpfl_rules.h
  

Comments

Qi Zhang Sept. 28, 2023, 3:37 a.m. UTC | #1
> -----Original Message-----
> From: Zhang, Yuying <yuying.zhang@intel.com>
> Sent: Wednesday, September 27, 2023 8:54 PM
> To: Zhang, Yuying <yuying.zhang@intel.com>; dev@dpdk.org; Zhang, Qi Z
> <qi.z.zhang@intel.com>; Wu, Jingjing <jingjing.wu@intel.com>; Xing, Beilei
> <beilei.xing@intel.com>
> Subject: [PATCH v8 0/9] add rte flow support for cpfl
> 
> From: Yuying Zhang <yuying.zhang@intel.com>
> 
> This patchset add rte flow support for cpfl driver.
> It depends on the following patch set:
> http://patchwork.dpdk.org/project/dpdk/cover/20230912173039.1612287-1-
> beilei.xing@intel.com/
> 
> Wenjing Qiao (2):
>   net/cpfl: add json parser for rte flow pattern rules
>   net/cpfl: build action mapping rules from JSON
> 
> Yuying Zhang (7):
>   net/cpfl: set up rte flow skeleton
>   net/cpfl: set up control path
>   net/cpfl: add FXP low level implementation
>   net/cpfl: add fxp rule module
>   net/cpfl: add fxp flow engine
>   net/cpfl: add flow support for representor
>   net/cpfl: add support of to represented port action
> ---
> v8:
> * fix compile issues
> * refine document and separate patch with different features
> v7:
> * refine commit log
> * fix compile issues
> 
> v6:
> * use existed jansson instead of json-c library.
> * refine "add FXP low level implementation"
> 
> V5:
> * Add input validation for some functions.
> 
>  doc/guides/nics/cpfl.rst                |   52 +
>  doc/guides/rel_notes/release_23_11.rst  |    1 +
>  drivers/net/cpfl/cpfl_actions.h         |  858 +++++++++++
>  drivers/net/cpfl/cpfl_controlq.c        |  801 ++++++++++
>  drivers/net/cpfl/cpfl_controlq.h        |   75 +
>  drivers/net/cpfl/cpfl_ethdev.c          |  392 ++++-
>  drivers/net/cpfl/cpfl_ethdev.h          |  128 ++
>  drivers/net/cpfl/cpfl_flow.c            |  339 +++++
>  drivers/net/cpfl/cpfl_flow.h            |   85 ++
>  drivers/net/cpfl/cpfl_flow_engine_fxp.c |  667 ++++++++
>  drivers/net/cpfl/cpfl_flow_parser.c     | 1839 +++++++++++++++++++++++
>  drivers/net/cpfl/cpfl_flow_parser.h     |  267 ++++
>  drivers/net/cpfl/cpfl_fxp_rule.c        |  296 ++++
>  drivers/net/cpfl/cpfl_fxp_rule.h        |   68 +
>  drivers/net/cpfl/cpfl_representor.c     |   29 +
>  drivers/net/cpfl/cpfl_rules.c           |  127 ++
>  drivers/net/cpfl/cpfl_rules.h           |  306 ++++
>  drivers/net/cpfl/cpfl_vchnl.c           |  144 ++
>  drivers/net/cpfl/meson.build            |   12 +
>  19 files changed, 6485 insertions(+), 1 deletion(-)  create mode 100644
> drivers/net/cpfl/cpfl_actions.h  create mode 100644
> drivers/net/cpfl/cpfl_controlq.c  create mode 100644
> drivers/net/cpfl/cpfl_controlq.h  create mode 100644
> drivers/net/cpfl/cpfl_flow.c  create mode 100644 drivers/net/cpfl/cpfl_flow.h
> create mode 100644 drivers/net/cpfl/cpfl_flow_engine_fxp.c
>  create mode 100644 drivers/net/cpfl/cpfl_flow_parser.c
>  create mode 100644 drivers/net/cpfl/cpfl_flow_parser.h
>  create mode 100644 drivers/net/cpfl/cpfl_fxp_rule.c  create mode 100644
> drivers/net/cpfl/cpfl_fxp_rule.h  create mode 100644
> drivers/net/cpfl/cpfl_rules.c  create mode 100644 drivers/net/cpfl/cpfl_rules.h
> 
> --
> 2.34.1

Please fix one checkpatch warning on PATCH 6 and also rebase to latest dpdk-next-net-intel in new version.

Otherwise Acked-by: Qi Zhang <qi.z.zhang@intel.com>