From patchwork Wed Sep 27 12:54:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhang, Yuying" X-Patchwork-Id: 193 Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8AEFA42651; Wed, 27 Sep 2023 14:54:33 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 660AE4028C; Wed, 27 Sep 2023 14:54:33 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.136]) by mails.dpdk.org (Postfix) with ESMTP id BBE0A4026C for ; Wed, 27 Sep 2023 14:54:31 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1695819272; x=1727355272; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=aBWTWv9ThI9LKtUlkXWzD56mP7bIItwQ4y18Lh23V1E=; b=R0VRI1eo15XT3Yz0DbuoYj7zwHWfUQRR7nSeZOGRlUgYB6uJ56Q/HEVG CDmirb+QIXpKvnAUVbypnGKnVVlEuHlq9ald+ziJQNT7H7S15nJzCVxo2 rcxNZv1m4W07No6zQZFjcqFFCHt7UUiyTkm6ljzi8e4ABtjIEp78HaDcg WKI22UT+TbXvXiZAacZFH99MQd1FTPnyaP0Q2cq3TUsf+WiaNbMR+YTYM O6VL/NbTFdWsImBjK8+9DzVrvk4qKZNvlZjAActTqqvb0ybOMq2xR/IhN o1FL60u3Yuz3ymSQGjThnE2OYuAYhUBH6EqKsfio/OfYKDB+UK3S+Egg2 g==; X-IronPort-AV: E=McAfee;i="6600,9927,10846"; a="361203995" X-IronPort-AV: E=Sophos;i="6.03,181,1694761200"; d="scan'208";a="361203995" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Sep 2023 05:54:30 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10846"; a="872873870" X-IronPort-AV: E=Sophos;i="6.03,181,1694761200"; d="scan'208";a="872873870" Received: from dpdk-wenjing-02.sh.intel.com ([10.67.119.3]) by orsmga004.jf.intel.com with ESMTP; 27 Sep 2023 05:54:28 -0700 From: yuying.zhang@intel.com To: yuying.zhang@intel.com, dev@dpdk.org, qi.z.zhang@intel.com, jingjing.wu@intel.com, beilei.xing@intel.com Subject: [PATCH v8 0/9] add rte flow support for cpfl Date: Wed, 27 Sep 2023 12:54:07 +0000 Message-Id: <20230927125416.2308974-1-yuying.zhang@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230926181703.2268199-1-yuying.zhang@intel.com> References: <20230926181703.2268199-1-yuying.zhang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Yuying Zhang This patchset add rte flow support for cpfl driver. It depends on the following patch set: http://patchwork.dpdk.org/project/dpdk/cover/20230912173039.1612287-1-beilei.xing@intel.com/ Wenjing Qiao (2): net/cpfl: add json parser for rte flow pattern rules net/cpfl: build action mapping rules from JSON Yuying Zhang (7): net/cpfl: set up rte flow skeleton net/cpfl: set up control path net/cpfl: add FXP low level implementation net/cpfl: add fxp rule module net/cpfl: add fxp flow engine net/cpfl: add flow support for representor net/cpfl: add support of to represented port action --- v8: * fix compile issues * refine document and separate patch with different features v7: * refine commit log * fix compile issues v6: * use existed jansson instead of json-c library. * refine "add FXP low level implementation" V5: * Add input validation for some functions. doc/guides/nics/cpfl.rst | 52 + doc/guides/rel_notes/release_23_11.rst | 1 + drivers/net/cpfl/cpfl_actions.h | 858 +++++++++++ drivers/net/cpfl/cpfl_controlq.c | 801 ++++++++++ drivers/net/cpfl/cpfl_controlq.h | 75 + drivers/net/cpfl/cpfl_ethdev.c | 392 ++++- drivers/net/cpfl/cpfl_ethdev.h | 128 ++ drivers/net/cpfl/cpfl_flow.c | 339 +++++ drivers/net/cpfl/cpfl_flow.h | 85 ++ drivers/net/cpfl/cpfl_flow_engine_fxp.c | 667 ++++++++ drivers/net/cpfl/cpfl_flow_parser.c | 1839 +++++++++++++++++++++++ drivers/net/cpfl/cpfl_flow_parser.h | 267 ++++ drivers/net/cpfl/cpfl_fxp_rule.c | 296 ++++ drivers/net/cpfl/cpfl_fxp_rule.h | 68 + drivers/net/cpfl/cpfl_representor.c | 29 + drivers/net/cpfl/cpfl_rules.c | 127 ++ drivers/net/cpfl/cpfl_rules.h | 306 ++++ drivers/net/cpfl/cpfl_vchnl.c | 144 ++ drivers/net/cpfl/meson.build | 12 + 19 files changed, 6485 insertions(+), 1 deletion(-) create mode 100644 drivers/net/cpfl/cpfl_actions.h create mode 100644 drivers/net/cpfl/cpfl_controlq.c create mode 100644 drivers/net/cpfl/cpfl_controlq.h create mode 100644 drivers/net/cpfl/cpfl_flow.c create mode 100644 drivers/net/cpfl/cpfl_flow.h create mode 100644 drivers/net/cpfl/cpfl_flow_engine_fxp.c create mode 100644 drivers/net/cpfl/cpfl_flow_parser.c create mode 100644 drivers/net/cpfl/cpfl_flow_parser.h create mode 100644 drivers/net/cpfl/cpfl_fxp_rule.c create mode 100644 drivers/net/cpfl/cpfl_fxp_rule.h create mode 100644 drivers/net/cpfl/cpfl_rules.c create mode 100644 drivers/net/cpfl/cpfl_rules.h