[dpdk-dev,01/10] bnx2x: Set cache line based on build configuration

Message ID 1468271491-28510-1-git-send-email-3chas3@gmail.com (mailing list archive)
State Superseded, archived
Delegated to: Bruce Richardson
Headers

Commit Message

Chas Williams July 11, 2016, 9:11 p.m. UTC
  Correctly hint the cache line size.  Remove unused macros associated
with the cache line size.

Fixes: 540a211084a7 ("bnx2x: driver core")

Signed-off-by: Chas Williams <3chas3@gmail.com>
---
 drivers/net/bnx2x/bnx2x.h | 5 +----
 1 file changed, 1 insertion(+), 4 deletions(-)
  

Comments

Harish Patil July 12, 2016, 5:39 a.m. UTC | #1
>

>Correctly hint the cache line size.  Remove unused macros associated

>with the cache line size.

>

>Fixes: 540a211084a7 ("bnx2x: driver core")

>

>Signed-off-by: Chas Williams <3chas3@gmail.com>

>---

> drivers/net/bnx2x/bnx2x.h | 5 +----

> 1 file changed, 1 insertion(+), 4 deletions(-)

>

>diff --git a/drivers/net/bnx2x/bnx2x.h b/drivers/net/bnx2x/bnx2x.h

>index 135a6eb..852ec94 100644

>--- a/drivers/net/bnx2x/bnx2x.h

>+++ b/drivers/net/bnx2x/bnx2x.h

>@@ -302,10 +302,7 @@ struct bnx2x_device_type {

> /* TCP with Timestamp Option (32) + IPv6 (40) */

> 

> /* max supported alignment is 256 (8 shift) */

>-#define BNX2X_RX_ALIGN_SHIFT 8

>-/* FW uses 2 cache lines alignment for start packet and size  */

>-#define BNX2X_FW_RX_ALIGN_START (1 << BNX2X_RX_ALIGN_SHIFT)

>-#define BNX2X_FW_RX_ALIGN_END   (1 << BNX2X_RX_ALIGN_SHIFT)

>+#define BNX2X_RX_ALIGN_SHIFT	RTE_MAX(6, min(8, RTE_CACHE_LINE_SIZE_LOG2))

> 

> #define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5)

> 

>-- 

>2.5.5

>

>


Acked-by: Harish Patil <harish.patil@qlogic.com>
  
Ferruh Yigit Sept. 14, 2016, 1:17 p.m. UTC | #2
Hi Harish,

On 7/12/2016 6:39 AM, Harish Patil wrote:
>>
>> Correctly hint the cache line size.  Remove unused macros associated
>> with the cache line size.
>>
>> Fixes: 540a211084a7 ("bnx2x: driver core")
>>
>> Signed-off-by: Chas Williams <3chas3@gmail.com>
>> ---
>> drivers/net/bnx2x/bnx2x.h | 5 +----
>> 1 file changed, 1 insertion(+), 4 deletions(-)
>>
>> diff --git a/drivers/net/bnx2x/bnx2x.h b/drivers/net/bnx2x/bnx2x.h
>> index 135a6eb..852ec94 100644
>> --- a/drivers/net/bnx2x/bnx2x.h
>> +++ b/drivers/net/bnx2x/bnx2x.h
>> @@ -302,10 +302,7 @@ struct bnx2x_device_type {
>> /* TCP with Timestamp Option (32) + IPv6 (40) */
>>
>> /* max supported alignment is 256 (8 shift) */
>> -#define BNX2X_RX_ALIGN_SHIFT 8
>> -/* FW uses 2 cache lines alignment for start packet and size  */
>> -#define BNX2X_FW_RX_ALIGN_START (1 << BNX2X_RX_ALIGN_SHIFT)
>> -#define BNX2X_FW_RX_ALIGN_END   (1 << BNX2X_RX_ALIGN_SHIFT)
>> +#define BNX2X_RX_ALIGN_SHIFT  RTE_MAX(6, min(8, RTE_CACHE_LINE_SIZE_LOG2))
>>
>> #define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5)
>>
>> --
>> 2.5.5
>>
>>
> 
> Acked-by: Harish Patil <harish.patil@qlogic.com>
> 

Is the Ack for this patch (01/10) or for the series?

Thanks,
ferruh
  
Patil, Harish Sept. 30, 2016, 2:36 p.m. UTC | #3
>


>Hi Harish,

>

>On 7/12/2016 6:39 AM, Harish Patil wrote:

>>>

>>> Correctly hint the cache line size.  Remove unused macros associated

>>> with the cache line size.

>>>

>>> Fixes: 540a211084a7 ("bnx2x: driver core")

>>>

>>> Signed-off-by: Chas Williams <3chas3@gmail.com>

>>> ---

>>> drivers/net/bnx2x/bnx2x.h | 5 +----

>>> 1 file changed, 1 insertion(+), 4 deletions(-)

>>>

>>> diff --git a/drivers/net/bnx2x/bnx2x.h b/drivers/net/bnx2x/bnx2x.h

>>> index 135a6eb..852ec94 100644

>>> --- a/drivers/net/bnx2x/bnx2x.h

>>> +++ b/drivers/net/bnx2x/bnx2x.h

>>> @@ -302,10 +302,7 @@ struct bnx2x_device_type {

>>> /* TCP with Timestamp Option (32) + IPv6 (40) */

>>>

>>> /* max supported alignment is 256 (8 shift) */

>>> -#define BNX2X_RX_ALIGN_SHIFT 8

>>> -/* FW uses 2 cache lines alignment for start packet and size  */

>>> -#define BNX2X_FW_RX_ALIGN_START (1 << BNX2X_RX_ALIGN_SHIFT)

>>> -#define BNX2X_FW_RX_ALIGN_END   (1 << BNX2X_RX_ALIGN_SHIFT)

>>> +#define BNX2X_RX_ALIGN_SHIFT  RTE_MAX(6, min(8,

>>>RTE_CACHE_LINE_SIZE_LOG2))

>>>

>>> #define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5)

>>>

>>> --

>>> 2.5.5

>>>

>>>

>> 

>> Acked-by: Harish Patil <harish.patil@qlogic.com>

>> 

>

>Is the Ack for this patch (01/10) or for the series?

>

>Thanks,

>ferruh

>

>


Hi Ferruh,
I meant it for only this patch.
Let me scan thru’ for the series and ack.
Thanks,
Harish
  

Patch

diff --git a/drivers/net/bnx2x/bnx2x.h b/drivers/net/bnx2x/bnx2x.h
index 135a6eb..852ec94 100644
--- a/drivers/net/bnx2x/bnx2x.h
+++ b/drivers/net/bnx2x/bnx2x.h
@@ -302,10 +302,7 @@  struct bnx2x_device_type {
 /* TCP with Timestamp Option (32) + IPv6 (40) */
 
 /* max supported alignment is 256 (8 shift) */
-#define BNX2X_RX_ALIGN_SHIFT 8
-/* FW uses 2 cache lines alignment for start packet and size  */
-#define BNX2X_FW_RX_ALIGN_START (1 << BNX2X_RX_ALIGN_SHIFT)
-#define BNX2X_FW_RX_ALIGN_END   (1 << BNX2X_RX_ALIGN_SHIFT)
+#define BNX2X_RX_ALIGN_SHIFT	RTE_MAX(6, min(8, RTE_CACHE_LINE_SIZE_LOG2))
 
 #define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5)