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GET /api/patches/98828/?format=api
{ "id": 98828, "url": "http://patches.dpdk.org/api/patches/98828/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210914053833.7760-5-talshn@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210914053833.7760-5-talshn@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210914053833.7760-5-talshn@nvidia.com", "date": "2021-09-14T05:38:27", "name": "[RFC,04/10] common/mlx5: add memory region OS agnostic functions for Linux", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "1fcb5e0d7c90f0ed335e74c711e2ffa4309e0d23", "submitter": { "id": 1893, "url": "http://patches.dpdk.org/api/people/1893/?format=api", "name": "Tal Shnaiderman", "email": "talshn@nvidia.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210914053833.7760-5-talshn@nvidia.com/mbox/", "series": [ { "id": 18890, "url": "http://patches.dpdk.org/api/series/18890/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=18890", "date": "2021-09-14T05:38:23", "name": "Support MLX5 crypto driver on Windows", "version": 1, "mbox": "http://patches.dpdk.org/series/18890/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/98828/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/98828/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id D947AA0C47;\n\tTue, 14 Sep 2021 07:40:26 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 5B53041101;\n\tTue, 14 Sep 2021 07:40:07 +0200 (CEST)", "from NAM10-BN7-obe.outbound.protection.outlook.com\n (mail-bn7nam10on2074.outbound.protection.outlook.com [40.107.92.74])\n by mails.dpdk.org (Postfix) with ESMTP id 380D34111B\n for <dev@dpdk.org>; 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mx.microsoft.com 1; spf=pass (sender ip is\n 216.228.112.32) smtp.rcpttodomain=monjalon.net smtp.mailfrom=nvidia.com;\n dmarc=pass (p=quarantine sp=none pct=100) action=none header.from=nvidia.com;\n dkim=none (message not signed); arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=qFPxK4WcYj+52WCp5u5gU7+0htHVNAbhTY6hnvJcLNc=;\n b=QG2bu/76sfl1urRKSSWSfmEcnpEynoYmqPRjl2qXOycEAZ11qt3EVBXrt2LlzBkW0t07VwRu7quycdxVcCYYpj0PJSZB26H1NSv9f9wWJxpX8eqIPAET5rmbOuNPcRcR+8qOLCJS8d/WB2AwUZhm9B3yq6Y6af2Y5BFb/ZVW0/+yNJsU7a391mjAwnGs7HZBR05p+sxm8EvSrb1qRgUXE7kGQprMfqMdWFguUBQJbmsa/g1j52pM7EeXMxVQddeXZvWxERSjwdYnBqa5opOyGxIdUrm3gPSwws7iypSq5laN+qhyR9qpU98ZNQ2kFQzGfCAoXnxwkO/hTMgN+AOR8A==", "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 216.228.112.32)\n smtp.mailfrom=nvidia.com; monjalon.net; dkim=none (message not signed)\n header.d=none;monjalon.net; dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.112.32 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.112.32; helo=mail.nvidia.com;", "From": "Tal Shnaiderman <talshn@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "<thomas@monjalon.net>, <matan@nvidia.com>, <rasland@nvidia.com>,\n <asafp@nvidia.com>, <gakhil@marvell.com>, <declan.doherty@intel.com>,\n <viacheslavo@nvidia.com>, <eilong@nvidia.com>", "Date": "Tue, 14 Sep 2021 08:38:27 +0300", "Message-ID": "<20210914053833.7760-5-talshn@nvidia.com>", "X-Mailer": "git-send-email 2.16.1.windows.4", "In-Reply-To": "<20210914053833.7760-1-talshn@nvidia.com>", "References": "<20210914053833.7760-1-talshn@nvidia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.187.6]", "X-ClientProxiedBy": "HQMAIL111.nvidia.com (172.20.187.18) To\n DRHQMAIL107.nvidia.com (10.27.9.16)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "ddc97aa1-3c53-4445-b482-08d977421a73", "X-MS-TrafficTypeDiagnostic": "BYAPR12MB3191:", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-Microsoft-Antispam-PRVS": "\n <BYAPR12MB3191AC39D8088070871A98B3A4DA9@BYAPR12MB3191.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:6790;", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n VDy1FRyoEY546AtpH340Ul1wM2iF0mbiFZb3tZRS+Kgv0P9iyB/pdU0AontYQLbtlPOGe1AYvJEo6D3Q6CM0QAG4ZEzpbf1OuIdvM+DeZKErvCnU6hLjvCwM7rsb9WEZD3sMbyggB4cdgAxz3FRfOm83BaqG2R3hbn3mR1IStwWZTl13Ytb0oJxL9lzsRJUgYyfWEdY6FWV6IAV8uBKApVPs1A1h4rH/XRmwpCeaGhbiZKkceSoozBSIo9eFT+3vTI3VQCIi8Vk7idQYQHQo4a9i/pfGDElFYkfr96NCmQt217Loqy/xxR9D9TLRvVKgm25bx41UH5QVzxrFbnRD8Ycd4pKvS4iJncOy1ZgnqqI3AjAOV8CN65OzSpjk6xr4PpxUANh76phzrTT2yJ9H0QAB8qv4p+CCbVP5gertLp7ZZj68qZ37xQG0nmVNzt9hK9gVUlqIZPU5u4a0IcoU9J5gt7quzF5k+HfQ7MYgvfsGJwsdGUFgwDq9H4s9PfjaRJrKBUQsscsHDukRmQ/oTomiCKRmI6eCgCEPdVgqPNAVjqhxeEVH9D2n9hxKX9P8mRtFvxj+C9suekDjwP74Yokyxg/QMV99oiEmuwZtUJ4sT4zlLjhIJFZr15nlUZ+3JmfTAVTczmLBXXeI2QbB3/n0e0/Tf8peKL4aMAiL4wxrfbI0RbZboVDF3ybD6nJ0DUDZ0E6RQHZbSufcH+bYlQ==", "X-Forefront-Antispam-Report": "CIP:216.228.112.32; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid01.nvidia.com; CAT:NONE;\n SFS:(4636009)(36840700001)(46966006)(8676002)(6666004)(356005)(82310400003)(54906003)(336012)(4326008)(426003)(8936002)(7636003)(5660300002)(16526019)(186003)(47076005)(6286002)(508600001)(83380400001)(55016002)(316002)(26005)(6916009)(2906002)(70586007)(70206006)(2616005)(1076003)(7696005)(107886003)(36756003)(86362001)(36860700001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "14 Sep 2021 05:40:04.2124 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n ddc97aa1-3c53-4445-b482-08d977421a73", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.32];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT016.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BYAPR12MB3191", "Subject": "[dpdk-dev] [RFC PATCH 04/10] common/mlx5: add memory region OS\n agnostic functions for Linux", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The OS agnostic functions for memory region registration/deregistration\n(mlx5_os_reg_mr mlx5_os_dereg_mr) exist only for Windows OS.\n\nAdding them for Linux as well as they are needed for memory region\nactivities in shared code.\n\nSigned-off-by: Tal Shnaiderman <talshn@nvidia.com>\n---\n drivers/common/mlx5/linux/mlx5_common_os.c | 35 ++++++++++++++++++++++++++++\n drivers/common/mlx5/mlx5_common.h | 9 +++++++\n drivers/common/mlx5/windows/mlx5_common_os.c | 2 +-\n drivers/common/mlx5/windows/mlx5_common_os.h | 6 -----\n 4 files changed, 45 insertions(+), 7 deletions(-)", "diff": "diff --git a/drivers/common/mlx5/linux/mlx5_common_os.c b/drivers/common/mlx5/linux/mlx5_common_os.c\nindex 4aada82669..fd0ec6b748 100644\n--- a/drivers/common/mlx5/linux/mlx5_common_os.c\n+++ b/drivers/common/mlx5/linux/mlx5_common_os.c\n@@ -491,3 +491,38 @@ mlx5_os_get_pdn(void *pd, uint32_t *pdn)\n \treturn -ENOTSUP;\n #endif /* HAVE_IBV_FLOW_DV_SUPPORT */\n }\n+\n+/**\n+ * Register mr. Given protection domain pointer, pointer to addr and length\n+ * register the memory region.\n+ *\n+ * @param[in] pd\n+ * Pointer to protection domain context (type mlx5_pd).\n+ * @param[in] addr\n+ * Pointer to memory start address (type devx_device_ctx).\n+ * @param[in] length\n+ * Lengtoh of the memory to register.\n+ * @param[out] pmd_mr\n+ * pmd_mr struct set with lkey, address, length, pointer to mr object, mkey\n+ *\n+ * @return\n+ * 0 on successful registration, -1 otherwise\n+ */\n+int\n+mlx5_os_reg_mr(void *pd,\n+\t void *addr, size_t length, struct mlx5_pmd_mr *pmd_mr)\n+{\n+\treturn mlx5_common_verbs_reg_mr(pd, addr, length, pmd_mr);\n+}\n+\n+/**\n+ * De-register mr.\n+ *\n+ * @param[in] pmd_mr\n+ * Pointer to PMD mr object\n+ */\n+void\n+mlx5_os_dereg_mr(struct mlx5_pmd_mr *pmd_mr)\n+{\n+\tmlx5_common_verbs_dereg_mr(pmd_mr);\n+}\ndiff --git a/drivers/common/mlx5/mlx5_common.h b/drivers/common/mlx5/mlx5_common.h\nindex fcdf376193..a87318db91 100644\n--- a/drivers/common/mlx5/mlx5_common.h\n+++ b/drivers/common/mlx5/mlx5_common.h\n@@ -21,6 +21,7 @@\n \n #include \"mlx5_prm.h\"\n #include \"mlx5_devx_cmds.h\"\n+#include \"mlx5_common_mr.h\"\n #include \"mlx5_common_os.h\"\n \n /* Reported driver name. */\n@@ -427,4 +428,12 @@ __rte_internal\n int\n mlx5_os_get_pdn(void *pd, uint32_t *pdn);\n \n+__rte_internal\n+int\n+mlx5_os_reg_mr(void *pd,\n+\t\t void *addr, size_t length, struct mlx5_pmd_mr *pmd_mr);\n+__rte_internal\n+void\n+mlx5_os_dereg_mr(struct mlx5_pmd_mr *pmd_mr);\n+\n #endif /* RTE_PMD_MLX5_COMMON_H_ */\ndiff --git a/drivers/common/mlx5/windows/mlx5_common_os.c b/drivers/common/mlx5/windows/mlx5_common_os.c\nindex 5c9cccd3e9..2ecdf78310 100644\n--- a/drivers/common/mlx5/windows/mlx5_common_os.c\n+++ b/drivers/common/mlx5/windows/mlx5_common_os.c\n@@ -134,7 +134,7 @@ mlx5_os_umem_dereg(void *pumem)\n }\n \n /**\n- * Register mr. Given protection doamin pointer, pointer to addr and length\n+ * Register mr. Given protection domain pointer, pointer to addr and length\n * register the memory region.\n *\n * @param[in] pd\ndiff --git a/drivers/common/mlx5/windows/mlx5_common_os.h b/drivers/common/mlx5/windows/mlx5_common_os.h\nindex c3d74d3b67..62bdcb40cd 100644\n--- a/drivers/common/mlx5/windows/mlx5_common_os.h\n+++ b/drivers/common/mlx5/windows/mlx5_common_os.h\n@@ -13,7 +13,6 @@\n #include \"mlx5_autoconf.h\"\n #include \"mlx5_glue.h\"\n #include \"mlx5_malloc.h\"\n-#include \"mlx5_common_mr.h\"\n #include \"mlx5_win_ext.h\"\n \n #define MLX5_BF_OFFSET 0x800\n@@ -256,11 +255,6 @@ __rte_internal\n void *mlx5_os_umem_reg(void *ctx, void *addr, size_t size, uint32_t access);\n __rte_internal\n int mlx5_os_umem_dereg(void *pumem);\n-__rte_internal\n-int mlx5_os_reg_mr(void *pd,\n-\t\t void *addr, size_t length, struct mlx5_pmd_mr *pmd_mr);\n-__rte_internal\n-void mlx5_os_dereg_mr(struct mlx5_pmd_mr *pmd_mr);\n int mlx5_os_match_devx_devices_to_addr(struct devx_device_bdf *devx_bdf,\n \t\t\t\tstruct rte_pci_addr *addr);\n #endif /* RTE_PMD_MLX5_COMMON_OS_H_ */\n", "prefixes": [ "RFC", "04/10" ] }