From patchwork Tue Sep 14 05:38:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tal Shnaiderman X-Patchwork-Id: 98825 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 886F2A0C47; Tue, 14 Sep 2021 07:40:06 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id F3809410E6; Tue, 14 Sep 2021 07:40:00 +0200 (CEST) Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2082.outbound.protection.outlook.com [40.107.220.82]) by mails.dpdk.org (Postfix) with ESMTP id 1C43C4068F for ; Tue, 14 Sep 2021 07:39:59 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=ApiiyBble1FoAFxj+N4DSxaj9MviORURlgVo4GXFtT6Xs5mfnuXZ4jfUqbYD/qFOd0UsYvmyv5JoiapmIG3xC8XFZtljKVMP8IjuJyBMAfyNzaeCkuTR/w+26nwMdVNse8jEIqmZ6Th2hicAW4U5ytJ6g3pvAzvFTcMQd/xYAih1NZOr4LcMQZEmm980GSkYsGDZlHvjO+mMjxSaolEWcnPmokhX2H2iRnxJ+d7xkO26DdrEruUFnVwJoE2FaaXdE+9TUK7zMXe8EkuYPsmUxppkSMY7xy2tTGbX7oaSXl1T5Y2JiAaW5RyDzBpDLQu/A2/vPJYfGdTf7HjN0WXU3A== ARC-Message-Signature: i=1; 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monjalon.net; dkim=none (message not signed) header.d=none;monjalon.net; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by CO1NAM11FT054.mail.protection.outlook.com (10.13.174.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4500.14 via Frontend Transport; Tue, 14 Sep 2021 05:39:55 +0000 Received: from DRHQMAIL107.nvidia.com (10.27.9.16) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 14 Sep 2021 05:39:55 +0000 Received: from nvidia.com (172.20.187.6) by DRHQMAIL107.nvidia.com (10.27.9.16) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 14 Sep 2021 05:39:52 +0000 From: Tal Shnaiderman To: CC: , , , , , , , Date: Tue, 14 Sep 2021 08:38:24 +0300 Message-ID: <20210914053833.7760-2-talshn@nvidia.com> X-Mailer: git-send-email 2.16.1.windows.4 In-Reply-To: <20210914053833.7760-1-talshn@nvidia.com> References: <20210914053833.7760-1-talshn@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL111.nvidia.com (172.20.187.18) To DRHQMAIL107.nvidia.com (10.27.9.16) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 013ebe24-6dbe-4e8e-a82a-08d977421507 X-MS-TrafficTypeDiagnostic: BYAPR12MB2951: X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:3044; 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CAT:NONE; SFS:(4636009)(346002)(376002)(136003)(396003)(39860400002)(46966006)(36840700001)(6666004)(5660300002)(2906002)(70206006)(26005)(186003)(70586007)(47076005)(16526019)(4326008)(55016002)(356005)(8676002)(4744005)(86362001)(1076003)(478600001)(7636003)(6916009)(426003)(2616005)(336012)(6286002)(107886003)(83380400001)(82740400003)(36860700001)(36756003)(36906005)(8936002)(7696005)(54906003)(316002)(82310400003); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Sep 2021 05:39:55.2936 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 013ebe24-6dbe-4e8e-a82a-08d977421507 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT054.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR12MB2951 Subject: [dpdk-dev] [RFC PATCH 01/10] common/mlx5: add DV enums to Windows defs file X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add needed DV enums used by the crypto PMD and missing for Windows OS. Signed-off-by: Tal Shnaiderman --- drivers/common/mlx5/windows/mlx5_win_defs.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/common/mlx5/windows/mlx5_win_defs.h b/drivers/common/mlx5/windows/mlx5_win_defs.h index 47bfc907e7..9f709ff30d 100644 --- a/drivers/common/mlx5/windows/mlx5_win_defs.h +++ b/drivers/common/mlx5/windows/mlx5_win_defs.h @@ -93,6 +93,18 @@ enum { MLX5_ETH_WQE_L4_CSUM = (1 << 7), }; +enum { + MLX5_WQE_CTRL_CQ_UPDATE = 2 << 2, + MLX5_WQE_CTRL_SOLICITED = 1 << 1, + MLX5_WQE_CTRL_FENCE = 4 << 5, + MLX5_WQE_CTRL_INITIATOR_SMALL_FENCE = 1 << 5, +}; + +enum { + MLX5_SEND_WQE_BB = 64, + MLX5_SEND_WQE_SHIFT = 6, +}; + /* * RX Hash fields enable to set which incoming packet's field should * participates in RX Hash. Each flag represent certain packet's field, From patchwork Tue Sep 14 05:38:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tal Shnaiderman X-Patchwork-Id: 98826 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B05D7A0C47; Tue, 14 Sep 2021 07:40:12 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 00814410ED; Tue, 14 Sep 2021 07:40:03 +0200 (CEST) Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2076.outbound.protection.outlook.com [40.107.243.76]) by mails.dpdk.org (Postfix) with ESMTP id 1ADAA410DC for ; Tue, 14 Sep 2021 07:40:00 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=S7lCc3O2gH+O31KTNvzdLXPtN2d75TZgHE7dZSAL5dvADnE1AnYoIq+aArfZMIwDOwkhisXgjXvdqqJKOXHFuEjOJv8mvD3IwIQ2s2pggnc929t9AHWJzaI2iL+JN2E7BJYKq4bsftf/DoYKvsfvOvqxGZ8E7nKKeJoRfH7Dnz98uyRLA54rv3ASx4X1MdsmMNTDMjfawQ8jCEXg5S7ZYv8PHGgNXCZ9Vl2EVCduFQF6FuoV28aJIUuwLf+UutW1+WUEDbyWUC3jMdn2+e/1jfVQb2EIsnu43rwKxS78npe+nOfBmZPOnrpum7NlAnEy0AVarj5idsWlMgy7X0+r+g== ARC-Message-Signature: i=1; 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monjalon.net; dkim=none (message not signed) header.d=none;monjalon.net; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.36 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.36; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.36) by DM6NAM11FT026.mail.protection.outlook.com (10.13.172.161) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4500.14 via Frontend Transport; Tue, 14 Sep 2021 05:39:58 +0000 Received: from DRHQMAIL107.nvidia.com (10.27.9.16) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 14 Sep 2021 05:39:57 +0000 Received: from nvidia.com (172.20.187.6) by DRHQMAIL107.nvidia.com (10.27.9.16) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 14 Sep 2021 05:39:54 +0000 From: Tal Shnaiderman To: CC: , , , , , , , Date: Tue, 14 Sep 2021 08:38:25 +0300 Message-ID: <20210914053833.7760-3-talshn@nvidia.com> X-Mailer: git-send-email 2.16.1.windows.4 In-Reply-To: <20210914053833.7760-1-talshn@nvidia.com> References: <20210914053833.7760-1-talshn@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL111.nvidia.com (172.20.187.18) To DRHQMAIL107.nvidia.com (10.27.9.16) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 340c7b75-e2cf-45f5-baa2-08d9774216bb X-MS-TrafficTypeDiagnostic: BN6PR1201MB0100: X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:8273; 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CAT:NONE; SFS:(4636009)(46966006)(36840700001)(7696005)(2906002)(83380400001)(36860700001)(54906003)(86362001)(8676002)(6916009)(55016002)(16526019)(186003)(26005)(6286002)(426003)(107886003)(70586007)(70206006)(336012)(1076003)(2616005)(82310400003)(508600001)(8936002)(4326008)(6666004)(36906005)(356005)(5660300002)(316002)(7636003)(47076005)(36756003); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Sep 2021 05:39:58.1055 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 340c7b75-e2cf-45f5-baa2-08d9774216bb X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.36]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT026.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR1201MB0100 Subject: [dpdk-dev] [RFC PATCH 02/10] common/mlx5: add an agnostic OS function to open device context X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add a function to open device context from a rte_device. Function mlx5_os_open_device_context can be used both on Windows and Linux OS. Signed-off-by: Tal Shnaiderman --- drivers/common/mlx5/linux/mlx5_common_os.c | 28 +++++++ drivers/common/mlx5/mlx5_common.h | 4 + drivers/common/mlx5/version.map | 2 + drivers/common/mlx5/windows/mlx5_common_os.c | 118 +++++++++++++++++++++++++++ drivers/common/mlx5/windows/mlx5_common_os.h | 2 + drivers/net/mlx5/windows/mlx5_os.c | 64 +-------------- 6 files changed, 155 insertions(+), 63 deletions(-) diff --git a/drivers/common/mlx5/linux/mlx5_common_os.c b/drivers/common/mlx5/linux/mlx5_common_os.c index 9e0c823c97..3ef507944f 100644 --- a/drivers/common/mlx5/linux/mlx5_common_os.c +++ b/drivers/common/mlx5/linux/mlx5_common_os.c @@ -428,3 +428,31 @@ mlx5_os_get_ibv_device(const struct rte_pci_addr *addr) mlx5_glue->free_device_list(ibv_list); return ibv_match; } + +/** + * Open device context from a rte_device. + * + * @param[in] dev + * Pointer to an rte_device struct. + * @return + * Pointer to device context or NULL in case context cannot be found. + */ +void * +mlx5_os_open_device_context(struct rte_device *dev) +{ + struct ibv_device *ibv; + void *ctx; + + ibv = mlx5_os_get_ibv_dev(dev); + if (ibv == NULL) { + DRV_LOG(ERR, "Failed getting ibv_dev"); + return NULL; + } + ctx = mlx5_glue->dv_open_device(ibv); + if (ctx == NULL) { + DRV_LOG(ERR, "Failed to open IB device \"%s\".", ibv->name); + rte_errno = ENODEV; + return NULL; + } + return ctx; +} diff --git a/drivers/common/mlx5/mlx5_common.h b/drivers/common/mlx5/mlx5_common.h index a772371200..249804b00c 100644 --- a/drivers/common/mlx5/mlx5_common.h +++ b/drivers/common/mlx5/mlx5_common.h @@ -419,4 +419,8 @@ __rte_internal bool mlx5_dev_is_pci(const struct rte_device *dev); +__rte_internal +void * +mlx5_os_open_device_context(struct rte_device *dev); + #endif /* RTE_PMD_MLX5_COMMON_H_ */ diff --git a/drivers/common/mlx5/version.map b/drivers/common/mlx5/version.map index e5cb6b7060..6d4258dd25 100644 --- a/drivers/common/mlx5/version.map +++ b/drivers/common/mlx5/version.map @@ -141,6 +141,8 @@ INTERNAL { mlx5_os_alloc_pd; mlx5_os_dealloc_pd; mlx5_os_dereg_mr; + mlx5_os_match_devx_devices_to_addr; + mlx5_os_open_device_context; mlx5_os_get_ibv_dev; # WINDOWS_NO_EXPORT mlx5_os_reg_mr; mlx5_os_umem_dereg; diff --git a/drivers/common/mlx5/windows/mlx5_common_os.c b/drivers/common/mlx5/windows/mlx5_common_os.c index 5031bdca26..3b59e57e57 100644 --- a/drivers/common/mlx5/windows/mlx5_common_os.c +++ b/drivers/common/mlx5/windows/mlx5_common_os.c @@ -6,6 +6,7 @@ #include #include +#include #include #include #include @@ -205,3 +206,120 @@ mlx5_os_dereg_mr(struct mlx5_pmd_mr *pmd_mr) claim_zero(mlx5_os_umem_dereg(pmd_mr->obj)); memset(pmd_mr, 0, sizeof(*pmd_mr)); } + +/** + * Detect if a devx_device_bdf object has identical DBDF values to the + * rte_pci_addr found in bus/pci probing + * + * @param[in] devx_bdf + * Pointer to the devx_device_bdf structure. + * @param[in] addr + * Pointer to the rte_pci_addr structure. + * + * @return + * 1 on Device match, 0 on mismatch. + */ +static int +mlx5_os_match_devx_bdf_to_addr(struct devx_device_bdf *devx_bdf, + struct rte_pci_addr *addr) +{ + if (addr->domain != (devx_bdf->bus_id >> 8) || + addr->bus != (devx_bdf->bus_id & 0xff) || + addr->devid != devx_bdf->dev_id || + addr->function != devx_bdf->fnc_id) { + return 0; + } + return 1; +} + +/** + * Detect if a devx_device_bdf object matches the rte_pci_addr + * found in bus/pci probing + * Compare both the Native/PF BDF and the raw_bdf representing a VF BDF. + * + * @param[in] devx_bdf + * Pointer to the devx_device_bdf structure. + * @param[in] addr + * Pointer to the rte_pci_addr structure. + * + * @return + * 1 on Device match, 0 on mismatch, rte_errno code on failure. + */ +int +mlx5_os_match_devx_devices_to_addr(struct devx_device_bdf *devx_bdf, + struct rte_pci_addr *addr) +{ + int err; + struct devx_device mlx5_dev; + + if (mlx5_os_match_devx_bdf_to_addr(devx_bdf, addr)) + return 1; + /** + * Didn't match on Native/PF BDF, could still + * Match a VF BDF, check it next + */ + err = mlx5_glue->query_device(devx_bdf, &mlx5_dev); + if (err) { + DRV_LOG(ERR, "query_device failed"); + rte_errno = err; + return rte_errno; + } + if (mlx5_os_match_devx_bdf_to_addr(&mlx5_dev.raw_bdf, addr)) + return 1; + return 0; +} + +/** + * Open device context from a rte_device. + * + * @param[in] dev + * Pointer to an rte_device struct. + * @return + * Pointer to device context or NULL in case context cannot be found. + */ +void * +mlx5_os_open_device_context(struct rte_device *dev) +{ + struct devx_device_bdf *devx_bdf_devs, *orig_devx_bdf_devs; + struct mlx5_context *devx_ctx_match = NULL; + int ret, err; + struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev); + + devx_bdf_devs = mlx5_glue->get_device_list(&ret); + orig_devx_bdf_devs = devx_bdf_devs; + if (!devx_bdf_devs) { + rte_errno = errno ? errno : ENOSYS; + DRV_LOG(ERR, "cannot list devices, is DevX configured?"); + return NULL; + } + while (ret-- > 0) { + err = mlx5_os_match_devx_devices_to_addr(devx_bdf_devs, + &pci_dev->addr); + if (err == 1) { + devx_ctx_match = mlx5_glue->open_device(devx_bdf_devs); + if (!devx_ctx_match) { + DRV_LOG(ERR, "open_device failed"); + err = errno; + goto exit; + } + err = mlx5_glue->query_device(devx_bdf_devs, + &devx_ctx_match->mlx5_dev); + if (err) { + DRV_LOG(ERR, "query device context failed."); + rte_errno = errno ? errno : ENOSYS; + claim_zero(mlx5_glue->close_device( + devx_ctx_match)); + goto exit; + } + } + if (err != 0) { + DRV_LOG(ERR, "failed to match addr to rte_device"); + ret = -err; + goto exit; + } + devx_bdf_devs++; + } +exit: + mlx5_glue->free_device_list(orig_devx_bdf_devs); + return devx_ctx_match; +} diff --git a/drivers/common/mlx5/windows/mlx5_common_os.h b/drivers/common/mlx5/windows/mlx5_common_os.h index 3756e1959b..c3d74d3b67 100644 --- a/drivers/common/mlx5/windows/mlx5_common_os.h +++ b/drivers/common/mlx5/windows/mlx5_common_os.h @@ -261,4 +261,6 @@ int mlx5_os_reg_mr(void *pd, void *addr, size_t length, struct mlx5_pmd_mr *pmd_mr); __rte_internal void mlx5_os_dereg_mr(struct mlx5_pmd_mr *pmd_mr); +int mlx5_os_match_devx_devices_to_addr(struct devx_device_bdf *devx_bdf, + struct rte_pci_addr *addr); #endif /* RTE_PMD_MLX5_COMMON_OS_H_ */ diff --git a/drivers/net/mlx5/windows/mlx5_os.c b/drivers/net/mlx5/windows/mlx5_os.c index 26fa927039..9dea6d639e 100644 --- a/drivers/net/mlx5/windows/mlx5_os.c +++ b/drivers/net/mlx5/windows/mlx5_os.c @@ -901,68 +901,6 @@ mlx5_os_set_allmulti(struct rte_eth_dev *dev, int enable) return -ENOTSUP; } -/** - * Detect if a devx_device_bdf object has identical DBDF values to the - * rte_pci_addr found in bus/pci probing - * - * @param[in] devx_bdf - * Pointer to the devx_device_bdf structure. - * @param[in] addr - * Pointer to the rte_pci_addr structure. - * - * @return - * 1 on Device match, 0 on mismatch. - */ -static int -mlx5_match_devx_bdf_to_addr(struct devx_device_bdf *devx_bdf, - struct rte_pci_addr *addr) -{ - if (addr->domain != (devx_bdf->bus_id >> 8) || - addr->bus != (devx_bdf->bus_id & 0xff) || - addr->devid != devx_bdf->dev_id || - addr->function != devx_bdf->fnc_id) { - return 0; - } - return 1; -} - -/** - * Detect if a devx_device_bdf object matches the rte_pci_addr - * found in bus/pci probing - * Compare both the Native/PF BDF and the raw_bdf representing a VF BDF. - * - * @param[in] devx_bdf - * Pointer to the devx_device_bdf structure. - * @param[in] addr - * Pointer to the rte_pci_addr structure. - * - * @return - * 1 on Device match, 0 on mismatch, rte_errno code on failure. - */ -static int -mlx5_match_devx_devices_to_addr(struct devx_device_bdf *devx_bdf, - struct rte_pci_addr *addr) -{ - int err; - struct devx_device mlx5_dev; - - if (mlx5_match_devx_bdf_to_addr(devx_bdf, addr)) - return 1; - /** - * Didn't match on Native/PF BDF, could still - * Match a VF BDF, check it next - */ - err = mlx5_glue->query_device(devx_bdf, &mlx5_dev); - if (err) { - DRV_LOG(ERR, "query_device failed"); - rte_errno = err; - return rte_errno; - } - if (mlx5_match_devx_bdf_to_addr(&mlx5_dev.raw_bdf, addr)) - return 1; - return 0; -} - /** * DPDK callback to register a PCI device. * @@ -1036,7 +974,7 @@ mlx5_os_net_probe(struct rte_device *dev) struct devx_device_bdf *devx_bdf_match[ret + 1]; while (ret-- > 0) { - err = mlx5_match_devx_devices_to_addr(devx_bdf_devs, + err = mlx5_os_match_devx_devices_to_addr(devx_bdf_devs, &pci_dev->addr); if (!err) { devx_bdf_devs++; From patchwork Tue Sep 14 05:38:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tal Shnaiderman X-Patchwork-Id: 98827 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C1BE3A0C47; Tue, 14 Sep 2021 07:40:18 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0882F410F7; Tue, 14 Sep 2021 07:40:04 +0200 (CEST) Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2061.outbound.protection.outlook.com [40.107.244.61]) by mails.dpdk.org (Postfix) with ESMTP id 4081D410EB for ; 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CAT:NONE; SFS:(4636009)(136003)(376002)(396003)(346002)(39860400002)(36840700001)(46966006)(82310400003)(6666004)(36906005)(8676002)(83380400001)(426003)(2616005)(107886003)(356005)(186003)(6286002)(54906003)(16526019)(316002)(82740400003)(2906002)(336012)(7636003)(1076003)(8936002)(478600001)(26005)(4326008)(6916009)(55016002)(7696005)(5660300002)(70206006)(70586007)(36860700001)(86362001)(47076005)(36756003); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Sep 2021 05:40:00.4125 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b1e229d7-49bb-4e06-445c-08d977421816 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.35]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT013.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1754 Subject: [dpdk-dev] [RFC PATCH 03/10] common/mlx5: move pdn getter to common driver X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Move to common and export the function mlx5_os_get_pdn. Signed-off-by: Tal Shnaiderman --- drivers/common/mlx5/linux/mlx5_common_os.c | 35 ++++++++++++++++++++++++++++ drivers/common/mlx5/mlx5_common.h | 4 ++++ drivers/common/mlx5/version.map | 1 + drivers/common/mlx5/windows/mlx5_common_os.c | 21 +++++++++++++++++ drivers/net/mlx5/linux/mlx5_os.c | 35 ---------------------------- drivers/net/mlx5/mlx5.h | 1 - drivers/net/mlx5/windows/mlx5_os.c | 21 ----------------- 7 files changed, 61 insertions(+), 57 deletions(-) diff --git a/drivers/common/mlx5/linux/mlx5_common_os.c b/drivers/common/mlx5/linux/mlx5_common_os.c index 3ef507944f..4aada82669 100644 --- a/drivers/common/mlx5/linux/mlx5_common_os.c +++ b/drivers/common/mlx5/linux/mlx5_common_os.c @@ -456,3 +456,38 @@ mlx5_os_open_device_context(struct rte_device *dev) } return ctx; } + +/** + * Extract pdn of PD object using DV API. + * + * @param[in] pd + * Pointer to the verbs PD object. + * @param[out] pdn + * Pointer to the PD object number variable. + * + * @return + * 0 on success, error value otherwise. + */ +int +mlx5_os_get_pdn(void *pd, uint32_t *pdn) +{ +#ifdef HAVE_IBV_FLOW_DV_SUPPORT + struct mlx5dv_obj obj; + struct mlx5dv_pd pd_info; + int ret = 0; + + obj.pd.in = pd; + obj.pd.out = &pd_info; + ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_PD); + if (ret) { + DRV_LOG(DEBUG, "Fail to get PD object info"); + return ret; + } + *pdn = pd_info.pdn; + return 0; +#else + (void)pd; + (void)pdn; + return -ENOTSUP; +#endif /* HAVE_IBV_FLOW_DV_SUPPORT */ +} diff --git a/drivers/common/mlx5/mlx5_common.h b/drivers/common/mlx5/mlx5_common.h index 249804b00c..fcdf376193 100644 --- a/drivers/common/mlx5/mlx5_common.h +++ b/drivers/common/mlx5/mlx5_common.h @@ -423,4 +423,8 @@ __rte_internal void * mlx5_os_open_device_context(struct rte_device *dev); +__rte_internal +int +mlx5_os_get_pdn(void *pd, uint32_t *pdn); + #endif /* RTE_PMD_MLX5_COMMON_H_ */ diff --git a/drivers/common/mlx5/version.map b/drivers/common/mlx5/version.map index 6d4258dd25..c6de706fdb 100644 --- a/drivers/common/mlx5/version.map +++ b/drivers/common/mlx5/version.map @@ -144,6 +144,7 @@ INTERNAL { mlx5_os_match_devx_devices_to_addr; mlx5_os_open_device_context; mlx5_os_get_ibv_dev; # WINDOWS_NO_EXPORT + mlx5_os_get_pdn; mlx5_os_reg_mr; mlx5_os_umem_dereg; mlx5_os_umem_reg; diff --git a/drivers/common/mlx5/windows/mlx5_common_os.c b/drivers/common/mlx5/windows/mlx5_common_os.c index 3b59e57e57..5c9cccd3e9 100644 --- a/drivers/common/mlx5/windows/mlx5_common_os.c +++ b/drivers/common/mlx5/windows/mlx5_common_os.c @@ -323,3 +323,24 @@ mlx5_os_open_device_context(struct rte_device *dev) mlx5_glue->free_device_list(orig_devx_bdf_devs); return devx_ctx_match; } + +/** + * Extract pdn of PD object using DevX + * + * @param[in] pd + * Pointer to the DevX PD object. + * @param[out] pdn + * Pointer to the PD object number variable. + * + * @return + * 0 on success, error value otherwise. + */ +int +mlx5_os_get_pdn(void *pd, uint32_t *pdn) +{ + if (!pd) + return -EINVAL; + + *pdn = ((struct mlx5_pd *)pd)->pdn; + return 0; +} diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c index 470b16cb9a..a7df1ddb2e 100644 --- a/drivers/net/mlx5/linux/mlx5_os.c +++ b/drivers/net/mlx5/linux/mlx5_os.c @@ -2811,41 +2811,6 @@ mlx5_restore_doorbell_mapping_env(int value) setenv(MLX5_SHUT_UP_BF, value ? "1" : "0", 1); } -/** - * Extract pdn of PD object using DV API. - * - * @param[in] pd - * Pointer to the verbs PD object. - * @param[out] pdn - * Pointer to the PD object number variable. - * - * @return - * 0 on success, error value otherwise. - */ -int -mlx5_os_get_pdn(void *pd, uint32_t *pdn) -{ -#ifdef HAVE_IBV_FLOW_DV_SUPPORT - struct mlx5dv_obj obj; - struct mlx5dv_pd pd_info; - int ret = 0; - - obj.pd.in = pd; - obj.pd.out = &pd_info; - ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_PD); - if (ret) { - DRV_LOG(DEBUG, "Fail to get PD object info"); - return ret; - } - *pdn = pd_info.pdn; - return 0; -#else - (void)pd; - (void)pdn; - return -ENOTSUP; -#endif /* HAVE_IBV_FLOW_DV_SUPPORT */ -} - /** * Function API to open IB device. * diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index e02714e231..cb05929efe 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -1770,7 +1770,6 @@ void mlx5_os_free_shared_dr(struct mlx5_priv *priv); int mlx5_os_open_device(const struct mlx5_dev_spawn_data *spawn, const struct mlx5_dev_config *config, struct mlx5_dev_ctx_shared *sh); -int mlx5_os_get_pdn(void *pd, uint32_t *pdn); int mlx5_os_net_probe(struct rte_device *dev); void mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh); void mlx5_os_dev_shared_handler_uninstall(struct mlx5_dev_ctx_shared *sh); diff --git a/drivers/net/mlx5/windows/mlx5_os.c b/drivers/net/mlx5/windows/mlx5_os.c index 9dea6d639e..336b41d33b 100644 --- a/drivers/net/mlx5/windows/mlx5_os.c +++ b/drivers/net/mlx5/windows/mlx5_os.c @@ -1102,25 +1102,4 @@ mlx5_os_set_reg_mr_cb(mlx5_reg_mr_t *reg_mr_cb, *dereg_mr_cb = mlx5_os_dereg_mr; } -/** - * Extract pdn of PD object using DevX - * - * @param[in] pd - * Pointer to the DevX PD object. - * @param[out] pdn - * Pointer to the PD object number variable. - * - * @return - * 0 on success, error value otherwise. - */ -int -mlx5_os_get_pdn(void *pd, uint32_t *pdn) -{ - if (!pd) - return -EINVAL; - - *pdn = ((struct mlx5_pd *)pd)->pdn; - return 0; -} - const struct mlx5_flow_driver_ops mlx5_flow_verbs_drv_ops = {0}; From patchwork Tue Sep 14 05:38:27 2021 Content-Type: text/plain; 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monjalon.net; dkim=none (message not signed) header.d=none;monjalon.net; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.32 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.32; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.32) by DM6NAM11FT016.mail.protection.outlook.com (10.13.173.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4500.14 via Frontend Transport; Tue, 14 Sep 2021 05:40:04 +0000 Received: from DRHQMAIL107.nvidia.com (10.27.9.16) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Mon, 13 Sep 2021 22:40:02 -0700 Received: from nvidia.com (172.20.187.6) by DRHQMAIL107.nvidia.com (10.27.9.16) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 14 Sep 2021 05:40:00 +0000 From: Tal Shnaiderman To: CC: , , , , , , , Date: Tue, 14 Sep 2021 08:38:27 +0300 Message-ID: <20210914053833.7760-5-talshn@nvidia.com> X-Mailer: git-send-email 2.16.1.windows.4 In-Reply-To: <20210914053833.7760-1-talshn@nvidia.com> References: <20210914053833.7760-1-talshn@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL111.nvidia.com (172.20.187.18) To DRHQMAIL107.nvidia.com (10.27.9.16) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: ddc97aa1-3c53-4445-b482-08d977421a73 X-MS-TrafficTypeDiagnostic: BYAPR12MB3191: X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:6790; 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CAT:NONE; SFS:(4636009)(36840700001)(46966006)(8676002)(6666004)(356005)(82310400003)(54906003)(336012)(4326008)(426003)(8936002)(7636003)(5660300002)(16526019)(186003)(47076005)(6286002)(508600001)(83380400001)(55016002)(316002)(26005)(6916009)(2906002)(70586007)(70206006)(2616005)(1076003)(7696005)(107886003)(36756003)(86362001)(36860700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Sep 2021 05:40:04.2124 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ddc97aa1-3c53-4445-b482-08d977421a73 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.32]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT016.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR12MB3191 Subject: [dpdk-dev] [RFC PATCH 04/10] common/mlx5: add memory region OS agnostic functions for Linux X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The OS agnostic functions for memory region registration/deregistration (mlx5_os_reg_mr mlx5_os_dereg_mr) exist only for Windows OS. Adding them for Linux as well as they are needed for memory region activities in shared code. Signed-off-by: Tal Shnaiderman --- drivers/common/mlx5/linux/mlx5_common_os.c | 35 ++++++++++++++++++++++++++++ drivers/common/mlx5/mlx5_common.h | 9 +++++++ drivers/common/mlx5/windows/mlx5_common_os.c | 2 +- drivers/common/mlx5/windows/mlx5_common_os.h | 6 ----- 4 files changed, 45 insertions(+), 7 deletions(-) diff --git a/drivers/common/mlx5/linux/mlx5_common_os.c b/drivers/common/mlx5/linux/mlx5_common_os.c index 4aada82669..fd0ec6b748 100644 --- a/drivers/common/mlx5/linux/mlx5_common_os.c +++ b/drivers/common/mlx5/linux/mlx5_common_os.c @@ -491,3 +491,38 @@ mlx5_os_get_pdn(void *pd, uint32_t *pdn) return -ENOTSUP; #endif /* HAVE_IBV_FLOW_DV_SUPPORT */ } + +/** + * Register mr. Given protection domain pointer, pointer to addr and length + * register the memory region. + * + * @param[in] pd + * Pointer to protection domain context (type mlx5_pd). + * @param[in] addr + * Pointer to memory start address (type devx_device_ctx). + * @param[in] length + * Lengtoh of the memory to register. + * @param[out] pmd_mr + * pmd_mr struct set with lkey, address, length, pointer to mr object, mkey + * + * @return + * 0 on successful registration, -1 otherwise + */ +int +mlx5_os_reg_mr(void *pd, + void *addr, size_t length, struct mlx5_pmd_mr *pmd_mr) +{ + return mlx5_common_verbs_reg_mr(pd, addr, length, pmd_mr); +} + +/** + * De-register mr. + * + * @param[in] pmd_mr + * Pointer to PMD mr object + */ +void +mlx5_os_dereg_mr(struct mlx5_pmd_mr *pmd_mr) +{ + mlx5_common_verbs_dereg_mr(pmd_mr); +} diff --git a/drivers/common/mlx5/mlx5_common.h b/drivers/common/mlx5/mlx5_common.h index fcdf376193..a87318db91 100644 --- a/drivers/common/mlx5/mlx5_common.h +++ b/drivers/common/mlx5/mlx5_common.h @@ -21,6 +21,7 @@ #include "mlx5_prm.h" #include "mlx5_devx_cmds.h" +#include "mlx5_common_mr.h" #include "mlx5_common_os.h" /* Reported driver name. */ @@ -427,4 +428,12 @@ __rte_internal int mlx5_os_get_pdn(void *pd, uint32_t *pdn); +__rte_internal +int +mlx5_os_reg_mr(void *pd, + void *addr, size_t length, struct mlx5_pmd_mr *pmd_mr); +__rte_internal +void +mlx5_os_dereg_mr(struct mlx5_pmd_mr *pmd_mr); + #endif /* RTE_PMD_MLX5_COMMON_H_ */ diff --git a/drivers/common/mlx5/windows/mlx5_common_os.c b/drivers/common/mlx5/windows/mlx5_common_os.c index 5c9cccd3e9..2ecdf78310 100644 --- a/drivers/common/mlx5/windows/mlx5_common_os.c +++ b/drivers/common/mlx5/windows/mlx5_common_os.c @@ -134,7 +134,7 @@ mlx5_os_umem_dereg(void *pumem) } /** - * Register mr. Given protection doamin pointer, pointer to addr and length + * Register mr. Given protection domain pointer, pointer to addr and length * register the memory region. * * @param[in] pd diff --git a/drivers/common/mlx5/windows/mlx5_common_os.h b/drivers/common/mlx5/windows/mlx5_common_os.h index c3d74d3b67..62bdcb40cd 100644 --- a/drivers/common/mlx5/windows/mlx5_common_os.h +++ b/drivers/common/mlx5/windows/mlx5_common_os.h @@ -13,7 +13,6 @@ #include "mlx5_autoconf.h" #include "mlx5_glue.h" #include "mlx5_malloc.h" -#include "mlx5_common_mr.h" #include "mlx5_win_ext.h" #define MLX5_BF_OFFSET 0x800 @@ -256,11 +255,6 @@ __rte_internal void *mlx5_os_umem_reg(void *ctx, void *addr, size_t size, uint32_t access); __rte_internal int mlx5_os_umem_dereg(void *pumem); -__rte_internal -int mlx5_os_reg_mr(void *pd, - void *addr, size_t length, struct mlx5_pmd_mr *pmd_mr); -__rte_internal -void mlx5_os_dereg_mr(struct mlx5_pmd_mr *pmd_mr); int mlx5_os_match_devx_devices_to_addr(struct devx_device_bdf *devx_bdf, struct rte_pci_addr *addr); #endif /* RTE_PMD_MLX5_COMMON_OS_H_ */ From patchwork Tue Sep 14 05:38:28 2021 Content-Type: text/plain; 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monjalon.net; dkim=none (message not signed) header.d=none;monjalon.net; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by DM6NAM11FT056.mail.protection.outlook.com (10.13.173.99) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4500.14 via Frontend Transport; Tue, 14 Sep 2021 05:40:05 +0000 Received: from DRHQMAIL107.nvidia.com (10.27.9.16) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 14 Sep 2021 05:40:05 +0000 Received: from nvidia.com (172.20.187.6) by DRHQMAIL107.nvidia.com (10.27.9.16) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 14 Sep 2021 05:40:02 +0000 From: Tal Shnaiderman To: CC: , , , , , , , Date: Tue, 14 Sep 2021 08:38:28 +0300 Message-ID: <20210914053833.7760-6-talshn@nvidia.com> X-Mailer: git-send-email 2.16.1.windows.4 In-Reply-To: <20210914053833.7760-1-talshn@nvidia.com> References: <20210914053833.7760-1-talshn@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL111.nvidia.com (172.20.187.18) To DRHQMAIL107.nvidia.com (10.27.9.16) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: bd1f6933-e2eb-42d7-101e-08d977421b49 X-MS-TrafficTypeDiagnostic: PH0PR12MB5402: X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:5797; 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CAT:NONE; SFS:(4636009)(46966006)(36840700001)(36860700001)(6916009)(86362001)(54906003)(47076005)(508600001)(2616005)(107886003)(83380400001)(70206006)(5660300002)(1076003)(336012)(70586007)(26005)(186003)(16526019)(426003)(7696005)(55016002)(8676002)(6286002)(316002)(36756003)(36906005)(8936002)(82310400003)(7636003)(6666004)(2906002)(356005)(4326008); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Sep 2021 05:40:05.7796 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bd1f6933-e2eb-42d7-101e-08d977421b49 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT056.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB5402 Subject: [dpdk-dev] [RFC PATCH 05/10] crypto/mlx5: replace UNIX functions with EAL functions X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Use the OS agnostic EAL function rte_mem_page_size to get page size value instead of the Linux specific implementation. Also remove the usage of PTHREAD_MUTEX_INITIALIZER which is not support in Windows and initialize priv_list_lock in RTE_INIT. Signed-off-by: Tal Shnaiderman --- drivers/crypto/mlx5/mlx5_crypto.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/crypto/mlx5/mlx5_crypto.c b/drivers/crypto/mlx5/mlx5_crypto.c index b3d5200ca3..3dac69f860 100644 --- a/drivers/crypto/mlx5/mlx5_crypto.c +++ b/drivers/crypto/mlx5/mlx5_crypto.c @@ -4,6 +4,7 @@ #include #include +#include #include #include #include @@ -33,7 +34,7 @@ TAILQ_HEAD(mlx5_crypto_privs, mlx5_crypto_priv) mlx5_crypto_priv_list = TAILQ_HEAD_INITIALIZER(mlx5_crypto_priv_list); -static pthread_mutex_t priv_list_lock = PTHREAD_MUTEX_INITIALIZER; +static pthread_mutex_t priv_list_lock; int mlx5_crypto_logtype; @@ -700,7 +701,7 @@ mlx5_crypto_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id, attr.pd = priv->pdn; attr.uar_index = mlx5_os_get_devx_uar_page_id(priv->uar); attr.cqn = qp->cq_obj.cq->id; - attr.log_page_size = rte_log2_u32(sysconf(_SC_PAGESIZE)); + attr.log_page_size = rte_log2_u32(rte_mem_page_size()); attr.rq_size = 0; attr.sq_size = RTE_BIT32(log_nb_desc); attr.dbr_umem_valid = 1; @@ -1134,6 +1135,7 @@ static struct mlx5_class_driver mlx5_crypto_driver = { RTE_INIT(rte_mlx5_crypto_init) { + pthread_mutex_init(&priv_list_lock, NULL); mlx5_common_init(); if (mlx5_glue != NULL) mlx5_class_driver_register(&mlx5_crypto_driver); From patchwork Tue Sep 14 05:38:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tal Shnaiderman X-Patchwork-Id: 98830 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 344CCA0C47; Tue, 14 Sep 2021 07:40:40 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1031741121; Tue, 14 Sep 2021 07:40:14 +0200 (CEST) Received: from NAM04-MW2-obe.outbound.protection.outlook.com (mail-mw2nam08on2043.outbound.protection.outlook.com [40.107.101.43]) by mails.dpdk.org (Postfix) with ESMTP id D85AF41130 for ; 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Tue, 14 Sep 2021 05:40:09 +0000 Received: from DRHQMAIL107.nvidia.com (10.27.9.16) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 14 Sep 2021 05:40:08 +0000 Received: from nvidia.com (172.20.187.6) by DRHQMAIL107.nvidia.com (10.27.9.16) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 14 Sep 2021 05:40:05 +0000 From: Tal Shnaiderman To: CC: , , , , , , , Date: Tue, 14 Sep 2021 08:38:29 +0300 Message-ID: <20210914053833.7760-7-talshn@nvidia.com> X-Mailer: git-send-email 2.16.1.windows.4 In-Reply-To: <20210914053833.7760-1-talshn@nvidia.com> References: <20210914053833.7760-1-talshn@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL111.nvidia.com (172.20.187.18) To DRHQMAIL107.nvidia.com (10.27.9.16) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: a890622a-35d6-4ed5-e848-08d977421da2 X-MS-TrafficTypeDiagnostic: BN6PR1201MB0148: X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:635; 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CAT:NONE; SFS:(4636009)(376002)(346002)(39860400002)(136003)(396003)(46966006)(36840700001)(6666004)(70206006)(70586007)(5660300002)(47076005)(26005)(16526019)(36860700001)(4326008)(186003)(8676002)(55016002)(356005)(86362001)(107886003)(82310400003)(478600001)(8936002)(7636003)(6916009)(2616005)(426003)(336012)(82740400003)(6286002)(83380400001)(36756003)(1076003)(36906005)(7696005)(54906003)(316002)(2906002); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Sep 2021 05:40:09.7208 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a890622a-35d6-4ed5-e848-08d977421da2 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.36]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT051.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR1201MB0148 Subject: [dpdk-dev] [RFC PATCH 06/10] crypto/mlx5: use OS agnostic functions for UMEM operations X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" use the functions mlx5_os_umem_reg, mlx5_os_umem_dereg mlx5_os_get_umem_id instead of the glue functions to support UMEM operations on all OSs. Signed-off-by: Tal Shnaiderman --- drivers/crypto/mlx5/mlx5_crypto.c | 14 +++++++------- drivers/crypto/mlx5/mlx5_crypto.h | 2 +- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/crypto/mlx5/mlx5_crypto.c b/drivers/crypto/mlx5/mlx5_crypto.c index 3dac69f860..ccae113770 100644 --- a/drivers/crypto/mlx5/mlx5_crypto.c +++ b/drivers/crypto/mlx5/mlx5_crypto.c @@ -261,7 +261,7 @@ mlx5_crypto_queue_pair_release(struct rte_cryptodev *dev, uint16_t qp_id) if (qp->qp_obj != NULL) claim_zero(mlx5_devx_cmd_destroy(qp->qp_obj)); if (qp->umem_obj != NULL) - claim_zero(mlx5_glue->devx_umem_dereg(qp->umem_obj)); + claim_zero(mlx5_os_umem_dereg(qp->umem_obj)); if (qp->umem_buf != NULL) rte_free(qp->umem_buf); mlx5_mr_btree_free(&qp->mr_ctrl.cache_bh); @@ -682,10 +682,10 @@ mlx5_crypto_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id, rte_errno = ENOMEM; goto error; } - qp->umem_obj = mlx5_glue->devx_umem_reg(priv->ctx, - (void *)(uintptr_t)qp->umem_buf, - umem_size, - IBV_ACCESS_LOCAL_WRITE); + qp->umem_obj = mlx5_os_umem_reg(priv->ctx, + (void *)(uintptr_t)qp->umem_buf, + umem_size, + IBV_ACCESS_LOCAL_WRITE); if (qp->umem_obj == NULL) { DRV_LOG(ERR, "Failed to register QP umem."); goto error; @@ -705,9 +705,9 @@ mlx5_crypto_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id, attr.rq_size = 0; attr.sq_size = RTE_BIT32(log_nb_desc); attr.dbr_umem_valid = 1; - attr.wq_umem_id = qp->umem_obj->umem_id; + attr.wq_umem_id = mlx5_os_get_umem_id(qp->umem_obj); attr.wq_umem_offset = 0; - attr.dbr_umem_id = qp->umem_obj->umem_id; + attr.dbr_umem_id = mlx5_os_get_umem_id(qp->umem_obj); attr.dbr_address = RTE_BIT64(log_nb_desc) * priv->wqe_set_size; qp->qp_obj = mlx5_devx_cmd_create_qp(priv->ctx, &attr); if (qp->qp_obj == NULL) { diff --git a/drivers/crypto/mlx5/mlx5_crypto.h b/drivers/crypto/mlx5/mlx5_crypto.h index d49b0001f0..d5cc509e42 100644 --- a/drivers/crypto/mlx5/mlx5_crypto.h +++ b/drivers/crypto/mlx5/mlx5_crypto.h @@ -45,7 +45,7 @@ struct mlx5_crypto_qp { struct mlx5_devx_cq cq_obj; struct mlx5_devx_obj *qp_obj; struct rte_cryptodev_stats stats; - struct mlx5dv_devx_umem *umem_obj; + void *umem_obj; void *umem_buf; volatile uint32_t *db_rec; struct rte_crypto_op **ops; From patchwork Tue Sep 14 05:38:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tal Shnaiderman X-Patchwork-Id: 98831 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 91F4BA0C47; Tue, 14 Sep 2021 07:40:45 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2F3A441124; Tue, 14 Sep 2021 07:40:16 +0200 (CEST) Received: from NAM11-BN8-obe.outbound.protection.outlook.com (mail-bn8nam11on2064.outbound.protection.outlook.com [40.107.236.64]) by mails.dpdk.org (Postfix) with ESMTP id A251E41137 for ; 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CAT:NONE; SFS:(4636009)(46966006)(36840700001)(2906002)(8676002)(7696005)(82310400003)(4326008)(7636003)(6666004)(508600001)(336012)(426003)(6286002)(54906003)(36860700001)(316002)(47076005)(55016002)(36906005)(70206006)(83380400001)(2616005)(8936002)(1076003)(86362001)(356005)(26005)(16526019)(5660300002)(186003)(36756003)(6916009)(70586007)(107886003); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Sep 2021 05:40:11.0874 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d771d7ed-9b1c-47e1-9a71-08d977421e71 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.35]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT026.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB3865 Subject: [dpdk-dev] [RFC PATCH 07/10] crypto/mlx5: use OS agnostic functions for PD operations X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" use the functions mlx5_os_alloc_pd, mlx5_os_dealloc_pd mlx5_os_get_pdn instead of the glue functions to support PD operations on all OSs. Signed-off-by: Tal Shnaiderman --- drivers/crypto/mlx5/mlx5_crypto.c | 15 ++++++--------- drivers/crypto/mlx5/mlx5_crypto.h | 2 +- 2 files changed, 7 insertions(+), 10 deletions(-) diff --git a/drivers/crypto/mlx5/mlx5_crypto.c b/drivers/crypto/mlx5/mlx5_crypto.c index ccae113770..35319d0115 100644 --- a/drivers/crypto/mlx5/mlx5_crypto.c +++ b/drivers/crypto/mlx5/mlx5_crypto.c @@ -784,7 +784,7 @@ static void mlx5_crypto_hw_global_release(struct mlx5_crypto_priv *priv) { if (priv->pd != NULL) { - claim_zero(mlx5_glue->dealloc_pd(priv->pd)); + claim_zero(mlx5_os_dealloc_pd(priv->pd)); priv->pd = NULL; } if (priv->uar != NULL) { @@ -801,21 +801,18 @@ mlx5_crypto_pd_create(struct mlx5_crypto_priv *priv) struct mlx5dv_pd pd_info; int ret; - priv->pd = mlx5_glue->alloc_pd(priv->ctx); + priv->pd = mlx5_os_alloc_pd(priv->ctx); if (priv->pd == NULL) { DRV_LOG(ERR, "Failed to allocate PD."); return errno ? -errno : -ENOMEM; } - obj.pd.in = priv->pd; - obj.pd.out = &pd_info; - ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_PD); + ret = mlx5_os_get_pdn(priv->pd, &priv->pdn); if (ret != 0) { - DRV_LOG(ERR, "Fail to get PD object info."); - mlx5_glue->dealloc_pd(priv->pd); + DRV_LOG(ERR, "Fail to get PDN."); + mlx5_os_dealloc_pd(priv->pd); priv->pd = NULL; return -errno; } - priv->pdn = pd_info.pdn; return 0; #else (void)priv; @@ -834,7 +831,7 @@ mlx5_crypto_hw_global_prepare(struct mlx5_crypto_priv *priv) priv->uar_addr = mlx5_os_get_devx_uar_reg_addr(priv->uar); if (priv->uar == NULL || priv->uar_addr == NULL) { rte_errno = errno; - claim_zero(mlx5_glue->dealloc_pd(priv->pd)); + claim_zero(mlx5_os_dealloc_pd(priv->pd)); DRV_LOG(ERR, "Failed to allocate UAR."); return -1; } diff --git a/drivers/crypto/mlx5/mlx5_crypto.h b/drivers/crypto/mlx5/mlx5_crypto.h index d5cc509e42..91e3f438b8 100644 --- a/drivers/crypto/mlx5/mlx5_crypto.h +++ b/drivers/crypto/mlx5/mlx5_crypto.h @@ -25,7 +25,7 @@ struct mlx5_crypto_priv { volatile uint64_t *uar_addr; uint32_t pdn; /* Protection Domain number. */ uint32_t max_segs_num; /* Maximum supported data segs. */ - struct ibv_pd *pd; + void *pd; struct mlx5_hlist *dek_hlist; /* Dek hash list. */ struct rte_cryptodev_config dev_config; struct mlx5_mr_share_cache mr_scache; /* Global shared MR cache. */ From patchwork Tue Sep 14 05:38:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tal Shnaiderman X-Patchwork-Id: 98832 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3A6B6A0C47; Tue, 14 Sep 2021 07:40:51 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1EB5C4113C; Tue, 14 Sep 2021 07:40:18 +0200 (CEST) Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2042.outbound.protection.outlook.com [40.107.94.42]) by mails.dpdk.org (Postfix) with ESMTP id 859A341124 for ; Tue, 14 Sep 2021 07:40:15 +0200 (CEST) ARC-Seal: i=1; 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Tue, 14 Sep 2021 05:40:13 +0000 Received: from DRHQMAIL107.nvidia.com (10.27.9.16) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Mon, 13 Sep 2021 22:40:13 -0700 Received: from nvidia.com (172.20.187.6) by DRHQMAIL107.nvidia.com (10.27.9.16) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 14 Sep 2021 05:40:10 +0000 From: Tal Shnaiderman To: CC: , , , , , , , Date: Tue, 14 Sep 2021 08:38:31 +0300 Message-ID: <20210914053833.7760-9-talshn@nvidia.com> X-Mailer: git-send-email 2.16.1.windows.4 In-Reply-To: <20210914053833.7760-1-talshn@nvidia.com> References: <20210914053833.7760-1-talshn@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL111.nvidia.com (172.20.187.18) To DRHQMAIL107.nvidia.com (10.27.9.16) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: abaf2a6e-676e-4c14-842a-08d977421fe7 X-MS-TrafficTypeDiagnostic: CH2PR12MB4921: X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1107; 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CAT:NONE; SFS:(4636009)(136003)(39860400002)(396003)(346002)(376002)(46966006)(36840700001)(47076005)(5660300002)(2616005)(4326008)(86362001)(8676002)(70586007)(2906002)(186003)(1076003)(82310400003)(16526019)(26005)(36756003)(356005)(8936002)(83380400001)(70206006)(82740400003)(316002)(54906003)(55016002)(7696005)(36860700001)(426003)(107886003)(6916009)(6286002)(336012)(6666004)(7636003)(478600001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Sep 2021 05:40:13.5309 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: abaf2a6e-676e-4c14-842a-08d977421fe7 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.32]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT019.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4921 Subject: [dpdk-dev] [RFC PATCH 08/10] crypto/mlx5: use OS agnostic functions for Verbs operations X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" use the functions mlx5_os_open_device_context, mlx5_os_get_ctx_device_name mlx5_os_reg_mr mlx5_os_dereg_mr instead of the ib verbs functions and variables to support device operations on all OSs. Signed-off-by: Tal Shnaiderman --- drivers/crypto/mlx5/mlx5_crypto.c | 41 +++++++++++++++++---------------------- drivers/crypto/mlx5/mlx5_crypto.h | 2 +- 2 files changed, 19 insertions(+), 24 deletions(-) diff --git a/drivers/crypto/mlx5/mlx5_crypto.c b/drivers/crypto/mlx5/mlx5_crypto.c index 35319d0115..3f5a6745dc 100644 --- a/drivers/crypto/mlx5/mlx5_crypto.c +++ b/drivers/crypto/mlx5/mlx5_crypto.c @@ -796,9 +796,6 @@ mlx5_crypto_hw_global_release(struct mlx5_crypto_priv *priv) static int mlx5_crypto_pd_create(struct mlx5_crypto_priv *priv) { -#ifdef HAVE_IBV_FLOW_DV_SUPPORT - struct mlx5dv_obj obj; - struct mlx5dv_pd pd_info; int ret; priv->pd = mlx5_os_alloc_pd(priv->ctx); @@ -814,11 +811,6 @@ mlx5_crypto_pd_create(struct mlx5_crypto_priv *priv) return -errno; } return 0; -#else - (void)priv; - DRV_LOG(ERR, "Cannot get pdn - no DV support."); - return -ENOTSUP; -#endif /* HAVE_IBV_FLOW_DV_SUPPORT */ } static int @@ -964,8 +956,8 @@ mlx5_crypto_mr_mem_event_cb(enum rte_mem_event event_type, const void *addr, /* Iterate all the existing mlx5 devices. */ TAILQ_FOREACH(priv, &mlx5_crypto_priv_list, next) mlx5_free_mr_by_addr(&priv->mr_scache, - priv->ctx->device->name, - addr, len); + mlx5_os_get_ctx_device_name( + priv->ctx), addr, len); pthread_mutex_unlock(&priv_list_lock); break; case RTE_MEM_EVENT_ALLOC: @@ -977,9 +969,9 @@ mlx5_crypto_mr_mem_event_cb(enum rte_mem_event event_type, const void *addr, static int mlx5_crypto_dev_probe(struct rte_device *dev) { - struct ibv_device *ibv; struct rte_cryptodev *crypto_dev; - struct ibv_context *ctx; + void *ctx; + const char *device_name; struct mlx5_devx_obj *login; struct mlx5_crypto_priv *priv; struct mlx5_crypto_devarg_params devarg_prms = { 0 }; @@ -999,15 +991,19 @@ mlx5_crypto_dev_probe(struct rte_device *dev) rte_errno = ENOTSUP; return -rte_errno; } - ibv = mlx5_os_get_ibv_dev(dev); - if (ibv == NULL) - return -rte_errno; - ctx = mlx5_glue->dv_open_device(ibv); + ctx = mlx5_os_open_device_context(dev); if (ctx == NULL) { - DRV_LOG(ERR, "Failed to open IB device \"%s\".", ibv->name); + DRV_LOG(ERR, "Failed to open IB device."); rte_errno = ENODEV; return -rte_errno; } + device_name = mlx5_os_get_ctx_device_name(ctx); + if (!device_name) { + DRV_LOG(ERR, "Failed getting device name"); + claim_zero(mlx5_glue->close_device(ctx)); + rte_errno = ENODEV; + return -ENODEV; + } if (mlx5_devx_cmd_query_hca_attr(ctx, &attr) != 0 || attr.crypto == 0 || attr.aes_xts == 0) { DRV_LOG(ERR, "Not enough capabilities to support crypto " @@ -1029,15 +1025,14 @@ mlx5_crypto_dev_probe(struct rte_device *dev) claim_zero(mlx5_glue->close_device(ctx)); return -rte_errno; } - crypto_dev = rte_cryptodev_pmd_create(ibv->name, dev, - &init_params); + crypto_dev = rte_cryptodev_pmd_create(device_name, dev, &init_params); if (crypto_dev == NULL) { - DRV_LOG(ERR, "Failed to create device \"%s\".", ibv->name); + DRV_LOG(ERR, "Failed to create device \"%s\".", device_name); claim_zero(mlx5_glue->close_device(ctx)); return -ENODEV; } DRV_LOG(INFO, - "Crypto device %s was created successfully.", ibv->name); + "Crypto device %s was created successfully.", device_name); crypto_dev->dev_ops = &mlx5_crypto_ops; crypto_dev->dequeue_burst = mlx5_crypto_dequeue_burst; crypto_dev->enqueue_burst = mlx5_crypto_enqueue_burst; @@ -1061,8 +1056,8 @@ mlx5_crypto_dev_probe(struct rte_device *dev) rte_errno = ENOMEM; return -rte_errno; } - priv->mr_scache.reg_mr_cb = mlx5_common_verbs_reg_mr; - priv->mr_scache.dereg_mr_cb = mlx5_common_verbs_dereg_mr; + priv->mr_scache.reg_mr_cb = mlx5_os_reg_mr; + priv->mr_scache.dereg_mr_cb = mlx5_os_dereg_mr; priv->keytag = rte_cpu_to_be_64(devarg_prms.keytag); priv->max_segs_num = devarg_prms.max_segs_num; priv->umr_wqe_size = sizeof(struct mlx5_wqe_umr_bsf_seg) + diff --git a/drivers/crypto/mlx5/mlx5_crypto.h b/drivers/crypto/mlx5/mlx5_crypto.h index 91e3f438b8..57461a8a33 100644 --- a/drivers/crypto/mlx5/mlx5_crypto.h +++ b/drivers/crypto/mlx5/mlx5_crypto.h @@ -19,7 +19,7 @@ struct mlx5_crypto_priv { TAILQ_ENTRY(mlx5_crypto_priv) next; - struct ibv_context *ctx; /* Device context. */ + void *ctx; /* Device context. */ struct rte_cryptodev *crypto_dev; void *uar; /* User Access Region. */ volatile uint64_t *uar_addr; From patchwork Tue Sep 14 05:38:32 2021 Content-Type: text/plain; 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monjalon.net; dkim=none (message not signed) header.d=none;monjalon.net; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by CO1NAM11FT055.mail.protection.outlook.com (10.13.175.129) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4500.14 via Frontend Transport; Tue, 14 Sep 2021 05:40:16 +0000 Received: from DRHQMAIL107.nvidia.com (10.27.9.16) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 14 Sep 2021 05:40:16 +0000 Received: from nvidia.com (172.20.187.6) by DRHQMAIL107.nvidia.com (10.27.9.16) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 14 Sep 2021 05:40:13 +0000 From: Tal Shnaiderman To: CC: , , , , , , , , Date: Tue, 14 Sep 2021 08:38:32 +0300 Message-ID: <20210914053833.7760-10-talshn@nvidia.com> X-Mailer: git-send-email 2.16.1.windows.4 In-Reply-To: <20210914053833.7760-1-talshn@nvidia.com> References: <20210914053833.7760-1-talshn@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL111.nvidia.com (172.20.187.18) To DRHQMAIL107.nvidia.com (10.27.9.16) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: af23ec07-c4b8-45ee-3a30-08d9774221bb X-MS-TrafficTypeDiagnostic: DM6PR12MB2970: X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7219; 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CAT:NONE; SFS:(4636009)(346002)(376002)(39860400002)(136003)(396003)(36840700001)(46966006)(2906002)(6666004)(82310400003)(4326008)(8676002)(7696005)(7636003)(336012)(426003)(54906003)(36860700001)(6286002)(316002)(47076005)(478600001)(70206006)(83380400001)(8936002)(2616005)(356005)(82740400003)(1076003)(86362001)(6916009)(5660300002)(186003)(36756003)(16526019)(26005)(55016002)(36906005)(70586007); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Sep 2021 05:40:16.5391 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: af23ec07-c4b8-45ee-3a30-08d9774221bb X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT055.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB2970 Subject: [dpdk-dev] [RFC PATCH 09/10] crypto/mlx5: fix size of UMR WQE X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The size of the UMR WQE allocated object is decided by a sizof operation on the struct, however since the struct contains a union of flexible array members this sizeof results can differ between compilers. GCC for example treats the union as 0 sized, MSVC adds a padding of 16Bits. To resolve the ambiguity the allocation size will be calculated by the sizes of the members excluding the flexible union. Fixes: a1978aa23bf4 ("crypto/mlx5: add maximum segments configuration") Cc: stable@dpdk.org Signed-off-by: Tal Shnaiderman --- drivers/crypto/mlx5/mlx5_crypto.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/crypto/mlx5/mlx5_crypto.c b/drivers/crypto/mlx5/mlx5_crypto.c index 3f5a6745dc..4b8d561e33 100644 --- a/drivers/crypto/mlx5/mlx5_crypto.c +++ b/drivers/crypto/mlx5/mlx5_crypto.c @@ -1061,7 +1061,9 @@ mlx5_crypto_dev_probe(struct rte_device *dev) priv->keytag = rte_cpu_to_be_64(devarg_prms.keytag); priv->max_segs_num = devarg_prms.max_segs_num; priv->umr_wqe_size = sizeof(struct mlx5_wqe_umr_bsf_seg) + - sizeof(struct mlx5_umr_wqe) + + sizeof(struct mlx5_wqe_cseg) + + sizeof(struct mlx5_wqe_umr_cseg) + + sizeof(struct mlx5_wqe_mkey_cseg) + RTE_ALIGN(priv->max_segs_num, 4) * sizeof(struct mlx5_wqe_dseg); rdmw_wqe_size = sizeof(struct mlx5_rdma_write_wqe) + From patchwork Tue Sep 14 05:38:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tal Shnaiderman X-Patchwork-Id: 98833 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4259DA0C47; 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Tue, 14 Sep 2021 05:40:19 +0000 Received: from DRHQMAIL107.nvidia.com (10.27.9.16) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 14 Sep 2021 05:40:18 +0000 Received: from nvidia.com (172.20.187.6) by DRHQMAIL107.nvidia.com (10.27.9.16) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 14 Sep 2021 05:40:15 +0000 From: Tal Shnaiderman To: CC: , , , , , , , Date: Tue, 14 Sep 2021 08:38:33 +0300 Message-ID: <20210914053833.7760-11-talshn@nvidia.com> X-Mailer: git-send-email 2.16.1.windows.4 In-Reply-To: <20210914053833.7760-1-talshn@nvidia.com> References: <20210914053833.7760-1-talshn@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL111.nvidia.com (172.20.187.18) To DRHQMAIL107.nvidia.com (10.27.9.16) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 02801406-d964-4c99-9b4a-08d977422342 X-MS-TrafficTypeDiagnostic: BL0PR12MB2547: X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7219; 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CAT:NONE; SFS:(4636009)(46966006)(36840700001)(107886003)(26005)(70206006)(7636003)(16526019)(186003)(356005)(6916009)(316002)(36906005)(82310400003)(2906002)(86362001)(47076005)(6666004)(4326008)(1076003)(36860700001)(426003)(336012)(54906003)(8676002)(2616005)(8936002)(55016002)(508600001)(36756003)(7696005)(6286002)(5660300002)(83380400001)(70586007); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Sep 2021 05:40:19.1231 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 02801406-d964-4c99-9b4a-08d977422342 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.36]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT066.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL0PR12MB2547 Subject: [dpdk-dev] [RFC PATCH 10/10] crypto/mlx5: support on Windows X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add support for mlx5 crypto pmd on Windows OS. Signed-off-by: Tal Shnaiderman --- drivers/common/mlx5/version.map | 2 +- drivers/crypto/aesni_gcm/meson.build | 6 ++++++ drivers/crypto/aesni_mb/meson.build | 6 ++++++ drivers/crypto/armv8/meson.build | 6 ++++++ drivers/crypto/bcmfs/meson.build | 6 ++++++ drivers/crypto/ccp/meson.build | 1 + drivers/crypto/kasumi/meson.build | 6 ++++++ drivers/crypto/meson.build | 3 --- drivers/crypto/mlx5/meson.build | 4 ++-- drivers/crypto/mvsam/meson.build | 6 ++++++ drivers/crypto/null/meson.build | 6 ++++++ drivers/crypto/octeontx/meson.build | 6 ++++++ drivers/crypto/openssl/meson.build | 6 ++++++ drivers/crypto/qat/meson.build | 6 ++++++ drivers/crypto/scheduler/meson.build | 6 ++++++ drivers/crypto/snow3g/meson.build | 6 ++++++ drivers/crypto/virtio/meson.build | 6 ++++++ drivers/crypto/zuc/meson.build | 6 ++++++ 18 files changed, 88 insertions(+), 6 deletions(-) diff --git a/drivers/common/mlx5/version.map b/drivers/common/mlx5/version.map index c6de706fdb..f595ef30fb 100644 --- a/drivers/common/mlx5/version.map +++ b/drivers/common/mlx5/version.map @@ -17,7 +17,7 @@ INTERNAL { mlx5_dev_is_pci; mlx5_dev_to_pci_str; - mlx5_devx_alloc_uar; # WINDOWS_NO_EXPORT + mlx5_devx_alloc_uar; mlx5_devx_cmd_alloc_pd; mlx5_devx_cmd_create_conn_track_offload_obj; diff --git a/drivers/crypto/aesni_gcm/meson.build b/drivers/crypto/aesni_gcm/meson.build index 0fcac2a8eb..7d0140ff22 100644 --- a/drivers/crypto/aesni_gcm/meson.build +++ b/drivers/crypto/aesni_gcm/meson.build @@ -1,6 +1,12 @@ # SPDX-License-Identifier: BSD-3-Clause # Copyright(c) 2018 Intel Corporation +if is_windows + build = false + reason = 'not supported on Windows' + subdir_done() +endif + IMB_required_ver = '0.52.0' lib = cc.find_library('IPSec_MB', required: false) if not lib.found() diff --git a/drivers/crypto/aesni_mb/meson.build b/drivers/crypto/aesni_mb/meson.build index ed6b9f53e4..b7512383c3 100644 --- a/drivers/crypto/aesni_mb/meson.build +++ b/drivers/crypto/aesni_mb/meson.build @@ -1,6 +1,12 @@ # SPDX-License-Identifier: BSD-3-Clause # Copyright(c) 2018 Intel Corporation +if is_windows + build = false + reason = 'not supported on Windows' + subdir_done() +endif + IMB_required_ver = '0.52.0' lib = cc.find_library('IPSec_MB', required: false) if not lib.found() diff --git a/drivers/crypto/armv8/meson.build b/drivers/crypto/armv8/meson.build index 40a4dbb7bb..5effba8bbc 100644 --- a/drivers/crypto/armv8/meson.build +++ b/drivers/crypto/armv8/meson.build @@ -1,6 +1,12 @@ # SPDX-License-Identifier: BSD-3-Clause # Copyright(c) 2019 Arm Limited +if is_windows + build = false + reason = 'not supported on Windows' + subdir_done() +endif + dep = dependency('libAArch64crypto', required: false, method: 'pkg-config') if not dep.found() build = false diff --git a/drivers/crypto/bcmfs/meson.build b/drivers/crypto/bcmfs/meson.build index d67e78d51b..5842f83a3b 100644 --- a/drivers/crypto/bcmfs/meson.build +++ b/drivers/crypto/bcmfs/meson.build @@ -3,6 +3,12 @@ # All rights reserved. # +if is_windows + build = false + reason = 'not supported on Windows' + subdir_done() +endif + deps += ['eal', 'bus_vdev'] sources = files( 'bcmfs_logs.c', diff --git a/drivers/crypto/ccp/meson.build b/drivers/crypto/ccp/meson.build index 0f82b9b90b..a4f3406009 100644 --- a/drivers/crypto/ccp/meson.build +++ b/drivers/crypto/ccp/meson.build @@ -4,6 +4,7 @@ if not is_linux build = false reason = 'only supported on Linux' + subdir_done() endif dep = dependency('libcrypto', required: false, method: 'pkg-config') if not dep.found() diff --git a/drivers/crypto/kasumi/meson.build b/drivers/crypto/kasumi/meson.build index e6e0f08c3d..966b8a5214 100644 --- a/drivers/crypto/kasumi/meson.build +++ b/drivers/crypto/kasumi/meson.build @@ -1,6 +1,12 @@ # SPDX-License-Identifier: BSD-3-Clause # Copyright(c) 2018-2020 Intel Corporation +if is_windows + build = false + reason = 'not supported on Windows' + subdir_done() +endif + IMB_required_ver = '0.53.0' lib = cc.find_library('IPSec_MB', required: false) if not lib.found() diff --git a/drivers/crypto/meson.build b/drivers/crypto/meson.build index ea239f4c56..c49ec501d4 100644 --- a/drivers/crypto/meson.build +++ b/drivers/crypto/meson.build @@ -1,9 +1,6 @@ # SPDX-License-Identifier: BSD-3-Clause # Copyright(c) 2017 Intel Corporation -if is_windows - subdir_done() -endif drivers = [ 'aesni_gcm', diff --git a/drivers/crypto/mlx5/meson.build b/drivers/crypto/mlx5/meson.build index 1d6e413dd5..9d9c9c00bc 100644 --- a/drivers/crypto/mlx5/meson.build +++ b/drivers/crypto/mlx5/meson.build @@ -1,9 +1,9 @@ # SPDX-License-Identifier: BSD-3-Clause # Copyright (c) 2021 NVIDIA Corporation & Affiliates -if not is_linux +if not (is_linux or is_windows) build = false - reason = 'only supported on Linux' + reason = 'only supported on Linux and Windows' subdir_done() endif diff --git a/drivers/crypto/mvsam/meson.build b/drivers/crypto/mvsam/meson.build index fec167bf29..bf3c4323de 100644 --- a/drivers/crypto/mvsam/meson.build +++ b/drivers/crypto/mvsam/meson.build @@ -3,6 +3,12 @@ # Copyright(c) 2018 Semihalf. # All rights reserved. +if is_windows + build = false + reason = 'not supported on Windows' + subdir_done() +endif + dep = dependency('libmusdk', required: false, method: 'pkg-config') if not dep.found() build = false diff --git a/drivers/crypto/null/meson.build b/drivers/crypto/null/meson.build index 1f7d644de1..acc16e7d81 100644 --- a/drivers/crypto/null/meson.build +++ b/drivers/crypto/null/meson.build @@ -1,5 +1,11 @@ # SPDX-License-Identifier: BSD-3-Clause # Copyright(c) 2017 Intel Corporation +if is_windows + build = false + reason = 'not supported on Windows' + subdir_done() +endif + deps += 'bus_vdev' sources = files('null_crypto_pmd.c', 'null_crypto_pmd_ops.c') diff --git a/drivers/crypto/octeontx/meson.build b/drivers/crypto/octeontx/meson.build index 244b16230e..48e8e263c1 100644 --- a/drivers/crypto/octeontx/meson.build +++ b/drivers/crypto/octeontx/meson.build @@ -1,6 +1,12 @@ # SPDX-License-Identifier: BSD-3-Clause # Copyright(c) 2018 Cavium, Inc +if is_windows + build = false + reason = 'not supported on Windows' + subdir_done() +endif + deps += ['bus_pci'] deps += ['bus_vdev'] deps += ['common_cpt'] diff --git a/drivers/crypto/openssl/meson.build b/drivers/crypto/openssl/meson.build index b21fca0be3..cd962da1d6 100644 --- a/drivers/crypto/openssl/meson.build +++ b/drivers/crypto/openssl/meson.build @@ -1,6 +1,12 @@ # SPDX-License-Identifier: BSD-3-Clause # Copyright(c) 2017 Intel Corporation +if is_windows + build = false + reason = 'not supported on Windows' + subdir_done() +endif + dep = dependency('libcrypto', required: false, method: 'pkg-config') if not dep.found() build = false diff --git a/drivers/crypto/qat/meson.build b/drivers/crypto/qat/meson.build index b3b2d17258..d08a24c7b3 100644 --- a/drivers/crypto/qat/meson.build +++ b/drivers/crypto/qat/meson.build @@ -1,6 +1,12 @@ # SPDX-License-Identifier: BSD-3-Clause # Copyright(c) 2017-2018 Intel Corporation +if is_windows + build = false + reason = 'not supported on Windows' + subdir_done() +endif + # this does not build the QAT driver, instead that is done in the compression # driver which comes later. Here we just add our sources files to the list build = false diff --git a/drivers/crypto/scheduler/meson.build b/drivers/crypto/scheduler/meson.build index d510f49970..cd18efc791 100644 --- a/drivers/crypto/scheduler/meson.build +++ b/drivers/crypto/scheduler/meson.build @@ -1,6 +1,12 @@ # SPDX-License-Identifier: BSD-3-Clause # Copyright(c) 2018 Luca Boccassi +if is_windows + build = false + reason = 'not supported on Windows' + subdir_done() +endif + deps += ['bus_vdev', 'reorder'] sources = files( 'rte_cryptodev_scheduler.c', diff --git a/drivers/crypto/snow3g/meson.build b/drivers/crypto/snow3g/meson.build index 0c087baa2a..ac4d0354ea 100644 --- a/drivers/crypto/snow3g/meson.build +++ b/drivers/crypto/snow3g/meson.build @@ -1,6 +1,12 @@ # SPDX-License-Identifier: BSD-3-Clause # Copyright(c) 2019-2020 Intel Corporation +if is_windows + build = false + reason = 'not supported on Windows' + subdir_done() +endif + IMB_required_ver = '0.53.0' lib = cc.find_library('IPSec_MB', required: false) if not lib.found() diff --git a/drivers/crypto/virtio/meson.build b/drivers/crypto/virtio/meson.build index 1b6d77f66f..45533c9b89 100644 --- a/drivers/crypto/virtio/meson.build +++ b/drivers/crypto/virtio/meson.build @@ -1,6 +1,12 @@ # SPDX-License-Identifier: BSD-3-Clause # Copyright(c) 2018 HUAWEI TECHNOLOGIES CO., LTD. +if is_windows + build = false + reason = 'not supported on Windows' + subdir_done() +endif + includes += include_directories('../../../lib/vhost') deps += 'bus_pci' sources = files( diff --git a/drivers/crypto/zuc/meson.build b/drivers/crypto/zuc/meson.build index a5f77a22d8..0a29885610 100644 --- a/drivers/crypto/zuc/meson.build +++ b/drivers/crypto/zuc/meson.build @@ -1,6 +1,12 @@ # SPDX-License-Identifier: BSD-3-Clause # Copyright(c) 2018-2020 Intel Corporation +if is_windows + build = false + reason = 'not supported on Windows' + subdir_done() +endif + IMB_required_ver = '0.53.0' lib = cc.find_library('IPSec_MB', required: false) if not lib.found()