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GET /api/patches/9529/?format=api
{ "id": 9529, "url": "http://patches.dpdk.org/api/patches/9529/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1450098032-21198-4-git-send-email-sshukla@mvista.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1450098032-21198-4-git-send-email-sshukla@mvista.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1450098032-21198-4-git-send-email-sshukla@mvista.com", "date": "2015-12-14T13:00:22", "name": "[dpdk-dev,[PATCH,v2] 03/13] rte_io: armv7/v8: Introduce api to emulate x86-style of PCI/ISA ioport access", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "c82e6488b7d816afeeb9fb5717a3a4d41d3a4f72", "submitter": { "id": 383, "url": "http://patches.dpdk.org/api/people/383/?format=api", "name": "Santosh Shukla", "email": "sshukla@mvista.com" }, "delegate": null, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1450098032-21198-4-git-send-email-sshukla@mvista.com/mbox/", "series": [], "comments": "http://patches.dpdk.org/api/patches/9529/comments/", "check": "pending", "checks": "http://patches.dpdk.org/api/patches/9529/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 9C6FC8D96;\n\tMon, 14 Dec 2015 14:00:53 +0100 (CET)", "from mail-pa0-f42.google.com (mail-pa0-f42.google.com\n\t[209.85.220.42]) by dpdk.org (Postfix) with ESMTP id 1EB3C8D96\n\tfor <dev@dpdk.org>; Mon, 14 Dec 2015 14:00:52 +0100 (CET)", "by padhk6 with SMTP id hk6so63498686pad.2\n\tfor <dev@dpdk.org>; Mon, 14 Dec 2015 05:00:51 -0800 (PST)", "from santosh-Latitude-E5530-non-vPro.mvista.com ([110.172.16.5])\n\tby smtp.gmail.com with ESMTPSA id\n\t9sm42506405pfn.51.2015.12.14.05.00.48\n\t(version=TLS1_1 cipher=ECDHE-RSA-AES128-SHA bits=128/128);\n\tMon, 14 Dec 2015 05:00:50 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=mvista-com.20150623.gappssmtp.com; s=20150623;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=j62W7wddXJb0zr1owBGvDlaQPc5eWYSxkU+WKHYPAvQ=;\n\tb=JB0IDaTS1GXzC6la1WCaz7WZlLV21dFhbLKBdKYfsokoOmNAg/diXG1g5ZtuTaJXgE\n\tvDl0VBrC8Jer/XTPGf20qfPe9GkFOHGwJYOZSqDWgG0VoSCpUvyrg5OJG8a2Bqk5pbTi\n\t0XQSMcJsIHDXZ48y23U2Ot535jDJxJ0A5vrs0jF+1vgE4KQa9dt5IRE06xFNn0vaCnvI\n\tcUj1F7RfuHkht2iLwVML0B8yIrnpy7D4S1WEgw37LeXHanVzkQGI1Mi361dO8dkC3ZMA\n\taN8LDfLR6r3aSPEY9rnXInDQhs5IbX9bTmG18hAlMj2sTpEyrXrIuavM0jTQXAqB6s4a\n\t4mqA==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20130820;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=j62W7wddXJb0zr1owBGvDlaQPc5eWYSxkU+WKHYPAvQ=;\n\tb=OUwSklnmEsTDn3VWCoffwiA278hoa8kIUdS7EXlabi7CIs8ResEbWHuJRw70tlQZDv\n\ty1LrNVrXZcze5Srt1bJ8Bve0lSAnXnrk7X2RQ69kI1s1JWS54HoL4deOH+WMjeaGwq6X\n\tbZzv7PN641UC+B/zyVaPLlyHuoqc6aNI4QKo5FPoGPPZ3zhsrBiTvjO1rZcC4tKWjBwO\n\tWiK2AUjtfra2d1x25eFy5PD4UvugKGJA9jLaHk8k1o1i4yaatjgqcY6pxQ2u3sqmG0Ht\n\trNIRAcO9ON7MUmAmFD0n0ZegSNYJUCfcJOKUJPuLAiQ3PfcKxXRW02hUruGim2dHipNa\n\tKlww==", "X-Gm-Message-State": "ALoCoQlaW6wy6aJ9ZiBh+54j/eP0gZifMj3CacpzBvAIFNZBi5a8OC2QWDhZ/e/29QIjP2J8jc109UmuirXME8Q82/imOqNavA==", "X-Received": "by 10.66.251.226 with SMTP id zn2mr45519066pac.44.1450098051487; \n\tMon, 14 Dec 2015 05:00:51 -0800 (PST)", "From": "Santosh Shukla <sshukla@mvista.com>", "To": "dev@dpdk.org", "Date": "Mon, 14 Dec 2015 18:30:22 +0530", "Message-Id": "<1450098032-21198-4-git-send-email-sshukla@mvista.com>", "X-Mailer": "git-send-email 1.7.9.5", "In-Reply-To": "<1450098032-21198-1-git-send-email-sshukla@mvista.com>", "References": "<1450098032-21198-1-git-send-email-sshukla@mvista.com>", "Subject": "[dpdk-dev] [ [PATCH v2] 03/13] rte_io: armv7/v8: Introduce api to\n\temulate x86-style of PCI/ISA ioport access", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Introducing rte_io.h header file to emulate x86-style of ioport rd/wr api\nexample {in,out}[bwl] and {in_p,out_p}[bwl]. Api support added for armv7 and\narmv8 both.\n\nCurrent use-case for this api is for virtio_pci module that does x86-style\nrd/wr.\n\nTested for armv8/ThunderX platform and build successfully for armv7.\n\nSigned-off-by: Santosh Shukla <sshukla@mvista.com>\n---\n lib/librte_eal/common/Makefile | 1 +\n lib/librte_eal/common/include/arch/arm/rte_io.h | 60 ++++++++\n lib/librte_eal/common/include/arch/arm/rte_io_32.h | 155 ++++++++++++++++++++\n lib/librte_eal/common/include/arch/arm/rte_io_64.h | 155 ++++++++++++++++++++\n lib/librte_eal/common/include/generic/rte_io.h | 81 ++++++++++\n 5 files changed, 452 insertions(+)\n create mode 100644 lib/librte_eal/common/include/arch/arm/rte_io.h\n create mode 100644 lib/librte_eal/common/include/arch/arm/rte_io_32.h\n create mode 100644 lib/librte_eal/common/include/arch/arm/rte_io_64.h\n create mode 100644 lib/librte_eal/common/include/generic/rte_io.h", "diff": "diff --git a/lib/librte_eal/common/Makefile b/lib/librte_eal/common/Makefile\nindex f5ea0ee..1021e1d 100644\n--- a/lib/librte_eal/common/Makefile\n+++ b/lib/librte_eal/common/Makefile\n@@ -48,6 +48,7 @@ endif\n \n GENERIC_INC := rte_atomic.h rte_byteorder.h rte_cycles.h rte_prefetch.h\n GENERIC_INC += rte_spinlock.h rte_memcpy.h rte_cpuflags.h rte_rwlock.h\n+GENERIC_INC += rte_io.h\n # defined in mk/arch/$(RTE_ARCH)/rte.vars.mk\n ARCH_DIR ?= $(RTE_ARCH)\n ARCH_INC := $(notdir $(wildcard $(RTE_SDK)/lib/librte_eal/common/include/arch/$(ARCH_DIR)/*.h))\ndiff --git a/lib/librte_eal/common/include/arch/arm/rte_io.h b/lib/librte_eal/common/include/arch/arm/rte_io.h\nnew file mode 100644\nindex 0000000..b4f1613\n--- /dev/null\n+++ b/lib/librte_eal/common/include/arch/arm/rte_io.h\n@@ -0,0 +1,60 @@\n+/*\n+ * BSD LICENSE\n+ *\n+ * Copyright(c) 2015 Cavium Networks. All rights reserved.\n+ * All rights reserved.\n+ *\n+ * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n+ * All rights reserved.\n+ *\n+ * ARM helper api to emulate x86-style of {in , out}[bwl] api used for\n+ * accessing PCI/ISA IO address space.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of Intel Corporation nor the names of its\n+ * contributors may be used to endorse or promote products derived\n+ * from this software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#ifndef _RTE_IO_ARM_H_\n+#define _RTE_IO_ARM_H_\n+\n+/*\n+ * @File\n+ * Use-case:\n+ * Currently virtio pci does IO access in x86-way i.e. IO_RESOURCE_IO way, It\n+ * access the pci address space by port_number. The ARM doesn't have\n+ * instructions for direct IO access. In ARM: IO's are memory mapped.\n+ *\n+ * Below helper api allow virtio_pci pmd driver to access IO's for arm/arm64\n+ * arch in x86-style of apis example: {in , out}[bwl] and {in_p , out_p}[bwl].\n+ */\n+\n+#ifdef RTE_ARCH_64\n+#include <rte_io_64.h>\n+#else\n+#include <rte_io_32.h>\n+#endif\n+\n+#endif /* _RTE_IO_ARM_H_ */\ndiff --git a/lib/librte_eal/common/include/arch/arm/rte_io_32.h b/lib/librte_eal/common/include/arch/arm/rte_io_32.h\nnew file mode 100644\nindex 0000000..0e79427\n--- /dev/null\n+++ b/lib/librte_eal/common/include/arch/arm/rte_io_32.h\n@@ -0,0 +1,155 @@\n+/*\n+ * BSD LICENSE\n+ *\n+ * Copyright(c) 2015 Cavium Networks. All rights reserved.\n+ * All rights reserved.\n+ *\n+ * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of Intel Corporation nor the names of its\n+ * contributors may be used to endorse or promote products derived\n+ * from this software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#ifndef _RTE_IO_ARM32_H_\n+#define _RTE_IO_ARM32_H_\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#include \"generic/rte_io.h\"\n+\n+/*\n+ * Generic IO read/write api for arm: Refer TRM\n+ */\n+static inline void raw_writeb(uint8_t val, uint32_t addr)\n+{\n+\tasm volatile(\"strb %0, [%1]\" : : \"r\" (val), \"r\" (addr));\n+}\n+\n+static inline void raw_writew(uint16_t val, uint32_t addr)\n+{\n+\tasm volatile(\"strh %0, [%1]\" : : \"r\" (val), \"r\" (addr));\n+}\n+\n+static inline void raw_writel(uint32_t val, uint32_t addr)\n+{\n+\tasm volatile(\"str %0, [%1]\" : : \"r\" (val), \"r\" (addr));\n+}\n+\n+static inline uint8_t raw_readb(uint32_t addr)\n+{\n+\tuint8_t val;\n+\tasm volatile(\"ldrb %0, [%1]\" : \"=r\" (val) : \"r\" (addr));\n+\treturn val;\n+}\n+\n+static inline uint16_t raw_readw(uint32_t addr)\n+{\n+\tuint16_t val;\n+\tasm volatile(\"ldrh %0, [%1]\" : \"=r\" (val) : \"r\" (addr));\n+\treturn val;\n+}\n+\n+static inline uint32_t raw_readl(uint32_t addr)\n+{\n+\tuint32_t val;\n+\tasm volatile(\"ldr %0, [%1]\" : \"=r\" (val) : \"r\" (addr));\n+\treturn val;\n+}\n+\n+/**\n+ * Emulate x86-style of ioport api implementation for arm/arm64. Included API\n+ * - {in, out}{b, w, l}()\n+ * - {in_p, out_p} {b, w, l} ()\n+ */\n+\n+static inline uint8_t inb(unsigned long addr)\n+{\n+\treturn raw_readb(addr);\n+}\n+\n+static inline uint16_t inw(unsigned long addr)\n+{\n+\treturn raw_readw(addr);\n+}\n+\n+static inline uint32_t inl(unsigned long addr)\n+{\n+\treturn raw_readl(addr);\n+}\n+\n+static inline void outb(uint8_t value, unsigned long addr)\n+{\n+\traw_writeb(value, addr);\n+}\n+\n+static inline void outw(uint16_t value, unsigned long addr)\n+{\n+\traw_writew(value, addr);\n+}\n+\n+static inline void outl(uint32_t value, unsigned long addr)\n+{\n+\traw_writel(value, addr);\n+}\n+\n+static inline uint8_t inb_p(unsigned long addr)\n+{\n+\treturn inb(addr);\n+}\n+\n+static inline uint16_t inw_p(unsigned long addr)\n+{\n+\treturn inw(addr);\n+}\n+\n+static inline uint32_t inl_p(unsigned long addr)\n+{\n+\treturn inl(addr);\n+}\n+\n+static inline void outb_p(uint8_t value, unsigned long addr)\n+{\n+\toutb(value, addr);\n+}\n+\n+static inline void outw_p(uint16_t value, unsigned long addr)\n+{\n+\toutw(value, addr);\n+}\n+\n+static inline void outl_p(uint32_t value, unsigned long addr)\n+{\n+\toutl(value, addr);\n+}\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* _RTE_IO_ARM32_H_ */\ndiff --git a/lib/librte_eal/common/include/arch/arm/rte_io_64.h b/lib/librte_eal/common/include/arch/arm/rte_io_64.h\nnew file mode 100644\nindex 0000000..b601f2a\n--- /dev/null\n+++ b/lib/librte_eal/common/include/arch/arm/rte_io_64.h\n@@ -0,0 +1,155 @@\n+/*\n+ * BSD LICENSE\n+ *\n+ * Copyright(c) 2015 Cavium Networks. All rights reserved.\n+ * All rights reserved.\n+ *\n+ * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of Intel Corporation nor the names of its\n+ * contributors may be used to endorse or promote products derived\n+ * from this software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#ifndef _RTE_IO_ARM64_H_\n+#define _RTE_IO_ARM64_H_\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#include \"generic/rte_io.h\"\n+\n+/*\n+ * Generic IO read/write api for arm64: Refer TRM\n+ */\n+static inline void raw_writeb(uint8_t val, uint64_t addr)\n+{\n+\tasm volatile(\"strb %w0, [%1]\" : : \"r\" (val), \"r\" (addr));\n+}\n+\n+static inline void raw_writew(uint16_t val, uint64_t addr)\n+{\n+\tasm volatile(\"strh %w0, [%1]\" : : \"r\" (val), \"r\" (addr));\n+}\n+\n+static inline void raw_writel(uint32_t val, uint64_t addr)\n+{\n+\tasm volatile(\"str %w0, [%1]\" : : \"r\" (val), \"r\" (addr));\n+}\n+\n+static inline uint8_t raw_readb(uint64_t addr)\n+{\n+\tuint8_t val;\n+\tasm volatile(\"ldrb %w0, [%1]\" : \"=r\" (val) : \"r\" (addr));\n+\treturn val;\n+}\n+\n+static inline uint16_t raw_readw(uint64_t addr)\n+{\n+\tuint16_t val;\n+\tasm volatile(\"ldrh %w0, [%1]\" : \"=r\" (val) : \"r\" (addr));\n+\treturn val;\n+}\n+\n+static inline uint32_t raw_readl(uint64_t addr)\n+{\n+\tuint32_t val;\n+\tasm volatile(\"ldr %w0, [%1]\" : \"=r\" (val) : \"r\" (addr));\n+\treturn val;\n+}\n+\n+/**\n+ * Emulate x86-style of ioport api implementation for arm/arm64. Included API\n+ * - {in, out}{b, w, l}()\n+ * - {in_p, out_p} {b, w, l} ()\n+ */\n+\n+static inline uint8_t inb(unsigned long addr)\n+{\n+\treturn raw_readb(addr);\n+}\n+\n+static inline uint16_t inw(unsigned long addr)\n+{\n+\treturn raw_readw(addr);\n+}\n+\n+static inline uint32_t inl(unsigned long addr)\n+{\n+\treturn raw_readl(addr);\n+}\n+\n+static inline void outb(uint8_t value, unsigned long addr)\n+{\n+\traw_writeb(value, addr);\n+}\n+\n+static inline void outw(uint16_t value, unsigned long addr)\n+{\n+\traw_writew(value, addr);\n+}\n+\n+static inline void outl(uint32_t value, unsigned long addr)\n+{\n+\traw_writel(value, addr);\n+}\n+\n+static inline uint8_t inb_p(unsigned long addr)\n+{\n+\treturn inb(addr);\n+}\n+\n+static inline uint16_t inw_p(unsigned long addr)\n+{\n+\treturn inw(addr);\n+}\n+\n+static inline uint32_t inl_p(unsigned long addr)\n+{\n+\treturn inl(addr);\n+}\n+\n+static inline void outb_p(uint8_t value, unsigned long addr)\n+{\n+\toutb(value, addr);\n+}\n+\n+static inline void outw_p(uint16_t value, unsigned long addr)\n+{\n+\toutw(value, addr);\n+}\n+\n+static inline void outl_p(uint32_t value, unsigned long addr)\n+{\n+\toutl(value, addr);\n+}\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* _RTE_IO_ARM64_H_ */\ndiff --git a/lib/librte_eal/common/include/generic/rte_io.h b/lib/librte_eal/common/include/generic/rte_io.h\nnew file mode 100644\nindex 0000000..7cc4279\n--- /dev/null\n+++ b/lib/librte_eal/common/include/generic/rte_io.h\n@@ -0,0 +1,81 @@\n+/*\n+ * BSD LICENSE\n+ *\n+ * Copyright(c) 2015 Cavium Networks. All rights reserved.\n+ * All rights reserved.\n+ *\n+ * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of Intel Corporation nor the names of its\n+ * contributors may be used to endorse or promote products derived\n+ * from this software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#ifndef _RTE_IO_H_\n+#define _RTE_IO_H_\n+\n+/**\n+ * @file\n+ *\n+ * IO operations.\n+ *\n+ * This file defines an API for IO rd/wr inline-functions, API's of the style\n+ * {in , out}[bwl] and {in_p, out_p} [bwl]. which are architecture-dependent.\n+ * Used by non-x86 archs. In particular used by arm/arm64 arch.\n+ */\n+\n+#include <stdint.h>\n+\n+#if defined(RTE_ARCH_X86_64) || defined(RTE_ARCH_I686)\n+#include <sys/io.h>\n+#else\n+\n+/**\n+ * Emulate x86-style of ioport api implementation for arm/arm64. Included API\n+ * - {in, out}{b, w, l}()\n+ * - {in_p, out_p} {b, w, l} ()\n+ */\n+\n+static inline uint8_t inb(unsigned long addr);\n+static inline uint16_t inw(unsigned long addr);\n+static inline uint32_t inl(unsigned long addr);\n+\n+static inline void outb(uint8_t value, unsigned long addr);\n+static inline void outw(uint16_t value, unsigned long addr);\n+static inline void outl(uint32_t value, unsigned long addr);\n+\n+static inline uint8_t inb_p(unsigned long addr);\n+static inline uint16_t inw_p(unsigned long addr);\n+static inline uint32_t inl_p(unsigned long addr);\n+\n+static inline void outb_p(uint8_t value, unsigned long addr);\n+static inline void outw_p(uint16_t value, unsigned long addr);\n+static inline void outl_p(uint32_t value, unsigned long addr);\n+\n+#endif\n+\n+#endif /* _RTE_IO_H_ */\n+\n", "prefixes": [ "dpdk-dev", "[PATCH", "v2" ] }