From patchwork Mon Dec 14 13:00:22 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Santosh Shukla X-Patchwork-Id: 9529 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [IPv6:::1]) by dpdk.org (Postfix) with ESMTP id 9C6FC8D96; Mon, 14 Dec 2015 14:00:53 +0100 (CET) Received: from mail-pa0-f42.google.com (mail-pa0-f42.google.com [209.85.220.42]) by dpdk.org (Postfix) with ESMTP id 1EB3C8D96 for ; Mon, 14 Dec 2015 14:00:52 +0100 (CET) Received: by padhk6 with SMTP id hk6so63498686pad.2 for ; Mon, 14 Dec 2015 05:00:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mvista-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=j62W7wddXJb0zr1owBGvDlaQPc5eWYSxkU+WKHYPAvQ=; b=JB0IDaTS1GXzC6la1WCaz7WZlLV21dFhbLKBdKYfsokoOmNAg/diXG1g5ZtuTaJXgE vDl0VBrC8Jer/XTPGf20qfPe9GkFOHGwJYOZSqDWgG0VoSCpUvyrg5OJG8a2Bqk5pbTi 0XQSMcJsIHDXZ48y23U2Ot535jDJxJ0A5vrs0jF+1vgE4KQa9dt5IRE06xFNn0vaCnvI cUj1F7RfuHkht2iLwVML0B8yIrnpy7D4S1WEgw37LeXHanVzkQGI1Mi361dO8dkC3ZMA aN8LDfLR6r3aSPEY9rnXInDQhs5IbX9bTmG18hAlMj2sTpEyrXrIuavM0jTQXAqB6s4a 4mqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=j62W7wddXJb0zr1owBGvDlaQPc5eWYSxkU+WKHYPAvQ=; b=OUwSklnmEsTDn3VWCoffwiA278hoa8kIUdS7EXlabi7CIs8ResEbWHuJRw70tlQZDv y1LrNVrXZcze5Srt1bJ8Bve0lSAnXnrk7X2RQ69kI1s1JWS54HoL4deOH+WMjeaGwq6X bZzv7PN641UC+B/zyVaPLlyHuoqc6aNI4QKo5FPoGPPZ3zhsrBiTvjO1rZcC4tKWjBwO WiK2AUjtfra2d1x25eFy5PD4UvugKGJA9jLaHk8k1o1i4yaatjgqcY6pxQ2u3sqmG0Ht rNIRAcO9ON7MUmAmFD0n0ZegSNYJUCfcJOKUJPuLAiQ3PfcKxXRW02hUruGim2dHipNa Klww== X-Gm-Message-State: ALoCoQlaW6wy6aJ9ZiBh+54j/eP0gZifMj3CacpzBvAIFNZBi5a8OC2QWDhZ/e/29QIjP2J8jc109UmuirXME8Q82/imOqNavA== X-Received: by 10.66.251.226 with SMTP id zn2mr45519066pac.44.1450098051487; Mon, 14 Dec 2015 05:00:51 -0800 (PST) Received: from santosh-Latitude-E5530-non-vPro.mvista.com ([110.172.16.5]) by smtp.gmail.com with ESMTPSA id 9sm42506405pfn.51.2015.12.14.05.00.48 (version=TLS1_1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 14 Dec 2015 05:00:50 -0800 (PST) From: Santosh Shukla To: dev@dpdk.org Date: Mon, 14 Dec 2015 18:30:22 +0530 Message-Id: <1450098032-21198-4-git-send-email-sshukla@mvista.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1450098032-21198-1-git-send-email-sshukla@mvista.com> References: <1450098032-21198-1-git-send-email-sshukla@mvista.com> Subject: [dpdk-dev] [ [PATCH v2] 03/13] rte_io: armv7/v8: Introduce api to emulate x86-style of PCI/ISA ioport access X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Introducing rte_io.h header file to emulate x86-style of ioport rd/wr api example {in,out}[bwl] and {in_p,out_p}[bwl]. Api support added for armv7 and armv8 both. Current use-case for this api is for virtio_pci module that does x86-style rd/wr. Tested for armv8/ThunderX platform and build successfully for armv7. Signed-off-by: Santosh Shukla --- lib/librte_eal/common/Makefile | 1 + lib/librte_eal/common/include/arch/arm/rte_io.h | 60 ++++++++ lib/librte_eal/common/include/arch/arm/rte_io_32.h | 155 ++++++++++++++++++++ lib/librte_eal/common/include/arch/arm/rte_io_64.h | 155 ++++++++++++++++++++ lib/librte_eal/common/include/generic/rte_io.h | 81 ++++++++++ 5 files changed, 452 insertions(+) create mode 100644 lib/librte_eal/common/include/arch/arm/rte_io.h create mode 100644 lib/librte_eal/common/include/arch/arm/rte_io_32.h create mode 100644 lib/librte_eal/common/include/arch/arm/rte_io_64.h create mode 100644 lib/librte_eal/common/include/generic/rte_io.h diff --git a/lib/librte_eal/common/Makefile b/lib/librte_eal/common/Makefile index f5ea0ee..1021e1d 100644 --- a/lib/librte_eal/common/Makefile +++ b/lib/librte_eal/common/Makefile @@ -48,6 +48,7 @@ endif GENERIC_INC := rte_atomic.h rte_byteorder.h rte_cycles.h rte_prefetch.h GENERIC_INC += rte_spinlock.h rte_memcpy.h rte_cpuflags.h rte_rwlock.h +GENERIC_INC += rte_io.h # defined in mk/arch/$(RTE_ARCH)/rte.vars.mk ARCH_DIR ?= $(RTE_ARCH) ARCH_INC := $(notdir $(wildcard $(RTE_SDK)/lib/librte_eal/common/include/arch/$(ARCH_DIR)/*.h)) diff --git a/lib/librte_eal/common/include/arch/arm/rte_io.h b/lib/librte_eal/common/include/arch/arm/rte_io.h new file mode 100644 index 0000000..b4f1613 --- /dev/null +++ b/lib/librte_eal/common/include/arch/arm/rte_io.h @@ -0,0 +1,60 @@ +/* + * BSD LICENSE + * + * Copyright(c) 2015 Cavium Networks. All rights reserved. + * All rights reserved. + * + * Copyright(c) 2010-2015 Intel Corporation. All rights reserved. + * All rights reserved. + * + * ARM helper api to emulate x86-style of {in , out}[bwl] api used for + * accessing PCI/ISA IO address space. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _RTE_IO_ARM_H_ +#define _RTE_IO_ARM_H_ + +/* + * @File + * Use-case: + * Currently virtio pci does IO access in x86-way i.e. IO_RESOURCE_IO way, It + * access the pci address space by port_number. The ARM doesn't have + * instructions for direct IO access. In ARM: IO's are memory mapped. + * + * Below helper api allow virtio_pci pmd driver to access IO's for arm/arm64 + * arch in x86-style of apis example: {in , out}[bwl] and {in_p , out_p}[bwl]. + */ + +#ifdef RTE_ARCH_64 +#include +#else +#include +#endif + +#endif /* _RTE_IO_ARM_H_ */ diff --git a/lib/librte_eal/common/include/arch/arm/rte_io_32.h b/lib/librte_eal/common/include/arch/arm/rte_io_32.h new file mode 100644 index 0000000..0e79427 --- /dev/null +++ b/lib/librte_eal/common/include/arch/arm/rte_io_32.h @@ -0,0 +1,155 @@ +/* + * BSD LICENSE + * + * Copyright(c) 2015 Cavium Networks. All rights reserved. + * All rights reserved. + * + * Copyright(c) 2010-2015 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _RTE_IO_ARM32_H_ +#define _RTE_IO_ARM32_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "generic/rte_io.h" + +/* + * Generic IO read/write api for arm: Refer TRM + */ +static inline void raw_writeb(uint8_t val, uint32_t addr) +{ + asm volatile("strb %0, [%1]" : : "r" (val), "r" (addr)); +} + +static inline void raw_writew(uint16_t val, uint32_t addr) +{ + asm volatile("strh %0, [%1]" : : "r" (val), "r" (addr)); +} + +static inline void raw_writel(uint32_t val, uint32_t addr) +{ + asm volatile("str %0, [%1]" : : "r" (val), "r" (addr)); +} + +static inline uint8_t raw_readb(uint32_t addr) +{ + uint8_t val; + asm volatile("ldrb %0, [%1]" : "=r" (val) : "r" (addr)); + return val; +} + +static inline uint16_t raw_readw(uint32_t addr) +{ + uint16_t val; + asm volatile("ldrh %0, [%1]" : "=r" (val) : "r" (addr)); + return val; +} + +static inline uint32_t raw_readl(uint32_t addr) +{ + uint32_t val; + asm volatile("ldr %0, [%1]" : "=r" (val) : "r" (addr)); + return val; +} + +/** + * Emulate x86-style of ioport api implementation for arm/arm64. Included API + * - {in, out}{b, w, l}() + * - {in_p, out_p} {b, w, l} () + */ + +static inline uint8_t inb(unsigned long addr) +{ + return raw_readb(addr); +} + +static inline uint16_t inw(unsigned long addr) +{ + return raw_readw(addr); +} + +static inline uint32_t inl(unsigned long addr) +{ + return raw_readl(addr); +} + +static inline void outb(uint8_t value, unsigned long addr) +{ + raw_writeb(value, addr); +} + +static inline void outw(uint16_t value, unsigned long addr) +{ + raw_writew(value, addr); +} + +static inline void outl(uint32_t value, unsigned long addr) +{ + raw_writel(value, addr); +} + +static inline uint8_t inb_p(unsigned long addr) +{ + return inb(addr); +} + +static inline uint16_t inw_p(unsigned long addr) +{ + return inw(addr); +} + +static inline uint32_t inl_p(unsigned long addr) +{ + return inl(addr); +} + +static inline void outb_p(uint8_t value, unsigned long addr) +{ + outb(value, addr); +} + +static inline void outw_p(uint16_t value, unsigned long addr) +{ + outw(value, addr); +} + +static inline void outl_p(uint32_t value, unsigned long addr) +{ + outl(value, addr); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _RTE_IO_ARM32_H_ */ diff --git a/lib/librte_eal/common/include/arch/arm/rte_io_64.h b/lib/librte_eal/common/include/arch/arm/rte_io_64.h new file mode 100644 index 0000000..b601f2a --- /dev/null +++ b/lib/librte_eal/common/include/arch/arm/rte_io_64.h @@ -0,0 +1,155 @@ +/* + * BSD LICENSE + * + * Copyright(c) 2015 Cavium Networks. All rights reserved. + * All rights reserved. + * + * Copyright(c) 2010-2015 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _RTE_IO_ARM64_H_ +#define _RTE_IO_ARM64_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "generic/rte_io.h" + +/* + * Generic IO read/write api for arm64: Refer TRM + */ +static inline void raw_writeb(uint8_t val, uint64_t addr) +{ + asm volatile("strb %w0, [%1]" : : "r" (val), "r" (addr)); +} + +static inline void raw_writew(uint16_t val, uint64_t addr) +{ + asm volatile("strh %w0, [%1]" : : "r" (val), "r" (addr)); +} + +static inline void raw_writel(uint32_t val, uint64_t addr) +{ + asm volatile("str %w0, [%1]" : : "r" (val), "r" (addr)); +} + +static inline uint8_t raw_readb(uint64_t addr) +{ + uint8_t val; + asm volatile("ldrb %w0, [%1]" : "=r" (val) : "r" (addr)); + return val; +} + +static inline uint16_t raw_readw(uint64_t addr) +{ + uint16_t val; + asm volatile("ldrh %w0, [%1]" : "=r" (val) : "r" (addr)); + return val; +} + +static inline uint32_t raw_readl(uint64_t addr) +{ + uint32_t val; + asm volatile("ldr %w0, [%1]" : "=r" (val) : "r" (addr)); + return val; +} + +/** + * Emulate x86-style of ioport api implementation for arm/arm64. Included API + * - {in, out}{b, w, l}() + * - {in_p, out_p} {b, w, l} () + */ + +static inline uint8_t inb(unsigned long addr) +{ + return raw_readb(addr); +} + +static inline uint16_t inw(unsigned long addr) +{ + return raw_readw(addr); +} + +static inline uint32_t inl(unsigned long addr) +{ + return raw_readl(addr); +} + +static inline void outb(uint8_t value, unsigned long addr) +{ + raw_writeb(value, addr); +} + +static inline void outw(uint16_t value, unsigned long addr) +{ + raw_writew(value, addr); +} + +static inline void outl(uint32_t value, unsigned long addr) +{ + raw_writel(value, addr); +} + +static inline uint8_t inb_p(unsigned long addr) +{ + return inb(addr); +} + +static inline uint16_t inw_p(unsigned long addr) +{ + return inw(addr); +} + +static inline uint32_t inl_p(unsigned long addr) +{ + return inl(addr); +} + +static inline void outb_p(uint8_t value, unsigned long addr) +{ + outb(value, addr); +} + +static inline void outw_p(uint16_t value, unsigned long addr) +{ + outw(value, addr); +} + +static inline void outl_p(uint32_t value, unsigned long addr) +{ + outl(value, addr); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _RTE_IO_ARM64_H_ */ diff --git a/lib/librte_eal/common/include/generic/rte_io.h b/lib/librte_eal/common/include/generic/rte_io.h new file mode 100644 index 0000000..7cc4279 --- /dev/null +++ b/lib/librte_eal/common/include/generic/rte_io.h @@ -0,0 +1,81 @@ +/* + * BSD LICENSE + * + * Copyright(c) 2015 Cavium Networks. All rights reserved. + * All rights reserved. + * + * Copyright(c) 2010-2015 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _RTE_IO_H_ +#define _RTE_IO_H_ + +/** + * @file + * + * IO operations. + * + * This file defines an API for IO rd/wr inline-functions, API's of the style + * {in , out}[bwl] and {in_p, out_p} [bwl]. which are architecture-dependent. + * Used by non-x86 archs. In particular used by arm/arm64 arch. + */ + +#include + +#if defined(RTE_ARCH_X86_64) || defined(RTE_ARCH_I686) +#include +#else + +/** + * Emulate x86-style of ioport api implementation for arm/arm64. Included API + * - {in, out}{b, w, l}() + * - {in_p, out_p} {b, w, l} () + */ + +static inline uint8_t inb(unsigned long addr); +static inline uint16_t inw(unsigned long addr); +static inline uint32_t inl(unsigned long addr); + +static inline void outb(uint8_t value, unsigned long addr); +static inline void outw(uint16_t value, unsigned long addr); +static inline void outl(uint32_t value, unsigned long addr); + +static inline uint8_t inb_p(unsigned long addr); +static inline uint16_t inw_p(unsigned long addr); +static inline uint32_t inl_p(unsigned long addr); + +static inline void outb_p(uint8_t value, unsigned long addr); +static inline void outw_p(uint16_t value, unsigned long addr); +static inline void outl_p(uint32_t value, unsigned long addr); + +#endif + +#endif /* _RTE_IO_H_ */ +