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{
    "id": 93693,
    "url": "http://patches.dpdk.org/api/patches/93693/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210530085929.29695-36-venkatkumar.duvvuru@broadcom.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20210530085929.29695-36-venkatkumar.duvvuru@broadcom.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20210530085929.29695-36-venkatkumar.duvvuru@broadcom.com",
    "date": "2021-05-30T08:59:06",
    "name": "[35/58] net/bnxt: add support for conditional goto processing",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "e25eb45f93096dc049dd53e680c2e6297c5c24dd",
    "submitter": {
        "id": 1635,
        "url": "http://patches.dpdk.org/api/people/1635/?format=api",
        "name": "Venkat Duvvuru",
        "email": "venkatkumar.duvvuru@broadcom.com"
    },
    "delegate": {
        "id": 1766,
        "url": "http://patches.dpdk.org/api/users/1766/?format=api",
        "username": "ajitkhaparde",
        "first_name": "Ajit",
        "last_name": "Khaparde",
        "email": "ajit.khaparde@broadcom.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210530085929.29695-36-venkatkumar.duvvuru@broadcom.com/mbox/",
    "series": [
        {
            "id": 17161,
            "url": "http://patches.dpdk.org/api/series/17161/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=17161",
            "date": "2021-05-30T08:58:31",
            "name": "enhancements to host based flow table management",
            "version": 1,
            "mbox": "http://patches.dpdk.org/series/17161/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/93693/comments/",
    "check": "warning",
    "checks": "http://patches.dpdk.org/api/patches/93693/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 42F9EA0524;\n\tTue,  1 Jun 2021 09:40:35 +0200 (CEST)",
            "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 85367410FC;\n\tTue,  1 Jun 2021 09:40:00 +0200 (CEST)",
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        ],
        "DKIM-Filter": "OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com E62C67DC2",
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com;\n s=dkimrelay; t=1622365287;\n bh=zvtt7fAYWJSARam8QP5J+HxOV7lewLfIDBQdRJFrm+E=;\n h=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n b=Au6al9HJh8w/p5nyw5Qk99c9/X3mH3j/rwBx5+vYB1x8bqMwswGcdRr1MnUhPN0hq\n gINgn7OGn097N9ADGyKknSCOnlnwQctgwU2fpkGgIR3hI1tCEBcV/NO5oLb3ffH12w\n eiIO8A3RtsqcGJOBXb6l8XYFYKUAp6cix9a5GYpM=",
        "From": "Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>",
        "To": "dev@dpdk.org",
        "Cc": "Kishore Padmanabha <kishore.padmanabha@broadcom.com>,\n Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>",
        "Date": "Sun, 30 May 2021 14:29:06 +0530",
        "Message-Id": "<20210530085929.29695-36-venkatkumar.duvvuru@broadcom.com>",
        "X-Mailer": "git-send-email 2.17.1",
        "In-Reply-To": "<20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com>",
        "References": "<20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com>",
        "X-Mailman-Approved-At": "Tue, 01 Jun 2021 09:39:53 +0200",
        "Subject": "[dpdk-dev] [PATCH 35/58] net/bnxt: add support for conditional goto\n processing",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>\n\nThe condition execute of the mapper tables have goto field that\ndefines the offset of the next table to be processed instead of\nsequential processing of the tables, this improving the performance.\nAlso, modify key and mask field opcode processing\n\nSigned-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>\nSigned-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>\nReviewed-by: Michael Baucom <michael.baucom@broadcom.com>\n---\n drivers/net/bnxt/tf_ulp/ulp_def_rules.c       |    6 +-\n drivers/net/bnxt/tf_ulp/ulp_mapper.c          |  393 +-\n drivers/net/bnxt/tf_ulp/ulp_rte_parser.c      |   36 +-\n drivers/net/bnxt/tf_ulp/ulp_template_db_act.c |   48 +-\n .../net/bnxt/tf_ulp/ulp_template_db_class.c   | 3286 ++++++++--\n .../net/bnxt/tf_ulp/ulp_template_db_enum.h    | 1222 ++--\n .../net/bnxt/tf_ulp/ulp_template_db_field.h   |  462 +-\n .../tf_ulp/ulp_template_db_stingray_act.c     |  585 +-\n .../tf_ulp/ulp_template_db_stingray_class.c   | 5638 +++++++---------\n drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c |  234 +-\n .../bnxt/tf_ulp/ulp_template_db_wh_plus_act.c |  581 +-\n .../tf_ulp/ulp_template_db_wh_plus_class.c    | 5656 +++++++----------\n drivers/net/bnxt/tf_ulp/ulp_template_struct.h |   16 +-\n drivers/net/bnxt/tf_ulp/ulp_tun.c             |    2 +-\n drivers/net/bnxt/tf_ulp/ulp_tun.h             |    2 +-\n 15 files changed, 9532 insertions(+), 8635 deletions(-)",
    "diff": "diff --git a/drivers/net/bnxt/tf_ulp/ulp_def_rules.c b/drivers/net/bnxt/tf_ulp/ulp_def_rules.c\nindex 5e9b12e4f5..6d6c22b157 100644\n--- a/drivers/net/bnxt/tf_ulp/ulp_def_rules.c\n+++ b/drivers/net/bnxt/tf_ulp/ulp_def_rules.c\n@@ -139,7 +139,7 @@ ulp_set_vlan_in_act_prop(uint16_t port_id,\n \tstruct ulp_rte_act_prop *act_prop = mapper_params->act_prop;\n \n \tif (ULP_BITMAP_ISSET(mapper_params->act->bits,\n-\t\t\t     BNXT_ULP_ACTION_BIT_SET_VLAN_VID)) {\n+\t\t\t     BNXT_ULP_ACT_BIT_SET_VLAN_VID)) {\n \t\tBNXT_TF_DBG(ERR,\n \t\t\t    \"VLAN already set, multiple VLANs unsupported\\n\");\n \t\treturn BNXT_TF_RC_ERROR;\n@@ -148,7 +148,7 @@ ulp_set_vlan_in_act_prop(uint16_t port_id,\n \tport_id = rte_cpu_to_be_16(port_id);\n \n \tULP_BITMAP_SET(mapper_params->act->bits,\n-\t\t       BNXT_ULP_ACTION_BIT_SET_VLAN_VID);\n+\t\t       BNXT_ULP_ACT_BIT_SET_VLAN_VID);\n \n \tmemcpy(&act_prop->act_details[BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG],\n \t       &port_id, sizeof(port_id));\n@@ -161,7 +161,7 @@ ulp_set_mark_in_act_prop(uint16_t port_id,\n \t\t\t struct bnxt_ulp_mapper_create_parms *mapper_params)\n {\n \tif (ULP_BITMAP_ISSET(mapper_params->act->bits,\n-\t\t\t     BNXT_ULP_ACTION_BIT_MARK)) {\n+\t\t\t     BNXT_ULP_ACT_BIT_MARK)) {\n \t\tBNXT_TF_DBG(ERR,\n \t\t\t    \"MARK already set, multiple MARKs unsupported\\n\");\n \t\treturn BNXT_TF_RC_ERROR;\ndiff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c\nindex ced446e189..ad5fde9730 100644\n--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c\n+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c\n@@ -892,26 +892,35 @@ ulp_mapper_field_process(struct bnxt_ulp_mapper_parms *parms,\n \tuint16_t write_idx = blob->write_idx;\n \tuint16_t idx, size_idx, bitlen;\n \tuint8_t\t*val = NULL;\n-\tuint8_t act_val[16];\n+\tuint8_t tmpval[16];\n \tuint8_t bit;\n+\tuint32_t src1_sel = 0;\n+\tenum bnxt_ulp_field_src fld_src;\n+\tuint8_t *fld_src_oper;\n \n \tbitlen = fld->field_bit_size;\n-\tswitch (fld->field_opcode) {\n-\tcase BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT:\n-\t\tval = fld->field_operand;\n-\t\tif (!ulp_blob_push(blob, val, bitlen)) {\n-\t\t\tBNXT_TF_DBG(ERR, \"%s push to blob failed\\n\", name);\n+\t/* Evaluate the condition */\n+\tswitch (fld->field_cond_src) {\n+\tcase BNXT_ULP_FIELD_COND_SRC_TRUE:\n+\t\tsrc1_sel = 1;\n+\t\tbreak;\n+\tcase BNXT_ULP_FIELD_COND_SRC_CF:\n+\t\tif (!ulp_operand_read(fld->field_cond_opr,\n+\t\t\t\t      (uint8_t *)&idx, sizeof(uint16_t))) {\n+\t\t\tBNXT_TF_DBG(ERR, \"%s operand read failed.\\n\", name);\n \t\t\treturn -EINVAL;\n \t\t}\n-\t\tbreak;\n-\tcase BNXT_ULP_FIELD_OPC_SET_TO_ZERO:\n-\t\tif (ulp_blob_pad_push(blob, bitlen) < 0) {\n-\t\t\tBNXT_TF_DBG(ERR, \"%s too large for blob\\n\", name);\n+\t\tidx = tfp_be_to_cpu_16(idx);\n+\t\tif (idx >= BNXT_ULP_CF_IDX_LAST) {\n+\t\t\tBNXT_TF_DBG(ERR, \"%s invalid index %u\\n\", name, idx);\n \t\t\treturn -EINVAL;\n \t\t}\n+\t\t/* check if the computed field is set */\n+\t\tif (ULP_COMP_FLD_IDX_RD(parms, idx))\n+\t\t\tsrc1_sel = 1;\n \t\tbreak;\n-\tcase BNXT_ULP_FIELD_OPC_SET_TO_REGFILE:\n-\t\tif (!ulp_operand_read(fld->field_operand,\n+\tcase BNXT_ULP_FIELD_COND_SRC_RF:\n+\t\tif (!ulp_operand_read(fld->field_cond_opr,\n \t\t\t\t      (uint8_t *)&idx, sizeof(uint16_t))) {\n \t\t\tBNXT_TF_DBG(ERR, \"%s operand read failed\\n\", name);\n \t\t\treturn -EINVAL;\n@@ -924,38 +933,78 @@ ulp_mapper_field_process(struct bnxt_ulp_mapper_parms *parms,\n \t\t\t\t    name, idx);\n \t\t\treturn -EINVAL;\n \t\t}\n-\n-\t\tval = ulp_blob_push_64(blob, &regval, bitlen);\n-\t\tif (!val) {\n-\t\t\tBNXT_TF_DBG(ERR, \"%s push to blob failed\\n\", name);\n+\t\tif (regval)\n+\t\t\tsrc1_sel = 1;\n+\t\tbreak;\n+\tcase BNXT_ULP_FIELD_COND_SRC_ACT_BIT:\n+\t\tif (!ulp_operand_read(fld->field_cond_opr,\n+\t\t\t\t      (uint8_t *)&act_bit, sizeof(uint64_t))) {\n+\t\t\tBNXT_TF_DBG(ERR, \"%s operand read failed\\n\", name);\n \t\t\treturn -EINVAL;\n \t\t}\n+\t\tact_bit = tfp_be_to_cpu_64(act_bit);\n+\t\tif (ULP_BITMAP_ISSET(parms->act_bitmap->bits, act_bit))\n+\t\t\tsrc1_sel = 1;\n \t\tbreak;\n-\tcase BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE:\n-\t\tif (!ulp_operand_read(fld->field_operand,\n-\t\t\t\t      (uint8_t *)&idx,\n+\tcase BNXT_ULP_FIELD_COND_SRC_HDR_BIT:\n+\t\tif (!ulp_operand_read(fld->field_cond_opr,\n+\t\t\t\t      (uint8_t *)&hdr_bit, sizeof(uint64_t))) {\n+\t\t\tBNXT_TF_DBG(ERR, \"%s operand read failed\\n\", name);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t\thdr_bit = tfp_be_to_cpu_64(hdr_bit);\n+\t\tif (ULP_BITMAP_ISSET(parms->hdr_bitmap->bits, hdr_bit))\n+\t\t\tsrc1_sel = 1;\n+\t\tbreak;\n+\tcase BNXT_ULP_FIELD_COND_SRC_FIELD_BIT:\n+\t\tif (!ulp_operand_read(fld->field_cond_opr, (uint8_t *)&idx,\n \t\t\t\t      sizeof(uint16_t))) {\n \t\t\tBNXT_TF_DBG(ERR, \"%s operand read failed.\\n\", name);\n \t\t\treturn -EINVAL;\n \t\t}\n \t\tidx = tfp_be_to_cpu_16(idx);\n-\t\tif (ulp_mapper_glb_resource_read(parms->mapper_data,\n-\t\t\t\t\t\t dir,\n-\t\t\t\t\t\t idx, &regval)) {\n-\t\t\tBNXT_TF_DBG(ERR, \"%s global regfile[%d] read failed.\\n\",\n-\t\t\t\t    name, idx);\n+\t\t/* get the index from the global field list */\n+\t\tif (ulp_mapper_glb_field_tbl_get(parms, idx, &bit)) {\n+\t\t\tBNXT_TF_DBG(ERR, \"invalid ulp_glb_field_tbl idx %d\\n\",\n+\t\t\t\t    idx);\n \t\t\treturn -EINVAL;\n \t\t}\n-\t\tval = ulp_blob_push_64(blob, &regval, bitlen);\n-\t\tif (!val) {\n+\t\tif (bit && (ULP_INDEX_BITMAP_GET(parms->fld_bitmap->bits, bit)))\n+\t\t\tsrc1_sel = 1;\n+\t\tbreak;\n+\tdefault:\n+\t\tBNXT_TF_DBG(ERR, \"%s invalid field opcode 0x%x at %d\\n\",\n+\t\t\t    name, fld->field_cond_src, write_idx);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* pick the selected source */\n+\tif (src1_sel) {\n+\t\tfld_src = fld->field_src1;\n+\t\tfld_src_oper = fld->field_opr1;\n+\t} else {\n+\t\tfld_src = fld->field_src2;\n+\t\tfld_src_oper = fld->field_opr2;\n+\t}\n+\n+\t/* Perform the action */\n+\tswitch (fld_src) {\n+\tcase BNXT_ULP_FIELD_SRC_ZERO:\n+\t\tif (ulp_blob_pad_push(blob, bitlen) < 0) {\n+\t\t\tBNXT_TF_DBG(ERR, \"%s too large for blob\\n\", name);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t\tbreak;\n+\tcase BNXT_ULP_FIELD_SRC_CONST:\n+\t\tval = fld_src_oper;\n+\t\tif (!ulp_blob_push(blob, val, bitlen)) {\n \t\t\tBNXT_TF_DBG(ERR, \"%s push to blob failed\\n\", name);\n \t\t\treturn -EINVAL;\n \t\t}\n \t\tbreak;\n-\tcase BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD:\n-\t\tif (!ulp_operand_read(fld->field_operand,\n-\t\t\t\t      (uint8_t *)&idx,\n-\t\t\t\t      sizeof(uint16_t))) {\n+\tcase BNXT_ULP_FIELD_SRC_CF:\n+\t\tif (!ulp_operand_read(fld_src_oper,\n+\t\t\t\t      (uint8_t *)&idx, sizeof(uint16_t))) {\n \t\t\tBNXT_TF_DBG(ERR, \"%s operand read failed.\\n\",\n \t\t\t\t    name);\n \t\t\treturn -EINVAL;\n@@ -969,126 +1018,29 @@ ulp_mapper_field_process(struct bnxt_ulp_mapper_parms *parms,\n \t\t\treturn -EINVAL;\n \t\t}\n \t\tbreak;\n-\tcase BNXT_ULP_FIELD_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST:\n-\t\tif (!ulp_operand_read(fld->field_operand,\n-\t\t\t\t      (uint8_t *)&act_bit, sizeof(uint64_t))) {\n-\t\t\tBNXT_TF_DBG(ERR, \"%s operand read failed\\n\", name);\n-\t\t\treturn -EINVAL;\n-\t\t}\n-\t\tact_bit = tfp_be_to_cpu_64(act_bit);\n-\t\tif (ULP_BITMAP_ISSET(parms->act_bitmap->bits, act_bit)) {\n-\t\t\t/* Action bit is set so consider operand_true */\n-\t\t\tif (!ulp_operand_read(fld->field_operand_true,\n-\t\t\t\t\t      (uint8_t *)&idx,\n-\t\t\t\t\t      sizeof(uint16_t))) {\n-\t\t\t\tBNXT_TF_DBG(ERR,\n-\t\t\t\t\t    \"%s true operand read failed\\n\",\n-\t\t\t\t\t    name);\n-\t\t\t\treturn -EINVAL;\n-\t\t\t}\n-\t\t\tidx = tfp_be_to_cpu_16(idx);\n-\t\t\tif (idx >= BNXT_ULP_ACT_PROP_IDX_LAST) {\n-\t\t\t\tBNXT_TF_DBG(ERR, \"%s act_prop[%d] oob\\n\",\n-\t\t\t\t\t    name, idx);\n-\t\t\t\treturn -EINVAL;\n-\t\t\t}\n-\t\t\tval = &parms->act_prop->act_details[idx];\n-\t\t\tfield_size = ulp_mapper_act_prop_size_get(idx);\n-\t\t\tif (bitlen < ULP_BYTE_2_BITS(field_size)) {\n-\t\t\t\tfield_size  = field_size - ((bitlen + 7) / 8);\n-\t\t\t\tval += field_size;\n-\t\t\t}\n-\t\t\tif (!ulp_blob_push(blob, val, bitlen)) {\n-\t\t\t\tBNXT_TF_DBG(ERR, \"%s push to blob failed\\n\",\n-\t\t\t\t\t    name);\n-\t\t\t\treturn -EINVAL;\n-\t\t\t}\n-\t\t} else {\n-\t\t\t/* action bit is not set, use the operand false */\n-\t\t\tval = fld->field_operand_false;\n-\t\t\tif (!ulp_blob_push(blob, val, bitlen)) {\n-\t\t\t\tBNXT_TF_DBG(ERR, \"%s push to blob failed\\n\",\n-\t\t\t\t\t    name);\n-\t\t\t\treturn -EINVAL;\n-\t\t\t}\n-\t\t}\n-\t\tbreak;\n-\tcase BNXT_ULP_FIELD_OPC_IF_ACT_BIT_THEN_CONST_ELSE_CONST:\n-\t\tif (!ulp_operand_read(fld->field_operand,\n-\t\t\t\t      (uint8_t *)&act_bit, sizeof(uint64_t))) {\n+\tcase BNXT_ULP_FIELD_SRC_RF:\n+\t\tif (!ulp_operand_read(fld_src_oper,\n+\t\t\t\t      (uint8_t *)&idx, sizeof(uint16_t))) {\n \t\t\tBNXT_TF_DBG(ERR, \"%s operand read failed\\n\", name);\n \t\t\treturn -EINVAL;\n \t\t}\n-\t\tact_bit = tfp_be_to_cpu_64(act_bit);\n-\t\tif (ULP_BITMAP_ISSET(parms->act_bitmap->bits, act_bit)) {\n-\t\t\t/* Action bit is set so consider operand_true */\n-\t\t\tval = fld->field_operand_true;\n-\t\t} else {\n-\t\t\t/* action bit is not set, use the operand false */\n-\t\t\tval = fld->field_operand_false;\n-\t\t}\n-\t\tif (!ulp_blob_push(blob, val, bitlen)) {\n-\t\t\tBNXT_TF_DBG(ERR, \"%s push to blob failed\\n\",\n-\t\t\t\t    name);\n-\t\t\treturn -EINVAL;\n-\t\t}\n-\t\tbreak;\n-\tcase BNXT_ULP_FIELD_OPC_IF_COMP_FIELD_THEN_CF_ELSE_CF:\n-\t\tif (!ulp_operand_read(fld->field_operand,\n-\t\t\t\t      (uint8_t *)&idx,\n-\t\t\t\t      sizeof(uint16_t))) {\n-\t\t\tBNXT_TF_DBG(ERR, \"%s operand read failed.\\n\", name);\n-\t\t\treturn -EINVAL;\n-\t\t}\n-\t\tidx = tfp_be_to_cpu_16(idx);\n-\t\tif (idx >= BNXT_ULP_CF_IDX_LAST) {\n-\t\t\tBNXT_TF_DBG(ERR, \"%s invalid index %u\\n\", name, idx);\n-\t\t\treturn -EINVAL;\n-\t\t}\n-\t\t/* check if the computed field is set */\n-\t\tif (ULP_COMP_FLD_IDX_RD(parms, idx))\n-\t\t\tval = fld->field_operand_true;\n-\t\telse\n-\t\t\tval = fld->field_operand_false;\n \n-\t\t/* read the appropriate computed field */\n-\t\tif (!ulp_operand_read(val, (uint8_t *)&idx, sizeof(uint16_t))) {\n-\t\t\tBNXT_TF_DBG(ERR, \"%s val operand read failed\\n\", name);\n-\t\t\treturn -EINVAL;\n-\t\t}\n \t\tidx = tfp_be_to_cpu_16(idx);\n-\t\tif (idx >= BNXT_ULP_CF_IDX_LAST) {\n-\t\t\tBNXT_TF_DBG(ERR, \"%s invalid index %u\\n\", name, idx);\n+\t\t/* Uninitialized regfile entries return 0 */\n+\t\tif (!ulp_regfile_read(parms->regfile, idx, &regval)) {\n+\t\t\tBNXT_TF_DBG(ERR, \"%s regfile[%d] read oob\\n\",\n+\t\t\t\t    name, idx);\n \t\t\treturn -EINVAL;\n \t\t}\n-\t\tval = ulp_blob_push_32(blob, &parms->comp_fld[idx], bitlen);\n+\n+\t\tval = ulp_blob_push_64(blob, &regval, bitlen);\n \t\tif (!val) {\n \t\t\tBNXT_TF_DBG(ERR, \"%s push to blob failed\\n\", name);\n \t\t\treturn -EINVAL;\n \t\t}\n \t\tbreak;\n-\tcase BNXT_ULP_FIELD_OPC_IF_HDR_BIT_THEN_CONST_ELSE_CONST:\n-\t\tif (!ulp_operand_read(fld->field_operand,\n-\t\t\t\t      (uint8_t *)&hdr_bit, sizeof(uint64_t))) {\n-\t\t\tBNXT_TF_DBG(ERR, \"%s operand read failed\\n\", name);\n-\t\t\treturn -EINVAL;\n-\t\t}\n-\t\thdr_bit = tfp_be_to_cpu_64(hdr_bit);\n-\t\tif (ULP_BITMAP_ISSET(parms->hdr_bitmap->bits, hdr_bit)) {\n-\t\t\t/* Header bit is set so consider operand_true */\n-\t\t\tval = fld->field_operand_true;\n-\t\t} else {\n-\t\t\t/* Header bit is not set, use the operand false */\n-\t\t\tval = fld->field_operand_false;\n-\t\t}\n-\t\tif (!ulp_blob_push(blob, val, bitlen)) {\n-\t\t\tBNXT_TF_DBG(ERR, \"%s push to blob failed\\n\",\n-\t\t\t\t    name);\n-\t\t\treturn -EINVAL;\n-\t\t}\n-\t\tbreak;\n-\tcase BNXT_ULP_FIELD_OPC_SET_TO_ACT_PROP:\n-\t\tif (!ulp_operand_read(fld->field_operand,\n+\tcase BNXT_ULP_FIELD_SRC_ACT_PROP:\n+\t\tif (!ulp_operand_read(fld_src_oper,\n \t\t\t\t      (uint8_t *)&idx, sizeof(uint16_t))) {\n \t\t\tBNXT_TF_DBG(ERR, \"%s operand read failed\\n\", name);\n \t\t\treturn -EINVAL;\n@@ -1110,28 +1062,8 @@ ulp_mapper_field_process(struct bnxt_ulp_mapper_parms *parms,\n \t\t\treturn -EINVAL;\n \t\t}\n \t\tbreak;\n-\tcase BNXT_ULP_FIELD_OPC_SET_TO_ACT_BIT:\n-\t\tif (!ulp_operand_read(fld->field_operand,\n-\t\t\t\t      (uint8_t *)&act_bit, sizeof(uint64_t))) {\n-\t\t\tBNXT_TF_DBG(ERR, \"%s operand read failed\\n\", name);\n-\t\t\treturn -EINVAL;\n-\t\t}\n-\t\tact_bit = tfp_be_to_cpu_64(act_bit);\n-\t\tmemset(act_val, 0, sizeof(act_val));\n-\t\tif (ULP_BITMAP_ISSET(parms->act_bitmap->bits, act_bit))\n-\t\t\tact_val[0] = 1;\n-\t\tif (bitlen > ULP_BYTE_2_BITS(sizeof(act_val))) {\n-\t\t\tBNXT_TF_DBG(ERR, \"%s field size is incorrect\\n\", name);\n-\t\t\treturn -EINVAL;\n-\t\t}\n-\t\tif (!ulp_blob_push(blob, act_val, bitlen)) {\n-\t\t\tBNXT_TF_DBG(ERR, \"%s push to blob failed\\n\", name);\n-\t\t\treturn -EINVAL;\n-\t\t}\n-\t\tval = act_val;\n-\t\tbreak;\n-\tcase BNXT_ULP_FIELD_OPC_SET_TO_ENCAP_ACT_PROP_SZ:\n-\t\tif (!ulp_operand_read(fld->field_operand,\n+\tcase BNXT_ULP_FIELD_SRC_ACT_PROP_SZ:\n+\t\tif (!ulp_operand_read(fld_src_oper,\n \t\t\t\t      (uint8_t *)&idx, sizeof(uint16_t))) {\n \t\t\tBNXT_TF_DBG(ERR, \"%s operand read failed\\n\", name);\n \t\t\treturn -EINVAL;\n@@ -1145,7 +1077,7 @@ ulp_mapper_field_process(struct bnxt_ulp_mapper_parms *parms,\n \t\tval = &parms->act_prop->act_details[idx];\n \n \t\t/* get the size index next */\n-\t\tif (!ulp_operand_read(&fld->field_operand[sizeof(uint16_t)],\n+\t\tif (!ulp_operand_read(&fld_src_oper[sizeof(uint16_t)],\n \t\t\t\t      (uint8_t *)&size_idx, sizeof(uint16_t))) {\n \t\t\tBNXT_TF_DBG(ERR, \"%s operand read failed\\n\", name);\n \t\t\treturn -EINVAL;\n@@ -1162,8 +1094,29 @@ ulp_mapper_field_process(struct bnxt_ulp_mapper_parms *parms,\n \t\tval_size = ULP_BYTE_2_BITS(val_size);\n \t\tulp_blob_push_encap(blob, val, val_size);\n \t\tbreak;\n-\tcase BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD:\n-\t\tif (!ulp_operand_read(fld->field_operand, (uint8_t *)&idx,\n+\tcase BNXT_ULP_FIELD_SRC_GLB_RF:\n+\t\tif (!ulp_operand_read(fld_src_oper,\n+\t\t\t\t      (uint8_t *)&idx,\n+\t\t\t\t      sizeof(uint16_t))) {\n+\t\t\tBNXT_TF_DBG(ERR, \"%s operand read failed.\\n\", name);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t\tidx = tfp_be_to_cpu_16(idx);\n+\t\tif (ulp_mapper_glb_resource_read(parms->mapper_data,\n+\t\t\t\t\t\t dir,\n+\t\t\t\t\t\t idx, &regval)) {\n+\t\t\tBNXT_TF_DBG(ERR, \"%s global regfile[%d] read failed.\\n\",\n+\t\t\t\t    name, idx);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t\tval = ulp_blob_push_64(blob, &regval, bitlen);\n+\t\tif (!val) {\n+\t\t\tBNXT_TF_DBG(ERR, \"%s push to blob failed\\n\", name);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t\tbreak;\n+\tcase BNXT_ULP_FIELD_SRC_HF:\n+\t\tif (!ulp_operand_read(fld_src_oper, (uint8_t *)&idx,\n \t\t\t\t      sizeof(uint16_t))) {\n \t\t\tBNXT_TF_DBG(ERR, \"%s operand read failed.\\n\", name);\n \t\t\treturn -EINVAL;\n@@ -1195,9 +1148,80 @@ ulp_mapper_field_process(struct bnxt_ulp_mapper_parms *parms,\n \t\t\treturn -EINVAL;\n \t\t}\n \t\tbreak;\n+\tcase BNXT_ULP_FIELD_SRC_HDR_BIT:\n+\t\tif (!ulp_operand_read(fld_src_oper,\n+\t\t\t\t      (uint8_t *)&hdr_bit, sizeof(uint64_t))) {\n+\t\t\tBNXT_TF_DBG(ERR, \"%s operand read failed\\n\", name);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t\thdr_bit = tfp_be_to_cpu_64(hdr_bit);\n+\t\tmemset(tmpval, 0, sizeof(tmpval));\n+\t\tif (ULP_BITMAP_ISSET(parms->hdr_bitmap->bits, hdr_bit))\n+\t\t\ttmpval[0] = 1;\n+\t\tif (bitlen > ULP_BYTE_2_BITS(sizeof(tmpval))) {\n+\t\t\tBNXT_TF_DBG(ERR, \"%s field size is incorrect\\n\", name);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t\tif (!ulp_blob_push(blob, tmpval, bitlen)) {\n+\t\t\tBNXT_TF_DBG(ERR, \"%s push to blob failed\\n\", name);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t\tval = tmpval;\n+\t\tbreak;\n+\tcase BNXT_ULP_FIELD_SRC_ACT_BIT:\n+\t\tif (!ulp_operand_read(fld_src_oper,\n+\t\t\t\t      (uint8_t *)&act_bit, sizeof(uint64_t))) {\n+\t\t\tBNXT_TF_DBG(ERR, \"%s operand read failed\\n\", name);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t\tact_bit = tfp_be_to_cpu_64(act_bit);\n+\t\tmemset(tmpval, 0, sizeof(tmpval));\n+\t\tif (ULP_BITMAP_ISSET(parms->act_bitmap->bits, act_bit))\n+\t\t\ttmpval[0] = 1;\n+\t\tif (bitlen > ULP_BYTE_2_BITS(sizeof(tmpval))) {\n+\t\t\tBNXT_TF_DBG(ERR, \"%s field size is incorrect\\n\", name);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t\tif (!ulp_blob_push(blob, tmpval, bitlen)) {\n+\t\t\tBNXT_TF_DBG(ERR, \"%s push to blob failed\\n\", name);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t\tval = tmpval;\n+\t\tbreak;\n+\tcase BNXT_ULP_FIELD_SRC_FIELD_BIT:\n+\t\tif (!ulp_operand_read(fld_src_oper, (uint8_t *)&idx,\n+\t\t\t\t      sizeof(uint16_t))) {\n+\t\t\tBNXT_TF_DBG(ERR, \"%s operand read failed.\\n\", name);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t\tidx = tfp_be_to_cpu_16(idx);\n+\t\t/* get the index from the global field list */\n+\t\tif (ulp_mapper_glb_field_tbl_get(parms, idx, &bit)) {\n+\t\t\tBNXT_TF_DBG(ERR, \"invalid ulp_glb_field_tbl idx %d\\n\",\n+\t\t\t\t    idx);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t\tmemset(tmpval, 0, sizeof(tmpval));\n+\t\tif (ULP_INDEX_BITMAP_GET(parms->fld_bitmap->bits, bit))\n+\t\t\ttmpval[0] = 1;\n+\t\tif (bitlen > ULP_BYTE_2_BITS(sizeof(tmpval))) {\n+\t\t\tBNXT_TF_DBG(ERR, \"%s field size is incorrect\\n\", name);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t\tif (!ulp_blob_push(blob, tmpval, bitlen)) {\n+\t\t\tBNXT_TF_DBG(ERR, \"%s push to blob failed\\n\", name);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t\tval = tmpval;\n+\t\tbreak;\n+\tcase BNXT_ULP_FIELD_SRC_SKIP:\n+\t\t/* do nothing */\n+\t\tbreak;\n+\tcase BNXT_ULP_FIELD_SRC_REJECT:\n+\t\treturn -EINVAL;\n \tdefault:\n \t\tBNXT_TF_DBG(ERR, \"%s invalid field opcode 0x%x at %d\\n\",\n-\t\t\t    name, fld->field_opcode, write_idx);\n+\t\t\t    name, fld_src, write_idx);\n \t\treturn -EINVAL;\n \t}\n \treturn 0;\n@@ -1267,7 +1291,7 @@ ulp_mapper_mark_gfid_process(struct bnxt_ulp_mapper_parms *parms,\n \tif (mark_op == BNXT_ULP_MARK_DB_OPC_NOP ||\n \t    !(mark_op == BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION &&\n \t     ULP_BITMAP_ISSET(parms->act_bitmap->bits,\n-\t\t\t      BNXT_ULP_ACTION_BIT_MARK)))\n+\t\t\t      BNXT_ULP_ACT_BIT_MARK)))\n \t\treturn rc; /* no need to perform gfid process */\n \n \t/* Get the mark id details from action property */\n@@ -1308,7 +1332,7 @@ ulp_mapper_mark_act_ptr_process(struct bnxt_ulp_mapper_parms *parms,\n \tif (mark_op == BNXT_ULP_MARK_DB_OPC_NOP ||\n \t    !(mark_op == BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION &&\n \t     ULP_BITMAP_ISSET(parms->act_bitmap->bits,\n-\t\t\t      BNXT_ULP_ACTION_BIT_MARK)))\n+\t\t\t      BNXT_ULP_ACT_BIT_MARK)))\n \t\treturn rc; /* no need to perform mark action process */\n \n \t/* Get the mark id details from action property */\n@@ -2500,7 +2524,7 @@ ulp_mapper_cond_opc_process(struct bnxt_ulp_mapper_parms *parms,\n \tuint64_t regval;\n \n \tswitch (opc) {\n-\tcase BNXT_ULP_COND_OPC_COMP_FIELD_IS_SET:\n+\tcase BNXT_ULP_COND_OPC_CF_IS_SET:\n \t\tif (operand < BNXT_ULP_CF_IDX_LAST) {\n \t\t\t*res = ULP_COMP_FLD_IDX_RD(parms, operand);\n \t\t} else {\n@@ -2509,7 +2533,7 @@ ulp_mapper_cond_opc_process(struct bnxt_ulp_mapper_parms *parms,\n \t\t\trc = -EINVAL;\n \t\t}\n \t\tbreak;\n-\tcase BNXT_ULP_COND_OPC_COMP_FIELD_NOT_SET:\n+\tcase BNXT_ULP_COND_OPC_CF_NOT_SET:\n \t\tif (operand < BNXT_ULP_CF_IDX_LAST) {\n \t\t\t*res = !ULP_COMP_FLD_IDX_RD(parms, operand);\n \t\t} else {\n@@ -2518,8 +2542,8 @@ ulp_mapper_cond_opc_process(struct bnxt_ulp_mapper_parms *parms,\n \t\t\trc = -EINVAL;\n \t\t}\n \t\tbreak;\n-\tcase BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET:\n-\t\tif (operand < BNXT_ULP_ACTION_BIT_LAST) {\n+\tcase BNXT_ULP_COND_OPC_ACT_BIT_IS_SET:\n+\t\tif (operand < BNXT_ULP_ACT_BIT_LAST) {\n \t\t\t*res = ULP_BITMAP_ISSET(parms->act_bitmap->bits,\n \t\t\t\t\t\toperand);\n \t\t} else {\n@@ -2528,8 +2552,8 @@ ulp_mapper_cond_opc_process(struct bnxt_ulp_mapper_parms *parms,\n \t\t\trc = -EINVAL;\n \t\t}\n \t\tbreak;\n-\tcase BNXT_ULP_COND_OPC_ACTION_BIT_NOT_SET:\n-\t\tif (operand < BNXT_ULP_ACTION_BIT_LAST) {\n+\tcase BNXT_ULP_COND_OPC_ACT_BIT_NOT_SET:\n+\t\tif (operand < BNXT_ULP_ACT_BIT_LAST) {\n \t\t\t*res = !ULP_BITMAP_ISSET(parms->act_bitmap->bits,\n \t\t\t\t\t       operand);\n \t\t} else {\n@@ -2576,14 +2600,14 @@ ulp_mapper_cond_opc_process(struct bnxt_ulp_mapper_parms *parms,\n \t\t}\n \t\t*res = !ULP_INDEX_BITMAP_GET(parms->fld_bitmap->bits, bit);\n \t\tbreak;\n-\tcase BNXT_ULP_COND_OPC_REGFILE_IS_SET:\n+\tcase BNXT_ULP_COND_OPC_RF_IS_SET:\n \t\tif (!ulp_regfile_read(parms->regfile, operand, &regval)) {\n \t\t\tBNXT_TF_DBG(ERR, \"regfile[%d] read oob\\n\", operand);\n \t\t\treturn -EINVAL;\n \t\t}\n \t\t*res = regval != 0;\n \t\tbreak;\n-\tcase BNXT_ULP_COND_OPC_REGFILE_NOT_SET:\n+\tcase BNXT_ULP_COND_OPC_RF_NOT_SET:\n \t\tif (!ulp_regfile_read(parms->regfile, operand, &regval)) {\n \t\t\tBNXT_TF_DBG(ERR, \"regfile[%d] read oob\\n\", operand);\n \t\t\treturn -EINVAL;\n@@ -2733,8 +2757,9 @@ ulp_mapper_tbls_process(struct bnxt_ulp_mapper_parms *parms, uint32_t tid)\n \tenum bnxt_ulp_cond_list_opc cond_opc;\n \tstruct bnxt_ulp_mapper_tbl_info *tbls;\n \tstruct bnxt_ulp_mapper_tbl_info *tbl;\n-\tuint32_t num_tbls, i, num_cond_tbls;\n+\tuint32_t num_tbls, tbl_idx, num_cond_tbls;\n \tint32_t rc = -EINVAL, cond_rc = 0;\n+\tuint32_t cond_goto = 1;\n \n \tcond_tbls = ulp_mapper_tmpl_reject_list_get(parms, tid,\n \t\t\t\t\t\t    &num_cond_tbls,\n@@ -2769,12 +2794,15 @@ ulp_mapper_tbls_process(struct bnxt_ulp_mapper_parms *parms, uint32_t tid)\n \t\treturn -EINVAL;\n \t}\n \n-\tfor (i = 0; i < num_tbls; i++) {\n-\t\ttbl = &tbls[i];\n-\n+\tfor (tbl_idx = 0; tbl_idx < num_tbls && cond_goto;) {\n+\t\ttbl = &tbls[tbl_idx];\n+\t\tcond_goto = tbl->execute_info.cond_goto;\n \t\t/* Handle the table level opcodes to determine if required. */\n-\t\tif (ulp_mapper_tbl_memtype_opcode_process(parms, tbl))\n+\t\tif (ulp_mapper_tbl_memtype_opcode_process(parms, tbl)) {\n+\t\t\ttbl_idx += 1;\n \t\t\tcontinue;\n+\t\t}\n+\n \t\tcond_tbls = ulp_mapper_tbl_execute_list_get(parms, tbl,\n \t\t\t\t\t\t\t    &num_cond_tbls,\n \t\t\t\t\t\t\t    &cond_opc);\n@@ -2787,8 +2815,10 @@ ulp_mapper_tbls_process(struct bnxt_ulp_mapper_parms *parms, uint32_t tid)\n \t\t\treturn rc;\n \t\t}\n \t\t/* Skip the table if False */\n-\t\tif (!cond_rc)\n+\t\tif (!cond_rc) {\n+\t\t\ttbl_idx += 1;\n \t\t\tcontinue;\n+\t\t}\n \n \t\t/* process the fdb opcode for alloc push */\n \t\tif (tbl->fdb_opcode == BNXT_ULP_FDB_OPC_ALLOC_PUSH_REGFILE) {\n@@ -2817,6 +2847,7 @@ ulp_mapper_tbls_process(struct bnxt_ulp_mapper_parms *parms, uint32_t tid)\n \t\t\trc = ulp_mapper_gen_tbl_process(parms, tbl);\n \t\t\tbreak;\n \t\tcase BNXT_ULP_RESOURCE_FUNC_INVALID:\n+\t\tcase BNXT_ULP_RESOURCE_FUNC_BRANCH_TABLE:\n \t\t\trc = 0;\n \t\t\tbreak;\n \t\tdefault:\n@@ -2840,6 +2871,7 @@ ulp_mapper_tbls_process(struct bnxt_ulp_mapper_parms *parms, uint32_t tid)\n \t\t\trc = -EINVAL;\n \t\t\tgoto error;\n \t\t}\n+\t\ttbl_idx += cond_goto;\n \t}\n \n \treturn rc;\n@@ -3081,6 +3113,7 @@ ulp_mapper_flow_create(struct bnxt_ulp_context *ulp_ctx,\n \tparms.hdr_bitmap = cparms->hdr_bitmap;\n \tparms.regfile = &regfile;\n \tparms.hdr_field = cparms->hdr_field;\n+\tparms.fld_bitmap = cparms->fld_bitmap;\n \tparms.comp_fld = cparms->comp_fld;\n \tparms.tfp = bnxt_ulp_cntxt_tfp_get(ulp_ctx);\n \tparms.ulp_ctx = ulp_ctx;\ndiff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c\nindex 7c048a33a0..02e2b7fdc0 100644\n--- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c\n+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c\n@@ -274,7 +274,7 @@ ulp_post_process_normal_flow(struct ulp_rte_parser_params *params)\n \n \t/* Update the decrement ttl computational fields */\n \tif (ULP_BITMAP_ISSET(params->act_bitmap.bits,\n-\t\t\t     BNXT_ULP_ACTION_BIT_DEC_TTL)) {\n+\t\t\t     BNXT_ULP_ACT_BIT_DEC_TTL)) {\n \t\t/*\n \t\t * Check that vxlan proto is included and vxlan decap\n \t\t * action is not set then decrement tunnel ttl.\n@@ -283,7 +283,7 @@ ulp_post_process_normal_flow(struct ulp_rte_parser_params *params)\n \t\tif ((ULP_BITMAP_ISSET(params->hdr_bitmap.bits,\n \t\t\t\t      BNXT_ULP_HDR_BIT_T_VXLAN) &&\n \t\t    !ULP_BITMAP_ISSET(params->act_bitmap.bits,\n-\t\t\t\t      BNXT_ULP_ACTION_BIT_VXLAN_DECAP))) {\n+\t\t\t\t      BNXT_ULP_ACT_BIT_VXLAN_DECAP))) {\n \t\t\tULP_COMP_FLD_IDX_WR(params,\n \t\t\t\t\t    BNXT_ULP_CF_IDX_ACT_T_DEC_TTL, 1);\n \t\t} else {\n@@ -1439,7 +1439,7 @@ ulp_rte_mark_act_handler(const struct rte_flow_action *action_item,\n \t\t       &mark_id, BNXT_ULP_ACT_PROP_SZ_MARK);\n \n \t\t/* Update the hdr_bitmap with vxlan */\n-\t\tULP_BITMAP_SET(act->bits, BNXT_ULP_ACTION_BIT_MARK);\n+\t\tULP_BITMAP_SET(act->bits, BNXT_ULP_ACT_BIT_MARK);\n \t\treturn BNXT_TF_RC_SUCCESS;\n \t}\n \tBNXT_TF_DBG(ERR, \"Parse Error: Mark arg is invalid\\n\");\n@@ -1455,7 +1455,7 @@ ulp_rte_rss_act_handler(const struct rte_flow_action *action_item,\n \n \tif (rss) {\n \t\t/* Update the hdr_bitmap with vxlan */\n-\t\tULP_BITMAP_SET(param->act_bitmap.bits, BNXT_ULP_ACTION_BIT_RSS);\n+\t\tULP_BITMAP_SET(param->act_bitmap.bits, BNXT_ULP_ACT_BIT_RSS);\n \t\treturn BNXT_TF_RC_SUCCESS;\n \t}\n \tBNXT_TF_DBG(ERR, \"Parse Error: RSS arg is invalid\\n\");\n@@ -1728,7 +1728,7 @@ ulp_rte_vxlan_encap_act_handler(const struct rte_flow_action *action_item,\n \t       &vxlan_size, sizeof(uint32_t));\n \n \t/* update the hdr_bitmap with vxlan */\n-\tULP_BITMAP_SET(act->bits, BNXT_ULP_ACTION_BIT_VXLAN_ENCAP);\n+\tULP_BITMAP_SET(act->bits, BNXT_ULP_ACT_BIT_VXLAN_ENCAP);\n \treturn BNXT_TF_RC_SUCCESS;\n }\n \n@@ -1740,7 +1740,7 @@ ulp_rte_vxlan_decap_act_handler(const struct rte_flow_action *action_item\n {\n \t/* update the hdr_bitmap with vxlan */\n \tULP_BITMAP_SET(params->act_bitmap.bits,\n-\t\t       BNXT_ULP_ACTION_BIT_VXLAN_DECAP);\n+\t\t       BNXT_ULP_ACT_BIT_VXLAN_DECAP);\n \t/* Update computational field with tunnel decap info */\n \tULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_L3_TUN_DECAP, 1);\n \tULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_L3_TUN, 1);\n@@ -1753,7 +1753,7 @@ ulp_rte_drop_act_handler(const struct rte_flow_action *action_item __rte_unused,\n \t\t\t struct ulp_rte_parser_params *params)\n {\n \t/* Update the hdr_bitmap with drop */\n-\tULP_BITMAP_SET(params->act_bitmap.bits, BNXT_ULP_ACTION_BIT_DROP);\n+\tULP_BITMAP_SET(params->act_bitmap.bits, BNXT_ULP_ACT_BIT_DROP);\n \treturn BNXT_TF_RC_SUCCESS;\n }\n \n@@ -1779,7 +1779,7 @@ ulp_rte_count_act_handler(const struct rte_flow_action *action_item,\n \t}\n \n \t/* Update the hdr_bitmap with count */\n-\tULP_BITMAP_SET(params->act_bitmap.bits, BNXT_ULP_ACTION_BIT_COUNT);\n+\tULP_BITMAP_SET(params->act_bitmap.bits, BNXT_ULP_ACT_BIT_COUNT);\n \treturn BNXT_TF_RC_SUCCESS;\n }\n \n@@ -1992,7 +1992,7 @@ ulp_rte_of_pop_vlan_act_handler(const struct rte_flow_action *a __rte_unused,\n \t\t\t\tstruct ulp_rte_parser_params *params)\n {\n \t/* Update the act_bitmap with pop */\n-\tULP_BITMAP_SET(params->act_bitmap.bits, BNXT_ULP_ACTION_BIT_POP_VLAN);\n+\tULP_BITMAP_SET(params->act_bitmap.bits, BNXT_ULP_ACT_BIT_POP_VLAN);\n \treturn BNXT_TF_RC_SUCCESS;\n }\n \n@@ -2017,7 +2017,7 @@ ulp_rte_of_push_vlan_act_handler(const struct rte_flow_action *action_item,\n \t\t       &ethertype, BNXT_ULP_ACT_PROP_SZ_PUSH_VLAN);\n \t\t/* Update the hdr_bitmap with push vlan */\n \t\tULP_BITMAP_SET(params->act_bitmap.bits,\n-\t\t\t       BNXT_ULP_ACTION_BIT_PUSH_VLAN);\n+\t\t\t       BNXT_ULP_ACT_BIT_PUSH_VLAN);\n \t\treturn BNXT_TF_RC_SUCCESS;\n \t}\n \tBNXT_TF_DBG(ERR, \"Parse Error: Push vlan arg is invalid\\n\");\n@@ -2040,7 +2040,7 @@ ulp_rte_of_set_vlan_vid_act_handler(const struct rte_flow_action *action_item,\n \t\t       &vid, BNXT_ULP_ACT_PROP_SZ_SET_VLAN_VID);\n \t\t/* Update the hdr_bitmap with vlan vid */\n \t\tULP_BITMAP_SET(params->act_bitmap.bits,\n-\t\t\t       BNXT_ULP_ACTION_BIT_SET_VLAN_VID);\n+\t\t\t       BNXT_ULP_ACT_BIT_SET_VLAN_VID);\n \t\treturn BNXT_TF_RC_SUCCESS;\n \t}\n \tBNXT_TF_DBG(ERR, \"Parse Error: Vlan vid arg is invalid\\n\");\n@@ -2063,7 +2063,7 @@ ulp_rte_of_set_vlan_pcp_act_handler(const struct rte_flow_action *action_item,\n \t\t       &pcp, BNXT_ULP_ACT_PROP_SZ_SET_VLAN_PCP);\n \t\t/* Update the hdr_bitmap with vlan vid */\n \t\tULP_BITMAP_SET(params->act_bitmap.bits,\n-\t\t\t       BNXT_ULP_ACTION_BIT_SET_VLAN_PCP);\n+\t\t\t       BNXT_ULP_ACT_BIT_SET_VLAN_PCP);\n \t\treturn BNXT_TF_RC_SUCCESS;\n \t}\n \tBNXT_TF_DBG(ERR, \"Parse Error: Vlan pcp arg is invalid\\n\");\n@@ -2084,7 +2084,7 @@ ulp_rte_set_ipv4_src_act_handler(const struct rte_flow_action *action_item,\n \t\t       &set_ipv4->ipv4_addr, BNXT_ULP_ACT_PROP_SZ_SET_IPV4_SRC);\n \t\t/* Update the hdr_bitmap with set ipv4 src */\n \t\tULP_BITMAP_SET(params->act_bitmap.bits,\n-\t\t\t       BNXT_ULP_ACTION_BIT_SET_IPV4_SRC);\n+\t\t\t       BNXT_ULP_ACT_BIT_SET_IPV4_SRC);\n \t\treturn BNXT_TF_RC_SUCCESS;\n \t}\n \tBNXT_TF_DBG(ERR, \"Parse Error: set ipv4 src arg is invalid\\n\");\n@@ -2105,7 +2105,7 @@ ulp_rte_set_ipv4_dst_act_handler(const struct rte_flow_action *action_item,\n \t\t       &set_ipv4->ipv4_addr, BNXT_ULP_ACT_PROP_SZ_SET_IPV4_DST);\n \t\t/* Update the hdr_bitmap with set ipv4 dst */\n \t\tULP_BITMAP_SET(params->act_bitmap.bits,\n-\t\t\t       BNXT_ULP_ACTION_BIT_SET_IPV4_DST);\n+\t\t\t       BNXT_ULP_ACT_BIT_SET_IPV4_DST);\n \t\treturn BNXT_TF_RC_SUCCESS;\n \t}\n \tBNXT_TF_DBG(ERR, \"Parse Error: set ipv4 dst arg is invalid\\n\");\n@@ -2126,7 +2126,7 @@ ulp_rte_set_tp_src_act_handler(const struct rte_flow_action *action_item,\n \t\t       &set_tp->port, BNXT_ULP_ACT_PROP_SZ_SET_TP_SRC);\n \t\t/* Update the hdr_bitmap with set tp src */\n \t\tULP_BITMAP_SET(params->act_bitmap.bits,\n-\t\t\t       BNXT_ULP_ACTION_BIT_SET_TP_SRC);\n+\t\t\t       BNXT_ULP_ACT_BIT_SET_TP_SRC);\n \t\treturn BNXT_TF_RC_SUCCESS;\n \t}\n \n@@ -2148,7 +2148,7 @@ ulp_rte_set_tp_dst_act_handler(const struct rte_flow_action *action_item,\n \t\t       &set_tp->port, BNXT_ULP_ACT_PROP_SZ_SET_TP_DST);\n \t\t/* Update the hdr_bitmap with set tp dst */\n \t\tULP_BITMAP_SET(params->act_bitmap.bits,\n-\t\t\t       BNXT_ULP_ACTION_BIT_SET_TP_DST);\n+\t\t\t       BNXT_ULP_ACT_BIT_SET_TP_DST);\n \t\treturn BNXT_TF_RC_SUCCESS;\n \t}\n \n@@ -2162,7 +2162,7 @@ ulp_rte_dec_ttl_act_handler(const struct rte_flow_action *act __rte_unused,\n \t\t\t    struct ulp_rte_parser_params *params)\n {\n \t/* Update the act_bitmap with dec ttl */\n-\tULP_BITMAP_SET(params->act_bitmap.bits, BNXT_ULP_ACTION_BIT_DEC_TTL);\n+\tULP_BITMAP_SET(params->act_bitmap.bits, BNXT_ULP_ACT_BIT_DEC_TTL);\n \treturn BNXT_TF_RC_SUCCESS;\n }\n \n@@ -2172,6 +2172,6 @@ ulp_rte_jump_act_handler(const struct rte_flow_action *action_item __rte_unused,\n \t\t\t    struct ulp_rte_parser_params *params)\n {\n \t/* Update the act_bitmap with dec ttl */\n-\tULP_BITMAP_SET(params->act_bitmap.bits, BNXT_ULP_ACTION_BIT_JUMP);\n+\tULP_BITMAP_SET(params->act_bitmap.bits, BNXT_ULP_ACT_BIT_JUMP);\n \treturn BNXT_TF_RC_SUCCESS;\n }\ndiff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c\nindex 509cbd26a8..fa7d67bcd0 100644\n--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c\n+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c\n@@ -3,7 +3,7 @@\n  * All rights reserved.\n  */\n \n-/* date: Mon Nov 23 17:33:02 2020 */\n+/* date: Tue Dec  1 11:40:24 2020 */\n \n #include \"ulp_template_db_enum.h\"\n #include \"ulp_template_db_field.h\"\n@@ -42,101 +42,101 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {\n \t[2] = {\n \t.act_hid = BNXT_ULP_ACT_HID_0001,\n \t.act_sig = { .bits =\n-\t\tBNXT_ULP_ACTION_BIT_DROP |\n+\t\tBNXT_ULP_ACT_BIT_DROP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.act_tid = 1\n \t},\n \t[3] = {\n \t.act_hid = BNXT_ULP_ACT_HID_0400,\n \t.act_sig = { .bits =\n-\t\tBNXT_ULP_ACTION_BIT_POP_VLAN |\n+\t\tBNXT_ULP_ACT_BIT_POP_VLAN |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.act_tid = 1\n \t},\n \t[4] = {\n \t.act_hid = BNXT_ULP_ACT_HID_0331,\n \t.act_sig = { .bits =\n-\t\tBNXT_ULP_ACTION_BIT_DEC_TTL |\n+\t\tBNXT_ULP_ACT_BIT_DEC_TTL |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.act_tid = 1\n \t},\n \t[5] = {\n \t.act_hid = BNXT_ULP_ACT_HID_0010,\n \t.act_sig = { .bits =\n-\t\tBNXT_ULP_ACTION_BIT_VXLAN_DECAP |\n+\t\tBNXT_ULP_ACT_BIT_VXLAN_DECAP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.act_tid = 1\n \t},\n \t[6] = {\n \t.act_hid = BNXT_ULP_ACT_HID_0731,\n \t.act_sig = { .bits =\n-\t\tBNXT_ULP_ACTION_BIT_DEC_TTL |\n-\t\tBNXT_ULP_ACTION_BIT_POP_VLAN |\n+\t\tBNXT_ULP_ACT_BIT_DEC_TTL |\n+\t\tBNXT_ULP_ACT_BIT_POP_VLAN |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.act_tid = 1\n \t},\n \t[7] = {\n \t.act_hid = BNXT_ULP_ACT_HID_0341,\n \t.act_sig = { .bits =\n-\t\tBNXT_ULP_ACTION_BIT_VXLAN_DECAP |\n-\t\tBNXT_ULP_ACTION_BIT_DEC_TTL |\n+\t\tBNXT_ULP_ACT_BIT_VXLAN_DECAP |\n+\t\tBNXT_ULP_ACT_BIT_DEC_TTL |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.act_tid = 1\n \t},\n \t[8] = {\n \t.act_hid = BNXT_ULP_ACT_HID_0002,\n \t.act_sig = { .bits =\n-\t\tBNXT_ULP_ACTION_BIT_COUNT |\n+\t\tBNXT_ULP_ACT_BIT_COUNT |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.act_tid = 1\n \t},\n \t[9] = {\n \t.act_hid = BNXT_ULP_ACT_HID_0003,\n \t.act_sig = { .bits =\n-\t\tBNXT_ULP_ACTION_BIT_COUNT |\n-\t\tBNXT_ULP_ACTION_BIT_DROP |\n+\t\tBNXT_ULP_ACT_BIT_COUNT |\n+\t\tBNXT_ULP_ACT_BIT_DROP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.act_tid = 1\n \t},\n \t[10] = {\n \t.act_hid = BNXT_ULP_ACT_HID_0402,\n \t.act_sig = { .bits =\n-\t\tBNXT_ULP_ACTION_BIT_COUNT |\n-\t\tBNXT_ULP_ACTION_BIT_POP_VLAN |\n+\t\tBNXT_ULP_ACT_BIT_COUNT |\n+\t\tBNXT_ULP_ACT_BIT_POP_VLAN |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.act_tid = 1\n \t},\n \t[11] = {\n \t.act_hid = BNXT_ULP_ACT_HID_0333,\n \t.act_sig = { .bits =\n-\t\tBNXT_ULP_ACTION_BIT_COUNT |\n-\t\tBNXT_ULP_ACTION_BIT_DEC_TTL |\n+\t\tBNXT_ULP_ACT_BIT_COUNT |\n+\t\tBNXT_ULP_ACT_BIT_DEC_TTL |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.act_tid = 1\n \t},\n \t[12] = {\n \t.act_hid = BNXT_ULP_ACT_HID_0012,\n \t.act_sig = { .bits =\n-\t\tBNXT_ULP_ACTION_BIT_COUNT |\n-\t\tBNXT_ULP_ACTION_BIT_VXLAN_DECAP |\n+\t\tBNXT_ULP_ACT_BIT_COUNT |\n+\t\tBNXT_ULP_ACT_BIT_VXLAN_DECAP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.act_tid = 1\n \t},\n \t[13] = {\n \t.act_hid = BNXT_ULP_ACT_HID_0733,\n \t.act_sig = { .bits =\n-\t\tBNXT_ULP_ACTION_BIT_COUNT |\n-\t\tBNXT_ULP_ACTION_BIT_DEC_TTL |\n-\t\tBNXT_ULP_ACTION_BIT_POP_VLAN |\n+\t\tBNXT_ULP_ACT_BIT_COUNT |\n+\t\tBNXT_ULP_ACT_BIT_DEC_TTL |\n+\t\tBNXT_ULP_ACT_BIT_POP_VLAN |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.act_tid = 1\n \t},\n \t[14] = {\n \t.act_hid = BNXT_ULP_ACT_HID_0343,\n \t.act_sig = { .bits =\n-\t\tBNXT_ULP_ACTION_BIT_COUNT |\n-\t\tBNXT_ULP_ACTION_BIT_VXLAN_DECAP |\n-\t\tBNXT_ULP_ACTION_BIT_DEC_TTL |\n+\t\tBNXT_ULP_ACT_BIT_COUNT |\n+\t\tBNXT_ULP_ACT_BIT_VXLAN_DECAP |\n+\t\tBNXT_ULP_ACT_BIT_DEC_TTL |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.act_tid = 1\n \t}\ndiff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c\nindex 38f523aa7a..a5133f7caf 100644\n--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c\n+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c\n@@ -3,7 +3,7 @@\n  * All rights reserved.\n  */\n \n-/* date: Mon Nov 23 17:33:02 2020 */\n+/* date: Tue Dec  1 11:40:24 2020 */\n \n #include \"ulp_template_db_enum.h\"\n #include \"ulp_template_db_field.h\"\n@@ -16,837 +16,1450 @@\n  * maps hash id to ulp_class_match_list[] index\n  */\n uint16_t ulp_class_sig_tbl[BNXT_ULP_CLASS_SIG_TBL_MAX_SZ] = {\n-\t[BNXT_ULP_CLASS_HID_00fc] = 1,\n-\t[BNXT_ULP_CLASS_HID_0046] = 2,\n-\t[BNXT_ULP_CLASS_HID_0056] = 3,\n-\t[BNXT_ULP_CLASS_HID_00b8] = 4,\n-\t[BNXT_ULP_CLASS_HID_0041] = 5,\n-\t[BNXT_ULP_CLASS_HID_00ab] = 6,\n-\t[BNXT_ULP_CLASS_HID_0053] = 7,\n-\t[BNXT_ULP_CLASS_HID_00a5] = 8,\n-\t[BNXT_ULP_CLASS_HID_0069] = 9,\n-\t[BNXT_ULP_CLASS_HID_009d] = 10,\n-\t[BNXT_ULP_CLASS_HID_0005] = 11,\n-\t[BNXT_ULP_CLASS_HID_006f] = 12,\n-\t[BNXT_ULP_CLASS_HID_00af] = 13,\n-\t[BNXT_ULP_CLASS_HID_00d3] = 14,\n-\t[BNXT_ULP_CLASS_HID_005b] = 15,\n-\t[BNXT_ULP_CLASS_HID_00ad] = 16,\n-\t[BNXT_ULP_CLASS_HID_0091] = 17,\n-\t[BNXT_ULP_CLASS_HID_00fb] = 18,\n-\t[BNXT_ULP_CLASS_HID_0063] = 19,\n-\t[BNXT_ULP_CLASS_HID_0097] = 20,\n-\t[BNXT_ULP_CLASS_HID_00cc] = 21,\n-\t[BNXT_ULP_CLASS_HID_00f0] = 22,\n-\t[BNXT_ULP_CLASS_HID_00c0] = 23,\n-\t[BNXT_ULP_CLASS_HID_002a] = 24,\n-\t[BNXT_ULP_CLASS_HID_00c7] = 25,\n-\t[BNXT_ULP_CLASS_HID_0029] = 26,\n-\t[BNXT_ULP_CLASS_HID_00d1] = 27,\n-\t[BNXT_ULP_CLASS_HID_003b] = 28,\n-\t[BNXT_ULP_CLASS_HID_00ef] = 29,\n-\t[BNXT_ULP_CLASS_HID_0013] = 30,\n-\t[BNXT_ULP_CLASS_HID_009b] = 31,\n-\t[BNXT_ULP_CLASS_HID_00ed] = 32,\n-\t[BNXT_ULP_CLASS_HID_002d] = 33,\n-\t[BNXT_ULP_CLASS_HID_0051] = 34,\n-\t[BNXT_ULP_CLASS_HID_00d9] = 35,\n-\t[BNXT_ULP_CLASS_HID_0023] = 36,\n-\t[BNXT_ULP_CLASS_HID_0017] = 37,\n-\t[BNXT_ULP_CLASS_HID_0079] = 38,\n-\t[BNXT_ULP_CLASS_HID_00e1] = 39,\n-\t[BNXT_ULP_CLASS_HID_0015] = 40\n+\t[BNXT_ULP_CLASS_HID_07e0] = 1,\n+\t[BNXT_ULP_CLASS_HID_01dc] = 2,\n+\t[BNXT_ULP_CLASS_HID_006e] = 3,\n+\t[BNXT_ULP_CLASS_HID_025a] = 4,\n+\t[BNXT_ULP_CLASS_HID_0146] = 5,\n+\t[BNXT_ULP_CLASS_HID_0332] = 6,\n+\t[BNXT_ULP_CLASS_HID_01c4] = 7,\n+\t[BNXT_ULP_CLASS_HID_078a] = 8,\n+\t[BNXT_ULP_CLASS_HID_02ed] = 9,\n+\t[BNXT_ULP_CLASS_HID_04d9] = 10,\n+\t[BNXT_ULP_CLASS_HID_036b] = 11,\n+\t[BNXT_ULP_CLASS_HID_0131] = 12,\n+\t[BNXT_ULP_CLASS_HID_0217] = 13,\n+\t[BNXT_ULP_CLASS_HID_03c3] = 14,\n+\t[BNXT_ULP_CLASS_HID_0295] = 15,\n+\t[BNXT_ULP_CLASS_HID_0441] = 16,\n+\t[BNXT_ULP_CLASS_HID_0095] = 17,\n+\t[BNXT_ULP_CLASS_HID_0241] = 18,\n+\t[BNXT_ULP_CLASS_HID_04ed] = 19,\n+\t[BNXT_ULP_CLASS_HID_06d9] = 20,\n+\t[BNXT_ULP_CLASS_HID_07bf] = 21,\n+\t[BNXT_ULP_CLASS_HID_016b] = 22,\n+\t[BNXT_ULP_CLASS_HID_0417] = 23,\n+\t[BNXT_ULP_CLASS_HID_05c3] = 24,\n+\t[BNXT_ULP_CLASS_HID_0187] = 25,\n+\t[BNXT_ULP_CLASS_HID_0373] = 26,\n+\t[BNXT_ULP_CLASS_HID_0205] = 27,\n+\t[BNXT_ULP_CLASS_HID_03f1] = 28,\n+\t[BNXT_ULP_CLASS_HID_00a1] = 29,\n+\t[BNXT_ULP_CLASS_HID_029d] = 30,\n+\t[BNXT_ULP_CLASS_HID_012f] = 31,\n+\t[BNXT_ULP_CLASS_HID_031b] = 32,\n+\t[BNXT_ULP_CLASS_HID_072f] = 33,\n+\t[BNXT_ULP_CLASS_HID_011b] = 34,\n+\t[BNXT_ULP_CLASS_HID_0387] = 35,\n+\t[BNXT_ULP_CLASS_HID_0573] = 36,\n+\t[BNXT_ULP_CLASS_HID_0649] = 37,\n+\t[BNXT_ULP_CLASS_HID_0005] = 38,\n+\t[BNXT_ULP_CLASS_HID_02a1] = 39,\n+\t[BNXT_ULP_CLASS_HID_049d] = 40,\n+\t[BNXT_ULP_CLASS_HID_01ea] = 41,\n+\t[BNXT_ULP_CLASS_HID_03de] = 42,\n+\t[BNXT_ULP_CLASS_HID_0672] = 43,\n+\t[BNXT_ULP_CLASS_HID_0026] = 44,\n+\t[BNXT_ULP_CLASS_HID_0746] = 45,\n+\t[BNXT_ULP_CLASS_HID_010a] = 46,\n+\t[BNXT_ULP_CLASS_HID_03ae] = 47,\n+\t[BNXT_ULP_CLASS_HID_0592] = 48,\n+\t[BNXT_ULP_CLASS_HID_07d0] = 49,\n+\t[BNXT_ULP_CLASS_HID_01ec] = 50,\n+\t[BNXT_ULP_CLASS_HID_005e] = 51,\n+\t[BNXT_ULP_CLASS_HID_026a] = 52,\n+\t[BNXT_ULP_CLASS_HID_0176] = 53,\n+\t[BNXT_ULP_CLASS_HID_0302] = 54,\n+\t[BNXT_ULP_CLASS_HID_01f4] = 55,\n+\t[BNXT_ULP_CLASS_HID_07ba] = 56,\n+\t[BNXT_ULP_CLASS_HID_06a7] = 57,\n+\t[BNXT_ULP_CLASS_HID_006b] = 58,\n+\t[BNXT_ULP_CLASS_HID_0725] = 59,\n+\t[BNXT_ULP_CLASS_HID_00e9] = 60,\n+\t[BNXT_ULP_CLASS_HID_05d9] = 61,\n+\t[BNXT_ULP_CLASS_HID_078d] = 62,\n+\t[BNXT_ULP_CLASS_HID_065f] = 63,\n+\t[BNXT_ULP_CLASS_HID_0003] = 64,\n+\t[BNXT_ULP_CLASS_HID_045f] = 65,\n+\t[BNXT_ULP_CLASS_HID_0603] = 66,\n+\t[BNXT_ULP_CLASS_HID_00a7] = 67,\n+\t[BNXT_ULP_CLASS_HID_026b] = 68,\n+\t[BNXT_ULP_CLASS_HID_0371] = 69,\n+\t[BNXT_ULP_CLASS_HID_0525] = 70,\n+\t[BNXT_ULP_CLASS_HID_07d9] = 71,\n+\t[BNXT_ULP_CLASS_HID_018d] = 72,\n+\t[BNXT_ULP_CLASS_HID_0177] = 73,\n+\t[BNXT_ULP_CLASS_HID_033b] = 74,\n+\t[BNXT_ULP_CLASS_HID_05df] = 75,\n+\t[BNXT_ULP_CLASS_HID_0783] = 76,\n+\t[BNXT_ULP_CLASS_HID_0069] = 77,\n+\t[BNXT_ULP_CLASS_HID_025d] = 78,\n+\t[BNXT_ULP_CLASS_HID_00ef] = 79,\n+\t[BNXT_ULP_CLASS_HID_06a5] = 80,\n+\t[BNXT_ULP_CLASS_HID_02f1] = 81,\n+\t[BNXT_ULP_CLASS_HID_04a5] = 82,\n+\t[BNXT_ULP_CLASS_HID_0377] = 83,\n+\t[BNXT_ULP_CLASS_HID_053b] = 84,\n+\t[BNXT_ULP_CLASS_HID_0601] = 85,\n+\t[BNXT_ULP_CLASS_HID_03df] = 86,\n+\t[BNXT_ULP_CLASS_HID_0269] = 87,\n+\t[BNXT_ULP_CLASS_HID_045d] = 88,\n+\t[BNXT_ULP_CLASS_HID_02dd] = 89,\n+\t[BNXT_ULP_CLASS_HID_04e9] = 90,\n+\t[BNXT_ULP_CLASS_HID_035b] = 91,\n+\t[BNXT_ULP_CLASS_HID_0101] = 92,\n+\t[BNXT_ULP_CLASS_HID_0227] = 93,\n+\t[BNXT_ULP_CLASS_HID_03f3] = 94,\n+\t[BNXT_ULP_CLASS_HID_02a5] = 95,\n+\t[BNXT_ULP_CLASS_HID_0471] = 96,\n+\t[BNXT_ULP_CLASS_HID_00a5] = 97,\n+\t[BNXT_ULP_CLASS_HID_0271] = 98,\n+\t[BNXT_ULP_CLASS_HID_04dd] = 99,\n+\t[BNXT_ULP_CLASS_HID_06e9] = 100,\n+\t[BNXT_ULP_CLASS_HID_078f] = 101,\n+\t[BNXT_ULP_CLASS_HID_015b] = 102,\n+\t[BNXT_ULP_CLASS_HID_0427] = 103,\n+\t[BNXT_ULP_CLASS_HID_05f3] = 104,\n+\t[BNXT_ULP_CLASS_HID_01b7] = 105,\n+\t[BNXT_ULP_CLASS_HID_0343] = 106,\n+\t[BNXT_ULP_CLASS_HID_0235] = 107,\n+\t[BNXT_ULP_CLASS_HID_03c1] = 108,\n+\t[BNXT_ULP_CLASS_HID_0091] = 109,\n+\t[BNXT_ULP_CLASS_HID_02ad] = 110,\n+\t[BNXT_ULP_CLASS_HID_011f] = 111,\n+\t[BNXT_ULP_CLASS_HID_032b] = 112,\n+\t[BNXT_ULP_CLASS_HID_071f] = 113,\n+\t[BNXT_ULP_CLASS_HID_012b] = 114,\n+\t[BNXT_ULP_CLASS_HID_03b7] = 115,\n+\t[BNXT_ULP_CLASS_HID_0543] = 116,\n+\t[BNXT_ULP_CLASS_HID_0679] = 117,\n+\t[BNXT_ULP_CLASS_HID_0035] = 118,\n+\t[BNXT_ULP_CLASS_HID_0291] = 119,\n+\t[BNXT_ULP_CLASS_HID_04ad] = 120,\n+\t[BNXT_ULP_CLASS_HID_01da] = 121,\n+\t[BNXT_ULP_CLASS_HID_03ee] = 122,\n+\t[BNXT_ULP_CLASS_HID_0642] = 123,\n+\t[BNXT_ULP_CLASS_HID_0016] = 124,\n+\t[BNXT_ULP_CLASS_HID_0776] = 125,\n+\t[BNXT_ULP_CLASS_HID_013a] = 126,\n+\t[BNXT_ULP_CLASS_HID_039e] = 127,\n+\t[BNXT_ULP_CLASS_HID_05a2] = 128,\n+\t[BNXT_ULP_CLASS_HID_0697] = 129,\n+\t[BNXT_ULP_CLASS_HID_005b] = 130,\n+\t[BNXT_ULP_CLASS_HID_0715] = 131,\n+\t[BNXT_ULP_CLASS_HID_00d9] = 132,\n+\t[BNXT_ULP_CLASS_HID_05e9] = 133,\n+\t[BNXT_ULP_CLASS_HID_07bd] = 134,\n+\t[BNXT_ULP_CLASS_HID_066f] = 135,\n+\t[BNXT_ULP_CLASS_HID_0033] = 136,\n+\t[BNXT_ULP_CLASS_HID_046f] = 137,\n+\t[BNXT_ULP_CLASS_HID_0633] = 138,\n+\t[BNXT_ULP_CLASS_HID_0097] = 139,\n+\t[BNXT_ULP_CLASS_HID_025b] = 140,\n+\t[BNXT_ULP_CLASS_HID_0341] = 141,\n+\t[BNXT_ULP_CLASS_HID_0515] = 142,\n+\t[BNXT_ULP_CLASS_HID_07e9] = 143,\n+\t[BNXT_ULP_CLASS_HID_01bd] = 144,\n+\t[BNXT_ULP_CLASS_HID_0147] = 145,\n+\t[BNXT_ULP_CLASS_HID_030b] = 146,\n+\t[BNXT_ULP_CLASS_HID_05ef] = 147,\n+\t[BNXT_ULP_CLASS_HID_07b3] = 148,\n+\t[BNXT_ULP_CLASS_HID_0059] = 149,\n+\t[BNXT_ULP_CLASS_HID_026d] = 150,\n+\t[BNXT_ULP_CLASS_HID_00df] = 151,\n+\t[BNXT_ULP_CLASS_HID_0695] = 152,\n+\t[BNXT_ULP_CLASS_HID_02c1] = 153,\n+\t[BNXT_ULP_CLASS_HID_0495] = 154,\n+\t[BNXT_ULP_CLASS_HID_0347] = 155,\n+\t[BNXT_ULP_CLASS_HID_050b] = 156,\n+\t[BNXT_ULP_CLASS_HID_0631] = 157,\n+\t[BNXT_ULP_CLASS_HID_03ef] = 158,\n+\t[BNXT_ULP_CLASS_HID_0259] = 159,\n+\t[BNXT_ULP_CLASS_HID_046d] = 160\n };\n \n /* Array for the proto matcher list */\n struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t[1] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_00fc,\n+\t.class_hid = BNXT_ULP_CLASS_HID_07e0,\n \t.class_tid = 1,\n \t.hdr_sig_id = 0,\n \t.flow_sig_id = 0,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF1_0_BITMASK_O_TCP_SRC_PORT |\n \t\tBNXT_ULP_HF1_0_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[2] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0046,\n+\t.class_hid = BNXT_ULP_CLASS_HID_01dc,\n \t.class_tid = 1,\n \t.hdr_sig_id = 0,\n \t.flow_sig_id = 1,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE |\n \t\tBNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF1_0_BITMASK_O_TCP_SRC_PORT |\n \t\tBNXT_ULP_HF1_0_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[3] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0056,\n+\t.class_hid = BNXT_ULP_CLASS_HID_006e,\n \t.class_tid = 1,\n \t.hdr_sig_id = 0,\n-\t.flow_sig_id = 1,\n+\t.flow_sig_id = 2,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_PROTO_ID |\n-\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF1_0_BITMASK_O_TCP_SRC_PORT |\n \t\tBNXT_ULP_HF1_0_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[4] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_00b8,\n+\t.class_hid = BNXT_ULP_CLASS_HID_025a,\n \t.class_tid = 1,\n \t.hdr_sig_id = 0,\n-\t.flow_sig_id = 1,\n+\t.flow_sig_id = 2,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE |\n \t\tBNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_PROTO_ID |\n-\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF1_0_BITMASK_O_TCP_SRC_PORT |\n \t\tBNXT_ULP_HF1_0_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[5] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0041,\n+\t.class_hid = BNXT_ULP_CLASS_HID_0146,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 1,\n-\t.flow_sig_id = 1,\n+\t.hdr_sig_id = 0,\n+\t.flow_sig_id = 2,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[6] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_00ab,\n+\t.class_hid = BNXT_ULP_CLASS_HID_0332,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 1,\n-\t.flow_sig_id = 1,\n+\t.hdr_sig_id = 0,\n+\t.flow_sig_id = 2,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[7] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0053,\n+\t.class_hid = BNXT_ULP_CLASS_HID_01c4,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 1,\n-\t.flow_sig_id = 1,\n+\t.hdr_sig_id = 0,\n+\t.flow_sig_id = 2,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[8] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_00a5,\n+\t.class_hid = BNXT_ULP_CLASS_HID_078a,\n \t.class_tid = 1,\n-\t.hdr_sig_id = 1,\n+\t.hdr_sig_id = 0,\n \t.flow_sig_id = 2,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_0_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[9] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0069,\n+\t.class_hid = BNXT_ULP_CLASS_HID_02ed,\n \t.class_tid = 1,\n \t.hdr_sig_id = 1,\n \t.flow_sig_id = 2,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n \t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[10] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_009d,\n+\t.class_hid = BNXT_ULP_CLASS_HID_04d9,\n \t.class_tid = 1,\n \t.hdr_sig_id = 1,\n \t.flow_sig_id = 2,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n \t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n \t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[11] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0005,\n+\t.class_hid = BNXT_ULP_CLASS_HID_036b,\n \t.class_tid = 1,\n \t.hdr_sig_id = 1,\n \t.flow_sig_id = 2,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n \t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[12] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_006f,\n+\t.class_hid = BNXT_ULP_CLASS_HID_0131,\n \t.class_tid = 1,\n \t.hdr_sig_id = 1,\n \t.flow_sig_id = 2,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n \t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n \t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[13] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_00af,\n+\t.class_hid = BNXT_ULP_CLASS_HID_0217,\n \t.class_tid = 1,\n \t.hdr_sig_id = 1,\n \t.flow_sig_id = 2,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n \t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[14] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_00d3,\n+\t.class_hid = BNXT_ULP_CLASS_HID_03c3,\n \t.class_tid = 1,\n \t.hdr_sig_id = 1,\n-\t.flow_sig_id = 2,\n+\t.flow_sig_id = 3,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n \t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n \t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[15] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_005b,\n+\t.class_hid = BNXT_ULP_CLASS_HID_0295,\n \t.class_tid = 1,\n \t.hdr_sig_id = 1,\n-\t.flow_sig_id = 2,\n+\t.flow_sig_id = 4,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n \t\tBNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n \t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[16] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_00ad,\n+\t.class_hid = BNXT_ULP_CLASS_HID_0441,\n \t.class_tid = 1,\n \t.hdr_sig_id = 1,\n-\t.flow_sig_id = 2,\n+\t.flow_sig_id = 4,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n \t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n \t\tBNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n \t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[17] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0091,\n+\t.class_hid = BNXT_ULP_CLASS_HID_0095,\n \t.class_tid = 1,\n \t.hdr_sig_id = 1,\n-\t.flow_sig_id = 2,\n+\t.flow_sig_id = 4,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n \t\tBNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n \t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[18] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_00fb,\n+\t.class_hid = BNXT_ULP_CLASS_HID_0241,\n \t.class_tid = 1,\n \t.hdr_sig_id = 1,\n-\t.flow_sig_id = 2,\n+\t.flow_sig_id = 4,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n \t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n \t\tBNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n \t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[19] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0063,\n+\t.class_hid = BNXT_ULP_CLASS_HID_04ed,\n \t.class_tid = 1,\n \t.hdr_sig_id = 1,\n-\t.flow_sig_id = 2,\n+\t.flow_sig_id = 4,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n \t\tBNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n \t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[20] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0097,\n+\t.class_hid = BNXT_ULP_CLASS_HID_06d9,\n \t.class_tid = 1,\n \t.hdr_sig_id = 1,\n-\t.flow_sig_id = 2,\n+\t.flow_sig_id = 4,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n \t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n \t\tBNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR |\n-\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |\n \t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n \t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[21] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_00cc,\n-\t.class_tid = 2,\n-\t.hdr_sig_id = 0,\n-\t.flow_sig_id = 2,\n+\t.class_hid = BNXT_ULP_CLASS_HID_07bf,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 4,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF2_0_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF2_0_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[22] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_00f0,\n-\t.class_tid = 2,\n-\t.hdr_sig_id = 0,\n-\t.flow_sig_id = 3,\n+\t.class_hid = BNXT_ULP_CLASS_HID_016b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 4,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF2_0_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF2_0_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[23] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_00c0,\n-\t.class_tid = 2,\n-\t.hdr_sig_id = 0,\n-\t.flow_sig_id = 3,\n+\t.class_hid = BNXT_ULP_CLASS_HID_0417,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 4,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF2_0_BITMASK_O_IPV4_PROTO_ID |\n-\t\tBNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF2_0_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF2_0_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[24] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_002a,\n-\t.class_tid = 2,\n-\t.hdr_sig_id = 0,\n-\t.flow_sig_id = 3,\n+\t.class_hid = BNXT_ULP_CLASS_HID_05c3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 1,\n+\t.flow_sig_id = 4,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF2_0_BITMASK_O_IPV4_PROTO_ID |\n-\t\tBNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF2_0_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF2_0_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[25] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_00c7,\n-\t.class_tid = 2,\n+\t.class_hid = BNXT_ULP_CLASS_HID_0187,\n+\t.class_tid = 1,\n \t.hdr_sig_id = 1,\n-\t.flow_sig_id = 3,\n+\t.flow_sig_id = 4,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[26] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0029,\n-\t.class_tid = 2,\n+\t.class_hid = BNXT_ULP_CLASS_HID_0373,\n+\t.class_tid = 1,\n \t.hdr_sig_id = 1,\n-\t.flow_sig_id = 3,\n+\t.flow_sig_id = 4,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[27] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_00d1,\n-\t.class_tid = 2,\n+\t.class_hid = BNXT_ULP_CLASS_HID_0205,\n+\t.class_tid = 1,\n \t.hdr_sig_id = 1,\n-\t.flow_sig_id = 3,\n+\t.flow_sig_id = 4,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF2_1_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[28] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_003b,\n-\t.class_tid = 2,\n+\t.class_hid = BNXT_ULP_CLASS_HID_03f1,\n+\t.class_tid = 1,\n \t.hdr_sig_id = 1,\n \t.flow_sig_id = 4,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF2_1_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[29] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_00ef,\n-\t.class_tid = 2,\n+\t.class_hid = BNXT_ULP_CLASS_HID_00a1,\n+\t.class_tid = 1,\n \t.hdr_sig_id = 1,\n \t.flow_sig_id = 4,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF2_1_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[30] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0013,\n-\t.class_tid = 2,\n+\t.class_hid = BNXT_ULP_CLASS_HID_029d,\n+\t.class_tid = 1,\n \t.hdr_sig_id = 1,\n \t.flow_sig_id = 4,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF2_1_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[31] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_009b,\n-\t.class_tid = 2,\n+\t.class_hid = BNXT_ULP_CLASS_HID_012f,\n+\t.class_tid = 1,\n \t.hdr_sig_id = 1,\n \t.flow_sig_id = 4,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF2_1_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF2_1_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[32] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_00ed,\n-\t.class_tid = 2,\n+\t.class_hid = BNXT_ULP_CLASS_HID_031b,\n+\t.class_tid = 1,\n \t.hdr_sig_id = 1,\n \t.flow_sig_id = 4,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF2_1_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF2_1_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[33] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_002d,\n-\t.class_tid = 2,\n+\t.class_hid = BNXT_ULP_CLASS_HID_072f,\n+\t.class_tid = 1,\n \t.hdr_sig_id = 1,\n \t.flow_sig_id = 4,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |\n-\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[34] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0051,\n-\t.class_tid = 2,\n+\t.class_hid = BNXT_ULP_CLASS_HID_011b,\n+\t.class_tid = 1,\n \t.hdr_sig_id = 1,\n \t.flow_sig_id = 4,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |\n-\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[35] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_00d9,\n-\t.class_tid = 2,\n+\t.class_hid = BNXT_ULP_CLASS_HID_0387,\n+\t.class_tid = 1,\n \t.hdr_sig_id = 1,\n \t.flow_sig_id = 4,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF2_1_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |\n-\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[36] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0023,\n-\t.class_tid = 2,\n+\t.class_hid = BNXT_ULP_CLASS_HID_0573,\n+\t.class_tid = 1,\n \t.hdr_sig_id = 1,\n \t.flow_sig_id = 4,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF2_1_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |\n-\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[37] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0017,\n-\t.class_tid = 2,\n+\t.class_hid = BNXT_ULP_CLASS_HID_0649,\n+\t.class_tid = 1,\n \t.hdr_sig_id = 1,\n \t.flow_sig_id = 4,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF2_1_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |\n-\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[38] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0079,\n-\t.class_tid = 2,\n+\t.class_hid = BNXT_ULP_CLASS_HID_0005,\n+\t.class_tid = 1,\n \t.hdr_sig_id = 1,\n \t.flow_sig_id = 4,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF2_1_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |\n-\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[39] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_00e1,\n-\t.class_tid = 2,\n+\t.class_hid = BNXT_ULP_CLASS_HID_02a1,\n+\t.class_tid = 1,\n \t.hdr_sig_id = 1,\n \t.flow_sig_id = 4,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n-\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF2_1_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF2_1_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |\n-\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t},\n \t[40] = {\n-\t.class_hid = BNXT_ULP_CLASS_HID_0015,\n-\t.class_tid = 2,\n+\t.class_hid = BNXT_ULP_CLASS_HID_049d,\n+\t.class_tid = 1,\n \t.hdr_sig_id = 1,\n \t.flow_sig_id = 4,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[41] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_01ea,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 4,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[42] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_03de,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 5,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[43] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0672,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 6,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[44] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0026,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 6,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[45] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0746,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 6,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[46] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_010a,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 6,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[47] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_03ae,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 6,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[48] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0592,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 2,\n+\t.flow_sig_id = 6,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_2_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[49] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_07d0,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 6,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[50] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_01ec,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 7,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[51] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_005e,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 8,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[52] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_026a,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 8,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[53] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0176,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 8,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[54] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0302,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 8,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[55] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_01f4,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 8,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[56] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_07ba,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 3,\n+\t.flow_sig_id = 8,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_3_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[57] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_06a7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 8,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[58] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_006b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 8,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[59] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0725,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 8,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[60] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_00e9,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 8,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[61] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_05d9,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 8,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[62] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_078d,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 9,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[63] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_065f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 10,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[64] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0003,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 10,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[65] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_045f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 10,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[66] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0603,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 10,\n \t.hdr_sig = { .bits =\n \t\tBNXT_ULP_HDR_BIT_O_ETH |\n \t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n@@ -854,14 +1467,1933 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {\n \t\tBNXT_ULP_HDR_BIT_O_TCP |\n \t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n \t.field_sig = { .bits =\n-\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE |\n-\t\tBNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC |\n-\t\tBNXT_ULP_HF2_1_BITMASK_OO_VLAN_VID |\n-\t\tBNXT_ULP_HF2_1_BITMASK_OO_VLAN_TYPE |\n-\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID |\n-\t\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR |\n-\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT |\n-\t\tBNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[67] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_00a7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 10,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[68] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_026b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 10,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[69] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0371,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 10,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[70] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0525,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 10,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[71] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_07d9,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 10,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[72] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_018d,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 10,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[73] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0177,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 10,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[74] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_033b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 10,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[75] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_05df,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 10,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[76] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0783,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 10,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[77] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0069,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 10,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[78] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_025d,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 10,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[79] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_00ef,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 10,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[80] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_06a5,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 10,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[81] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_02f1,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 10,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[82] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_04a5,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 10,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[83] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0377,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 10,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[84] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_053b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 10,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[85] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0601,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 10,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[86] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_03df,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 10,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[87] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0269,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 10,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[88] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_045d,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 4,\n+\t.flow_sig_id = 10,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_TCP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[89] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_02dd,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 10,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[90] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_04e9,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 10,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[91] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_035b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 10,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[92] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0101,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 10,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[93] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0227,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 10,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[94] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_03f3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 11,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[95] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_02a5,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 12,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[96] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0471,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 12,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[97] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_00a5,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 12,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[98] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0271,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 12,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[99] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_04dd,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 12,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[100] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_06e9,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 12,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[101] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_078f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 12,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[102] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_015b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 12,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[103] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0427,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 12,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[104] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_05f3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 12,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[105] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_01b7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 12,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[106] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0343,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 12,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[107] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0235,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 12,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[108] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_03c1,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 12,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[109] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0091,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 12,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[110] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_02ad,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 12,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[111] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_011f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 12,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[112] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_032b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 12,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[113] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_071f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 12,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[114] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_012b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 12,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[115] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_03b7,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 12,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[116] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0543,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 12,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[117] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0679,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 12,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[118] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0035,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 12,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[119] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0291,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 12,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[120] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_04ad,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 5,\n+\t.flow_sig_id = 12,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV6 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[121] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_01da,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 12,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[122] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_03ee,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 13,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[123] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0642,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 14,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[124] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0016,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 14,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[125] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0776,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 14,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[126] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_013a,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 14,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[127] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_039e,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 14,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[128] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_05a2,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 6,\n+\t.flow_sig_id = 14,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[129] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0697,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 14,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[130] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_005b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 14,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[131] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0715,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 14,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[132] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_00d9,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 14,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[133] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_05e9,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 14,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[134] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_07bd,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 15,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[135] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_066f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 16,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[136] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0033,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 16,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[137] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_046f,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 16,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[138] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0633,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 16,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[139] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0097,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 16,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[140] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_025b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 16,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[141] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0341,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 16,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[142] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0515,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 16,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[143] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_07e9,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 16,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[144] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_01bd,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 16,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[145] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0147,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 16,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[146] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_030b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 16,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[147] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_05ef,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 16,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[148] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_07b3,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 16,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[149] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0059,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 16,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[150] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_026d,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 16,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[151] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_00df,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 16,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[152] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0695,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 16,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[153] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_02c1,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 16,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[154] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0495,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 16,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[155] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0347,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 16,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[156] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_050b,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 16,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[157] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0631,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 16,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[158] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_03ef,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 16,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[159] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_0259,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 16,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |\n+\t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n+\t},\n+\t[160] = {\n+\t.class_hid = BNXT_ULP_CLASS_HID_046d,\n+\t.class_tid = 1,\n+\t.hdr_sig_id = 7,\n+\t.flow_sig_id = 16,\n+\t.hdr_sig = { .bits =\n+\t\tBNXT_ULP_HDR_BIT_O_ETH |\n+\t\tBNXT_ULP_HDR_BIT_OO_VLAN |\n+\t\tBNXT_ULP_HDR_BIT_O_IPV4 |\n+\t\tBNXT_ULP_HDR_BIT_O_UDP |\n+\t\tBNXT_ULP_FLOW_DIR_BITMASK_ING },\n+\t.field_sig = { .bits =\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT |\n+\t\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT |\n \t\tBNXT_ULP_MATCH_TYPE_BITMASK_EM },\n \t}\n };\ndiff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h\nindex 12d91e6aa4..fc342bef0a 100644\n--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h\n+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h\n@@ -3,7 +3,7 @@\n  * All rights reserved.\n  */\n \n-/* date: Mon Nov 23 17:33:02 2020 */\n+/* date: Tue Dec  1 10:17:11 2020 */\n \n #ifndef ULP_TEMPLATE_DB_H_\n #define ULP_TEMPLATE_DB_H_\n@@ -12,13 +12,13 @@\n #define BNXT_ULP_MAX_NUM_DEVICES 4\n #define BNXT_ULP_LOG2_MAX_NUM_DEV 2\n #define BNXT_ULP_GEN_TBL_MAX_SZ 6\n-#define BNXT_ULP_CLASS_SIG_TBL_MAX_SZ 256\n-#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 41\n-#define BNXT_ULP_CLASS_HID_LOW_PRIME 3793\n+#define BNXT_ULP_CLASS_SIG_TBL_MAX_SZ 2048\n+#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 161\n+#define BNXT_ULP_CLASS_HID_LOW_PRIME 7669\n #define BNXT_ULP_CLASS_HID_HIGH_PRIME 7919\n #define BNXT_ULP_CLASS_HID_SHFTR 24\n #define BNXT_ULP_CLASS_HID_SHFTL 23\n-#define BNXT_ULP_CLASS_HID_MASK 255\n+#define BNXT_ULP_CLASS_HID_MASK 2047\n #define BNXT_ULP_ACT_SIG_TBL_MAX_SZ 2048\n #define BNXT_ULP_ACT_MATCH_LIST_MAX_SZ 15\n #define BNXT_ULP_ACT_HID_LOW_PRIME 7919\n@@ -30,18 +30,18 @@\n #define BNXT_ULP_GLB_TEMPLATE_TBL_MAX_SZ 1\n #define BNXT_ULP_GLB_FIELD_TBL_SHIFT 7\n #define BNXT_ULP_HDR_SIG_ID_SHIFT 4\n-#define BNXT_ULP_GLB_FIELD_TBL_SIZE 4441\n-#define ULP_WH_PLUS_CLASS_TMPL_LIST_SIZE 8\n-#define ULP_WH_PLUS_CLASS_TBL_LIST_SIZE 41\n-#define ULP_WH_PLUS_CLASS_KEY_INFO_LIST_SIZE 273\n-#define ULP_WH_PLUS_CLASS_IDENT_LIST_SIZE 14\n-#define ULP_WH_PLUS_CLASS_RESULT_FIELD_LIST_SIZE 385\n+#define BNXT_ULP_GLB_FIELD_TBL_SIZE 3033\n+#define ULP_WH_PLUS_CLASS_TMPL_LIST_SIZE 7\n+#define ULP_WH_PLUS_CLASS_TBL_LIST_SIZE 38\n+#define ULP_WH_PLUS_CLASS_KEY_INFO_LIST_SIZE 192\n+#define ULP_WH_PLUS_CLASS_IDENT_LIST_SIZE 10\n+#define ULP_WH_PLUS_CLASS_RESULT_FIELD_LIST_SIZE 341\n #define ULP_WH_PLUS_CLASS_COND_LIST_SIZE 10\n-#define ULP_STINGRAY_CLASS_TMPL_LIST_SIZE 8\n-#define ULP_STINGRAY_CLASS_TBL_LIST_SIZE 41\n-#define ULP_STINGRAY_CLASS_KEY_INFO_LIST_SIZE 273\n-#define ULP_STINGRAY_CLASS_IDENT_LIST_SIZE 14\n-#define ULP_STINGRAY_CLASS_RESULT_FIELD_LIST_SIZE 385\n+#define ULP_STINGRAY_CLASS_TMPL_LIST_SIZE 7\n+#define ULP_STINGRAY_CLASS_TBL_LIST_SIZE 38\n+#define ULP_STINGRAY_CLASS_KEY_INFO_LIST_SIZE 192\n+#define ULP_STINGRAY_CLASS_IDENT_LIST_SIZE 10\n+#define ULP_STINGRAY_CLASS_RESULT_FIELD_LIST_SIZE 341\n #define ULP_STINGRAY_CLASS_COND_LIST_SIZE 10\n #define ULP_WH_PLUS_ACT_TMPL_LIST_SIZE 2\n #define ULP_WH_PLUS_ACT_TBL_LIST_SIZE 4\n@@ -56,35 +56,35 @@\n #define ULP_STINGRAY_ACT_RESULT_FIELD_LIST_SIZE 65\n #define ULP_STINGRAY_ACT_COND_LIST_SIZE 2\n \n-enum bnxt_ulp_action_bit {\n-\tBNXT_ULP_ACTION_BIT_MARK             = 0x0000000000000001,\n-\tBNXT_ULP_ACTION_BIT_DROP             = 0x0000000000000002,\n-\tBNXT_ULP_ACTION_BIT_COUNT            = 0x0000000000000004,\n-\tBNXT_ULP_ACTION_BIT_RSS              = 0x0000000000000008,\n-\tBNXT_ULP_ACTION_BIT_METER            = 0x0000000000000010,\n-\tBNXT_ULP_ACTION_BIT_VXLAN_DECAP      = 0x0000000000000020,\n-\tBNXT_ULP_ACTION_BIT_POP_MPLS         = 0x0000000000000040,\n-\tBNXT_ULP_ACTION_BIT_PUSH_MPLS        = 0x0000000000000080,\n-\tBNXT_ULP_ACTION_BIT_MAC_SWAP         = 0x0000000000000100,\n-\tBNXT_ULP_ACTION_BIT_SET_MAC_SRC      = 0x0000000000000200,\n-\tBNXT_ULP_ACTION_BIT_SET_MAC_DST      = 0x0000000000000400,\n-\tBNXT_ULP_ACTION_BIT_POP_VLAN         = 0x0000000000000800,\n-\tBNXT_ULP_ACTION_BIT_PUSH_VLAN        = 0x0000000000001000,\n-\tBNXT_ULP_ACTION_BIT_SET_VLAN_PCP     = 0x0000000000002000,\n-\tBNXT_ULP_ACTION_BIT_SET_VLAN_VID     = 0x0000000000004000,\n-\tBNXT_ULP_ACTION_BIT_SET_IPV4_SRC     = 0x0000000000008000,\n-\tBNXT_ULP_ACTION_BIT_SET_IPV4_DST     = 0x0000000000010000,\n-\tBNXT_ULP_ACTION_BIT_SET_IPV6_SRC     = 0x0000000000020000,\n-\tBNXT_ULP_ACTION_BIT_SET_IPV6_DST     = 0x0000000000040000,\n-\tBNXT_ULP_ACTION_BIT_DEC_TTL          = 0x0000000000080000,\n-\tBNXT_ULP_ACTION_BIT_SET_TP_SRC       = 0x0000000000100000,\n-\tBNXT_ULP_ACTION_BIT_SET_TP_DST       = 0x0000000000200000,\n-\tBNXT_ULP_ACTION_BIT_VXLAN_ENCAP      = 0x0000000000400000,\n-\tBNXT_ULP_ACTION_BIT_JUMP             = 0x0000000000800000,\n-\tBNXT_ULP_ACTION_BIT_SHARED           = 0x0000000001000000,\n-\tBNXT_ULP_ACTION_BIT_SAMPLE           = 0x0000000002000000,\n-\tBNXT_ULP_ACTION_BIT_SHARED_SAMPLE    = 0x0000000004000000,\n-\tBNXT_ULP_ACTION_BIT_LAST             = 0x0000000008000000\n+enum bnxt_ulp_act_bit {\n+\tBNXT_ULP_ACT_BIT_MARK                = 0x0000000000000001,\n+\tBNXT_ULP_ACT_BIT_DROP                = 0x0000000000000002,\n+\tBNXT_ULP_ACT_BIT_COUNT               = 0x0000000000000004,\n+\tBNXT_ULP_ACT_BIT_RSS                 = 0x0000000000000008,\n+\tBNXT_ULP_ACT_BIT_METER               = 0x0000000000000010,\n+\tBNXT_ULP_ACT_BIT_VXLAN_DECAP         = 0x0000000000000020,\n+\tBNXT_ULP_ACT_BIT_POP_MPLS            = 0x0000000000000040,\n+\tBNXT_ULP_ACT_BIT_PUSH_MPLS           = 0x0000000000000080,\n+\tBNXT_ULP_ACT_BIT_MAC_SWAP            = 0x0000000000000100,\n+\tBNXT_ULP_ACT_BIT_SET_MAC_SRC         = 0x0000000000000200,\n+\tBNXT_ULP_ACT_BIT_SET_MAC_DST         = 0x0000000000000400,\n+\tBNXT_ULP_ACT_BIT_POP_VLAN            = 0x0000000000000800,\n+\tBNXT_ULP_ACT_BIT_PUSH_VLAN           = 0x0000000000001000,\n+\tBNXT_ULP_ACT_BIT_SET_VLAN_PCP        = 0x0000000000002000,\n+\tBNXT_ULP_ACT_BIT_SET_VLAN_VID        = 0x0000000000004000,\n+\tBNXT_ULP_ACT_BIT_SET_IPV4_SRC        = 0x0000000000008000,\n+\tBNXT_ULP_ACT_BIT_SET_IPV4_DST        = 0x0000000000010000,\n+\tBNXT_ULP_ACT_BIT_SET_IPV6_SRC        = 0x0000000000020000,\n+\tBNXT_ULP_ACT_BIT_SET_IPV6_DST        = 0x0000000000040000,\n+\tBNXT_ULP_ACT_BIT_DEC_TTL             = 0x0000000000080000,\n+\tBNXT_ULP_ACT_BIT_SET_TP_SRC          = 0x0000000000100000,\n+\tBNXT_ULP_ACT_BIT_SET_TP_DST          = 0x0000000000200000,\n+\tBNXT_ULP_ACT_BIT_VXLAN_ENCAP         = 0x0000000000400000,\n+\tBNXT_ULP_ACT_BIT_JUMP                = 0x0000000000800000,\n+\tBNXT_ULP_ACT_BIT_SHARED              = 0x0000000001000000,\n+\tBNXT_ULP_ACT_BIT_SAMPLE              = 0x0000000002000000,\n+\tBNXT_ULP_ACT_BIT_SHARED_SAMPLE       = 0x0000000004000000,\n+\tBNXT_ULP_ACT_BIT_LAST                = 0x0000000008000000\n };\n \n enum bnxt_ulp_hdr_bit {\n@@ -188,16 +188,16 @@ enum bnxt_ulp_cond_list_opc {\n };\n \n enum bnxt_ulp_cond_opc {\n-\tBNXT_ULP_COND_OPC_COMP_FIELD_IS_SET = 0,\n-\tBNXT_ULP_COND_OPC_COMP_FIELD_NOT_SET = 1,\n-\tBNXT_ULP_COND_OPC_ACTION_BIT_IS_SET = 2,\n-\tBNXT_ULP_COND_OPC_ACTION_BIT_NOT_SET = 3,\n+\tBNXT_ULP_COND_OPC_CF_IS_SET = 0,\n+\tBNXT_ULP_COND_OPC_CF_NOT_SET = 1,\n+\tBNXT_ULP_COND_OPC_ACT_BIT_IS_SET = 2,\n+\tBNXT_ULP_COND_OPC_ACT_BIT_NOT_SET = 3,\n \tBNXT_ULP_COND_OPC_HDR_BIT_IS_SET = 4,\n \tBNXT_ULP_COND_OPC_HDR_BIT_NOT_SET = 5,\n \tBNXT_ULP_COND_OPC_FIELD_BIT_IS_SET = 6,\n \tBNXT_ULP_COND_OPC_FIELD_BIT_NOT_SET = 7,\n-\tBNXT_ULP_COND_OPC_REGFILE_IS_SET = 8,\n-\tBNXT_ULP_COND_OPC_REGFILE_NOT_SET = 9,\n+\tBNXT_ULP_COND_OPC_RF_IS_SET = 8,\n+\tBNXT_ULP_COND_OPC_RF_NOT_SET = 9,\n \tBNXT_ULP_COND_OPC_LAST = 10\n };\n \n@@ -241,26 +241,31 @@ enum bnxt_ulp_fdb_type {\n \tBNXT_ULP_FDB_TYPE_LAST = 3\n };\n \n-enum bnxt_ulp_field_opc {\n-\tBNXT_ULP_FIELD_OPC_SET_TO_CONSTANT = 0,\n-\tBNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD = 1,\n-\tBNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD = 2,\n-\tBNXT_ULP_FIELD_OPC_SET_TO_REGFILE = 3,\n-\tBNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE = 4,\n-\tBNXT_ULP_FIELD_OPC_SET_TO_ZERO = 5,\n-\tBNXT_ULP_FIELD_OPC_SET_TO_ACT_BIT = 6,\n-\tBNXT_ULP_FIELD_OPC_SET_TO_ACT_PROP = 7,\n-\tBNXT_ULP_FIELD_OPC_SET_TO_ENCAP_ACT_PROP_SZ = 8,\n-\tBNXT_ULP_FIELD_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST = 9,\n-\tBNXT_ULP_FIELD_OPC_IF_ACT_BIT_THEN_CONST_ELSE_CONST = 10,\n-\tBNXT_ULP_FIELD_OPC_IF_COMP_FIELD_THEN_CF_ELSE_CF = 11,\n-\tBNXT_ULP_FIELD_OPC_IF_HDR_BIT_THEN_CONST_ELSE_CONST = 12,\n-\tBNXT_ULP_FIELD_OPC_IF_COMP_FIELD_THEN_ACT_PROP_ELSE_CONST = 13,\n-\tBNXT_ULP_FIELD_OPC_IF_NOT_COMP_FIELD_THEN_ACT_PROP_ELSE_CONST = 14,\n-\tBNXT_ULP_FIELD_OPC_IF_COMP_FIELD_THEN_CONST_ELSE_CF = 15,\n-\tBNXT_ULP_FIELD_OPC_IF_NOT_COMP_FIELD_THEN_CONST_ELSE_CF = 16,\n-\tBNXT_ULP_FIELD_OPC_IF_FIELD_BIT_THEN_ONES_ELSE_ZERO = 17,\n-\tBNXT_ULP_FIELD_OPC_LAST = 18\n+enum bnxt_ulp_field_cond_src {\n+\tBNXT_ULP_FIELD_COND_SRC_TRUE = 0,\n+\tBNXT_ULP_FIELD_COND_SRC_CF = 1,\n+\tBNXT_ULP_FIELD_COND_SRC_RF = 2,\n+\tBNXT_ULP_FIELD_COND_SRC_ACT_BIT = 3,\n+\tBNXT_ULP_FIELD_COND_SRC_HDR_BIT = 4,\n+\tBNXT_ULP_FIELD_COND_SRC_FIELD_BIT = 5,\n+\tBNXT_ULP_FIELD_COND_SRC_LAST = 6\n+};\n+\n+enum bnxt_ulp_field_src {\n+\tBNXT_ULP_FIELD_SRC_ZERO = 0,\n+\tBNXT_ULP_FIELD_SRC_CONST = 1,\n+\tBNXT_ULP_FIELD_SRC_CF = 2,\n+\tBNXT_ULP_FIELD_SRC_RF = 3,\n+\tBNXT_ULP_FIELD_SRC_ACT_PROP = 4,\n+\tBNXT_ULP_FIELD_SRC_ACT_PROP_SZ = 5,\n+\tBNXT_ULP_FIELD_SRC_GLB_RF = 6,\n+\tBNXT_ULP_FIELD_SRC_HF = 7,\n+\tBNXT_ULP_FIELD_SRC_HDR_BIT = 8,\n+\tBNXT_ULP_FIELD_SRC_ACT_BIT = 9,\n+\tBNXT_ULP_FIELD_SRC_FIELD_BIT = 10,\n+\tBNXT_ULP_FIELD_SRC_SKIP = 11,\n+\tBNXT_ULP_FIELD_SRC_REJECT = 12,\n+\tBNXT_ULP_FIELD_SRC_LAST = 13\n };\n \n enum bnxt_ulp_generic_tbl_opc {\n@@ -409,7 +414,8 @@ enum bnxt_ulp_resource_func {\n \tBNXT_ULP_RESOURCE_FUNC_IF_TABLE = 0x84,\n \tBNXT_ULP_RESOURCE_FUNC_HW_FID = 0x85,\n \tBNXT_ULP_RESOURCE_FUNC_PARENT_FLOW = 0x86,\n-\tBNXT_ULP_RESOURCE_FUNC_CHILD_FLOW = 0x87\n+\tBNXT_ULP_RESOURCE_FUNC_CHILD_FLOW = 0x87,\n+\tBNXT_ULP_RESOURCE_FUNC_BRANCH_TABLE = 0x88\n };\n \n enum bnxt_ulp_resource_sub_type {\n@@ -516,483 +522,603 @@ enum bnxt_ulp_act_prop_idx {\n \tBNXT_ULP_ACT_PROP_IDX_LAST = 269\n };\n \n-enum bnxt_ulp_wh_plus_sym {\n-\tBNXT_ULP_WH_PLUS_SYM_PKT_TYPE_IGNORE = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_PKT_TYPE_L2 = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_PKT_TYPE_0_IGNORE = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_PKT_TYPE_0_L2 = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_PKT_TYPE_1_IGNORE = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_PKT_TYPE_1_L2 = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_RECYCLE_CNT_IGNORE = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_RECYCLE_CNT_ZERO = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_RECYCLE_CNT_ONE = 1,\n-\tBNXT_ULP_WH_PLUS_SYM_RECYCLE_CNT_TWO = 2,\n-\tBNXT_ULP_WH_PLUS_SYM_RECYCLE_CNT_THREE = 3,\n-\tBNXT_ULP_WH_PLUS_SYM_AGG_ERROR_IGNORE = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_AGG_ERROR_NO = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_AGG_ERROR_YES = 1,\n-\tBNXT_ULP_WH_PLUS_SYM_RESERVED_IGNORE = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_HREC_NEXT_IGNORE = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_HREC_NEXT_NO = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_HREC_NEXT_YES = 1,\n-\tBNXT_ULP_WH_PLUS_SYM_TL2_HDR_VALID_IGNORE = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_TL2_HDR_VALID_NO = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_TL2_HDR_VALID_YES = 1,\n-\tBNXT_ULP_WH_PLUS_SYM_TL2_HDR_TYPE_IGNORE = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_TL2_HDR_TYPE_DIX = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_TL2_UC_MC_BC_IGNORE = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_TL2_UC_MC_BC_UC = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_TL2_UC_MC_BC_MC = 2,\n-\tBNXT_ULP_WH_PLUS_SYM_TL2_UC_MC_BC_BC = 3,\n-\tBNXT_ULP_WH_PLUS_SYM_TL2_VTAG_PRESENT_IGNORE = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_TL2_VTAG_PRESENT_NO = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_TL2_VTAG_PRESENT_YES = 1,\n-\tBNXT_ULP_WH_PLUS_SYM_TL2_TWO_VTAGS_IGNORE = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_TL2_TWO_VTAGS_NO = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_TL2_TWO_VTAGS_YES = 1,\n-\tBNXT_ULP_WH_PLUS_SYM_TL3_HDR_VALID_IGNORE = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_TL3_HDR_VALID_NO = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_TL3_HDR_VALID_YES = 1,\n-\tBNXT_ULP_WH_PLUS_SYM_TL3_HDR_ERROR_IGNORE = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_TL3_HDR_ERROR_NO = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_TL3_HDR_ERROR_YES = 1,\n-\tBNXT_ULP_WH_PLUS_SYM_TL3_HDR_TYPE_IGNORE = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_TL3_HDR_TYPE_IPV4 = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_TL3_HDR_TYPE_IPV6 = 1,\n-\tBNXT_ULP_WH_PLUS_SYM_TL3_HDR_ISIP_IGNORE = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_TL3_HDR_ISIP_NO = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_TL3_HDR_ISIP_YES = 1,\n-\tBNXT_ULP_WH_PLUS_SYM_TL3_IPV6_CMP_SRC_IGNORE = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_TL3_IPV6_CMP_SRC_NO = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_TL3_IPV6_CMP_SRC_YES = 1,\n-\tBNXT_ULP_WH_PLUS_SYM_TL3_IPV6_CMP_DST_IGNORE = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_TL3_IPV6_CMP_DST_NO = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_TL3_IPV6_CMP_DST_YES = 1,\n-\tBNXT_ULP_WH_PLUS_SYM_TL4_HDR_VALID_IGNORE = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_TL4_HDR_VALID_NO = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_TL4_HDR_VALID_YES = 1,\n-\tBNXT_ULP_WH_PLUS_SYM_TL4_HDR_ERROR_IGNORE = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_TL4_HDR_ERROR_NO = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_TL4_HDR_ERROR_YES = 1,\n-\tBNXT_ULP_WH_PLUS_SYM_TL4_HDR_IS_UDP_TCP_IGNORE = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_TL4_HDR_IS_UDP_TCP_NO = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_TL4_HDR_IS_UDP_TCP_YES = 1,\n-\tBNXT_ULP_WH_PLUS_SYM_TL4_HDR_TYPE_IGNORE = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_TL4_HDR_TYPE_TCP = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_TL4_HDR_TYPE_UDP = 1,\n-\tBNXT_ULP_WH_PLUS_SYM_TUN_HDR_VALID_IGNORE = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_TUN_HDR_VALID_NO = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_TUN_HDR_VALID_YES = 1,\n-\tBNXT_ULP_WH_PLUS_SYM_TUN_HDR_ERROR_IGNORE = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_TUN_HDR_ERROR_NO = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_TUN_HDR_ERROR_YES = 1,\n-\tBNXT_ULP_WH_PLUS_SYM_TUN_HDR_TYPE_IGNORE = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_TUN_HDR_TYPE_VXLAN = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_TUN_HDR_TYPE_GENEVE = 1,\n-\tBNXT_ULP_WH_PLUS_SYM_TUN_HDR_TYPE_NVGRE = 2,\n-\tBNXT_ULP_WH_PLUS_SYM_TUN_HDR_TYPE_GRE = 3,\n-\tBNXT_ULP_WH_PLUS_SYM_TUN_HDR_TYPE_IPV4 = 4,\n-\tBNXT_ULP_WH_PLUS_SYM_TUN_HDR_TYPE_IPV6 = 5,\n-\tBNXT_ULP_WH_PLUS_SYM_TUN_HDR_TYPE_PPPOE = 6,\n-\tBNXT_ULP_WH_PLUS_SYM_TUN_HDR_TYPE_MPLS = 7,\n-\tBNXT_ULP_WH_PLUS_SYM_TUN_HDR_TYPE_UPAR1 = 8,\n-\tBNXT_ULP_WH_PLUS_SYM_TUN_HDR_TYPE_UPAR2 = 9,\n-\tBNXT_ULP_WH_PLUS_SYM_TUN_HDR_TYPE_NONE = 15,\n-\tBNXT_ULP_WH_PLUS_SYM_TUN_HDR_FLAGS_IGNORE = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_L2_HDR_VALID_IGNORE = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_L2_HDR_VALID_NO = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_L2_HDR_VALID_YES = 1,\n-\tBNXT_ULP_WH_PLUS_SYM_L2_HDR_ERROR_IGNORE = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_L2_HDR_ERROR_NO = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_L2_HDR_ERROR_YES = 1,\n-\tBNXT_ULP_WH_PLUS_SYM_L2_HDR_TYPE_IGNORE = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_L2_HDR_TYPE_DIX = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_L2_HDR_TYPE_LLC_SNAP = 1,\n-\tBNXT_ULP_WH_PLUS_SYM_L2_HDR_TYPE_LLC = 2,\n-\tBNXT_ULP_WH_PLUS_SYM_L2_UC_MC_BC_IGNORE = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_L2_UC_MC_BC_UC = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_L2_UC_MC_BC_MC = 2,\n-\tBNXT_ULP_WH_PLUS_SYM_L2_UC_MC_BC_BC = 3,\n-\tBNXT_ULP_WH_PLUS_SYM_L2_VTAG_PRESENT_IGNORE = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_L2_VTAG_PRESENT_NO = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_L2_VTAG_PRESENT_YES = 1,\n-\tBNXT_ULP_WH_PLUS_SYM_L2_TWO_VTAGS_IGNORE = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_L2_TWO_VTAGS_NO = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_L2_TWO_VTAGS_YES = 1,\n-\tBNXT_ULP_WH_PLUS_SYM_L3_HDR_VALID_IGNORE = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_L3_HDR_VALID_NO = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_L3_HDR_VALID_YES = 1,\n-\tBNXT_ULP_WH_PLUS_SYM_L3_HDR_ERROR_IGNORE = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_L3_HDR_ERROR_NO = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_L3_HDR_ERROR_YES = 1,\n-\tBNXT_ULP_WH_PLUS_SYM_L3_HDR_TYPE_IGNORE = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_L3_HDR_TYPE_IPV4 = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_L3_HDR_TYPE_IPV6 = 1,\n-\tBNXT_ULP_WH_PLUS_SYM_L3_HDR_TYPE_ARP = 2,\n-\tBNXT_ULP_WH_PLUS_SYM_L3_HDR_TYPE_PTP = 3,\n-\tBNXT_ULP_WH_PLUS_SYM_L3_HDR_TYPE_EAPOL = 4,\n-\tBNXT_ULP_WH_PLUS_SYM_L3_HDR_TYPE_ROCE = 5,\n-\tBNXT_ULP_WH_PLUS_SYM_L3_HDR_TYPE_FCOE = 6,\n-\tBNXT_ULP_WH_PLUS_SYM_L3_HDR_TYPE_UPAR1 = 7,\n-\tBNXT_ULP_WH_PLUS_SYM_L3_HDR_TYPE_UPAR2 = 8,\n-\tBNXT_ULP_WH_PLUS_SYM_L3_HDR_ISIP_IGNORE = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_L3_HDR_ISIP_NO = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_L3_HDR_ISIP_YES = 1,\n-\tBNXT_ULP_WH_PLUS_SYM_L3_IPV6_CMP_SRC_IGNORE = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_L3_IPV6_CMP_SRC_NO = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_L3_IPV6_CMP_SRC_YES = 1,\n-\tBNXT_ULP_WH_PLUS_SYM_L3_IPV6_CMP_DST_IGNORE = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_L3_IPV6_CMP_DST_NO = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_L3_IPV6_CMP_DST_YES = 1,\n-\tBNXT_ULP_WH_PLUS_SYM_L4_HDR_VALID_IGNORE = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_L4_HDR_VALID_NO = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_L4_HDR_VALID_YES = 1,\n-\tBNXT_ULP_WH_PLUS_SYM_L4_HDR_ERROR_IGNORE = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_L4_HDR_ERROR_NO = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_L4_HDR_ERROR_YES = 1,\n-\tBNXT_ULP_WH_PLUS_SYM_L4_HDR_TYPE_IGNORE = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_L4_HDR_TYPE_TCP = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_L4_HDR_TYPE_UDP = 1,\n-\tBNXT_ULP_WH_PLUS_SYM_L4_HDR_TYPE_ICMP = 2,\n-\tBNXT_ULP_WH_PLUS_SYM_L4_HDR_TYPE_UPAR1 = 3,\n-\tBNXT_ULP_WH_PLUS_SYM_L4_HDR_TYPE_UPAR2 = 4,\n-\tBNXT_ULP_WH_PLUS_SYM_L4_HDR_TYPE_BTH_V1 = 5,\n-\tBNXT_ULP_WH_PLUS_SYM_L4_HDR_IS_UDP_TCP_IGNORE = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_L4_HDR_IS_UDP_TCP_NO = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_L4_HDR_IS_UDP_TCP_YES = 1,\n-\tBNXT_ULP_WH_PLUS_SYM_POP_VLAN_NO = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_POP_VLAN_YES = 1,\n-\tBNXT_ULP_WH_PLUS_SYM_DECAP_FUNC_NONE = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_DECAP_FUNC_THRU_TL2 = 3,\n-\tBNXT_ULP_WH_PLUS_SYM_DECAP_FUNC_THRU_TL3 = 8,\n-\tBNXT_ULP_WH_PLUS_SYM_DECAP_FUNC_THRU_TL4 = 9,\n-\tBNXT_ULP_WH_PLUS_SYM_DECAP_FUNC_THRU_TUN = 10,\n-\tBNXT_ULP_WH_PLUS_SYM_DECAP_FUNC_THRU_L2 = 11,\n-\tBNXT_ULP_WH_PLUS_SYM_DECAP_FUNC_THRU_L3 = 12,\n-\tBNXT_ULP_WH_PLUS_SYM_DECAP_FUNC_THRU_L4 = 13,\n-\tBNXT_ULP_WH_PLUS_SYM_ECV_VALID_NO = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_ECV_VALID_YES = 1,\n-\tBNXT_ULP_WH_PLUS_SYM_ECV_CUSTOM_EN_NO = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_ECV_CUSTOM_EN_YES = 1,\n-\tBNXT_ULP_WH_PLUS_SYM_ECV_L2_EN_NO = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_ECV_L2_EN_YES = 1,\n-\tBNXT_ULP_WH_PLUS_SYM_ECV_VTAG_TYPE_NOP = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI = 1,\n-\tBNXT_ULP_WH_PLUS_SYM_ECV_VTAG_TYPE_ADD_1_IVLAN_PRI = 2,\n-\tBNXT_ULP_WH_PLUS_SYM_ECV_VTAG_TYPE_ADD_1_REMAP_DIFFSERV = 3,\n-\tBNXT_ULP_WH_PLUS_SYM_ECV_VTAG_TYPE_ADD_2_ENCAP_PRI = 4,\n-\tBNXT_ULP_WH_PLUS_SYM_ECV_VTAG_TYPE_ADD_2_REMAP_DIFFSERV = 5,\n-\tBNXT_ULP_WH_PLUS_SYM_ECV_VTAG_TYPE_ADD_0_ENCAP_PRI = 6,\n-\tBNXT_ULP_WH_PLUS_SYM_ECV_VTAG_TYPE_ADD_0_REMAP_DIFFSERV = 7,\n-\tBNXT_ULP_WH_PLUS_SYM_ECV_VTAG_TYPE_ADD_0_PRI_0 = 8,\n-\tBNXT_ULP_WH_PLUS_SYM_ECV_VTAG_TYPE_ADD_0_PRI_1 = 8,\n-\tBNXT_ULP_WH_PLUS_SYM_ECV_VTAG_TYPE_ADD_0_PRI_2 = 8,\n-\tBNXT_ULP_WH_PLUS_SYM_ECV_VTAG_TYPE_ADD_0_PRI_3 = 8,\n-\tBNXT_ULP_WH_PLUS_SYM_ECV_VTAG_TYPE_ADD_0_PRI_4 = 8,\n-\tBNXT_ULP_WH_PLUS_SYM_ECV_VTAG_TYPE_ADD_0_PRI_5 = 8,\n-\tBNXT_ULP_WH_PLUS_SYM_ECV_VTAG_TYPE_ADD_0_PRI_6 = 8,\n-\tBNXT_ULP_WH_PLUS_SYM_ECV_VTAG_TYPE_ADD_0_PRI_7 = 8,\n-\tBNXT_ULP_WH_PLUS_SYM_ECV_L3_TYPE_NONE = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_ECV_L3_TYPE_IPV4 = 4,\n-\tBNXT_ULP_WH_PLUS_SYM_ECV_L3_TYPE_IPV6 = 5,\n-\tBNXT_ULP_WH_PLUS_SYM_ECV_L3_TYPE_MPLS_8847 = 6,\n-\tBNXT_ULP_WH_PLUS_SYM_ECV_L3_TYPE_MPLS_8848 = 7,\n-\tBNXT_ULP_WH_PLUS_SYM_ECV_L4_TYPE_NONE = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_ECV_L4_TYPE_UDP = 4,\n-\tBNXT_ULP_WH_PLUS_SYM_ECV_L4_TYPE_UDP_CSUM = 5,\n-\tBNXT_ULP_WH_PLUS_SYM_ECV_L4_TYPE_UDP_ENTROPY = 6,\n-\tBNXT_ULP_WH_PLUS_SYM_ECV_L4_TYPE_UDP_ENTROPY_CSUM = 7,\n-\tBNXT_ULP_WH_PLUS_SYM_ECV_TUN_TYPE_NONE = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_ECV_TUN_TYPE_GENERIC = 1,\n-\tBNXT_ULP_WH_PLUS_SYM_ECV_TUN_TYPE_VXLAN = 2,\n-\tBNXT_ULP_WH_PLUS_SYM_ECV_TUN_TYPE_NGE = 3,\n-\tBNXT_ULP_WH_PLUS_SYM_ECV_TUN_TYPE_NVGRE = 4,\n-\tBNXT_ULP_WH_PLUS_SYM_ECV_TUN_TYPE_GRE = 5,\n-\tBNXT_ULP_WH_PLUS_SYM_EEM_ACT_REC_INT = 1,\n-\tBNXT_ULP_WH_PLUS_SYM_EEM_EXT_FLOW_CNTR = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_UC_ACT_REC = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_MC_ACT_REC = 1,\n-\tBNXT_ULP_WH_PLUS_SYM_ACT_REC_DROP_YES = 1,\n-\tBNXT_ULP_WH_PLUS_SYM_ACT_REC_DROP_NO = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_ACT_REC_POP_VLAN_YES = 1,\n-\tBNXT_ULP_WH_PLUS_SYM_ACT_REC_POP_VLAN_NO = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_ACT_REC_METER_EN_YES = 1,\n-\tBNXT_ULP_WH_PLUS_SYM_ACT_REC_METER_EN_NO = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_LOOPBACK_PORT = 4,\n-\tBNXT_ULP_WH_PLUS_SYM_LOOPBACK_PARIF = 15,\n-\tBNXT_ULP_WH_PLUS_SYM_EXT_EM_MAX_KEY_SIZE = 448,\n-\tBNXT_ULP_WH_PLUS_SYM_MATCH_TYPE_EM = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_MATCH_TYPE_WM = 1,\n-\tBNXT_ULP_WH_PLUS_SYM_IP_PROTO_ICMP = 1,\n-\tBNXT_ULP_WH_PLUS_SYM_IP_PROTO_IGMP = 2,\n-\tBNXT_ULP_WH_PLUS_SYM_IP_PROTO_IP_IN_IP = 4,\n-\tBNXT_ULP_WH_PLUS_SYM_IP_PROTO_TCP = 6,\n-\tBNXT_ULP_WH_PLUS_SYM_IP_PROTO_UDP = 17,\n-\tBNXT_ULP_WH_PLUS_SYM_VF_FUNC_PARIF = 15,\n-\tBNXT_ULP_WH_PLUS_SYM_NO = 0,\n-\tBNXT_ULP_WH_PLUS_SYM_YES = 1,\n-\tBNXT_ULP_WH_PLUS_SYM_RECYCLE_DST = 0x800\n-};\n-\n-enum bnxt_ulp_stingray_sym {\n-\tBNXT_ULP_STINGRAY_SYM_PKT_TYPE_IGNORE = 0,\n-\tBNXT_ULP_STINGRAY_SYM_PKT_TYPE_L2 = 0,\n-\tBNXT_ULP_STINGRAY_SYM_PKT_TYPE_0_IGNORE = 0,\n-\tBNXT_ULP_STINGRAY_SYM_PKT_TYPE_0_L2 = 0,\n-\tBNXT_ULP_STINGRAY_SYM_PKT_TYPE_1_IGNORE = 0,\n-\tBNXT_ULP_STINGRAY_SYM_PKT_TYPE_1_L2 = 0,\n-\tBNXT_ULP_STINGRAY_SYM_RECYCLE_CNT_IGNORE = 0,\n-\tBNXT_ULP_STINGRAY_SYM_RECYCLE_CNT_ZERO = 0,\n-\tBNXT_ULP_STINGRAY_SYM_RECYCLE_CNT_ONE = 1,\n-\tBNXT_ULP_STINGRAY_SYM_RECYCLE_CNT_TWO = 2,\n-\tBNXT_ULP_STINGRAY_SYM_RECYCLE_CNT_THREE = 3,\n-\tBNXT_ULP_STINGRAY_SYM_AGG_ERROR_IGNORE = 0,\n-\tBNXT_ULP_STINGRAY_SYM_AGG_ERROR_NO = 0,\n-\tBNXT_ULP_STINGRAY_SYM_AGG_ERROR_YES = 1,\n-\tBNXT_ULP_STINGRAY_SYM_RESERVED_IGNORE = 0,\n-\tBNXT_ULP_STINGRAY_SYM_HREC_NEXT_IGNORE = 0,\n-\tBNXT_ULP_STINGRAY_SYM_HREC_NEXT_NO = 0,\n-\tBNXT_ULP_STINGRAY_SYM_HREC_NEXT_YES = 1,\n-\tBNXT_ULP_STINGRAY_SYM_TL2_HDR_VALID_IGNORE = 0,\n-\tBNXT_ULP_STINGRAY_SYM_TL2_HDR_VALID_NO = 0,\n-\tBNXT_ULP_STINGRAY_SYM_TL2_HDR_VALID_YES = 1,\n-\tBNXT_ULP_STINGRAY_SYM_TL2_HDR_TYPE_IGNORE = 0,\n-\tBNXT_ULP_STINGRAY_SYM_TL2_HDR_TYPE_DIX = 0,\n-\tBNXT_ULP_STINGRAY_SYM_TL2_UC_MC_BC_IGNORE = 0,\n-\tBNXT_ULP_STINGRAY_SYM_TL2_UC_MC_BC_UC = 0,\n-\tBNXT_ULP_STINGRAY_SYM_TL2_UC_MC_BC_MC = 2,\n-\tBNXT_ULP_STINGRAY_SYM_TL2_UC_MC_BC_BC = 3,\n-\tBNXT_ULP_STINGRAY_SYM_TL2_VTAG_PRESENT_IGNORE = 0,\n-\tBNXT_ULP_STINGRAY_SYM_TL2_VTAG_PRESENT_NO = 0,\n-\tBNXT_ULP_STINGRAY_SYM_TL2_VTAG_PRESENT_YES = 1,\n-\tBNXT_ULP_STINGRAY_SYM_TL2_TWO_VTAGS_IGNORE = 0,\n-\tBNXT_ULP_STINGRAY_SYM_TL2_TWO_VTAGS_NO = 0,\n-\tBNXT_ULP_STINGRAY_SYM_TL2_TWO_VTAGS_YES = 1,\n-\tBNXT_ULP_STINGRAY_SYM_TL3_HDR_VALID_IGNORE = 0,\n-\tBNXT_ULP_STINGRAY_SYM_TL3_HDR_VALID_NO = 0,\n-\tBNXT_ULP_STINGRAY_SYM_TL3_HDR_VALID_YES = 1,\n-\tBNXT_ULP_STINGRAY_SYM_TL3_HDR_ERROR_IGNORE = 0,\n-\tBNXT_ULP_STINGRAY_SYM_TL3_HDR_ERROR_NO = 0,\n-\tBNXT_ULP_STINGRAY_SYM_TL3_HDR_ERROR_YES = 1,\n-\tBNXT_ULP_STINGRAY_SYM_TL3_HDR_TYPE_IGNORE = 0,\n-\tBNXT_ULP_STINGRAY_SYM_TL3_HDR_TYPE_IPV4 = 0,\n-\tBNXT_ULP_STINGRAY_SYM_TL3_HDR_TYPE_IPV6 = 1,\n-\tBNXT_ULP_STINGRAY_SYM_TL3_HDR_ISIP_IGNORE = 0,\n-\tBNXT_ULP_STINGRAY_SYM_TL3_HDR_ISIP_NO = 0,\n-\tBNXT_ULP_STINGRAY_SYM_TL3_HDR_ISIP_YES = 1,\n-\tBNXT_ULP_STINGRAY_SYM_TL3_IPV6_CMP_SRC_IGNORE = 0,\n-\tBNXT_ULP_STINGRAY_SYM_TL3_IPV6_CMP_SRC_NO = 0,\n-\tBNXT_ULP_STINGRAY_SYM_TL3_IPV6_CMP_SRC_YES = 1,\n-\tBNXT_ULP_STINGRAY_SYM_TL3_IPV6_CMP_DST_IGNORE = 0,\n-\tBNXT_ULP_STINGRAY_SYM_TL3_IPV6_CMP_DST_NO = 0,\n-\tBNXT_ULP_STINGRAY_SYM_TL3_IPV6_CMP_DST_YES = 1,\n-\tBNXT_ULP_STINGRAY_SYM_TL4_HDR_VALID_IGNORE = 0,\n-\tBNXT_ULP_STINGRAY_SYM_TL4_HDR_VALID_NO = 0,\n-\tBNXT_ULP_STINGRAY_SYM_TL4_HDR_VALID_YES = 1,\n-\tBNXT_ULP_STINGRAY_SYM_TL4_HDR_ERROR_IGNORE = 0,\n-\tBNXT_ULP_STINGRAY_SYM_TL4_HDR_ERROR_NO = 0,\n-\tBNXT_ULP_STINGRAY_SYM_TL4_HDR_ERROR_YES = 1,\n-\tBNXT_ULP_STINGRAY_SYM_TL4_HDR_IS_UDP_TCP_IGNORE = 0,\n-\tBNXT_ULP_STINGRAY_SYM_TL4_HDR_IS_UDP_TCP_NO = 0,\n-\tBNXT_ULP_STINGRAY_SYM_TL4_HDR_IS_UDP_TCP_YES = 1,\n-\tBNXT_ULP_STINGRAY_SYM_TL4_HDR_TYPE_IGNORE = 0,\n-\tBNXT_ULP_STINGRAY_SYM_TL4_HDR_TYPE_TCP = 0,\n-\tBNXT_ULP_STINGRAY_SYM_TL4_HDR_TYPE_UDP = 1,\n-\tBNXT_ULP_STINGRAY_SYM_TUN_HDR_VALID_IGNORE = 0,\n-\tBNXT_ULP_STINGRAY_SYM_TUN_HDR_VALID_NO = 0,\n-\tBNXT_ULP_STINGRAY_SYM_TUN_HDR_VALID_YES = 1,\n-\tBNXT_ULP_STINGRAY_SYM_TUN_HDR_ERROR_IGNORE = 0,\n-\tBNXT_ULP_STINGRAY_SYM_TUN_HDR_ERROR_NO = 0,\n-\tBNXT_ULP_STINGRAY_SYM_TUN_HDR_ERROR_YES = 1,\n-\tBNXT_ULP_STINGRAY_SYM_TUN_HDR_TYPE_IGNORE = 0,\n-\tBNXT_ULP_STINGRAY_SYM_TUN_HDR_TYPE_VXLAN = 0,\n-\tBNXT_ULP_STINGRAY_SYM_TUN_HDR_TYPE_GENEVE = 1,\n-\tBNXT_ULP_STINGRAY_SYM_TUN_HDR_TYPE_NVGRE = 2,\n-\tBNXT_ULP_STINGRAY_SYM_TUN_HDR_TYPE_GRE = 3,\n-\tBNXT_ULP_STINGRAY_SYM_TUN_HDR_TYPE_IPV4 = 4,\n-\tBNXT_ULP_STINGRAY_SYM_TUN_HDR_TYPE_IPV6 = 5,\n-\tBNXT_ULP_STINGRAY_SYM_TUN_HDR_TYPE_PPPOE = 6,\n-\tBNXT_ULP_STINGRAY_SYM_TUN_HDR_TYPE_MPLS = 7,\n-\tBNXT_ULP_STINGRAY_SYM_TUN_HDR_TYPE_UPAR1 = 8,\n-\tBNXT_ULP_STINGRAY_SYM_TUN_HDR_TYPE_UPAR2 = 9,\n-\tBNXT_ULP_STINGRAY_SYM_TUN_HDR_TYPE_NONE = 15,\n-\tBNXT_ULP_STINGRAY_SYM_TUN_HDR_FLAGS_IGNORE = 0,\n-\tBNXT_ULP_STINGRAY_SYM_L2_HDR_VALID_IGNORE = 0,\n-\tBNXT_ULP_STINGRAY_SYM_L2_HDR_VALID_NO = 0,\n-\tBNXT_ULP_STINGRAY_SYM_L2_HDR_VALID_YES = 1,\n-\tBNXT_ULP_STINGRAY_SYM_L2_HDR_ERROR_IGNORE = 0,\n-\tBNXT_ULP_STINGRAY_SYM_L2_HDR_ERROR_NO = 0,\n-\tBNXT_ULP_STINGRAY_SYM_L2_HDR_ERROR_YES = 1,\n-\tBNXT_ULP_STINGRAY_SYM_L2_HDR_TYPE_IGNORE = 0,\n-\tBNXT_ULP_STINGRAY_SYM_L2_HDR_TYPE_DIX = 0,\n-\tBNXT_ULP_STINGRAY_SYM_L2_HDR_TYPE_LLC_SNAP = 1,\n-\tBNXT_ULP_STINGRAY_SYM_L2_HDR_TYPE_LLC = 2,\n-\tBNXT_ULP_STINGRAY_SYM_L2_UC_MC_BC_IGNORE = 0,\n-\tBNXT_ULP_STINGRAY_SYM_L2_UC_MC_BC_UC = 0,\n-\tBNXT_ULP_STINGRAY_SYM_L2_UC_MC_BC_MC = 2,\n-\tBNXT_ULP_STINGRAY_SYM_L2_UC_MC_BC_BC = 3,\n-\tBNXT_ULP_STINGRAY_SYM_L2_VTAG_PRESENT_IGNORE = 0,\n-\tBNXT_ULP_STINGRAY_SYM_L2_VTAG_PRESENT_NO = 0,\n-\tBNXT_ULP_STINGRAY_SYM_L2_VTAG_PRESENT_YES = 1,\n-\tBNXT_ULP_STINGRAY_SYM_L2_TWO_VTAGS_IGNORE = 0,\n-\tBNXT_ULP_STINGRAY_SYM_L2_TWO_VTAGS_NO = 0,\n-\tBNXT_ULP_STINGRAY_SYM_L2_TWO_VTAGS_YES = 1,\n-\tBNXT_ULP_STINGRAY_SYM_L3_HDR_VALID_IGNORE = 0,\n-\tBNXT_ULP_STINGRAY_SYM_L3_HDR_VALID_NO = 0,\n-\tBNXT_ULP_STINGRAY_SYM_L3_HDR_VALID_YES = 1,\n-\tBNXT_ULP_STINGRAY_SYM_L3_HDR_ERROR_IGNORE = 0,\n-\tBNXT_ULP_STINGRAY_SYM_L3_HDR_ERROR_NO = 0,\n-\tBNXT_ULP_STINGRAY_SYM_L3_HDR_ERROR_YES = 1,\n-\tBNXT_ULP_STINGRAY_SYM_L3_HDR_TYPE_IGNORE = 0,\n-\tBNXT_ULP_STINGRAY_SYM_L3_HDR_TYPE_IPV4 = 0,\n-\tBNXT_ULP_STINGRAY_SYM_L3_HDR_TYPE_IPV6 = 1,\n-\tBNXT_ULP_STINGRAY_SYM_L3_HDR_TYPE_ARP = 2,\n-\tBNXT_ULP_STINGRAY_SYM_L3_HDR_TYPE_PTP = 3,\n-\tBNXT_ULP_STINGRAY_SYM_L3_HDR_TYPE_EAPOL = 4,\n-\tBNXT_ULP_STINGRAY_SYM_L3_HDR_TYPE_ROCE = 5,\n-\tBNXT_ULP_STINGRAY_SYM_L3_HDR_TYPE_FCOE = 6,\n-\tBNXT_ULP_STINGRAY_SYM_L3_HDR_TYPE_UPAR1 = 7,\n-\tBNXT_ULP_STINGRAY_SYM_L3_HDR_TYPE_UPAR2 = 8,\n-\tBNXT_ULP_STINGRAY_SYM_L3_HDR_ISIP_IGNORE = 0,\n-\tBNXT_ULP_STINGRAY_SYM_L3_HDR_ISIP_NO = 0,\n-\tBNXT_ULP_STINGRAY_SYM_L3_HDR_ISIP_YES = 1,\n-\tBNXT_ULP_STINGRAY_SYM_L3_IPV6_CMP_SRC_IGNORE = 0,\n-\tBNXT_ULP_STINGRAY_SYM_L3_IPV6_CMP_SRC_NO = 0,\n-\tBNXT_ULP_STINGRAY_SYM_L3_IPV6_CMP_SRC_YES = 1,\n-\tBNXT_ULP_STINGRAY_SYM_L3_IPV6_CMP_DST_IGNORE = 0,\n-\tBNXT_ULP_STINGRAY_SYM_L3_IPV6_CMP_DST_NO = 0,\n-\tBNXT_ULP_STINGRAY_SYM_L3_IPV6_CMP_DST_YES = 1,\n-\tBNXT_ULP_STINGRAY_SYM_L4_HDR_VALID_IGNORE = 0,\n-\tBNXT_ULP_STINGRAY_SYM_L4_HDR_VALID_NO = 0,\n-\tBNXT_ULP_STINGRAY_SYM_L4_HDR_VALID_YES = 1,\n-\tBNXT_ULP_STINGRAY_SYM_L4_HDR_ERROR_IGNORE = 0,\n-\tBNXT_ULP_STINGRAY_SYM_L4_HDR_ERROR_NO = 0,\n-\tBNXT_ULP_STINGRAY_SYM_L4_HDR_ERROR_YES = 1,\n-\tBNXT_ULP_STINGRAY_SYM_L4_HDR_TYPE_IGNORE = 0,\n-\tBNXT_ULP_STINGRAY_SYM_L4_HDR_TYPE_TCP = 0,\n-\tBNXT_ULP_STINGRAY_SYM_L4_HDR_TYPE_UDP = 1,\n-\tBNXT_ULP_STINGRAY_SYM_L4_HDR_TYPE_ICMP = 2,\n-\tBNXT_ULP_STINGRAY_SYM_L4_HDR_TYPE_UPAR1 = 3,\n-\tBNXT_ULP_STINGRAY_SYM_L4_HDR_TYPE_UPAR2 = 4,\n-\tBNXT_ULP_STINGRAY_SYM_L4_HDR_TYPE_BTH_V1 = 5,\n-\tBNXT_ULP_STINGRAY_SYM_L4_HDR_IS_UDP_TCP_IGNORE = 0,\n-\tBNXT_ULP_STINGRAY_SYM_L4_HDR_IS_UDP_TCP_NO = 0,\n-\tBNXT_ULP_STINGRAY_SYM_L4_HDR_IS_UDP_TCP_YES = 1,\n-\tBNXT_ULP_STINGRAY_SYM_POP_VLAN_NO = 0,\n-\tBNXT_ULP_STINGRAY_SYM_POP_VLAN_YES = 1,\n-\tBNXT_ULP_STINGRAY_SYM_DECAP_FUNC_NONE = 0,\n-\tBNXT_ULP_STINGRAY_SYM_DECAP_FUNC_THRU_TL2 = 3,\n-\tBNXT_ULP_STINGRAY_SYM_DECAP_FUNC_THRU_TL3 = 8,\n-\tBNXT_ULP_STINGRAY_SYM_DECAP_FUNC_THRU_TL4 = 9,\n-\tBNXT_ULP_STINGRAY_SYM_DECAP_FUNC_THRU_TUN = 10,\n-\tBNXT_ULP_STINGRAY_SYM_DECAP_FUNC_THRU_L2 = 11,\n-\tBNXT_ULP_STINGRAY_SYM_DECAP_FUNC_THRU_L3 = 12,\n-\tBNXT_ULP_STINGRAY_SYM_DECAP_FUNC_THRU_L4 = 13,\n-\tBNXT_ULP_STINGRAY_SYM_ECV_VALID_NO = 0,\n-\tBNXT_ULP_STINGRAY_SYM_ECV_VALID_YES = 1,\n-\tBNXT_ULP_STINGRAY_SYM_ECV_CUSTOM_EN_NO = 0,\n-\tBNXT_ULP_STINGRAY_SYM_ECV_CUSTOM_EN_YES = 1,\n-\tBNXT_ULP_STINGRAY_SYM_ECV_L2_EN_NO = 0,\n-\tBNXT_ULP_STINGRAY_SYM_ECV_L2_EN_YES = 1,\n-\tBNXT_ULP_STINGRAY_SYM_ECV_VTAG_TYPE_NOP = 0,\n-\tBNXT_ULP_STINGRAY_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI = 1,\n-\tBNXT_ULP_STINGRAY_SYM_ECV_VTAG_TYPE_ADD_1_IVLAN_PRI = 2,\n-\tBNXT_ULP_STINGRAY_SYM_ECV_VTAG_TYPE_ADD_1_REMAP_DIFFSERV = 3,\n-\tBNXT_ULP_STINGRAY_SYM_ECV_VTAG_TYPE_ADD_2_ENCAP_PRI = 4,\n-\tBNXT_ULP_STINGRAY_SYM_ECV_VTAG_TYPE_ADD_2_REMAP_DIFFSERV = 5,\n-\tBNXT_ULP_STINGRAY_SYM_ECV_VTAG_TYPE_ADD_0_ENCAP_PRI = 6,\n-\tBNXT_ULP_STINGRAY_SYM_ECV_VTAG_TYPE_ADD_0_REMAP_DIFFSERV = 7,\n-\tBNXT_ULP_STINGRAY_SYM_ECV_VTAG_TYPE_ADD_0_PRI_0 = 8,\n-\tBNXT_ULP_STINGRAY_SYM_ECV_VTAG_TYPE_ADD_0_PRI_1 = 8,\n-\tBNXT_ULP_STINGRAY_SYM_ECV_VTAG_TYPE_ADD_0_PRI_2 = 8,\n-\tBNXT_ULP_STINGRAY_SYM_ECV_VTAG_TYPE_ADD_0_PRI_3 = 8,\n-\tBNXT_ULP_STINGRAY_SYM_ECV_VTAG_TYPE_ADD_0_PRI_4 = 8,\n-\tBNXT_ULP_STINGRAY_SYM_ECV_VTAG_TYPE_ADD_0_PRI_5 = 8,\n-\tBNXT_ULP_STINGRAY_SYM_ECV_VTAG_TYPE_ADD_0_PRI_6 = 8,\n-\tBNXT_ULP_STINGRAY_SYM_ECV_VTAG_TYPE_ADD_0_PRI_7 = 8,\n-\tBNXT_ULP_STINGRAY_SYM_ECV_L3_TYPE_NONE = 0,\n-\tBNXT_ULP_STINGRAY_SYM_ECV_L3_TYPE_IPV4 = 4,\n-\tBNXT_ULP_STINGRAY_SYM_ECV_L3_TYPE_IPV6 = 5,\n-\tBNXT_ULP_STINGRAY_SYM_ECV_L3_TYPE_MPLS_8847 = 6,\n-\tBNXT_ULP_STINGRAY_SYM_ECV_L3_TYPE_MPLS_8848 = 7,\n-\tBNXT_ULP_STINGRAY_SYM_ECV_L4_TYPE_NONE = 0,\n-\tBNXT_ULP_STINGRAY_SYM_ECV_L4_TYPE_UDP = 4,\n-\tBNXT_ULP_STINGRAY_SYM_ECV_L4_TYPE_UDP_CSUM = 5,\n-\tBNXT_ULP_STINGRAY_SYM_ECV_L4_TYPE_UDP_ENTROPY = 6,\n-\tBNXT_ULP_STINGRAY_SYM_ECV_L4_TYPE_UDP_ENTROPY_CSUM = 7,\n-\tBNXT_ULP_STINGRAY_SYM_ECV_TUN_TYPE_NONE = 0,\n-\tBNXT_ULP_STINGRAY_SYM_ECV_TUN_TYPE_GENERIC = 1,\n-\tBNXT_ULP_STINGRAY_SYM_ECV_TUN_TYPE_VXLAN = 2,\n-\tBNXT_ULP_STINGRAY_SYM_ECV_TUN_TYPE_NGE = 3,\n-\tBNXT_ULP_STINGRAY_SYM_ECV_TUN_TYPE_NVGRE = 4,\n-\tBNXT_ULP_STINGRAY_SYM_ECV_TUN_TYPE_GRE = 5,\n-\tBNXT_ULP_STINGRAY_SYM_EEM_ACT_REC_INT = 0,\n-\tBNXT_ULP_STINGRAY_SYM_EEM_EXT_FLOW_CNTR = 1,\n-\tBNXT_ULP_STINGRAY_SYM_UC_ACT_REC = 0,\n-\tBNXT_ULP_STINGRAY_SYM_MC_ACT_REC = 1,\n-\tBNXT_ULP_STINGRAY_SYM_ACT_REC_DROP_YES = 1,\n-\tBNXT_ULP_STINGRAY_SYM_ACT_REC_DROP_NO = 0,\n-\tBNXT_ULP_STINGRAY_SYM_ACT_REC_POP_VLAN_YES = 1,\n-\tBNXT_ULP_STINGRAY_SYM_ACT_REC_POP_VLAN_NO = 0,\n-\tBNXT_ULP_STINGRAY_SYM_ACT_REC_METER_EN_YES = 1,\n-\tBNXT_ULP_STINGRAY_SYM_ACT_REC_METER_EN_NO = 0,\n-\tBNXT_ULP_STINGRAY_SYM_LOOPBACK_PORT = 16,\n-\tBNXT_ULP_STINGRAY_SYM_LOOPBACK_PARIF = 15,\n-\tBNXT_ULP_STINGRAY_SYM_EXT_EM_MAX_KEY_SIZE = 448,\n-\tBNXT_ULP_STINGRAY_SYM_MATCH_TYPE_EM = 0,\n-\tBNXT_ULP_STINGRAY_SYM_MATCH_TYPE_WM = 1,\n-\tBNXT_ULP_STINGRAY_SYM_IP_PROTO_ICMP = 1,\n-\tBNXT_ULP_STINGRAY_SYM_IP_PROTO_IGMP = 2,\n-\tBNXT_ULP_STINGRAY_SYM_IP_PROTO_IP_IN_IP = 4,\n-\tBNXT_ULP_STINGRAY_SYM_IP_PROTO_TCP = 6,\n-\tBNXT_ULP_STINGRAY_SYM_IP_PROTO_UDP = 17,\n-\tBNXT_ULP_STINGRAY_SYM_VF_FUNC_PARIF = 15,\n-\tBNXT_ULP_STINGRAY_SYM_NO = 0,\n-\tBNXT_ULP_STINGRAY_SYM_YES = 1,\n-\tBNXT_ULP_STINGRAY_SYM_RECYCLE_DST = 0x800\n+enum ulp_wp_sym {\n+\tULP_WP_SYM_PKT_TYPE_IGNORE = 0,\n+\tULP_WP_SYM_PKT_TYPE_L2 = 0,\n+\tULP_WP_SYM_PKT_TYPE_0_IGNORE = 0,\n+\tULP_WP_SYM_PKT_TYPE_0_L2 = 0,\n+\tULP_WP_SYM_PKT_TYPE_1_IGNORE = 0,\n+\tULP_WP_SYM_PKT_TYPE_1_L2 = 0,\n+\tULP_WP_SYM_RECYCLE_CNT_IGNORE = 0,\n+\tULP_WP_SYM_RECYCLE_CNT_ZERO = 0,\n+\tULP_WP_SYM_RECYCLE_CNT_ONE = 1,\n+\tULP_WP_SYM_RECYCLE_CNT_TWO = 2,\n+\tULP_WP_SYM_RECYCLE_CNT_THREE = 3,\n+\tULP_WP_SYM_AGG_ERROR_IGNORE = 0,\n+\tULP_WP_SYM_AGG_ERROR_NO = 0,\n+\tULP_WP_SYM_AGG_ERROR_YES = 1,\n+\tULP_WP_SYM_RESERVED_IGNORE = 0,\n+\tULP_WP_SYM_HREC_NEXT_IGNORE = 0,\n+\tULP_WP_SYM_HREC_NEXT_NO = 0,\n+\tULP_WP_SYM_HREC_NEXT_YES = 1,\n+\tULP_WP_SYM_TL2_HDR_VALID_IGNORE = 0,\n+\tULP_WP_SYM_TL2_HDR_VALID_NO = 0,\n+\tULP_WP_SYM_TL2_HDR_VALID_YES = 1,\n+\tULP_WP_SYM_TL2_HDR_TYPE_IGNORE = 0,\n+\tULP_WP_SYM_TL2_HDR_TYPE_DIX = 0,\n+\tULP_WP_SYM_TL2_UC_MC_BC_IGNORE = 0,\n+\tULP_WP_SYM_TL2_UC_MC_BC_UC = 0,\n+\tULP_WP_SYM_TL2_UC_MC_BC_MC = 2,\n+\tULP_WP_SYM_TL2_UC_MC_BC_BC = 3,\n+\tULP_WP_SYM_TL2_VTAG_PRESENT_IGNORE = 0,\n+\tULP_WP_SYM_TL2_VTAG_PRESENT_NO = 0,\n+\tULP_WP_SYM_TL2_VTAG_PRESENT_YES = 1,\n+\tULP_WP_SYM_TL2_TWO_VTAGS_IGNORE = 0,\n+\tULP_WP_SYM_TL2_TWO_VTAGS_NO = 0,\n+\tULP_WP_SYM_TL2_TWO_VTAGS_YES = 1,\n+\tULP_WP_SYM_TL3_HDR_VALID_IGNORE = 0,\n+\tULP_WP_SYM_TL3_HDR_VALID_NO = 0,\n+\tULP_WP_SYM_TL3_HDR_VALID_YES = 1,\n+\tULP_WP_SYM_TL3_HDR_ERROR_IGNORE = 0,\n+\tULP_WP_SYM_TL3_HDR_ERROR_NO = 0,\n+\tULP_WP_SYM_TL3_HDR_ERROR_YES = 1,\n+\tULP_WP_SYM_TL3_HDR_TYPE_IGNORE = 0,\n+\tULP_WP_SYM_TL3_HDR_TYPE_IPV4 = 0,\n+\tULP_WP_SYM_TL3_HDR_TYPE_IPV6 = 1,\n+\tULP_WP_SYM_TL3_HDR_ISIP_IGNORE = 0,\n+\tULP_WP_SYM_TL3_HDR_ISIP_NO = 0,\n+\tULP_WP_SYM_TL3_HDR_ISIP_YES = 1,\n+\tULP_WP_SYM_TL3_IPV6_CMP_SRC_IGNORE = 0,\n+\tULP_WP_SYM_TL3_IPV6_CMP_SRC_NO = 0,\n+\tULP_WP_SYM_TL3_IPV6_CMP_SRC_YES = 1,\n+\tULP_WP_SYM_TL3_IPV6_CMP_DST_IGNORE = 0,\n+\tULP_WP_SYM_TL3_IPV6_CMP_DST_NO = 0,\n+\tULP_WP_SYM_TL3_IPV6_CMP_DST_YES = 1,\n+\tULP_WP_SYM_TL4_HDR_VALID_IGNORE = 0,\n+\tULP_WP_SYM_TL4_HDR_VALID_NO = 0,\n+\tULP_WP_SYM_TL4_HDR_VALID_YES = 1,\n+\tULP_WP_SYM_TL4_HDR_ERROR_IGNORE = 0,\n+\tULP_WP_SYM_TL4_HDR_ERROR_NO = 0,\n+\tULP_WP_SYM_TL4_HDR_ERROR_YES = 1,\n+\tULP_WP_SYM_TL4_HDR_IS_UDP_TCP_IGNORE = 0,\n+\tULP_WP_SYM_TL4_HDR_IS_UDP_TCP_NO = 0,\n+\tULP_WP_SYM_TL4_HDR_IS_UDP_TCP_YES = 1,\n+\tULP_WP_SYM_TL4_HDR_TYPE_IGNORE = 0,\n+\tULP_WP_SYM_TL4_HDR_TYPE_TCP = 0,\n+\tULP_WP_SYM_TL4_HDR_TYPE_UDP = 1,\n+\tULP_WP_SYM_TUN_HDR_VALID_IGNORE = 0,\n+\tULP_WP_SYM_TUN_HDR_VALID_NO = 0,\n+\tULP_WP_SYM_TUN_HDR_VALID_YES = 1,\n+\tULP_WP_SYM_TUN_HDR_ERROR_IGNORE = 0,\n+\tULP_WP_SYM_TUN_HDR_ERROR_NO = 0,\n+\tULP_WP_SYM_TUN_HDR_ERROR_YES = 1,\n+\tULP_WP_SYM_TUN_HDR_TYPE_IGNORE = 0,\n+\tULP_WP_SYM_TUN_HDR_TYPE_VXLAN = 0,\n+\tULP_WP_SYM_TUN_HDR_TYPE_GENEVE = 1,\n+\tULP_WP_SYM_TUN_HDR_TYPE_NVGRE = 2,\n+\tULP_WP_SYM_TUN_HDR_TYPE_GRE = 3,\n+\tULP_WP_SYM_TUN_HDR_TYPE_IPV4 = 4,\n+\tULP_WP_SYM_TUN_HDR_TYPE_IPV6 = 5,\n+\tULP_WP_SYM_TUN_HDR_TYPE_PPPOE = 6,\n+\tULP_WP_SYM_TUN_HDR_TYPE_MPLS = 7,\n+\tULP_WP_SYM_TUN_HDR_TYPE_UPAR1 = 8,\n+\tULP_WP_SYM_TUN_HDR_TYPE_UPAR2 = 9,\n+\tULP_WP_SYM_TUN_HDR_TYPE_NONE = 15,\n+\tULP_WP_SYM_TUN_HDR_FLAGS_IGNORE = 0,\n+\tULP_WP_SYM_L2_HDR_VALID_IGNORE = 0,\n+\tULP_WP_SYM_L2_HDR_VALID_NO = 0,\n+\tULP_WP_SYM_L2_HDR_VALID_YES = 1,\n+\tULP_WP_SYM_L2_HDR_ERROR_IGNORE = 0,\n+\tULP_WP_SYM_L2_HDR_ERROR_NO = 0,\n+\tULP_WP_SYM_L2_HDR_ERROR_YES = 1,\n+\tULP_WP_SYM_L2_HDR_TYPE_IGNORE = 0,\n+\tULP_WP_SYM_L2_HDR_TYPE_DIX = 0,\n+\tULP_WP_SYM_L2_HDR_TYPE_LLC_SNAP = 1,\n+\tULP_WP_SYM_L2_HDR_TYPE_LLC = 2,\n+\tULP_WP_SYM_L2_UC_MC_BC_IGNORE = 0,\n+\tULP_WP_SYM_L2_UC_MC_BC_UC = 0,\n+\tULP_WP_SYM_L2_UC_MC_BC_MC = 2,\n+\tULP_WP_SYM_L2_UC_MC_BC_BC = 3,\n+\tULP_WP_SYM_L2_VTAG_PRESENT_IGNORE = 0,\n+\tULP_WP_SYM_L2_VTAG_PRESENT_NO = 0,\n+\tULP_WP_SYM_L2_VTAG_PRESENT_YES = 1,\n+\tULP_WP_SYM_L2_TWO_VTAGS_IGNORE = 0,\n+\tULP_WP_SYM_L2_TWO_VTAGS_NO = 0,\n+\tULP_WP_SYM_L2_TWO_VTAGS_YES = 1,\n+\tULP_WP_SYM_L3_HDR_VALID_IGNORE = 0,\n+\tULP_WP_SYM_L3_HDR_VALID_NO = 0,\n+\tULP_WP_SYM_L3_HDR_VALID_YES = 1,\n+\tULP_WP_SYM_L3_HDR_ERROR_IGNORE = 0,\n+\tULP_WP_SYM_L3_HDR_ERROR_NO = 0,\n+\tULP_WP_SYM_L3_HDR_ERROR_YES = 1,\n+\tULP_WP_SYM_L3_HDR_TYPE_IGNORE = 0,\n+\tULP_WP_SYM_L3_HDR_TYPE_IPV4 = 0,\n+\tULP_WP_SYM_L3_HDR_TYPE_IPV6 = 1,\n+\tULP_WP_SYM_L3_HDR_TYPE_ARP = 2,\n+\tULP_WP_SYM_L3_HDR_TYPE_PTP = 3,\n+\tULP_WP_SYM_L3_HDR_TYPE_EAPOL = 4,\n+\tULP_WP_SYM_L3_HDR_TYPE_ROCE = 5,\n+\tULP_WP_SYM_L3_HDR_TYPE_FCOE = 6,\n+\tULP_WP_SYM_L3_HDR_TYPE_UPAR1 = 7,\n+\tULP_WP_SYM_L3_HDR_TYPE_UPAR2 = 8,\n+\tULP_WP_SYM_L3_HDR_ISIP_IGNORE = 0,\n+\tULP_WP_SYM_L3_HDR_ISIP_NO = 0,\n+\tULP_WP_SYM_L3_HDR_ISIP_YES = 1,\n+\tULP_WP_SYM_L3_IPV6_CMP_SRC_IGNORE = 0,\n+\tULP_WP_SYM_L3_IPV6_CMP_SRC_NO = 0,\n+\tULP_WP_SYM_L3_IPV6_CMP_SRC_YES = 1,\n+\tULP_WP_SYM_L3_IPV6_CMP_DST_IGNORE = 0,\n+\tULP_WP_SYM_L3_IPV6_CMP_DST_NO = 0,\n+\tULP_WP_SYM_L3_IPV6_CMP_DST_YES = 1,\n+\tULP_WP_SYM_L4_HDR_VALID_IGNORE = 0,\n+\tULP_WP_SYM_L4_HDR_VALID_NO = 0,\n+\tULP_WP_SYM_L4_HDR_VALID_YES = 1,\n+\tULP_WP_SYM_L4_HDR_ERROR_IGNORE = 0,\n+\tULP_WP_SYM_L4_HDR_ERROR_NO = 0,\n+\tULP_WP_SYM_L4_HDR_ERROR_YES = 1,\n+\tULP_WP_SYM_L4_HDR_TYPE_IGNORE = 0,\n+\tULP_WP_SYM_L4_HDR_TYPE_TCP = 0,\n+\tULP_WP_SYM_L4_HDR_TYPE_UDP = 1,\n+\tULP_WP_SYM_L4_HDR_TYPE_ICMP = 2,\n+\tULP_WP_SYM_L4_HDR_TYPE_UPAR1 = 3,\n+\tULP_WP_SYM_L4_HDR_TYPE_UPAR2 = 4,\n+\tULP_WP_SYM_L4_HDR_TYPE_BTH_V1 = 5,\n+\tULP_WP_SYM_L4_HDR_IS_UDP_TCP_IGNORE = 0,\n+\tULP_WP_SYM_L4_HDR_IS_UDP_TCP_NO = 0,\n+\tULP_WP_SYM_L4_HDR_IS_UDP_TCP_YES = 1,\n+\tULP_WP_SYM_POP_VLAN_NO = 0,\n+\tULP_WP_SYM_POP_VLAN_YES = 1,\n+\tULP_WP_SYM_DECAP_FUNC_NONE = 0,\n+\tULP_WP_SYM_DECAP_FUNC_THRU_TL2 = 3,\n+\tULP_WP_SYM_DECAP_FUNC_THRU_TL3 = 8,\n+\tULP_WP_SYM_DECAP_FUNC_THRU_TL4 = 9,\n+\tULP_WP_SYM_DECAP_FUNC_THRU_TUN = 10,\n+\tULP_WP_SYM_DECAP_FUNC_THRU_L2 = 11,\n+\tULP_WP_SYM_DECAP_FUNC_THRU_L3 = 12,\n+\tULP_WP_SYM_DECAP_FUNC_THRU_L4 = 13,\n+\tULP_WP_SYM_ECV_VALID_NO = 0,\n+\tULP_WP_SYM_ECV_VALID_YES = 1,\n+\tULP_WP_SYM_ECV_CUSTOM_EN_NO = 0,\n+\tULP_WP_SYM_ECV_CUSTOM_EN_YES = 1,\n+\tULP_WP_SYM_ECV_L2_EN_NO = 0,\n+\tULP_WP_SYM_ECV_L2_EN_YES = 1,\n+\tULP_WP_SYM_ECV_VTAG_TYPE_NOP = 0,\n+\tULP_WP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI = 1,\n+\tULP_WP_SYM_ECV_VTAG_TYPE_ADD_1_IVLAN_PRI = 2,\n+\tULP_WP_SYM_ECV_VTAG_TYPE_ADD_1_REMAP_DIFFSERV = 3,\n+\tULP_WP_SYM_ECV_VTAG_TYPE_ADD_2_ENCAP_PRI = 4,\n+\tULP_WP_SYM_ECV_VTAG_TYPE_ADD_2_REMAP_DIFFSERV = 5,\n+\tULP_WP_SYM_ECV_VTAG_TYPE_ADD_0_ENCAP_PRI = 6,\n+\tULP_WP_SYM_ECV_VTAG_TYPE_ADD_0_REMAP_DIFFSERV = 7,\n+\tULP_WP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_0 = 8,\n+\tULP_WP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_1 = 8,\n+\tULP_WP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_2 = 8,\n+\tULP_WP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_3 = 8,\n+\tULP_WP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_4 = 8,\n+\tULP_WP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_5 = 8,\n+\tULP_WP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_6 = 8,\n+\tULP_WP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_7 = 8,\n+\tULP_WP_SYM_ECV_L3_TYPE_NONE = 0,\n+\tULP_WP_SYM_ECV_L3_TYPE_IPV4 = 4,\n+\tULP_WP_SYM_ECV_L3_TYPE_IPV6 = 5,\n+\tULP_WP_SYM_ECV_L3_TYPE_MPLS_8847 = 6,\n+\tULP_WP_SYM_ECV_L3_TYPE_MPLS_8848 = 7,\n+\tULP_WP_SYM_ECV_L4_TYPE_NONE = 0,\n+\tULP_WP_SYM_ECV_L4_TYPE_UDP = 4,\n+\tULP_WP_SYM_ECV_L4_TYPE_UDP_CSUM = 5,\n+\tULP_WP_SYM_ECV_L4_TYPE_UDP_ENTROPY = 6,\n+\tULP_WP_SYM_ECV_L4_TYPE_UDP_ENTROPY_CSUM = 7,\n+\tULP_WP_SYM_ECV_TUN_TYPE_NONE = 0,\n+\tULP_WP_SYM_ECV_TUN_TYPE_GENERIC = 1,\n+\tULP_WP_SYM_ECV_TUN_TYPE_VXLAN = 2,\n+\tULP_WP_SYM_ECV_TUN_TYPE_NGE = 3,\n+\tULP_WP_SYM_ECV_TUN_TYPE_NVGRE = 4,\n+\tULP_WP_SYM_ECV_TUN_TYPE_GRE = 5,\n+\tULP_WP_SYM_EEM_ACT_REC_INT = 1,\n+\tULP_WP_SYM_EEM_EXT_FLOW_CNTR = 0,\n+\tULP_WP_SYM_UC_ACT_REC = 0,\n+\tULP_WP_SYM_MC_ACT_REC = 1,\n+\tULP_WP_SYM_ACT_REC_DROP_YES = 1,\n+\tULP_WP_SYM_ACT_REC_DROP_NO = 0,\n+\tULP_WP_SYM_ACT_REC_POP_VLAN_YES = 1,\n+\tULP_WP_SYM_ACT_REC_POP_VLAN_NO = 0,\n+\tULP_WP_SYM_ACT_REC_METER_EN_YES = 1,\n+\tULP_WP_SYM_ACT_REC_METER_EN_NO = 0,\n+\tULP_WP_SYM_LOOPBACK_PORT = 4,\n+\tULP_WP_SYM_LOOPBACK_PARIF = 15,\n+\tULP_WP_SYM_EXT_EM_MAX_KEY_SIZE = 448,\n+\tULP_WP_SYM_MATCH_TYPE_EM = 0,\n+\tULP_WP_SYM_MATCH_TYPE_WM = 1,\n+\tULP_WP_SYM_IP_PROTO_ICMP = 1,\n+\tULP_WP_SYM_IP_PROTO_IGMP = 2,\n+\tULP_WP_SYM_IP_PROTO_IP_IN_IP = 4,\n+\tULP_WP_SYM_IP_PROTO_TCP = 6,\n+\tULP_WP_SYM_IP_PROTO_UDP = 17,\n+\tULP_WP_SYM_VF_FUNC_PARIF = 15,\n+\tULP_WP_SYM_NO = 0,\n+\tULP_WP_SYM_YES = 1,\n+\tULP_WP_SYM_RECYCLE_DST = 0x800\n+};\n+\n+enum ulp_sr_sym {\n+\tULP_SR_SYM_PKT_TYPE_IGNORE = 0,\n+\tULP_SR_SYM_PKT_TYPE_L2 = 0,\n+\tULP_SR_SYM_PKT_TYPE_0_IGNORE = 0,\n+\tULP_SR_SYM_PKT_TYPE_0_L2 = 0,\n+\tULP_SR_SYM_PKT_TYPE_1_IGNORE = 0,\n+\tULP_SR_SYM_PKT_TYPE_1_L2 = 0,\n+\tULP_SR_SYM_RECYCLE_CNT_IGNORE = 0,\n+\tULP_SR_SYM_RECYCLE_CNT_ZERO = 0,\n+\tULP_SR_SYM_RECYCLE_CNT_ONE = 1,\n+\tULP_SR_SYM_RECYCLE_CNT_TWO = 2,\n+\tULP_SR_SYM_RECYCLE_CNT_THREE = 3,\n+\tULP_SR_SYM_AGG_ERROR_IGNORE = 0,\n+\tULP_SR_SYM_AGG_ERROR_NO = 0,\n+\tULP_SR_SYM_AGG_ERROR_YES = 1,\n+\tULP_SR_SYM_RESERVED_IGNORE = 0,\n+\tULP_SR_SYM_HREC_NEXT_IGNORE = 0,\n+\tULP_SR_SYM_HREC_NEXT_NO = 0,\n+\tULP_SR_SYM_HREC_NEXT_YES = 1,\n+\tULP_SR_SYM_TL2_HDR_VALID_IGNORE = 0,\n+\tULP_SR_SYM_TL2_HDR_VALID_NO = 0,\n+\tULP_SR_SYM_TL2_HDR_VALID_YES = 1,\n+\tULP_SR_SYM_TL2_HDR_TYPE_IGNORE = 0,\n+\tULP_SR_SYM_TL2_HDR_TYPE_DIX = 0,\n+\tULP_SR_SYM_TL2_UC_MC_BC_IGNORE = 0,\n+\tULP_SR_SYM_TL2_UC_MC_BC_UC = 0,\n+\tULP_SR_SYM_TL2_UC_MC_BC_MC = 2,\n+\tULP_SR_SYM_TL2_UC_MC_BC_BC = 3,\n+\tULP_SR_SYM_TL2_VTAG_PRESENT_IGNORE = 0,\n+\tULP_SR_SYM_TL2_VTAG_PRESENT_NO = 0,\n+\tULP_SR_SYM_TL2_VTAG_PRESENT_YES = 1,\n+\tULP_SR_SYM_TL2_TWO_VTAGS_IGNORE = 0,\n+\tULP_SR_SYM_TL2_TWO_VTAGS_NO = 0,\n+\tULP_SR_SYM_TL2_TWO_VTAGS_YES = 1,\n+\tULP_SR_SYM_TL3_HDR_VALID_IGNORE = 0,\n+\tULP_SR_SYM_TL3_HDR_VALID_NO = 0,\n+\tULP_SR_SYM_TL3_HDR_VALID_YES = 1,\n+\tULP_SR_SYM_TL3_HDR_ERROR_IGNORE = 0,\n+\tULP_SR_SYM_TL3_HDR_ERROR_NO = 0,\n+\tULP_SR_SYM_TL3_HDR_ERROR_YES = 1,\n+\tULP_SR_SYM_TL3_HDR_TYPE_IGNORE = 0,\n+\tULP_SR_SYM_TL3_HDR_TYPE_IPV4 = 0,\n+\tULP_SR_SYM_TL3_HDR_TYPE_IPV6 = 1,\n+\tULP_SR_SYM_TL3_HDR_ISIP_IGNORE = 0,\n+\tULP_SR_SYM_TL3_HDR_ISIP_NO = 0,\n+\tULP_SR_SYM_TL3_HDR_ISIP_YES = 1,\n+\tULP_SR_SYM_TL3_IPV6_CMP_SRC_IGNORE = 0,\n+\tULP_SR_SYM_TL3_IPV6_CMP_SRC_NO = 0,\n+\tULP_SR_SYM_TL3_IPV6_CMP_SRC_YES = 1,\n+\tULP_SR_SYM_TL3_IPV6_CMP_DST_IGNORE = 0,\n+\tULP_SR_SYM_TL3_IPV6_CMP_DST_NO = 0,\n+\tULP_SR_SYM_TL3_IPV6_CMP_DST_YES = 1,\n+\tULP_SR_SYM_TL4_HDR_VALID_IGNORE = 0,\n+\tULP_SR_SYM_TL4_HDR_VALID_NO = 0,\n+\tULP_SR_SYM_TL4_HDR_VALID_YES = 1,\n+\tULP_SR_SYM_TL4_HDR_ERROR_IGNORE = 0,\n+\tULP_SR_SYM_TL4_HDR_ERROR_NO = 0,\n+\tULP_SR_SYM_TL4_HDR_ERROR_YES = 1,\n+\tULP_SR_SYM_TL4_HDR_IS_UDP_TCP_IGNORE = 0,\n+\tULP_SR_SYM_TL4_HDR_IS_UDP_TCP_NO = 0,\n+\tULP_SR_SYM_TL4_HDR_IS_UDP_TCP_YES = 1,\n+\tULP_SR_SYM_TL4_HDR_TYPE_IGNORE = 0,\n+\tULP_SR_SYM_TL4_HDR_TYPE_TCP = 0,\n+\tULP_SR_SYM_TL4_HDR_TYPE_UDP = 1,\n+\tULP_SR_SYM_TUN_HDR_VALID_IGNORE = 0,\n+\tULP_SR_SYM_TUN_HDR_VALID_NO = 0,\n+\tULP_SR_SYM_TUN_HDR_VALID_YES = 1,\n+\tULP_SR_SYM_TUN_HDR_ERROR_IGNORE = 0,\n+\tULP_SR_SYM_TUN_HDR_ERROR_NO = 0,\n+\tULP_SR_SYM_TUN_HDR_ERROR_YES = 1,\n+\tULP_SR_SYM_TUN_HDR_TYPE_IGNORE = 0,\n+\tULP_SR_SYM_TUN_HDR_TYPE_VXLAN = 0,\n+\tULP_SR_SYM_TUN_HDR_TYPE_GENEVE = 1,\n+\tULP_SR_SYM_TUN_HDR_TYPE_NVGRE = 2,\n+\tULP_SR_SYM_TUN_HDR_TYPE_GRE = 3,\n+\tULP_SR_SYM_TUN_HDR_TYPE_IPV4 = 4,\n+\tULP_SR_SYM_TUN_HDR_TYPE_IPV6 = 5,\n+\tULP_SR_SYM_TUN_HDR_TYPE_PPPOE = 6,\n+\tULP_SR_SYM_TUN_HDR_TYPE_MPLS = 7,\n+\tULP_SR_SYM_TUN_HDR_TYPE_UPAR1 = 8,\n+\tULP_SR_SYM_TUN_HDR_TYPE_UPAR2 = 9,\n+\tULP_SR_SYM_TUN_HDR_TYPE_NONE = 15,\n+\tULP_SR_SYM_TUN_HDR_FLAGS_IGNORE = 0,\n+\tULP_SR_SYM_L2_HDR_VALID_IGNORE = 0,\n+\tULP_SR_SYM_L2_HDR_VALID_NO = 0,\n+\tULP_SR_SYM_L2_HDR_VALID_YES = 1,\n+\tULP_SR_SYM_L2_HDR_ERROR_IGNORE = 0,\n+\tULP_SR_SYM_L2_HDR_ERROR_NO = 0,\n+\tULP_SR_SYM_L2_HDR_ERROR_YES = 1,\n+\tULP_SR_SYM_L2_HDR_TYPE_IGNORE = 0,\n+\tULP_SR_SYM_L2_HDR_TYPE_DIX = 0,\n+\tULP_SR_SYM_L2_HDR_TYPE_LLC_SNAP = 1,\n+\tULP_SR_SYM_L2_HDR_TYPE_LLC = 2,\n+\tULP_SR_SYM_L2_UC_MC_BC_IGNORE = 0,\n+\tULP_SR_SYM_L2_UC_MC_BC_UC = 0,\n+\tULP_SR_SYM_L2_UC_MC_BC_MC = 2,\n+\tULP_SR_SYM_L2_UC_MC_BC_BC = 3,\n+\tULP_SR_SYM_L2_VTAG_PRESENT_IGNORE = 0,\n+\tULP_SR_SYM_L2_VTAG_PRESENT_NO = 0,\n+\tULP_SR_SYM_L2_VTAG_PRESENT_YES = 1,\n+\tULP_SR_SYM_L2_TWO_VTAGS_IGNORE = 0,\n+\tULP_SR_SYM_L2_TWO_VTAGS_NO = 0,\n+\tULP_SR_SYM_L2_TWO_VTAGS_YES = 1,\n+\tULP_SR_SYM_L3_HDR_VALID_IGNORE = 0,\n+\tULP_SR_SYM_L3_HDR_VALID_NO = 0,\n+\tULP_SR_SYM_L3_HDR_VALID_YES = 1,\n+\tULP_SR_SYM_L3_HDR_ERROR_IGNORE = 0,\n+\tULP_SR_SYM_L3_HDR_ERROR_NO = 0,\n+\tULP_SR_SYM_L3_HDR_ERROR_YES = 1,\n+\tULP_SR_SYM_L3_HDR_TYPE_IGNORE = 0,\n+\tULP_SR_SYM_L3_HDR_TYPE_IPV4 = 0,\n+\tULP_SR_SYM_L3_HDR_TYPE_IPV6 = 1,\n+\tULP_SR_SYM_L3_HDR_TYPE_ARP = 2,\n+\tULP_SR_SYM_L3_HDR_TYPE_PTP = 3,\n+\tULP_SR_SYM_L3_HDR_TYPE_EAPOL = 4,\n+\tULP_SR_SYM_L3_HDR_TYPE_ROCE = 5,\n+\tULP_SR_SYM_L3_HDR_TYPE_FCOE = 6,\n+\tULP_SR_SYM_L3_HDR_TYPE_UPAR1 = 7,\n+\tULP_SR_SYM_L3_HDR_TYPE_UPAR2 = 8,\n+\tULP_SR_SYM_L3_HDR_ISIP_IGNORE = 0,\n+\tULP_SR_SYM_L3_HDR_ISIP_NO = 0,\n+\tULP_SR_SYM_L3_HDR_ISIP_YES = 1,\n+\tULP_SR_SYM_L3_IPV6_CMP_SRC_IGNORE = 0,\n+\tULP_SR_SYM_L3_IPV6_CMP_SRC_NO = 0,\n+\tULP_SR_SYM_L3_IPV6_CMP_SRC_YES = 1,\n+\tULP_SR_SYM_L3_IPV6_CMP_DST_IGNORE = 0,\n+\tULP_SR_SYM_L3_IPV6_CMP_DST_NO = 0,\n+\tULP_SR_SYM_L3_IPV6_CMP_DST_YES = 1,\n+\tULP_SR_SYM_L4_HDR_VALID_IGNORE = 0,\n+\tULP_SR_SYM_L4_HDR_VALID_NO = 0,\n+\tULP_SR_SYM_L4_HDR_VALID_YES = 1,\n+\tULP_SR_SYM_L4_HDR_ERROR_IGNORE = 0,\n+\tULP_SR_SYM_L4_HDR_ERROR_NO = 0,\n+\tULP_SR_SYM_L4_HDR_ERROR_YES = 1,\n+\tULP_SR_SYM_L4_HDR_TYPE_IGNORE = 0,\n+\tULP_SR_SYM_L4_HDR_TYPE_TCP = 0,\n+\tULP_SR_SYM_L4_HDR_TYPE_UDP = 1,\n+\tULP_SR_SYM_L4_HDR_TYPE_ICMP = 2,\n+\tULP_SR_SYM_L4_HDR_TYPE_UPAR1 = 3,\n+\tULP_SR_SYM_L4_HDR_TYPE_UPAR2 = 4,\n+\tULP_SR_SYM_L4_HDR_TYPE_BTH_V1 = 5,\n+\tULP_SR_SYM_L4_HDR_IS_UDP_TCP_IGNORE = 0,\n+\tULP_SR_SYM_L4_HDR_IS_UDP_TCP_NO = 0,\n+\tULP_SR_SYM_L4_HDR_IS_UDP_TCP_YES = 1,\n+\tULP_SR_SYM_POP_VLAN_NO = 0,\n+\tULP_SR_SYM_POP_VLAN_YES = 1,\n+\tULP_SR_SYM_DECAP_FUNC_NONE = 0,\n+\tULP_SR_SYM_DECAP_FUNC_THRU_TL2 = 3,\n+\tULP_SR_SYM_DECAP_FUNC_THRU_TL3 = 8,\n+\tULP_SR_SYM_DECAP_FUNC_THRU_TL4 = 9,\n+\tULP_SR_SYM_DECAP_FUNC_THRU_TUN = 10,\n+\tULP_SR_SYM_DECAP_FUNC_THRU_L2 = 11,\n+\tULP_SR_SYM_DECAP_FUNC_THRU_L3 = 12,\n+\tULP_SR_SYM_DECAP_FUNC_THRU_L4 = 13,\n+\tULP_SR_SYM_ECV_VALID_NO = 0,\n+\tULP_SR_SYM_ECV_VALID_YES = 1,\n+\tULP_SR_SYM_ECV_CUSTOM_EN_NO = 0,\n+\tULP_SR_SYM_ECV_CUSTOM_EN_YES = 1,\n+\tULP_SR_SYM_ECV_L2_EN_NO = 0,\n+\tULP_SR_SYM_ECV_L2_EN_YES = 1,\n+\tULP_SR_SYM_ECV_VTAG_TYPE_NOP = 0,\n+\tULP_SR_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI = 1,\n+\tULP_SR_SYM_ECV_VTAG_TYPE_ADD_1_IVLAN_PRI = 2,\n+\tULP_SR_SYM_ECV_VTAG_TYPE_ADD_1_REMAP_DIFFSERV = 3,\n+\tULP_SR_SYM_ECV_VTAG_TYPE_ADD_2_ENCAP_PRI = 4,\n+\tULP_SR_SYM_ECV_VTAG_TYPE_ADD_2_REMAP_DIFFSERV = 5,\n+\tULP_SR_SYM_ECV_VTAG_TYPE_ADD_0_ENCAP_PRI = 6,\n+\tULP_SR_SYM_ECV_VTAG_TYPE_ADD_0_REMAP_DIFFSERV = 7,\n+\tULP_SR_SYM_ECV_VTAG_TYPE_ADD_0_PRI_0 = 8,\n+\tULP_SR_SYM_ECV_VTAG_TYPE_ADD_0_PRI_1 = 8,\n+\tULP_SR_SYM_ECV_VTAG_TYPE_ADD_0_PRI_2 = 8,\n+\tULP_SR_SYM_ECV_VTAG_TYPE_ADD_0_PRI_3 = 8,\n+\tULP_SR_SYM_ECV_VTAG_TYPE_ADD_0_PRI_4 = 8,\n+\tULP_SR_SYM_ECV_VTAG_TYPE_ADD_0_PRI_5 = 8,\n+\tULP_SR_SYM_ECV_VTAG_TYPE_ADD_0_PRI_6 = 8,\n+\tULP_SR_SYM_ECV_VTAG_TYPE_ADD_0_PRI_7 = 8,\n+\tULP_SR_SYM_ECV_L3_TYPE_NONE = 0,\n+\tULP_SR_SYM_ECV_L3_TYPE_IPV4 = 4,\n+\tULP_SR_SYM_ECV_L3_TYPE_IPV6 = 5,\n+\tULP_SR_SYM_ECV_L3_TYPE_MPLS_8847 = 6,\n+\tULP_SR_SYM_ECV_L3_TYPE_MPLS_8848 = 7,\n+\tULP_SR_SYM_ECV_L4_TYPE_NONE = 0,\n+\tULP_SR_SYM_ECV_L4_TYPE_UDP = 4,\n+\tULP_SR_SYM_ECV_L4_TYPE_UDP_CSUM = 5,\n+\tULP_SR_SYM_ECV_L4_TYPE_UDP_ENTROPY = 6,\n+\tULP_SR_SYM_ECV_L4_TYPE_UDP_ENTROPY_CSUM = 7,\n+\tULP_SR_SYM_ECV_TUN_TYPE_NONE = 0,\n+\tULP_SR_SYM_ECV_TUN_TYPE_GENERIC = 1,\n+\tULP_SR_SYM_ECV_TUN_TYPE_VXLAN = 2,\n+\tULP_SR_SYM_ECV_TUN_TYPE_NGE = 3,\n+\tULP_SR_SYM_ECV_TUN_TYPE_NVGRE = 4,\n+\tULP_SR_SYM_ECV_TUN_TYPE_GRE = 5,\n+\tULP_SR_SYM_EEM_ACT_REC_INT = 0,\n+\tULP_SR_SYM_EEM_EXT_FLOW_CNTR = 1,\n+\tULP_SR_SYM_UC_ACT_REC = 0,\n+\tULP_SR_SYM_MC_ACT_REC = 1,\n+\tULP_SR_SYM_ACT_REC_DROP_YES = 1,\n+\tULP_SR_SYM_ACT_REC_DROP_NO = 0,\n+\tULP_SR_SYM_ACT_REC_POP_VLAN_YES = 1,\n+\tULP_SR_SYM_ACT_REC_POP_VLAN_NO = 0,\n+\tULP_SR_SYM_ACT_REC_METER_EN_YES = 1,\n+\tULP_SR_SYM_ACT_REC_METER_EN_NO = 0,\n+\tULP_SR_SYM_LOOPBACK_PORT = 16,\n+\tULP_SR_SYM_LOOPBACK_PARIF = 15,\n+\tULP_SR_SYM_EXT_EM_MAX_KEY_SIZE = 448,\n+\tULP_SR_SYM_MATCH_TYPE_EM = 0,\n+\tULP_SR_SYM_MATCH_TYPE_WM = 1,\n+\tULP_SR_SYM_IP_PROTO_ICMP = 1,\n+\tULP_SR_SYM_IP_PROTO_IGMP = 2,\n+\tULP_SR_SYM_IP_PROTO_IP_IN_IP = 4,\n+\tULP_SR_SYM_IP_PROTO_TCP = 6,\n+\tULP_SR_SYM_IP_PROTO_UDP = 17,\n+\tULP_SR_SYM_VF_FUNC_PARIF = 15,\n+\tULP_SR_SYM_NO = 0,\n+\tULP_SR_SYM_YES = 1,\n+\tULP_SR_SYM_RECYCLE_DST = 0x800\n };\n \n enum bnxt_ulp_class_hid {\n-\tBNXT_ULP_CLASS_HID_00fc = 0x00fc,\n-\tBNXT_ULP_CLASS_HID_0046 = 0x0046,\n-\tBNXT_ULP_CLASS_HID_0056 = 0x0056,\n-\tBNXT_ULP_CLASS_HID_00b8 = 0x00b8,\n-\tBNXT_ULP_CLASS_HID_0041 = 0x0041,\n-\tBNXT_ULP_CLASS_HID_00ab = 0x00ab,\n-\tBNXT_ULP_CLASS_HID_0053 = 0x0053,\n-\tBNXT_ULP_CLASS_HID_00a5 = 0x00a5,\n-\tBNXT_ULP_CLASS_HID_0069 = 0x0069,\n-\tBNXT_ULP_CLASS_HID_009d = 0x009d,\n+\tBNXT_ULP_CLASS_HID_07e0 = 0x07e0,\n+\tBNXT_ULP_CLASS_HID_01dc = 0x01dc,\n+\tBNXT_ULP_CLASS_HID_006e = 0x006e,\n+\tBNXT_ULP_CLASS_HID_025a = 0x025a,\n+\tBNXT_ULP_CLASS_HID_0146 = 0x0146,\n+\tBNXT_ULP_CLASS_HID_0332 = 0x0332,\n+\tBNXT_ULP_CLASS_HID_01c4 = 0x01c4,\n+\tBNXT_ULP_CLASS_HID_078a = 0x078a,\n+\tBNXT_ULP_CLASS_HID_02ed = 0x02ed,\n+\tBNXT_ULP_CLASS_HID_04d9 = 0x04d9,\n+\tBNXT_ULP_CLASS_HID_036b = 0x036b,\n+\tBNXT_ULP_CLASS_HID_0131 = 0x0131,\n+\tBNXT_ULP_CLASS_HID_0217 = 0x0217,\n+\tBNXT_ULP_CLASS_HID_03c3 = 0x03c3,\n+\tBNXT_ULP_CLASS_HID_0295 = 0x0295,\n+\tBNXT_ULP_CLASS_HID_0441 = 0x0441,\n+\tBNXT_ULP_CLASS_HID_0095 = 0x0095,\n+\tBNXT_ULP_CLASS_HID_0241 = 0x0241,\n+\tBNXT_ULP_CLASS_HID_04ed = 0x04ed,\n+\tBNXT_ULP_CLASS_HID_06d9 = 0x06d9,\n+\tBNXT_ULP_CLASS_HID_07bf = 0x07bf,\n+\tBNXT_ULP_CLASS_HID_016b = 0x016b,\n+\tBNXT_ULP_CLASS_HID_0417 = 0x0417,\n+\tBNXT_ULP_CLASS_HID_05c3 = 0x05c3,\n+\tBNXT_ULP_CLASS_HID_0187 = 0x0187,\n+\tBNXT_ULP_CLASS_HID_0373 = 0x0373,\n+\tBNXT_ULP_CLASS_HID_0205 = 0x0205,\n+\tBNXT_ULP_CLASS_HID_03f1 = 0x03f1,\n+\tBNXT_ULP_CLASS_HID_00a1 = 0x00a1,\n+\tBNXT_ULP_CLASS_HID_029d = 0x029d,\n+\tBNXT_ULP_CLASS_HID_012f = 0x012f,\n+\tBNXT_ULP_CLASS_HID_031b = 0x031b,\n+\tBNXT_ULP_CLASS_HID_072f = 0x072f,\n+\tBNXT_ULP_CLASS_HID_011b = 0x011b,\n+\tBNXT_ULP_CLASS_HID_0387 = 0x0387,\n+\tBNXT_ULP_CLASS_HID_0573 = 0x0573,\n+\tBNXT_ULP_CLASS_HID_0649 = 0x0649,\n \tBNXT_ULP_CLASS_HID_0005 = 0x0005,\n-\tBNXT_ULP_CLASS_HID_006f = 0x006f,\n-\tBNXT_ULP_CLASS_HID_00af = 0x00af,\n-\tBNXT_ULP_CLASS_HID_00d3 = 0x00d3,\n-\tBNXT_ULP_CLASS_HID_005b = 0x005b,\n-\tBNXT_ULP_CLASS_HID_00ad = 0x00ad,\n-\tBNXT_ULP_CLASS_HID_0091 = 0x0091,\n-\tBNXT_ULP_CLASS_HID_00fb = 0x00fb,\n-\tBNXT_ULP_CLASS_HID_0063 = 0x0063,\n-\tBNXT_ULP_CLASS_HID_0097 = 0x0097,\n-\tBNXT_ULP_CLASS_HID_00cc = 0x00cc,\n-\tBNXT_ULP_CLASS_HID_00f0 = 0x00f0,\n-\tBNXT_ULP_CLASS_HID_00c0 = 0x00c0,\n-\tBNXT_ULP_CLASS_HID_002a = 0x002a,\n-\tBNXT_ULP_CLASS_HID_00c7 = 0x00c7,\n-\tBNXT_ULP_CLASS_HID_0029 = 0x0029,\n-\tBNXT_ULP_CLASS_HID_00d1 = 0x00d1,\n-\tBNXT_ULP_CLASS_HID_003b = 0x003b,\n+\tBNXT_ULP_CLASS_HID_02a1 = 0x02a1,\n+\tBNXT_ULP_CLASS_HID_049d = 0x049d,\n+\tBNXT_ULP_CLASS_HID_01ea = 0x01ea,\n+\tBNXT_ULP_CLASS_HID_03de = 0x03de,\n+\tBNXT_ULP_CLASS_HID_0672 = 0x0672,\n+\tBNXT_ULP_CLASS_HID_0026 = 0x0026,\n+\tBNXT_ULP_CLASS_HID_0746 = 0x0746,\n+\tBNXT_ULP_CLASS_HID_010a = 0x010a,\n+\tBNXT_ULP_CLASS_HID_03ae = 0x03ae,\n+\tBNXT_ULP_CLASS_HID_0592 = 0x0592,\n+\tBNXT_ULP_CLASS_HID_07d0 = 0x07d0,\n+\tBNXT_ULP_CLASS_HID_01ec = 0x01ec,\n+\tBNXT_ULP_CLASS_HID_005e = 0x005e,\n+\tBNXT_ULP_CLASS_HID_026a = 0x026a,\n+\tBNXT_ULP_CLASS_HID_0176 = 0x0176,\n+\tBNXT_ULP_CLASS_HID_0302 = 0x0302,\n+\tBNXT_ULP_CLASS_HID_01f4 = 0x01f4,\n+\tBNXT_ULP_CLASS_HID_07ba = 0x07ba,\n+\tBNXT_ULP_CLASS_HID_06a7 = 0x06a7,\n+\tBNXT_ULP_CLASS_HID_006b = 0x006b,\n+\tBNXT_ULP_CLASS_HID_0725 = 0x0725,\n+\tBNXT_ULP_CLASS_HID_00e9 = 0x00e9,\n+\tBNXT_ULP_CLASS_HID_05d9 = 0x05d9,\n+\tBNXT_ULP_CLASS_HID_078d = 0x078d,\n+\tBNXT_ULP_CLASS_HID_065f = 0x065f,\n+\tBNXT_ULP_CLASS_HID_0003 = 0x0003,\n+\tBNXT_ULP_CLASS_HID_045f = 0x045f,\n+\tBNXT_ULP_CLASS_HID_0603 = 0x0603,\n+\tBNXT_ULP_CLASS_HID_00a7 = 0x00a7,\n+\tBNXT_ULP_CLASS_HID_026b = 0x026b,\n+\tBNXT_ULP_CLASS_HID_0371 = 0x0371,\n+\tBNXT_ULP_CLASS_HID_0525 = 0x0525,\n+\tBNXT_ULP_CLASS_HID_07d9 = 0x07d9,\n+\tBNXT_ULP_CLASS_HID_018d = 0x018d,\n+\tBNXT_ULP_CLASS_HID_0177 = 0x0177,\n+\tBNXT_ULP_CLASS_HID_033b = 0x033b,\n+\tBNXT_ULP_CLASS_HID_05df = 0x05df,\n+\tBNXT_ULP_CLASS_HID_0783 = 0x0783,\n+\tBNXT_ULP_CLASS_HID_0069 = 0x0069,\n+\tBNXT_ULP_CLASS_HID_025d = 0x025d,\n \tBNXT_ULP_CLASS_HID_00ef = 0x00ef,\n-\tBNXT_ULP_CLASS_HID_0013 = 0x0013,\n-\tBNXT_ULP_CLASS_HID_009b = 0x009b,\n-\tBNXT_ULP_CLASS_HID_00ed = 0x00ed,\n-\tBNXT_ULP_CLASS_HID_002d = 0x002d,\n-\tBNXT_ULP_CLASS_HID_0051 = 0x0051,\n+\tBNXT_ULP_CLASS_HID_06a5 = 0x06a5,\n+\tBNXT_ULP_CLASS_HID_02f1 = 0x02f1,\n+\tBNXT_ULP_CLASS_HID_04a5 = 0x04a5,\n+\tBNXT_ULP_CLASS_HID_0377 = 0x0377,\n+\tBNXT_ULP_CLASS_HID_053b = 0x053b,\n+\tBNXT_ULP_CLASS_HID_0601 = 0x0601,\n+\tBNXT_ULP_CLASS_HID_03df = 0x03df,\n+\tBNXT_ULP_CLASS_HID_0269 = 0x0269,\n+\tBNXT_ULP_CLASS_HID_045d = 0x045d,\n+\tBNXT_ULP_CLASS_HID_02dd = 0x02dd,\n+\tBNXT_ULP_CLASS_HID_04e9 = 0x04e9,\n+\tBNXT_ULP_CLASS_HID_035b = 0x035b,\n+\tBNXT_ULP_CLASS_HID_0101 = 0x0101,\n+\tBNXT_ULP_CLASS_HID_0227 = 0x0227,\n+\tBNXT_ULP_CLASS_HID_03f3 = 0x03f3,\n+\tBNXT_ULP_CLASS_HID_02a5 = 0x02a5,\n+\tBNXT_ULP_CLASS_HID_0471 = 0x0471,\n+\tBNXT_ULP_CLASS_HID_00a5 = 0x00a5,\n+\tBNXT_ULP_CLASS_HID_0271 = 0x0271,\n+\tBNXT_ULP_CLASS_HID_04dd = 0x04dd,\n+\tBNXT_ULP_CLASS_HID_06e9 = 0x06e9,\n+\tBNXT_ULP_CLASS_HID_078f = 0x078f,\n+\tBNXT_ULP_CLASS_HID_015b = 0x015b,\n+\tBNXT_ULP_CLASS_HID_0427 = 0x0427,\n+\tBNXT_ULP_CLASS_HID_05f3 = 0x05f3,\n+\tBNXT_ULP_CLASS_HID_01b7 = 0x01b7,\n+\tBNXT_ULP_CLASS_HID_0343 = 0x0343,\n+\tBNXT_ULP_CLASS_HID_0235 = 0x0235,\n+\tBNXT_ULP_CLASS_HID_03c1 = 0x03c1,\n+\tBNXT_ULP_CLASS_HID_0091 = 0x0091,\n+\tBNXT_ULP_CLASS_HID_02ad = 0x02ad,\n+\tBNXT_ULP_CLASS_HID_011f = 0x011f,\n+\tBNXT_ULP_CLASS_HID_032b = 0x032b,\n+\tBNXT_ULP_CLASS_HID_071f = 0x071f,\n+\tBNXT_ULP_CLASS_HID_012b = 0x012b,\n+\tBNXT_ULP_CLASS_HID_03b7 = 0x03b7,\n+\tBNXT_ULP_CLASS_HID_0543 = 0x0543,\n+\tBNXT_ULP_CLASS_HID_0679 = 0x0679,\n+\tBNXT_ULP_CLASS_HID_0035 = 0x0035,\n+\tBNXT_ULP_CLASS_HID_0291 = 0x0291,\n+\tBNXT_ULP_CLASS_HID_04ad = 0x04ad,\n+\tBNXT_ULP_CLASS_HID_01da = 0x01da,\n+\tBNXT_ULP_CLASS_HID_03ee = 0x03ee,\n+\tBNXT_ULP_CLASS_HID_0642 = 0x0642,\n+\tBNXT_ULP_CLASS_HID_0016 = 0x0016,\n+\tBNXT_ULP_CLASS_HID_0776 = 0x0776,\n+\tBNXT_ULP_CLASS_HID_013a = 0x013a,\n+\tBNXT_ULP_CLASS_HID_039e = 0x039e,\n+\tBNXT_ULP_CLASS_HID_05a2 = 0x05a2,\n+\tBNXT_ULP_CLASS_HID_0697 = 0x0697,\n+\tBNXT_ULP_CLASS_HID_005b = 0x005b,\n+\tBNXT_ULP_CLASS_HID_0715 = 0x0715,\n \tBNXT_ULP_CLASS_HID_00d9 = 0x00d9,\n-\tBNXT_ULP_CLASS_HID_0023 = 0x0023,\n-\tBNXT_ULP_CLASS_HID_0017 = 0x0017,\n-\tBNXT_ULP_CLASS_HID_0079 = 0x0079,\n-\tBNXT_ULP_CLASS_HID_00e1 = 0x00e1,\n-\tBNXT_ULP_CLASS_HID_0015 = 0x0015\n+\tBNXT_ULP_CLASS_HID_05e9 = 0x05e9,\n+\tBNXT_ULP_CLASS_HID_07bd = 0x07bd,\n+\tBNXT_ULP_CLASS_HID_066f = 0x066f,\n+\tBNXT_ULP_CLASS_HID_0033 = 0x0033,\n+\tBNXT_ULP_CLASS_HID_046f = 0x046f,\n+\tBNXT_ULP_CLASS_HID_0633 = 0x0633,\n+\tBNXT_ULP_CLASS_HID_0097 = 0x0097,\n+\tBNXT_ULP_CLASS_HID_025b = 0x025b,\n+\tBNXT_ULP_CLASS_HID_0341 = 0x0341,\n+\tBNXT_ULP_CLASS_HID_0515 = 0x0515,\n+\tBNXT_ULP_CLASS_HID_07e9 = 0x07e9,\n+\tBNXT_ULP_CLASS_HID_01bd = 0x01bd,\n+\tBNXT_ULP_CLASS_HID_0147 = 0x0147,\n+\tBNXT_ULP_CLASS_HID_030b = 0x030b,\n+\tBNXT_ULP_CLASS_HID_05ef = 0x05ef,\n+\tBNXT_ULP_CLASS_HID_07b3 = 0x07b3,\n+\tBNXT_ULP_CLASS_HID_0059 = 0x0059,\n+\tBNXT_ULP_CLASS_HID_026d = 0x026d,\n+\tBNXT_ULP_CLASS_HID_00df = 0x00df,\n+\tBNXT_ULP_CLASS_HID_0695 = 0x0695,\n+\tBNXT_ULP_CLASS_HID_02c1 = 0x02c1,\n+\tBNXT_ULP_CLASS_HID_0495 = 0x0495,\n+\tBNXT_ULP_CLASS_HID_0347 = 0x0347,\n+\tBNXT_ULP_CLASS_HID_050b = 0x050b,\n+\tBNXT_ULP_CLASS_HID_0631 = 0x0631,\n+\tBNXT_ULP_CLASS_HID_03ef = 0x03ef,\n+\tBNXT_ULP_CLASS_HID_0259 = 0x0259,\n+\tBNXT_ULP_CLASS_HID_046d = 0x046d\n };\n \n enum bnxt_ulp_act_hid {\n@@ -1013,11 +1139,11 @@ enum bnxt_ulp_act_hid {\n };\n \n enum bnxt_ulp_df_tpl {\n-\tBNXT_ULP_DF_TPL_PORT_TO_VS = 3,\n-\tBNXT_ULP_DF_TPL_VS_TO_PORT = 4,\n-\tBNXT_ULP_DF_TPL_VFREP_TO_VF = 5,\n-\tBNXT_ULP_DF_TPL_VF_TO_VFREP = 6,\n-\tBNXT_ULP_DF_TPL_LOOPBACK_ACTION_REC = 7\n+\tBNXT_ULP_DF_TPL_PORT_TO_VS = 2,\n+\tBNXT_ULP_DF_TPL_VS_TO_PORT = 3,\n+\tBNXT_ULP_DF_TPL_VFREP_TO_VF = 4,\n+\tBNXT_ULP_DF_TPL_VF_TO_VFREP = 5,\n+\tBNXT_ULP_DF_TPL_LOOPBACK_ACTION_REC = 6\n };\n \n #endif\ndiff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h\nindex 0e7278a38f..0e197e362e 100644\n--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h\n+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h\n@@ -3,108 +3,108 @@\n  * All rights reserved.\n  */\n \n-/* date: Wed Nov 18 12:19:40 2020 */\n+/* date: Tue Dec  1 10:17:11 2020 */\n \n #ifndef ULP_HDR_FIELD_ENUMS_H_\n #define ULP_HDR_FIELD_ENUMS_H_\n \n enum bnxt_ulp_glb_hf {\n-\tBNXT_ULP_GLB_HF_WM,\n-\tBNXT_ULP_GLB_HF_SVIF_INDEX,\n-\tBNXT_ULP_GLB_HF_O_ETH_DMAC,\n-\tBNXT_ULP_GLB_HF_I_ETH_DMAC,\n-\tBNXT_ULP_GLB_HF_O_ETH_SMAC,\n-\tBNXT_ULP_GLB_HF_I_ETH_SMAC,\n-\tBNXT_ULP_GLB_HF_O_ETH_TYPE,\n-\tBNXT_ULP_GLB_HF_I_ETH_TYPE,\n-\tBNXT_ULP_GLB_HF_O_IPV4_VER,\n-\tBNXT_ULP_GLB_HF_I_IPV4_VER,\n-\tBNXT_ULP_GLB_HF_O_IPV4_TOS,\n-\tBNXT_ULP_GLB_HF_I_IPV4_TOS,\n-\tBNXT_ULP_GLB_HF_O_IPV4_LEN,\n-\tBNXT_ULP_GLB_HF_I_IPV4_LEN,\n-\tBNXT_ULP_GLB_HF_O_IPV4_FRAG_ID,\n-\tBNXT_ULP_GLB_HF_I_IPV4_FRAG_ID,\n-\tBNXT_ULP_GLB_HF_O_IPV4_FRAG_OFF,\n-\tBNXT_ULP_GLB_HF_I_IPV4_FRAG_OFF,\n-\tBNXT_ULP_GLB_HF_O_IPV4_TTL,\n-\tBNXT_ULP_GLB_HF_I_IPV4_TTL,\n-\tBNXT_ULP_GLB_HF_O_IPV4_PROTO_ID,\n-\tBNXT_ULP_GLB_HF_I_IPV4_PROTO_ID,\n-\tBNXT_ULP_GLB_HF_O_IPV4_CSUM,\n-\tBNXT_ULP_GLB_HF_I_IPV4_CSUM,\n-\tBNXT_ULP_GLB_HF_O_IPV4_SRC_ADDR,\n-\tBNXT_ULP_GLB_HF_I_IPV4_SRC_ADDR,\n-\tBNXT_ULP_GLB_HF_O_IPV4_DST_ADDR,\n-\tBNXT_ULP_GLB_HF_I_IPV4_DST_ADDR,\n-\tBNXT_ULP_GLB_HF_O_IPV6_VER,\n-\tBNXT_ULP_GLB_HF_I_IPV6_VER,\n-\tBNXT_ULP_GLB_HF_O_IPV6_TC,\n-\tBNXT_ULP_GLB_HF_I_IPV6_TC,\n-\tBNXT_ULP_GLB_HF_O_IPV6_FLOW_LABEL,\n-\tBNXT_ULP_GLB_HF_I_IPV6_FLOW_LABEL,\n-\tBNXT_ULP_GLB_HF_O_IPV6_PAYLOAD_LEN,\n-\tBNXT_ULP_GLB_HF_I_IPV6_PAYLOAD_LEN,\n-\tBNXT_ULP_GLB_HF_O_IPV6_PROTO_ID,\n-\tBNXT_ULP_GLB_HF_I_IPV6_PROTO_ID,\n-\tBNXT_ULP_GLB_HF_O_IPV6_TTL,\n-\tBNXT_ULP_GLB_HF_I_IPV6_TTL,\n-\tBNXT_ULP_GLB_HF_O_IPV6_SRC_ADDR,\n-\tBNXT_ULP_GLB_HF_I_IPV6_SRC_ADDR,\n-\tBNXT_ULP_GLB_HF_O_IPV6_DST_ADDR,\n-\tBNXT_ULP_GLB_HF_I_IPV6_DST_ADDR,\n-\tBNXT_ULP_GLB_HF_O_L3_PROTO_ID,\n-\tBNXT_ULP_GLB_HF_I_L3_PROTO_ID,\n-\tBNXT_ULP_GLB_HF_O_L3_SRC_ADDR,\n-\tBNXT_ULP_GLB_HF_I_L3_SRC_ADDR,\n-\tBNXT_ULP_GLB_HF_O_L3_DST_ADDR,\n-\tBNXT_ULP_GLB_HF_I_L3_DST_ADDR,\n-\tBNXT_ULP_GLB_HF_O_L4_SRC_PORT,\n-\tBNXT_ULP_GLB_HF_I_L4_SRC_PORT,\n-\tBNXT_ULP_GLB_HF_O_L4_DST_PORT,\n-\tBNXT_ULP_GLB_HF_I_L4_DST_PORT,\n-\tBNXT_ULP_GLB_HF_O_TCP_SRC_PORT,\n-\tBNXT_ULP_GLB_HF_I_TCP_SRC_PORT,\n-\tBNXT_ULP_GLB_HF_O_TCP_DST_PORT,\n-\tBNXT_ULP_GLB_HF_I_TCP_DST_PORT,\n-\tBNXT_ULP_GLB_HF_O_TCP_SENT_SEQ,\n-\tBNXT_ULP_GLB_HF_I_TCP_SENT_SEQ,\n-\tBNXT_ULP_GLB_HF_O_TCP_RECV_ACK,\n-\tBNXT_ULP_GLB_HF_I_TCP_RECV_ACK,\n-\tBNXT_ULP_GLB_HF_O_TCP_DATA_OFF,\n-\tBNXT_ULP_GLB_HF_I_TCP_DATA_OFF,\n-\tBNXT_ULP_GLB_HF_O_TCP_TCP_FLAGS,\n-\tBNXT_ULP_GLB_HF_I_TCP_TCP_FLAGS,\n-\tBNXT_ULP_GLB_HF_O_TCP_RX_WIN,\n-\tBNXT_ULP_GLB_HF_I_TCP_RX_WIN,\n-\tBNXT_ULP_GLB_HF_O_TCP_CSUM,\n-\tBNXT_ULP_GLB_HF_I_TCP_CSUM,\n-\tBNXT_ULP_GLB_HF_O_TCP_URP,\n-\tBNXT_ULP_GLB_HF_I_TCP_URP,\n-\tBNXT_ULP_GLB_HF_O_UDP_SRC_PORT,\n-\tBNXT_ULP_GLB_HF_I_UDP_SRC_PORT,\n-\tBNXT_ULP_GLB_HF_O_UDP_DST_PORT,\n-\tBNXT_ULP_GLB_HF_I_UDP_DST_PORT,\n-\tBNXT_ULP_GLB_HF_O_UDP_LENGTH,\n-\tBNXT_ULP_GLB_HF_I_UDP_LENGTH,\n-\tBNXT_ULP_GLB_HF_O_UDP_CSUM,\n-\tBNXT_ULP_GLB_HF_I_UDP_CSUM,\n-\tBNXT_ULP_GLB_HF_OO_VLAN_CFI_PRI,\n-\tBNXT_ULP_GLB_HF_OI_VLAN_CFI_PRI,\n-\tBNXT_ULP_GLB_HF_IO_VLAN_CFI_PRI,\n-\tBNXT_ULP_GLB_HF_II_VLAN_CFI_PRI,\n-\tBNXT_ULP_GLB_HF_OO_VLAN_VID,\n-\tBNXT_ULP_GLB_HF_OI_VLAN_VID,\n-\tBNXT_ULP_GLB_HF_IO_VLAN_VID,\n-\tBNXT_ULP_GLB_HF_II_VLAN_VID,\n-\tBNXT_ULP_GLB_HF_OO_VLAN_TYPE,\n-\tBNXT_ULP_GLB_HF_OI_VLAN_TYPE,\n-\tBNXT_ULP_GLB_HF_IO_VLAN_TYPE,\n-\tBNXT_ULP_GLB_HF_II_VLAN_TYPE,\n-\tBNXT_ULP_GLB_HF_T_VXLAN_FLAGS,\n-\tBNXT_ULP_GLB_HF_T_VXLAN_RSVD0,\n-\tBNXT_ULP_GLB_HF_T_VXLAN_VNI,\n-\tBNXT_ULP_GLB_HF_T_VXLAN_RSVD1\n+\tBNXT_ULP_GLB_HF_ID_WM,\n+\tBNXT_ULP_GLB_HF_ID_SVIF_INDEX,\n+\tBNXT_ULP_GLB_HF_ID_O_ETH_DMAC,\n+\tBNXT_ULP_GLB_HF_ID_I_ETH_DMAC,\n+\tBNXT_ULP_GLB_HF_ID_O_ETH_SMAC,\n+\tBNXT_ULP_GLB_HF_ID_I_ETH_SMAC,\n+\tBNXT_ULP_GLB_HF_ID_O_ETH_TYPE,\n+\tBNXT_ULP_GLB_HF_ID_I_ETH_TYPE,\n+\tBNXT_ULP_GLB_HF_ID_O_IPV4_VER,\n+\tBNXT_ULP_GLB_HF_ID_I_IPV4_VER,\n+\tBNXT_ULP_GLB_HF_ID_O_IPV4_TOS,\n+\tBNXT_ULP_GLB_HF_ID_I_IPV4_TOS,\n+\tBNXT_ULP_GLB_HF_ID_O_IPV4_LEN,\n+\tBNXT_ULP_GLB_HF_ID_I_IPV4_LEN,\n+\tBNXT_ULP_GLB_HF_ID_O_IPV4_FRAG_ID,\n+\tBNXT_ULP_GLB_HF_ID_I_IPV4_FRAG_ID,\n+\tBNXT_ULP_GLB_HF_ID_O_IPV4_FRAG_OFF,\n+\tBNXT_ULP_GLB_HF_ID_I_IPV4_FRAG_OFF,\n+\tBNXT_ULP_GLB_HF_ID_O_IPV4_TTL,\n+\tBNXT_ULP_GLB_HF_ID_I_IPV4_TTL,\n+\tBNXT_ULP_GLB_HF_ID_O_IPV4_PROTO_ID,\n+\tBNXT_ULP_GLB_HF_ID_I_IPV4_PROTO_ID,\n+\tBNXT_ULP_GLB_HF_ID_O_IPV4_CSUM,\n+\tBNXT_ULP_GLB_HF_ID_I_IPV4_CSUM,\n+\tBNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR,\n+\tBNXT_ULP_GLB_HF_ID_I_IPV4_SRC_ADDR,\n+\tBNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR,\n+\tBNXT_ULP_GLB_HF_ID_I_IPV4_DST_ADDR,\n+\tBNXT_ULP_GLB_HF_ID_O_IPV6_VER,\n+\tBNXT_ULP_GLB_HF_ID_I_IPV6_VER,\n+\tBNXT_ULP_GLB_HF_ID_O_IPV6_TC,\n+\tBNXT_ULP_GLB_HF_ID_I_IPV6_TC,\n+\tBNXT_ULP_GLB_HF_ID_O_IPV6_FLOW_LABEL,\n+\tBNXT_ULP_GLB_HF_ID_I_IPV6_FLOW_LABEL,\n+\tBNXT_ULP_GLB_HF_ID_O_IPV6_PAYLOAD_LEN,\n+\tBNXT_ULP_GLB_HF_ID_I_IPV6_PAYLOAD_LEN,\n+\tBNXT_ULP_GLB_HF_ID_O_IPV6_PROTO_ID,\n+\tBNXT_ULP_GLB_HF_ID_I_IPV6_PROTO_ID,\n+\tBNXT_ULP_GLB_HF_ID_O_IPV6_TTL,\n+\tBNXT_ULP_GLB_HF_ID_I_IPV6_TTL,\n+\tBNXT_ULP_GLB_HF_ID_O_IPV6_SRC_ADDR,\n+\tBNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR,\n+\tBNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR,\n+\tBNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR,\n+\tBNXT_ULP_GLB_HF_ID_O_L3_PROTO_ID,\n+\tBNXT_ULP_GLB_HF_ID_I_L3_PROTO_ID,\n+\tBNXT_ULP_GLB_HF_ID_O_L3_SRC_ADDR,\n+\tBNXT_ULP_GLB_HF_ID_I_L3_SRC_ADDR,\n+\tBNXT_ULP_GLB_HF_ID_O_L3_DST_ADDR,\n+\tBNXT_ULP_GLB_HF_ID_I_L3_DST_ADDR,\n+\tBNXT_ULP_GLB_HF_ID_O_L4_SRC_PORT,\n+\tBNXT_ULP_GLB_HF_ID_I_L4_SRC_PORT,\n+\tBNXT_ULP_GLB_HF_ID_O_L4_DST_PORT,\n+\tBNXT_ULP_GLB_HF_ID_I_L4_DST_PORT,\n+\tBNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT,\n+\tBNXT_ULP_GLB_HF_ID_I_TCP_SRC_PORT,\n+\tBNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT,\n+\tBNXT_ULP_GLB_HF_ID_I_TCP_DST_PORT,\n+\tBNXT_ULP_GLB_HF_ID_O_TCP_SENT_SEQ,\n+\tBNXT_ULP_GLB_HF_ID_I_TCP_SENT_SEQ,\n+\tBNXT_ULP_GLB_HF_ID_O_TCP_RECV_ACK,\n+\tBNXT_ULP_GLB_HF_ID_I_TCP_RECV_ACK,\n+\tBNXT_ULP_GLB_HF_ID_O_TCP_DATA_OFF,\n+\tBNXT_ULP_GLB_HF_ID_I_TCP_DATA_OFF,\n+\tBNXT_ULP_GLB_HF_ID_O_TCP_TCP_FLAGS,\n+\tBNXT_ULP_GLB_HF_ID_I_TCP_TCP_FLAGS,\n+\tBNXT_ULP_GLB_HF_ID_O_TCP_RX_WIN,\n+\tBNXT_ULP_GLB_HF_ID_I_TCP_RX_WIN,\n+\tBNXT_ULP_GLB_HF_ID_O_TCP_CSUM,\n+\tBNXT_ULP_GLB_HF_ID_I_TCP_CSUM,\n+\tBNXT_ULP_GLB_HF_ID_O_TCP_URP,\n+\tBNXT_ULP_GLB_HF_ID_I_TCP_URP,\n+\tBNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT,\n+\tBNXT_ULP_GLB_HF_ID_I_UDP_SRC_PORT,\n+\tBNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT,\n+\tBNXT_ULP_GLB_HF_ID_I_UDP_DST_PORT,\n+\tBNXT_ULP_GLB_HF_ID_O_UDP_LENGTH,\n+\tBNXT_ULP_GLB_HF_ID_I_UDP_LENGTH,\n+\tBNXT_ULP_GLB_HF_ID_O_UDP_CSUM,\n+\tBNXT_ULP_GLB_HF_ID_I_UDP_CSUM,\n+\tBNXT_ULP_GLB_HF_ID_OO_VLAN_CFI_PRI,\n+\tBNXT_ULP_GLB_HF_ID_OI_VLAN_CFI_PRI,\n+\tBNXT_ULP_GLB_HF_ID_IO_VLAN_CFI_PRI,\n+\tBNXT_ULP_GLB_HF_ID_II_VLAN_CFI_PRI,\n+\tBNXT_ULP_GLB_HF_ID_OO_VLAN_VID,\n+\tBNXT_ULP_GLB_HF_ID_OI_VLAN_VID,\n+\tBNXT_ULP_GLB_HF_ID_IO_VLAN_VID,\n+\tBNXT_ULP_GLB_HF_ID_II_VLAN_VID,\n+\tBNXT_ULP_GLB_HF_ID_OO_VLAN_TYPE,\n+\tBNXT_ULP_GLB_HF_ID_OI_VLAN_TYPE,\n+\tBNXT_ULP_GLB_HF_ID_IO_VLAN_TYPE,\n+\tBNXT_ULP_GLB_HF_ID_II_VLAN_TYPE,\n+\tBNXT_ULP_GLB_HF_ID_T_VXLAN_FLAGS,\n+\tBNXT_ULP_GLB_HF_ID_T_VXLAN_RSVD0,\n+\tBNXT_ULP_GLB_HF_ID_T_VXLAN_VNI,\n+\tBNXT_ULP_GLB_HF_ID_T_VXLAN_RSVD1\n };\n \n enum bnxt_ulp_hf1_0_bitmask {\n@@ -113,25 +113,23 @@ enum bnxt_ulp_hf1_0_bitmask {\n \tBNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC         = 0x2000000000000000,\n \tBNXT_ULP_HF1_0_BITMASK_O_ETH_SMAC         = 0x1000000000000000,\n \tBNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE         = 0x0800000000000000,\n-\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_VER         = 0x0400000000000000,\n-\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_TOS         = 0x0200000000000000,\n-\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_LEN         = 0x0100000000000000,\n-\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_FRAG_ID     = 0x0080000000000000,\n-\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_FRAG_OFF    = 0x0040000000000000,\n-\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_TTL         = 0x0020000000000000,\n-\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_PROTO_ID    = 0x0010000000000000,\n-\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_CSUM        = 0x0008000000000000,\n-\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR    = 0x0004000000000000,\n-\tBNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR    = 0x0002000000000000,\n-\tBNXT_ULP_HF1_0_BITMASK_O_TCP_SRC_PORT     = 0x0001000000000000,\n-\tBNXT_ULP_HF1_0_BITMASK_O_TCP_DST_PORT     = 0x0000800000000000,\n-\tBNXT_ULP_HF1_0_BITMASK_O_TCP_SENT_SEQ     = 0x0000400000000000,\n-\tBNXT_ULP_HF1_0_BITMASK_O_TCP_RECV_ACK     = 0x0000200000000000,\n-\tBNXT_ULP_HF1_0_BITMASK_O_TCP_DATA_OFF     = 0x0000100000000000,\n-\tBNXT_ULP_HF1_0_BITMASK_O_TCP_TCP_FLAGS    = 0x0000080000000000,\n-\tBNXT_ULP_HF1_0_BITMASK_O_TCP_RX_WIN       = 0x0000040000000000,\n-\tBNXT_ULP_HF1_0_BITMASK_O_TCP_CSUM         = 0x0000020000000000,\n-\tBNXT_ULP_HF1_0_BITMASK_O_TCP_URP          = 0x0000010000000000\n+\tBNXT_ULP_HF1_0_BITMASK_O_IPV6_VER         = 0x0400000000000000,\n+\tBNXT_ULP_HF1_0_BITMASK_O_IPV6_TC          = 0x0200000000000000,\n+\tBNXT_ULP_HF1_0_BITMASK_O_IPV6_FLOW_LABEL  = 0x0100000000000000,\n+\tBNXT_ULP_HF1_0_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000,\n+\tBNXT_ULP_HF1_0_BITMASK_O_IPV6_PROTO_ID    = 0x0040000000000000,\n+\tBNXT_ULP_HF1_0_BITMASK_O_IPV6_TTL         = 0x0020000000000000,\n+\tBNXT_ULP_HF1_0_BITMASK_O_IPV6_SRC_ADDR    = 0x0010000000000000,\n+\tBNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR    = 0x0008000000000000,\n+\tBNXT_ULP_HF1_0_BITMASK_O_TCP_SRC_PORT     = 0x0004000000000000,\n+\tBNXT_ULP_HF1_0_BITMASK_O_TCP_DST_PORT     = 0x0002000000000000,\n+\tBNXT_ULP_HF1_0_BITMASK_O_TCP_SENT_SEQ     = 0x0001000000000000,\n+\tBNXT_ULP_HF1_0_BITMASK_O_TCP_RECV_ACK     = 0x0000800000000000,\n+\tBNXT_ULP_HF1_0_BITMASK_O_TCP_DATA_OFF     = 0x0000400000000000,\n+\tBNXT_ULP_HF1_0_BITMASK_O_TCP_TCP_FLAGS    = 0x0000200000000000,\n+\tBNXT_ULP_HF1_0_BITMASK_O_TCP_RX_WIN       = 0x0000100000000000,\n+\tBNXT_ULP_HF1_0_BITMASK_O_TCP_CSUM         = 0x0000080000000000,\n+\tBNXT_ULP_HF1_0_BITMASK_O_TCP_URP          = 0x0000040000000000\n };\n \n enum bnxt_ulp_hf1_1_bitmask {\n@@ -143,81 +141,169 @@ enum bnxt_ulp_hf1_1_bitmask {\n \tBNXT_ULP_HF1_1_BITMASK_OO_VLAN_CFI_PRI    = 0x0400000000000000,\n \tBNXT_ULP_HF1_1_BITMASK_OO_VLAN_VID        = 0x0200000000000000,\n \tBNXT_ULP_HF1_1_BITMASK_OO_VLAN_TYPE       = 0x0100000000000000,\n-\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_VER         = 0x0080000000000000,\n-\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_TOS         = 0x0040000000000000,\n-\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_LEN         = 0x0020000000000000,\n-\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_FRAG_ID     = 0x0010000000000000,\n-\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_FRAG_OFF    = 0x0008000000000000,\n-\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_TTL         = 0x0004000000000000,\n-\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID    = 0x0002000000000000,\n-\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_CSUM        = 0x0001000000000000,\n-\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR    = 0x0000800000000000,\n-\tBNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR    = 0x0000400000000000,\n-\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT     = 0x0000200000000000,\n-\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT     = 0x0000100000000000,\n-\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SENT_SEQ     = 0x0000080000000000,\n-\tBNXT_ULP_HF1_1_BITMASK_O_TCP_RECV_ACK     = 0x0000040000000000,\n-\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DATA_OFF     = 0x0000020000000000,\n-\tBNXT_ULP_HF1_1_BITMASK_O_TCP_TCP_FLAGS    = 0x0000010000000000,\n-\tBNXT_ULP_HF1_1_BITMASK_O_TCP_RX_WIN       = 0x0000008000000000,\n-\tBNXT_ULP_HF1_1_BITMASK_O_TCP_CSUM         = 0x0000004000000000,\n-\tBNXT_ULP_HF1_1_BITMASK_O_TCP_URP          = 0x0000002000000000\n+\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_VER         = 0x0080000000000000,\n+\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_TC          = 0x0040000000000000,\n+\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_FLOW_LABEL  = 0x0020000000000000,\n+\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000,\n+\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_PROTO_ID    = 0x0008000000000000,\n+\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_TTL         = 0x0004000000000000,\n+\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_SRC_ADDR    = 0x0002000000000000,\n+\tBNXT_ULP_HF1_1_BITMASK_O_IPV6_DST_ADDR    = 0x0001000000000000,\n+\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT     = 0x0000800000000000,\n+\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT     = 0x0000400000000000,\n+\tBNXT_ULP_HF1_1_BITMASK_O_TCP_SENT_SEQ     = 0x0000200000000000,\n+\tBNXT_ULP_HF1_1_BITMASK_O_TCP_RECV_ACK     = 0x0000100000000000,\n+\tBNXT_ULP_HF1_1_BITMASK_O_TCP_DATA_OFF     = 0x0000080000000000,\n+\tBNXT_ULP_HF1_1_BITMASK_O_TCP_TCP_FLAGS    = 0x0000040000000000,\n+\tBNXT_ULP_HF1_1_BITMASK_O_TCP_RX_WIN       = 0x0000020000000000,\n+\tBNXT_ULP_HF1_1_BITMASK_O_TCP_CSUM         = 0x0000010000000000,\n+\tBNXT_ULP_HF1_1_BITMASK_O_TCP_URP          = 0x0000008000000000\n };\n \n-enum bnxt_ulp_hf2_0_bitmask {\n-\tBNXT_ULP_HF2_0_BITMASK_WM                 = 0x8000000000000000,\n-\tBNXT_ULP_HF2_0_BITMASK_SVIF_INDEX         = 0x4000000000000000,\n-\tBNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC         = 0x2000000000000000,\n-\tBNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC         = 0x1000000000000000,\n-\tBNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE         = 0x0800000000000000,\n-\tBNXT_ULP_HF2_0_BITMASK_O_IPV4_VER         = 0x0400000000000000,\n-\tBNXT_ULP_HF2_0_BITMASK_O_IPV4_TOS         = 0x0200000000000000,\n-\tBNXT_ULP_HF2_0_BITMASK_O_IPV4_LEN         = 0x0100000000000000,\n-\tBNXT_ULP_HF2_0_BITMASK_O_IPV4_FRAG_ID     = 0x0080000000000000,\n-\tBNXT_ULP_HF2_0_BITMASK_O_IPV4_FRAG_OFF    = 0x0040000000000000,\n-\tBNXT_ULP_HF2_0_BITMASK_O_IPV4_TTL         = 0x0020000000000000,\n-\tBNXT_ULP_HF2_0_BITMASK_O_IPV4_PROTO_ID    = 0x0010000000000000,\n-\tBNXT_ULP_HF2_0_BITMASK_O_IPV4_CSUM        = 0x0008000000000000,\n-\tBNXT_ULP_HF2_0_BITMASK_O_IPV4_SRC_ADDR    = 0x0004000000000000,\n-\tBNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR    = 0x0002000000000000,\n-\tBNXT_ULP_HF2_0_BITMASK_O_TCP_SRC_PORT     = 0x0001000000000000,\n-\tBNXT_ULP_HF2_0_BITMASK_O_TCP_DST_PORT     = 0x0000800000000000,\n-\tBNXT_ULP_HF2_0_BITMASK_O_TCP_SENT_SEQ     = 0x0000400000000000,\n-\tBNXT_ULP_HF2_0_BITMASK_O_TCP_RECV_ACK     = 0x0000200000000000,\n-\tBNXT_ULP_HF2_0_BITMASK_O_TCP_DATA_OFF     = 0x0000100000000000,\n-\tBNXT_ULP_HF2_0_BITMASK_O_TCP_TCP_FLAGS    = 0x0000080000000000,\n-\tBNXT_ULP_HF2_0_BITMASK_O_TCP_RX_WIN       = 0x0000040000000000,\n-\tBNXT_ULP_HF2_0_BITMASK_O_TCP_CSUM         = 0x0000020000000000,\n-\tBNXT_ULP_HF2_0_BITMASK_O_TCP_URP          = 0x0000010000000000\n+enum bnxt_ulp_hf1_2_bitmask {\n+\tBNXT_ULP_HF1_2_BITMASK_WM                 = 0x8000000000000000,\n+\tBNXT_ULP_HF1_2_BITMASK_SVIF_INDEX         = 0x4000000000000000,\n+\tBNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC         = 0x2000000000000000,\n+\tBNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC         = 0x1000000000000000,\n+\tBNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE         = 0x0800000000000000,\n+\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_VER         = 0x0400000000000000,\n+\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_TOS         = 0x0200000000000000,\n+\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_LEN         = 0x0100000000000000,\n+\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_FRAG_ID     = 0x0080000000000000,\n+\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_FRAG_OFF    = 0x0040000000000000,\n+\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_TTL         = 0x0020000000000000,\n+\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID    = 0x0010000000000000,\n+\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_CSUM        = 0x0008000000000000,\n+\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR    = 0x0004000000000000,\n+\tBNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR    = 0x0002000000000000,\n+\tBNXT_ULP_HF1_2_BITMASK_O_TCP_SRC_PORT     = 0x0001000000000000,\n+\tBNXT_ULP_HF1_2_BITMASK_O_TCP_DST_PORT     = 0x0000800000000000,\n+\tBNXT_ULP_HF1_2_BITMASK_O_TCP_SENT_SEQ     = 0x0000400000000000,\n+\tBNXT_ULP_HF1_2_BITMASK_O_TCP_RECV_ACK     = 0x0000200000000000,\n+\tBNXT_ULP_HF1_2_BITMASK_O_TCP_DATA_OFF     = 0x0000100000000000,\n+\tBNXT_ULP_HF1_2_BITMASK_O_TCP_TCP_FLAGS    = 0x0000080000000000,\n+\tBNXT_ULP_HF1_2_BITMASK_O_TCP_RX_WIN       = 0x0000040000000000,\n+\tBNXT_ULP_HF1_2_BITMASK_O_TCP_CSUM         = 0x0000020000000000,\n+\tBNXT_ULP_HF1_2_BITMASK_O_TCP_URP          = 0x0000010000000000\n };\n \n-enum bnxt_ulp_hf2_1_bitmask {\n-\tBNXT_ULP_HF2_1_BITMASK_WM                 = 0x8000000000000000,\n-\tBNXT_ULP_HF2_1_BITMASK_SVIF_INDEX         = 0x4000000000000000,\n-\tBNXT_ULP_HF2_1_BITMASK_O_ETH_DMAC         = 0x2000000000000000,\n-\tBNXT_ULP_HF2_1_BITMASK_O_ETH_SMAC         = 0x1000000000000000,\n-\tBNXT_ULP_HF2_1_BITMASK_O_ETH_TYPE         = 0x0800000000000000,\n-\tBNXT_ULP_HF2_1_BITMASK_OO_VLAN_CFI_PRI    = 0x0400000000000000,\n-\tBNXT_ULP_HF2_1_BITMASK_OO_VLAN_VID        = 0x0200000000000000,\n-\tBNXT_ULP_HF2_1_BITMASK_OO_VLAN_TYPE       = 0x0100000000000000,\n-\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_VER         = 0x0080000000000000,\n-\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_TOS         = 0x0040000000000000,\n-\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_LEN         = 0x0020000000000000,\n-\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_FRAG_ID     = 0x0010000000000000,\n-\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_FRAG_OFF    = 0x0008000000000000,\n-\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_TTL         = 0x0004000000000000,\n-\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID    = 0x0002000000000000,\n-\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_CSUM        = 0x0001000000000000,\n-\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR    = 0x0000800000000000,\n-\tBNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR    = 0x0000400000000000,\n-\tBNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT     = 0x0000200000000000,\n-\tBNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT     = 0x0000100000000000,\n-\tBNXT_ULP_HF2_1_BITMASK_O_TCP_SENT_SEQ     = 0x0000080000000000,\n-\tBNXT_ULP_HF2_1_BITMASK_O_TCP_RECV_ACK     = 0x0000040000000000,\n-\tBNXT_ULP_HF2_1_BITMASK_O_TCP_DATA_OFF     = 0x0000020000000000,\n-\tBNXT_ULP_HF2_1_BITMASK_O_TCP_TCP_FLAGS    = 0x0000010000000000,\n-\tBNXT_ULP_HF2_1_BITMASK_O_TCP_RX_WIN       = 0x0000008000000000,\n-\tBNXT_ULP_HF2_1_BITMASK_O_TCP_CSUM         = 0x0000004000000000,\n-\tBNXT_ULP_HF2_1_BITMASK_O_TCP_URP          = 0x0000002000000000\n+enum bnxt_ulp_hf1_3_bitmask {\n+\tBNXT_ULP_HF1_3_BITMASK_WM                 = 0x8000000000000000,\n+\tBNXT_ULP_HF1_3_BITMASK_SVIF_INDEX         = 0x4000000000000000,\n+\tBNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC         = 0x2000000000000000,\n+\tBNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC         = 0x1000000000000000,\n+\tBNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE         = 0x0800000000000000,\n+\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_VER         = 0x0400000000000000,\n+\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_TC          = 0x0200000000000000,\n+\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_FLOW_LABEL  = 0x0100000000000000,\n+\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000,\n+\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID    = 0x0040000000000000,\n+\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_TTL         = 0x0020000000000000,\n+\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR    = 0x0010000000000000,\n+\tBNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR    = 0x0008000000000000,\n+\tBNXT_ULP_HF1_3_BITMASK_O_UDP_SRC_PORT     = 0x0004000000000000,\n+\tBNXT_ULP_HF1_3_BITMASK_O_UDP_DST_PORT     = 0x0002000000000000,\n+\tBNXT_ULP_HF1_3_BITMASK_O_UDP_LENGTH       = 0x0001000000000000,\n+\tBNXT_ULP_HF1_3_BITMASK_O_UDP_CSUM         = 0x0000800000000000\n+};\n+\n+enum bnxt_ulp_hf1_4_bitmask {\n+\tBNXT_ULP_HF1_4_BITMASK_WM                 = 0x8000000000000000,\n+\tBNXT_ULP_HF1_4_BITMASK_SVIF_INDEX         = 0x4000000000000000,\n+\tBNXT_ULP_HF1_4_BITMASK_O_ETH_DMAC         = 0x2000000000000000,\n+\tBNXT_ULP_HF1_4_BITMASK_O_ETH_SMAC         = 0x1000000000000000,\n+\tBNXT_ULP_HF1_4_BITMASK_O_ETH_TYPE         = 0x0800000000000000,\n+\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_CFI_PRI    = 0x0400000000000000,\n+\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_VID        = 0x0200000000000000,\n+\tBNXT_ULP_HF1_4_BITMASK_OO_VLAN_TYPE       = 0x0100000000000000,\n+\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_VER         = 0x0080000000000000,\n+\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_TOS         = 0x0040000000000000,\n+\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_LEN         = 0x0020000000000000,\n+\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_FRAG_ID     = 0x0010000000000000,\n+\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_FRAG_OFF    = 0x0008000000000000,\n+\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_TTL         = 0x0004000000000000,\n+\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_PROTO_ID    = 0x0002000000000000,\n+\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_CSUM        = 0x0001000000000000,\n+\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_SRC_ADDR    = 0x0000800000000000,\n+\tBNXT_ULP_HF1_4_BITMASK_O_IPV4_DST_ADDR    = 0x0000400000000000,\n+\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SRC_PORT     = 0x0000200000000000,\n+\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DST_PORT     = 0x0000100000000000,\n+\tBNXT_ULP_HF1_4_BITMASK_O_TCP_SENT_SEQ     = 0x0000080000000000,\n+\tBNXT_ULP_HF1_4_BITMASK_O_TCP_RECV_ACK     = 0x0000040000000000,\n+\tBNXT_ULP_HF1_4_BITMASK_O_TCP_DATA_OFF     = 0x0000020000000000,\n+\tBNXT_ULP_HF1_4_BITMASK_O_TCP_TCP_FLAGS    = 0x0000010000000000,\n+\tBNXT_ULP_HF1_4_BITMASK_O_TCP_RX_WIN       = 0x0000008000000000,\n+\tBNXT_ULP_HF1_4_BITMASK_O_TCP_CSUM         = 0x0000004000000000,\n+\tBNXT_ULP_HF1_4_BITMASK_O_TCP_URP          = 0x0000002000000000\n+};\n+\n+enum bnxt_ulp_hf1_5_bitmask {\n+\tBNXT_ULP_HF1_5_BITMASK_WM                 = 0x8000000000000000,\n+\tBNXT_ULP_HF1_5_BITMASK_SVIF_INDEX         = 0x4000000000000000,\n+\tBNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC         = 0x2000000000000000,\n+\tBNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC         = 0x1000000000000000,\n+\tBNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE         = 0x0800000000000000,\n+\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_CFI_PRI    = 0x0400000000000000,\n+\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_VID        = 0x0200000000000000,\n+\tBNXT_ULP_HF1_5_BITMASK_OO_VLAN_TYPE       = 0x0100000000000000,\n+\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_VER         = 0x0080000000000000,\n+\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_TC          = 0x0040000000000000,\n+\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_FLOW_LABEL  = 0x0020000000000000,\n+\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000,\n+\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID    = 0x0008000000000000,\n+\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_TTL         = 0x0004000000000000,\n+\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR    = 0x0002000000000000,\n+\tBNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR    = 0x0001000000000000,\n+\tBNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT     = 0x0000800000000000,\n+\tBNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT     = 0x0000400000000000,\n+\tBNXT_ULP_HF1_5_BITMASK_O_UDP_LENGTH       = 0x0000200000000000,\n+\tBNXT_ULP_HF1_5_BITMASK_O_UDP_CSUM         = 0x0000100000000000\n+};\n+\n+enum bnxt_ulp_hf1_6_bitmask {\n+\tBNXT_ULP_HF1_6_BITMASK_WM                 = 0x8000000000000000,\n+\tBNXT_ULP_HF1_6_BITMASK_SVIF_INDEX         = 0x4000000000000000,\n+\tBNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC         = 0x2000000000000000,\n+\tBNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC         = 0x1000000000000000,\n+\tBNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE         = 0x0800000000000000,\n+\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_VER         = 0x0400000000000000,\n+\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_TOS         = 0x0200000000000000,\n+\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_LEN         = 0x0100000000000000,\n+\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_FRAG_ID     = 0x0080000000000000,\n+\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_FRAG_OFF    = 0x0040000000000000,\n+\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_TTL         = 0x0020000000000000,\n+\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID    = 0x0010000000000000,\n+\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_CSUM        = 0x0008000000000000,\n+\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR    = 0x0004000000000000,\n+\tBNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR    = 0x0002000000000000,\n+\tBNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT     = 0x0001000000000000,\n+\tBNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT     = 0x0000800000000000,\n+\tBNXT_ULP_HF1_6_BITMASK_O_UDP_LENGTH       = 0x0000400000000000,\n+\tBNXT_ULP_HF1_6_BITMASK_O_UDP_CSUM         = 0x0000200000000000\n+};\n+\n+enum bnxt_ulp_hf1_7_bitmask {\n+\tBNXT_ULP_HF1_7_BITMASK_WM                 = 0x8000000000000000,\n+\tBNXT_ULP_HF1_7_BITMASK_SVIF_INDEX         = 0x4000000000000000,\n+\tBNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC         = 0x2000000000000000,\n+\tBNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC         = 0x1000000000000000,\n+\tBNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE         = 0x0800000000000000,\n+\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_CFI_PRI    = 0x0400000000000000,\n+\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID        = 0x0200000000000000,\n+\tBNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE       = 0x0100000000000000,\n+\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_VER         = 0x0080000000000000,\n+\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_TOS         = 0x0040000000000000,\n+\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_LEN         = 0x0020000000000000,\n+\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_FRAG_ID     = 0x0010000000000000,\n+\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_FRAG_OFF    = 0x0008000000000000,\n+\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_TTL         = 0x0004000000000000,\n+\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID    = 0x0002000000000000,\n+\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_CSUM        = 0x0001000000000000,\n+\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR    = 0x0000800000000000,\n+\tBNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR    = 0x0000400000000000,\n+\tBNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT     = 0x0000200000000000,\n+\tBNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT     = 0x0000100000000000,\n+\tBNXT_ULP_HF1_7_BITMASK_O_UDP_LENGTH       = 0x0000080000000000,\n+\tBNXT_ULP_HF1_7_BITMASK_O_UDP_CSUM         = 0x0000040000000000\n };\n #endif\ndiff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_act.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_act.c\nindex 87d6347196..7610950507 100644\n--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_act.c\n+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_act.c\n@@ -3,7 +3,7 @@\n  * All rights reserved.\n  */\n \n-/* date: Mon Nov 23 17:33:02 2020 */\n+/* date: Tue Dec  1 17:07:12 2020 */\n \n #include \"ulp_template_db_enum.h\"\n #include \"ulp_template_db_field.h\"\n@@ -32,6 +32,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = {\n \t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT,\n \t.direction = TF_DIR_RX,\n \t.execute_info = {\n+\t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n \t\t.cond_start_idx = 0,\n \t\t.cond_nums = 1 },\n@@ -53,6 +54,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = {\n \t.direction = TF_DIR_RX,\n \t.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT,\n \t.execute_info = {\n+\t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n \t\t.cond_start_idx = 1,\n \t\t.cond_nums = 1 },\n@@ -74,6 +76,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = {\n \t.direction = TF_DIR_RX,\n \t.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT,\n \t.execute_info = {\n+\t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 2,\n \t\t.cond_nums = 0 },\n@@ -95,6 +98,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = {\n \t.direction = TF_DIR_RX,\n \t.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT,\n \t.execute_info = {\n+\t\t.cond_goto = 0,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 2,\n \t\t.cond_nums = 0 },\n@@ -112,12 +116,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = {\n \n struct bnxt_ulp_mapper_cond_info ulp_stingray_act_cond_list[] = {\n \t{\n-\t.cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET,\n-\t.cond_operand = BNXT_ULP_ACTION_BIT_COUNT\n+\t.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,\n+\t.cond_operand = BNXT_ULP_ACT_BIT_COUNT\n \t},\n \t{\n-\t.cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET,\n-\t.cond_operand = BNXT_ULP_ACTION_BIT_PUSH_VLAN\n+\t.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,\n+\t.cond_operand = BNXT_ULP_ACT_BIT_PUSH_VLAN\n \t}\n };\n \n@@ -126,559 +130,580 @@ struct bnxt_ulp_mapper_field_info ulp_stingray_act_result_field_list[] = {\n \t{\n \t.description = \"count\",\n \t.field_bit_size = 64,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t/* act_tid: 1, stingray, table: int_vtag_encap_record.0 */\n \t{\n \t.description = \"ecv_tun_type\",\n \t.field_bit_size = 3,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"ecv_l4_type\",\n \t.field_bit_size = 3,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"ecv_l3_type\",\n \t.field_bit_size = 3,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"ecv_l2_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"ecv_vtag_type\",\n \t.field_bit_size = 4,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {\n-\t\tBNXT_ULP_STINGRAY_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\tULP_SR_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI}\n \t},\n \t{\n \t.description = \"ecv_custom_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"ecv_valid\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t1}\n \t},\n \t{\n \t.description = \"vtag_tpid\",\n \t.field_bit_size = 16,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_PROP,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN >> 8) & 0xff,\n-\t\tBNXT_ULP_ACT_PROP_IDX_PUSH_VLAN & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_ACT_PROP_IDX_PUSH_VLAN & 0xff}\n \t},\n \t{\n \t.description = \"vtag_vid\",\n \t.field_bit_size = 12,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_PROP,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID >> 8) & 0xff,\n-\t\tBNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID & 0xff}\n \t},\n \t{\n \t.description = \"vtag_de\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"vtag_pcp\",\n \t.field_bit_size = 3,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_PROP,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff,\n-\t\tBNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff}\n \t},\n \t{\n \t.description = \"spare\",\n \t.field_bit_size = 80,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t/* act_tid: 1, stingray, table: int_full_act_record.0 */\n \t{\n \t.description = \"flow_cntr_ptr\",\n \t.field_bit_size = 14,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}\n \t},\n \t{\n \t.description = \"age_enable\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"agg_cntr_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"rate_cntr_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"flow_cntr_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_BIT,\n-\t.field_operand = {\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 56) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 48) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 40) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 32) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 24) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 16) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 8) & 0xff,\n-\t\t(uint64_t)BNXT_ULP_ACTION_BIT_COUNT & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,\n+\t.field_opr1 = {\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff,\n+\t\t(uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff}\n \t},\n \t{\n \t.description = \"tcpflags_key\",\n \t.field_bit_size = 8,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tcpflags_mir\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tcpflags_match\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"encap_ptr\",\n \t.field_bit_size = 11,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff}\n \t},\n \t{\n \t.description = \"dst_ip_ptr\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 & 0xff}\n \t},\n \t{\n \t.description = \"tcp_dst_port\",\n \t.field_bit_size = 16,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST,\n-\t.field_operand = {\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 56) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 48) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 40) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 32) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 24) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 16) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 8) & 0xff,\n-\t\t(uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},\n-\t.field_operand_true = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT,\n+\t.field_cond_opr = {\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff,\n+\t\t(uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff},\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff,\n-\t\tBNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff},\n+\t.field_src2 = BNXT_ULP_FIELD_SRC_CONST\n \t},\n \t{\n \t.description = \"src_ip_ptr\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 & 0xff}\n \t},\n \t{\n \t.description = \"tcp_src_port\",\n \t.field_bit_size = 16,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST,\n-\t.field_operand = {\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 56) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 48) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 40) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 32) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 24) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 16) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 8) & 0xff,\n-\t\t(uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},\n-\t.field_operand_true = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT,\n+\t.field_cond_opr = {\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff,\n+\t\t(uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff},\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff,\n-\t\tBNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff},\n+\t.field_src2 = BNXT_ULP_FIELD_SRC_CONST\n \t},\n \t{\n \t.description = \"meter_id\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"l3_rdir\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tl3_rdir\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"l3_ttl_dec\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff}\n \t},\n \t{\n \t.description = \"tl3_ttl_dec\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff}\n \t},\n \t{\n \t.description = \"decap_func\",\n \t.field_bit_size = 4,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_IF_ACT_BIT_THEN_CONST_ELSE_CONST,\n-\t.field_operand = {\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 56) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 48) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 40) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 32) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 24) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 16) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 8) & 0xff,\n-\t\t(uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},\n-\t.field_operand_true = {0x0a, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT,\n+\t.field_cond_opr = {\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 56) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 48) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 40) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 32) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 24) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 16) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 8) & 0xff,\n+\t\t(uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP & 0xff},\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\tULP_SR_SYM_DECAP_FUNC_THRU_TUN},\n+\t.field_src2 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr2 = {\n+\t\tULP_SR_SYM_DECAP_FUNC_NONE}\n \t},\n \t{\n \t.description = \"vnic_or_vport\",\n \t.field_bit_size = 12,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_PROP,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,\n-\t\tBNXT_ULP_ACT_PROP_IDX_VNIC & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_ACT_PROP_IDX_VNIC & 0xff}\n \t},\n \t{\n \t.description = \"pop_vlan\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_BIT,\n-\t.field_operand = {\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 56) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 48) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 40) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 32) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 24) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 16) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 8) & 0xff,\n-\t\t(uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,\n+\t.field_opr1 = {\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 56) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 48) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 40) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 32) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 24) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 16) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 8) & 0xff,\n+\t\t(uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN & 0xff}\n \t},\n \t{\n \t.description = \"meter\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"mirror\",\n \t.field_bit_size = 2,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"drop\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_BIT,\n-\t.field_operand = {\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 56) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 48) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 40) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 32) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 24) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 16) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 8) & 0xff,\n-\t\t(uint64_t)BNXT_ULP_ACTION_BIT_DROP & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,\n+\t.field_opr1 = {\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff,\n+\t\t(uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff}\n \t},\n \t{\n \t.description = \"hit\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"type\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t/* act_tid: 1, stingray, table: ext_full_act_record.0 */\n \t{\n \t.description = \"flow_cntr_ptr\",\n \t.field_bit_size = 14,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}\n \t},\n \t{\n \t.description = \"age_enable\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"agg_cntr_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"rate_cntr_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"flow_cntr_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_BIT,\n-\t.field_operand = {\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 56) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 48) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 40) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 32) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 24) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 16) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 8) & 0xff,\n-\t\t(uint64_t)BNXT_ULP_ACTION_BIT_COUNT & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,\n+\t.field_opr1 = {\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff,\n+\t\t(uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff}\n \t},\n \t{\n \t.description = \"flow_cntr_ext\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tcpflags_key\",\n \t.field_bit_size = 8,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tcpflags_mir\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tcpflags_match\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"encap_ptr\",\n \t.field_bit_size = 11,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"encap_rec_int\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"dst_ip_ptr\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 & 0xff}\n \t},\n \t{\n \t.description = \"tcp_dst_port\",\n \t.field_bit_size = 16,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST,\n-\t.field_operand = {\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 56) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 48) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 40) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 32) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 24) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 16) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 8) & 0xff,\n-\t\t(uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},\n-\t.field_operand_true = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT,\n+\t.field_cond_opr = {\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff,\n+\t\t(uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff},\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff,\n-\t\tBNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff},\n+\t.field_src2 = BNXT_ULP_FIELD_SRC_CONST\n \t},\n \t{\n \t.description = \"src_ip_ptr\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 & 0xff}\n \t},\n \t{\n \t.description = \"tcp_src_port\",\n \t.field_bit_size = 16,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST,\n-\t.field_operand = {\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 56) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 48) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 40) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 32) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 24) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 16) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 8) & 0xff,\n-\t\t(uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},\n-\t.field_operand_true = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT,\n+\t.field_cond_opr = {\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff,\n+\t\t(uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff},\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff,\n-\t\tBNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff},\n+\t.field_src2 = BNXT_ULP_FIELD_SRC_CONST\n \t},\n \t{\n \t.description = \"meter_id\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"l3_rdir\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tl3_rdir\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"l3_ttl_dec\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff}\n \t},\n \t{\n \t.description = \"tl3_ttl_dec\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff}\n \t},\n \t{\n \t.description = \"decap_func\",\n \t.field_bit_size = 4,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_IF_ACT_BIT_THEN_CONST_ELSE_CONST,\n-\t.field_operand = {\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 56) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 48) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 40) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 32) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 24) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 16) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 8) & 0xff,\n-\t\t(uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},\n-\t.field_operand_true = {0x0a, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT,\n+\t.field_cond_opr = {\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 56) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 48) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 40) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 32) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 24) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 16) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 8) & 0xff,\n+\t\t(uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP & 0xff},\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\tULP_SR_SYM_DECAP_FUNC_THRU_TUN},\n+\t.field_src2 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr2 = {\n+\t\tULP_SR_SYM_DECAP_FUNC_NONE}\n \t},\n \t{\n \t.description = \"vnic_or_vport\",\n \t.field_bit_size = 12,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_PROP,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,\n-\t\tBNXT_ULP_ACT_PROP_IDX_VNIC & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_ACT_PROP_IDX_VNIC & 0xff}\n \t},\n \t{\n \t.description = \"pop_vlan\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_BIT,\n-\t.field_operand = {\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 56) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 48) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 40) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 32) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 24) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 16) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 8) & 0xff,\n-\t\t(uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,\n+\t.field_opr1 = {\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 56) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 48) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 40) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 32) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 24) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 16) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 8) & 0xff,\n+\t\t(uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN & 0xff}\n \t},\n \t{\n \t.description = \"meter\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"mirror\",\n \t.field_bit_size = 2,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"drop\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_BIT,\n-\t.field_operand = {\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 56) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 48) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 40) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 32) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 24) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 16) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 8) & 0xff,\n-\t\t(uint64_t)BNXT_ULP_ACTION_BIT_DROP & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,\n+\t.field_opr1 = {\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff,\n+\t\t(uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff}\n \t}\n };\ndiff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_class.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_class.c\nindex c836e2f8ed..a0cab178ec 100644\n--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_class.c\n+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_class.c\n@@ -3,7 +3,7 @@\n  * All rights reserved.\n  */\n \n-/* date: Mon Nov 23 17:33:02 2020 */\n+/* date: Wed Dec  2 12:05:11 2020 */\n \n #include \"ulp_template_db_enum.h\"\n #include \"ulp_template_db_field.h\"\n@@ -15,7 +15,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_stingray_class_tmpl_list[] = {\n \t/* class_tid: 1, stingray, ingress */\n \t[1] = {\n \t.device_name = BNXT_ULP_DEVICE_ID_STINGRAY,\n-\t.num_tbls = 6,\n+\t.num_tbls = 9,\n \t.start_tbl_idx = 0,\n \t.reject_info = {\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,\n@@ -26,17 +26,17 @@ struct bnxt_ulp_mapper_tmpl_info ulp_stingray_class_tmpl_list[] = {\n \t[2] = {\n \t.device_name = BNXT_ULP_DEVICE_ID_STINGRAY,\n \t.num_tbls = 6,\n-\t.start_tbl_idx = 6,\n+\t.start_tbl_idx = 9,\n \t.reject_info = {\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,\n-\t\t.cond_start_idx = 2,\n+\t\t.cond_start_idx = 4,\n \t\t.cond_nums = 0 }\n \t},\n-\t/* class_tid: 3, stingray, ingress */\n+\t/* class_tid: 3, stingray, egress */\n \t[3] = {\n \t.device_name = BNXT_ULP_DEVICE_ID_STINGRAY,\n-\t.num_tbls = 6,\n-\t.start_tbl_idx = 12,\n+\t.num_tbls = 8,\n+\t.start_tbl_idx = 15,\n \t.reject_info = {\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,\n \t\t.cond_start_idx = 4,\n@@ -45,18 +45,18 @@ struct bnxt_ulp_mapper_tmpl_info ulp_stingray_class_tmpl_list[] = {\n \t/* class_tid: 4, stingray, egress */\n \t[4] = {\n \t.device_name = BNXT_ULP_DEVICE_ID_STINGRAY,\n-\t.num_tbls = 8,\n-\t.start_tbl_idx = 18,\n+\t.num_tbls = 7,\n+\t.start_tbl_idx = 23,\n \t.reject_info = {\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,\n-\t\t.cond_start_idx = 4,\n+\t\t.cond_start_idx = 10,\n \t\t.cond_nums = 0 }\n \t},\n \t/* class_tid: 5, stingray, egress */\n \t[5] = {\n \t.device_name = BNXT_ULP_DEVICE_ID_STINGRAY,\n \t.num_tbls = 7,\n-\t.start_tbl_idx = 26,\n+\t.start_tbl_idx = 30,\n \t.reject_info = {\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,\n \t\t.cond_start_idx = 10,\n@@ -65,18 +65,8 @@ struct bnxt_ulp_mapper_tmpl_info ulp_stingray_class_tmpl_list[] = {\n \t/* class_tid: 6, stingray, egress */\n \t[6] = {\n \t.device_name = BNXT_ULP_DEVICE_ID_STINGRAY,\n-\t.num_tbls = 7,\n-\t.start_tbl_idx = 33,\n-\t.reject_info = {\n-\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,\n-\t\t.cond_start_idx = 10,\n-\t\t.cond_nums = 0 }\n-\t},\n-\t/* class_tid: 7, stingray, egress */\n-\t[7] = {\n-\t.device_name = BNXT_ULP_DEVICE_ID_STINGRAY,\n \t.num_tbls = 1,\n-\t.start_tbl_idx = 40,\n+\t.start_tbl_idx = 37,\n \t.reject_info = {\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,\n \t\t.cond_start_idx = 10,\n@@ -85,13 +75,35 @@ struct bnxt_ulp_mapper_tmpl_info ulp_stingray_class_tmpl_list[] = {\n };\n \n struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {\n+\t{ /* class_tid: 1, stingray, table: l2_cntxt_tcam_cache.rd */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,\n+\t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,\n+\t.resource_sub_type =\n+\t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,\n+\t.direction = TF_DIR_RX,\n+\t.execute_info = {\n+\t\t.cond_goto = 2,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n+\t\t.cond_start_idx = 0,\n+\t\t.cond_nums = 1 },\n+\t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,\n+\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n+\t.key_start_idx = 0,\n+\t.blob_key_bit_size = 8,\n+\t.key_bit_size = 8,\n+\t.key_num_fields = 1,\n+\t.ident_start_idx = 0,\n+\t.ident_nums = 1\n+\t},\n \t{ /* class_tid: 1, stingray, table: l2_cntxt_tcam.0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n \t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,\n \t.direction = TF_DIR_RX,\n \t.execute_info = {\n+\t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 0,\n+\t\t.cond_start_idx = 1,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_SRCH_ALLOC_WR_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,\n@@ -99,7 +111,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n \t.pri_opcode  = BNXT_ULP_PRI_OPC_CONST,\n \t.pri_operand = 0,\n-\t.key_start_idx = 0,\n+\t.key_start_idx = 1,\n \t.blob_key_bit_size = 167,\n \t.key_bit_size = 167,\n \t.key_num_fields = 13,\n@@ -107,7 +119,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {\n \t.result_bit_size = 64,\n \t.result_num_fields = 13,\n \t.encap_num_fields = 0,\n-\t.ident_start_idx = 0,\n+\t.ident_start_idx = 1,\n \t.ident_nums = 1\n \t},\n \t{ /* class_tid: 1, stingray, table: profile_tcam_cache.rd */\n@@ -117,27 +129,40 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {\n \t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,\n \t.direction = TF_DIR_RX,\n \t.execute_info = {\n+\t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 0,\n+\t\t.cond_start_idx = 1,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_FLOW_SIG_ID_MATCH,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.key_start_idx = 13,\n+\t.key_start_idx = 14,\n \t.blob_key_bit_size = 14,\n \t.key_bit_size = 14,\n \t.key_num_fields = 3,\n-\t.ident_start_idx = 1,\n+\t.ident_start_idx = 2,\n \t.ident_nums = 3\n \t},\n+\t{ /* class_tid: 1, stingray, table: branch.0 */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_BRANCH_TABLE,\n+\t.direction = TF_DIR_RX,\n+\t.execute_info = {\n+\t\t.cond_goto = 3,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n+\t\t.cond_start_idx = 1,\n+\t\t.cond_nums = 1 },\n+\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH\n+\t},\n \t{ /* class_tid: 1, stingray, table: profile_tcam.0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n \t.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,\n \t.direction = TF_DIR_RX,\n \t.execute_info = {\n-\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n-\t\t.cond_start_idx = 0,\n-\t\t.cond_nums = 1 },\n+\t\t.cond_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n+\t\t.cond_start_idx = 2,\n+\t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n@@ -145,7 +170,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {\n \t.fdb_operand = BNXT_ULP_RF_IDX_RID,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n \t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,\n-\t.key_start_idx = 16,\n+\t.key_start_idx = 17,\n \t.blob_key_bit_size = 81,\n \t.key_bit_size = 81,\n \t.key_num_fields = 43,\n@@ -153,7 +178,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {\n \t.result_bit_size = 38,\n \t.result_num_fields = 8,\n \t.encap_num_fields = 0,\n-\t.ident_start_idx = 4,\n+\t.ident_start_idx = 5,\n \t.ident_nums = 1\n \t},\n \t{ /* class_tid: 1, stingray, table: profile_tcam_cache.wr */\n@@ -163,13 +188,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {\n \t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,\n \t.direction = TF_DIR_RX,\n \t.execute_info = {\n-\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n-\t\t.cond_start_idx = 1,\n-\t\t.cond_nums = 1 },\n+\t\t.cond_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n+\t\t.cond_start_idx = 2,\n+\t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.key_start_idx = 59,\n+\t.key_start_idx = 60,\n \t.blob_key_bit_size = 14,\n \t.key_bit_size = 14,\n \t.key_num_fields = 3,\n@@ -178,194 +204,71 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {\n \t.result_num_fields = 5,\n \t.encap_num_fields = 0\n \t},\n-\t{ /* class_tid: 1, stingray, table: eem.ext_0 */\n-\t.resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE,\n-\t.resource_type = TF_MEM_EXTERNAL,\n-\t.direction = TF_DIR_RX,\n-\t.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT,\n-\t.execute_info = {\n-\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 2,\n-\t\t.cond_nums = 0 },\n-\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,\n-\t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,\n-\t.key_start_idx = 62,\n-\t.blob_key_bit_size = 448,\n-\t.key_bit_size = 448,\n-\t.key_num_fields = 10,\n-\t.result_start_idx = 26,\n-\t.result_bit_size = 64,\n-\t.result_num_fields = 9,\n-\t.encap_num_fields = 0\n-\t},\n \t{ /* class_tid: 1, stingray, table: em.int_0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE,\n \t.resource_type = TF_MEM_INTERNAL,\n \t.direction = TF_DIR_RX,\n \t.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT,\n \t.execute_info = {\n-\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n+\t\t.cond_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n \t\t.cond_start_idx = 2,\n-\t\t.cond_nums = 0 },\n+\t\t.cond_nums = 1 },\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,\n \t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,\n-\t.key_start_idx = 72,\n+\t.key_start_idx = 63,\n \t.blob_key_bit_size = 176,\n \t.key_bit_size = 176,\n \t.key_num_fields = 10,\n-\t.result_start_idx = 35,\n+\t.result_start_idx = 26,\n \t.result_bit_size = 64,\n \t.result_num_fields = 9,\n \t.encap_num_fields = 0\n \t},\n-\t{ /* class_tid: 2, stingray, table: l2_cntxt_tcam.0 */\n-\t.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n-\t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,\n-\t.direction = TF_DIR_RX,\n-\t.execute_info = {\n-\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 2,\n-\t\t.cond_nums = 0 },\n-\t.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_SRCH_ALLOC_WR_REGFILE,\n-\t.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,\n-\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.pri_opcode  = BNXT_ULP_PRI_OPC_CONST,\n-\t.pri_operand = 0,\n-\t.key_start_idx = 82,\n-\t.blob_key_bit_size = 167,\n-\t.key_bit_size = 167,\n-\t.key_num_fields = 13,\n-\t.result_start_idx = 44,\n-\t.result_bit_size = 64,\n-\t.result_num_fields = 13,\n-\t.encap_num_fields = 0,\n-\t.ident_start_idx = 5,\n-\t.ident_nums = 1\n-\t},\n-\t{ /* class_tid: 2, stingray, table: profile_tcam_cache.rd */\n-\t.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,\n-\t.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,\n-\t.resource_sub_type =\n-\t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,\n-\t.direction = TF_DIR_RX,\n-\t.execute_info = {\n-\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 2,\n-\t\t.cond_nums = 0 },\n-\t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,\n-\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_FLOW_SIG_ID_MATCH,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.key_start_idx = 95,\n-\t.blob_key_bit_size = 14,\n-\t.key_bit_size = 14,\n-\t.key_num_fields = 3,\n-\t.ident_start_idx = 6,\n-\t.ident_nums = 3\n-\t},\n-\t{ /* class_tid: 2, stingray, table: profile_tcam.0 */\n-\t.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n-\t.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,\n-\t.direction = TF_DIR_RX,\n-\t.execute_info = {\n-\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n-\t\t.cond_start_idx = 2,\n-\t\t.cond_nums = 1 },\n-\t.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,\n-\t.tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,\n-\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_PUSH_REGFILE,\n-\t.fdb_operand = BNXT_ULP_RF_IDX_RID,\n-\t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n-\t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,\n-\t.key_start_idx = 98,\n-\t.blob_key_bit_size = 81,\n-\t.key_bit_size = 81,\n-\t.key_num_fields = 43,\n-\t.result_start_idx = 57,\n-\t.result_bit_size = 38,\n-\t.result_num_fields = 8,\n-\t.encap_num_fields = 0,\n-\t.ident_start_idx = 9,\n-\t.ident_nums = 1\n-\t},\n-\t{ /* class_tid: 2, stingray, table: profile_tcam_cache.wr */\n-\t.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,\n-\t.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,\n-\t.resource_sub_type =\n-\t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,\n-\t.direction = TF_DIR_RX,\n-\t.execute_info = {\n-\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n-\t\t.cond_start_idx = 3,\n-\t\t.cond_nums = 1 },\n-\t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,\n-\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.key_start_idx = 141,\n-\t.blob_key_bit_size = 14,\n-\t.key_bit_size = 14,\n-\t.key_num_fields = 3,\n-\t.result_start_idx = 65,\n-\t.result_bit_size = 66,\n-\t.result_num_fields = 5,\n-\t.encap_num_fields = 0\n-\t},\n-\t{ /* class_tid: 2, stingray, table: eem.ext_0 */\n+\t{ /* class_tid: 1, stingray, table: eem.ext_0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE,\n \t.resource_type = TF_MEM_EXTERNAL,\n \t.direction = TF_DIR_RX,\n \t.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT,\n \t.execute_info = {\n-\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 4,\n-\t\t.cond_nums = 0 },\n+\t\t.cond_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n+\t\t.cond_start_idx = 3,\n+\t\t.cond_nums = 1 },\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,\n \t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,\n-\t.key_start_idx = 144,\n+\t.key_start_idx = 73,\n \t.blob_key_bit_size = 448,\n \t.key_bit_size = 448,\n \t.key_num_fields = 10,\n-\t.result_start_idx = 70,\n+\t.result_start_idx = 35,\n \t.result_bit_size = 64,\n \t.result_num_fields = 9,\n \t.encap_num_fields = 0\n \t},\n-\t{ /* class_tid: 2, stingray, table: em.int_0 */\n-\t.resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE,\n-\t.resource_type = TF_MEM_INTERNAL,\n+\t{ /* class_tid: 1, stingray, table: last */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_BRANCH_TABLE,\n \t.direction = TF_DIR_RX,\n-\t.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT,\n \t.execute_info = {\n+\t\t.cond_goto = 0,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 4,\n \t\t.cond_nums = 0 },\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,\n-\t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,\n-\t.key_start_idx = 154,\n-\t.blob_key_bit_size = 176,\n-\t.key_bit_size = 176,\n-\t.key_num_fields = 10,\n-\t.result_start_idx = 79,\n-\t.result_bit_size = 64,\n-\t.result_num_fields = 9,\n-\t.encap_num_fields = 0\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH\n \t},\n-\t{ /* class_tid: 3, stingray, table: int_full_act_record.0 */\n+\t{ /* class_tid: 2, stingray, table: int_full_act_record.0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n \t.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,\n \t.resource_sub_type =\n \t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,\n \t.direction = TF_DIR_RX,\n \t.execute_info = {\n+\t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 4,\n \t\t.cond_nums = 0 },\n@@ -374,16 +277,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n-\t.result_start_idx = 88,\n+\t.result_start_idx = 44,\n \t.result_bit_size = 128,\n \t.result_num_fields = 26,\n \t.encap_num_fields = 0\n \t},\n-\t{ /* class_tid: 3, stingray, table: l2_cntxt_tcam.0 */\n+\t{ /* class_tid: 2, stingray, table: l2_cntxt_tcam.0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n \t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,\n \t.direction = TF_DIR_RX,\n \t.execute_info = {\n+\t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 4,\n \t\t.cond_nums = 0 },\n@@ -396,44 +300,46 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {\n \t.pri_operand = 0,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n \t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,\n-\t.key_start_idx = 164,\n+\t.key_start_idx = 83,\n \t.blob_key_bit_size = 167,\n \t.key_bit_size = 167,\n \t.key_num_fields = 13,\n-\t.result_start_idx = 114,\n+\t.result_start_idx = 70,\n \t.result_bit_size = 64,\n \t.result_num_fields = 13,\n \t.encap_num_fields = 0,\n-\t.ident_start_idx = 10,\n+\t.ident_start_idx = 6,\n \t.ident_nums = 1\n \t},\n-\t{ /* class_tid: 3, stingray, table: l2_cntxt_tcam_cache.wr */\n+\t{ /* class_tid: 2, stingray, table: l2_cntxt_tcam_cache.wr */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,\n \t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,\n \t.resource_sub_type =\n \t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,\n \t.direction = TF_DIR_RX,\n \t.execute_info = {\n+\t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 4,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.key_start_idx = 177,\n+\t.key_start_idx = 96,\n \t.blob_key_bit_size = 8,\n \t.key_bit_size = 8,\n \t.key_num_fields = 1,\n-\t.result_start_idx = 127,\n+\t.result_start_idx = 83,\n \t.result_bit_size = 62,\n \t.result_num_fields = 4,\n \t.encap_num_fields = 0\n \t},\n-\t{ /* class_tid: 3, stingray, table: parif_def_lkup_arec_ptr.0 */\n+\t{ /* class_tid: 2, stingray, table: parif_def_lkup_arec_ptr.0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,\n \t.resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR,\n \t.direction = TF_DIR_RX,\n \t.execute_info = {\n+\t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 4,\n \t\t.cond_nums = 0 },\n@@ -441,16 +347,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {\n \t.tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.result_start_idx = 131,\n+\t.result_start_idx = 87,\n \t.result_bit_size = 32,\n \t.result_num_fields = 1,\n \t.encap_num_fields = 0\n \t},\n-\t{ /* class_tid: 3, stingray, table: parif_def_arec_ptr.0 */\n+\t{ /* class_tid: 2, stingray, table: parif_def_arec_ptr.0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,\n \t.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,\n \t.direction = TF_DIR_RX,\n \t.execute_info = {\n+\t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 4,\n \t\t.cond_nums = 0 },\n@@ -458,16 +365,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {\n \t.tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.result_start_idx = 132,\n+\t.result_start_idx = 88,\n \t.result_bit_size = 32,\n \t.result_num_fields = 1,\n \t.encap_num_fields = 0\n \t},\n-\t{ /* class_tid: 3, stingray, table: parif_def_err_arec_ptr.0 */\n+\t{ /* class_tid: 2, stingray, table: parif_def_err_arec_ptr.0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,\n \t.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,\n \t.direction = TF_DIR_RX,\n \t.execute_info = {\n+\t\t.cond_goto = 0,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 4,\n \t\t.cond_nums = 0 },\n@@ -475,18 +383,19 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {\n \t.tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.result_start_idx = 133,\n+\t.result_start_idx = 89,\n \t.result_bit_size = 32,\n \t.result_num_fields = 1,\n \t.encap_num_fields = 0\n \t},\n-\t{ /* class_tid: 4, stingray, table: int_full_act_record.0 */\n+\t{ /* class_tid: 3, stingray, table: int_full_act_record.0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n \t.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,\n \t.resource_sub_type =\n \t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,\n \t.direction = TF_DIR_TX,\n \t.execute_info = {\n+\t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 4,\n \t\t.cond_nums = 0 },\n@@ -495,16 +404,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n-\t.result_start_idx = 134,\n+\t.result_start_idx = 90,\n \t.result_bit_size = 128,\n \t.result_num_fields = 26,\n \t.encap_num_fields = 0\n \t},\n-\t{ /* class_tid: 4, stingray, table: l2_cntxt_tcam_bypass.vfr_0 */\n+\t{ /* class_tid: 3, stingray, table: l2_cntxt_tcam_bypass.vfr_0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n \t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,\n \t.direction = TF_DIR_TX,\n \t.execute_info = {\n+\t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n \t\t.cond_start_idx = 4,\n \t\t.cond_nums = 1 },\n@@ -516,42 +426,44 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {\n \t.pri_operand = 0,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n \t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,\n-\t.key_start_idx = 178,\n+\t.key_start_idx = 97,\n \t.blob_key_bit_size = 167,\n \t.key_bit_size = 167,\n \t.key_num_fields = 13,\n-\t.result_start_idx = 160,\n+\t.result_start_idx = 116,\n \t.result_bit_size = 64,\n \t.result_num_fields = 13,\n \t.encap_num_fields = 0,\n-\t.ident_start_idx = 11,\n+\t.ident_start_idx = 7,\n \t.ident_nums = 0\n \t},\n-\t{ /* class_tid: 4, stingray, table: l2_cntxt_tcam_cache.rd */\n+\t{ /* class_tid: 3, stingray, table: l2_cntxt_tcam_cache.rd */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,\n \t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,\n \t.resource_sub_type =\n \t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,\n \t.direction = TF_DIR_TX,\n \t.execute_info = {\n+\t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n \t\t.cond_start_idx = 5,\n \t\t.cond_nums = 1 },\n \t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.key_start_idx = 191,\n+\t.key_start_idx = 110,\n \t.blob_key_bit_size = 8,\n \t.key_bit_size = 8,\n \t.key_num_fields = 1,\n-\t.ident_start_idx = 11,\n+\t.ident_start_idx = 7,\n \t.ident_nums = 1\n \t},\n-\t{ /* class_tid: 4, stingray, table: l2_cntxt_tcam.0 */\n+\t{ /* class_tid: 3, stingray, table: l2_cntxt_tcam.0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n \t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,\n \t.direction = TF_DIR_TX,\n \t.execute_info = {\n+\t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,\n \t\t.cond_start_idx = 6,\n \t\t.cond_nums = 2 },\n@@ -562,44 +474,46 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {\n \t.fdb_operand = BNXT_ULP_RF_IDX_RID,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n \t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,\n-\t.key_start_idx = 192,\n+\t.key_start_idx = 111,\n \t.blob_key_bit_size = 167,\n \t.key_bit_size = 167,\n \t.key_num_fields = 13,\n-\t.result_start_idx = 173,\n+\t.result_start_idx = 129,\n \t.result_bit_size = 64,\n \t.result_num_fields = 13,\n \t.encap_num_fields = 0,\n-\t.ident_start_idx = 12,\n+\t.ident_start_idx = 8,\n \t.ident_nums = 1\n \t},\n-\t{ /* class_tid: 4, stingray, table: l2_cntxt_tcam_cache.wr */\n+\t{ /* class_tid: 3, stingray, table: l2_cntxt_tcam_cache.wr */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,\n \t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,\n \t.resource_sub_type =\n \t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,\n \t.direction = TF_DIR_TX,\n \t.execute_info = {\n+\t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,\n \t\t.cond_start_idx = 8,\n \t\t.cond_nums = 2 },\n \t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.key_start_idx = 205,\n+\t.key_start_idx = 124,\n \t.blob_key_bit_size = 8,\n \t.key_bit_size = 8,\n \t.key_num_fields = 1,\n-\t.result_start_idx = 186,\n+\t.result_start_idx = 142,\n \t.result_bit_size = 62,\n \t.result_num_fields = 4,\n \t.encap_num_fields = 0\n \t},\n-\t{ /* class_tid: 4, stingray, table: parif_def_lkup_arec_ptr.0 */\n+\t{ /* class_tid: 3, stingray, table: parif_def_lkup_arec_ptr.0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,\n \t.resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR,\n \t.direction = TF_DIR_TX,\n \t.execute_info = {\n+\t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 10,\n \t\t.cond_nums = 0 },\n@@ -607,16 +521,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {\n \t.tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.result_start_idx = 190,\n+\t.result_start_idx = 146,\n \t.result_bit_size = 32,\n \t.result_num_fields = 1,\n \t.encap_num_fields = 0\n \t},\n-\t{ /* class_tid: 4, stingray, table: parif_def_arec_ptr.0 */\n+\t{ /* class_tid: 3, stingray, table: parif_def_arec_ptr.0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,\n \t.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,\n \t.direction = TF_DIR_TX,\n \t.execute_info = {\n+\t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 10,\n \t\t.cond_nums = 0 },\n@@ -624,16 +539,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {\n \t.tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.result_start_idx = 191,\n+\t.result_start_idx = 147,\n \t.result_bit_size = 32,\n \t.result_num_fields = 1,\n \t.encap_num_fields = 0\n \t},\n-\t{ /* class_tid: 4, stingray, table: parif_def_err_arec_ptr.0 */\n+\t{ /* class_tid: 3, stingray, table: parif_def_err_arec_ptr.0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,\n \t.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,\n \t.direction = TF_DIR_TX,\n \t.execute_info = {\n+\t\t.cond_goto = 0,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 10,\n \t\t.cond_nums = 0 },\n@@ -641,18 +557,19 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {\n \t.tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.result_start_idx = 192,\n+\t.result_start_idx = 148,\n \t.result_bit_size = 32,\n \t.result_num_fields = 1,\n \t.encap_num_fields = 0\n \t},\n-\t{ /* class_tid: 5, stingray, table: int_vtag_encap_record.egr0 */\n+\t{ /* class_tid: 4, stingray, table: int_vtag_encap_record.egr0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n \t.resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,\n \t.resource_sub_type =\n \t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,\n \t.direction = TF_DIR_TX,\n \t.execute_info = {\n+\t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 10,\n \t\t.cond_nums = 0 },\n@@ -661,18 +578,19 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n-\t.result_start_idx = 193,\n+\t.result_start_idx = 149,\n \t.result_bit_size = 0,\n \t.result_num_fields = 0,\n \t.encap_num_fields = 12\n \t},\n-\t{ /* class_tid: 5, stingray, table: int_full_act_record.egr0 */\n+\t{ /* class_tid: 4, stingray, table: int_full_act_record.egr0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n \t.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,\n \t.resource_sub_type =\n \t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,\n \t.direction = TF_DIR_TX,\n \t.execute_info = {\n+\t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 10,\n \t\t.cond_nums = 0 },\n@@ -681,16 +599,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n-\t.result_start_idx = 205,\n+\t.result_start_idx = 161,\n \t.result_bit_size = 128,\n \t.result_num_fields = 26,\n \t.encap_num_fields = 0\n \t},\n-\t{ /* class_tid: 5, stingray, table: l2_cntxt_tcam_bypass.egr0 */\n+\t{ /* class_tid: 4, stingray, table: l2_cntxt_tcam_bypass.egr0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n \t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,\n \t.direction = TF_DIR_TX,\n \t.execute_info = {\n+\t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 10,\n \t\t.cond_nums = 0 },\n@@ -701,48 +620,50 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {\n \t.fdb_operand = BNXT_ULP_RF_IDX_RID,\n \t.pri_opcode  = BNXT_ULP_PRI_OPC_CONST,\n \t.pri_operand = 0,\n-\t.key_start_idx = 206,\n+\t.key_start_idx = 125,\n \t.blob_key_bit_size = 167,\n \t.key_bit_size = 167,\n \t.key_num_fields = 13,\n-\t.result_start_idx = 231,\n+\t.result_start_idx = 187,\n \t.result_bit_size = 64,\n \t.result_num_fields = 13,\n \t.encap_num_fields = 0,\n-\t.ident_start_idx = 13,\n+\t.ident_start_idx = 9,\n \t.ident_nums = 0\n \t},\n-\t{ /* class_tid: 5, stingray, table: l2_cntxt_tcam_cache.wr_egr0 */\n+\t{ /* class_tid: 4, stingray, table: l2_cntxt_tcam_cache.wr_egr0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,\n \t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,\n \t.resource_sub_type =\n \t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,\n \t.direction = TF_DIR_TX,\n \t.execute_info = {\n+\t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 10,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.key_start_idx = 219,\n+\t.key_start_idx = 138,\n \t.blob_key_bit_size = 8,\n \t.key_bit_size = 8,\n \t.key_num_fields = 1,\n-\t.result_start_idx = 244,\n+\t.result_start_idx = 200,\n \t.result_bit_size = 62,\n \t.result_num_fields = 4,\n \t.encap_num_fields = 0,\n-\t.ident_start_idx = 13,\n+\t.ident_start_idx = 9,\n \t.ident_nums = 0\n \t},\n-\t{ /* class_tid: 5, stingray, table: int_full_act_record.ing0 */\n+\t{ /* class_tid: 4, stingray, table: int_full_act_record.ing0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n \t.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,\n \t.resource_sub_type =\n \t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,\n \t.direction = TF_DIR_RX,\n \t.execute_info = {\n+\t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 10,\n \t\t.cond_nums = 0 },\n@@ -751,16 +672,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n-\t.result_start_idx = 248,\n+\t.result_start_idx = 204,\n \t.result_bit_size = 128,\n \t.result_num_fields = 26,\n \t.encap_num_fields = 0\n \t},\n-\t{ /* class_tid: 5, stingray, table: l2_cntxt_tcam_bypass.dtagged_ing0 */\n+\t{ /* class_tid: 4, stingray, table: l2_cntxt_tcam_bypass.dtagged_ing0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n \t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,\n \t.direction = TF_DIR_RX,\n \t.execute_info = {\n+\t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 10,\n \t\t.cond_nums = 0 },\n@@ -772,22 +694,23 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {\n \t.pri_operand = 0,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n \t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,\n-\t.key_start_idx = 220,\n+\t.key_start_idx = 139,\n \t.blob_key_bit_size = 167,\n \t.key_bit_size = 167,\n \t.key_num_fields = 13,\n-\t.result_start_idx = 274,\n+\t.result_start_idx = 230,\n \t.result_bit_size = 64,\n \t.result_num_fields = 13,\n \t.encap_num_fields = 0,\n-\t.ident_start_idx = 13,\n+\t.ident_start_idx = 9,\n \t.ident_nums = 0\n \t},\n-\t{ /* class_tid: 5, stingray, table: l2_cntxt_tcam_bypass.stagged_ing0 */\n+\t{ /* class_tid: 4, stingray, table: l2_cntxt_tcam_bypass.stagged_ing0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n \t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,\n \t.direction = TF_DIR_RX,\n \t.execute_info = {\n+\t\t.cond_goto = 0,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 10,\n \t\t.cond_nums = 0 },\n@@ -799,22 +722,23 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {\n \t.pri_operand = 0,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n \t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,\n-\t.key_start_idx = 233,\n+\t.key_start_idx = 152,\n \t.blob_key_bit_size = 167,\n \t.key_bit_size = 167,\n \t.key_num_fields = 13,\n-\t.result_start_idx = 287,\n+\t.result_start_idx = 243,\n \t.result_bit_size = 64,\n \t.result_num_fields = 13,\n \t.encap_num_fields = 0,\n-\t.ident_start_idx = 13,\n+\t.ident_start_idx = 9,\n \t.ident_nums = 0\n \t},\n-\t{ /* class_tid: 6, stingray, table: l2_cntxt_tcam.egr */\n+\t{ /* class_tid: 5, stingray, table: l2_cntxt_tcam.egr */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n \t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,\n \t.direction = TF_DIR_TX,\n \t.execute_info = {\n+\t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 10,\n \t\t.cond_nums = 0 },\n@@ -825,44 +749,46 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {\n \t.fdb_operand = BNXT_ULP_RF_IDX_RID,\n \t.pri_opcode  = BNXT_ULP_PRI_OPC_CONST,\n \t.pri_operand = 0,\n-\t.key_start_idx = 246,\n+\t.key_start_idx = 165,\n \t.blob_key_bit_size = 167,\n \t.key_bit_size = 167,\n \t.key_num_fields = 13,\n-\t.result_start_idx = 300,\n+\t.result_start_idx = 256,\n \t.result_bit_size = 64,\n \t.result_num_fields = 13,\n \t.encap_num_fields = 0,\n-\t.ident_start_idx = 13,\n+\t.ident_start_idx = 9,\n \t.ident_nums = 1\n \t},\n-\t{ /* class_tid: 6, stingray, table: l2_cntxt_tcam_cache.egr_wr */\n+\t{ /* class_tid: 5, stingray, table: l2_cntxt_tcam_cache.egr_wr */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,\n \t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,\n \t.resource_sub_type =\n \t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,\n \t.direction = TF_DIR_TX,\n \t.execute_info = {\n+\t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 10,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.key_start_idx = 259,\n+\t.key_start_idx = 178,\n \t.blob_key_bit_size = 8,\n \t.key_bit_size = 8,\n \t.key_num_fields = 1,\n-\t.result_start_idx = 313,\n+\t.result_start_idx = 269,\n \t.result_bit_size = 62,\n \t.result_num_fields = 4,\n \t.encap_num_fields = 0\n \t},\n-\t{ /* class_tid: 6, stingray, table: parif_def_lkup_arec_ptr.egr */\n+\t{ /* class_tid: 5, stingray, table: parif_def_lkup_arec_ptr.egr */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,\n \t.resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR,\n \t.direction = TF_DIR_TX,\n \t.execute_info = {\n+\t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 10,\n \t\t.cond_nums = 0 },\n@@ -870,16 +796,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {\n \t.tbl_operand = BNXT_ULP_CF_IDX_VF_FUNC_PARIF,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.result_start_idx = 317,\n+\t.result_start_idx = 273,\n \t.result_bit_size = 32,\n \t.result_num_fields = 1,\n \t.encap_num_fields = 0\n \t},\n-\t{ /* class_tid: 6, stingray, table: parif_def_arec_ptr.egr */\n+\t{ /* class_tid: 5, stingray, table: parif_def_arec_ptr.egr */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,\n \t.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,\n \t.direction = TF_DIR_TX,\n \t.execute_info = {\n+\t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 10,\n \t\t.cond_nums = 0 },\n@@ -887,16 +814,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {\n \t.tbl_operand = BNXT_ULP_CF_IDX_VF_FUNC_PARIF,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.result_start_idx = 318,\n+\t.result_start_idx = 274,\n \t.result_bit_size = 32,\n \t.result_num_fields = 1,\n \t.encap_num_fields = 0\n \t},\n-\t{ /* class_tid: 6, stingray, table: parif_def_err_arec_ptr.egr */\n+\t{ /* class_tid: 5, stingray, table: parif_def_err_arec_ptr.egr */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,\n \t.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,\n \t.direction = TF_DIR_TX,\n \t.execute_info = {\n+\t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 10,\n \t\t.cond_nums = 0 },\n@@ -904,18 +832,19 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {\n \t.tbl_operand = BNXT_ULP_CF_IDX_VF_FUNC_PARIF,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.result_start_idx = 319,\n+\t.result_start_idx = 275,\n \t.result_bit_size = 32,\n \t.result_num_fields = 1,\n \t.encap_num_fields = 0\n \t},\n-\t{ /* class_tid: 6, stingray, table: int_full_act_record.ing */\n+\t{ /* class_tid: 5, stingray, table: int_full_act_record.ing */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n \t.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,\n \t.resource_sub_type =\n \t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,\n \t.direction = TF_DIR_RX,\n \t.execute_info = {\n+\t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 10,\n \t\t.cond_nums = 0 },\n@@ -924,16 +853,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_AND_SET_VFR_FLAG,\n-\t.result_start_idx = 320,\n+\t.result_start_idx = 276,\n \t.result_bit_size = 128,\n \t.result_num_fields = 26,\n \t.encap_num_fields = 0\n \t},\n-\t{ /* class_tid: 6, stingray, table: l2_cntxt_tcam_bypass.ing */\n+\t{ /* class_tid: 5, stingray, table: l2_cntxt_tcam_bypass.ing */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n \t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,\n \t.direction = TF_DIR_RX,\n \t.execute_info = {\n+\t\t.cond_goto = 0,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 10,\n \t\t.cond_nums = 0 },\n@@ -945,24 +875,25 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {\n \t.pri_operand = 0,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n \t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,\n-\t.key_start_idx = 260,\n+\t.key_start_idx = 179,\n \t.blob_key_bit_size = 167,\n \t.key_bit_size = 167,\n \t.key_num_fields = 13,\n-\t.result_start_idx = 346,\n+\t.result_start_idx = 302,\n \t.result_bit_size = 64,\n \t.result_num_fields = 13,\n \t.encap_num_fields = 0,\n-\t.ident_start_idx = 14,\n+\t.ident_start_idx = 10,\n \t.ident_nums = 0\n \t},\n-\t{ /* class_tid: 7, stingray, table: int_full_act_record.0 */\n+\t{ /* class_tid: 6, stingray, table: int_full_act_record.0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n \t.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,\n \t.resource_sub_type =\n \t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,\n \t.direction = TF_DIR_TX,\n \t.execute_info = {\n+\t\t.cond_goto = 0,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 10,\n \t\t.cond_nums = 0 },\n@@ -971,7 +902,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n-\t.result_start_idx = 359,\n+\t.result_start_idx = 315,\n \t.result_bit_size = 128,\n \t.result_num_fields = 26,\n \t.encap_num_fields = 0\n@@ -980,246 +911,279 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {\n \n struct bnxt_ulp_mapper_cond_info ulp_stingray_class_cond_list[] = {\n \t{\n-\t.cond_opcode = BNXT_ULP_COND_OPC_REGFILE_NOT_SET,\n-\t.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT\n+\t.cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_NOT_SET,\n+\t.cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC\n \t},\n \t{\n-\t.cond_opcode = BNXT_ULP_COND_OPC_REGFILE_NOT_SET,\n+\t.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,\n \t.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT\n \t},\n \t{\n-\t.cond_opcode = BNXT_ULP_COND_OPC_REGFILE_NOT_SET,\n-\t.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT\n+\t.cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,\n+\t.cond_operand = BNXT_ULP_HDR_BIT_O_IPV4\n \t},\n \t{\n-\t.cond_opcode = BNXT_ULP_COND_OPC_REGFILE_NOT_SET,\n-\t.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT\n+\t.cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,\n+\t.cond_operand = BNXT_ULP_HDR_BIT_O_IPV4\n \t},\n \t{\n-\t.cond_opcode = BNXT_ULP_COND_OPC_COMP_FIELD_IS_SET,\n+\t.cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,\n \t.cond_operand = BNXT_ULP_CF_IDX_VFR_MODE\n \t},\n \t{\n-\t.cond_opcode = BNXT_ULP_COND_OPC_COMP_FIELD_NOT_SET,\n+\t.cond_opcode = BNXT_ULP_COND_OPC_CF_NOT_SET,\n \t.cond_operand = BNXT_ULP_CF_IDX_VFR_MODE\n \t},\n \t{\n-\t.cond_opcode = BNXT_ULP_COND_OPC_COMP_FIELD_NOT_SET,\n+\t.cond_opcode = BNXT_ULP_COND_OPC_CF_NOT_SET,\n \t.cond_operand = BNXT_ULP_CF_IDX_VFR_MODE\n \t},\n \t{\n-\t.cond_opcode = BNXT_ULP_COND_OPC_REGFILE_NOT_SET,\n+\t.cond_opcode = BNXT_ULP_COND_OPC_RF_NOT_SET,\n \t.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT\n \t},\n \t{\n-\t.cond_opcode = BNXT_ULP_COND_OPC_COMP_FIELD_NOT_SET,\n+\t.cond_opcode = BNXT_ULP_COND_OPC_CF_NOT_SET,\n \t.cond_operand = BNXT_ULP_CF_IDX_VFR_MODE\n \t},\n \t{\n-\t.cond_opcode = BNXT_ULP_COND_OPC_REGFILE_NOT_SET,\n+\t.cond_opcode = BNXT_ULP_COND_OPC_RF_NOT_SET,\n \t.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT\n \t}\n };\n \n struct bnxt_ulp_mapper_key_info ulp_stingray_class_key_info_list[] = {\n+\t/* class_tid: 1, stingray, table: l2_cntxt_tcam_cache.rd */\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}\n+\t\t}\n+\t},\n \t/* class_tid: 1, stingray, table: l2_cntxt_tcam.0 */\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l2_ivlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_GLB_HF_OO_VLAN_VID >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_OO_VLAN_VID & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l2_ivlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_GLB_HF_OO_VLAN_VID >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_OO_VLAN_VID & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l2_ovlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l2_ovlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"mac0_addr\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_GLB_HF_O_ETH_DMAC >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_O_ETH_DMAC & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"mac0_addr\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_GLB_HF_O_ETH_DMAC >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_O_ETH_DMAC & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"svif\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_GLB_HF_SVIF_INDEX >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_SVIF_INDEX & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"svif\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_GLB_HF_SVIF_INDEX >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_SVIF_INDEX & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"sparif\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"sparif\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl2_ivlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl2_ivlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl2_ovlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl2_ovlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"mac1_addr\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"mac1_addr\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l2_num_vtags\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l2_num_vtags\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,\n-\t\t.field_operand = {\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n \t\t\t(BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff,\n-\t\t\tBNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t\tBNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl2_num_vtags\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl2_num_vtags\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tun_hdr_type\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tun_hdr_type\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"key_type\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"key_type\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"valid\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"valid\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t1}\n \t\t}\n \t},\n \t/* class_tid: 1, stingray, table: profile_tcam_cache.rd */\n@@ -1227,52 +1191,54 @@ struct bnxt_ulp_mapper_key_info ulp_stingray_class_key_info_list[] = {\n \t.field_info_mask = {\n \t\t.description = \"recycle_cnt\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"recycle_cnt\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"prof_func_id\",\n \t\t.field_bit_size = 7,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"prof_func_id\",\n \t\t.field_bit_size = 7,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE,\n-\t\t.field_operand = {\n-\t\t(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"hdr_sig_id\",\n \t\t.field_bit_size = 5,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"hdr_sig_id\",\n \t\t.field_bit_size = 5,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,\n-\t\t.field_operand = {\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n \t\t\t(BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,\n-\t\t\tBNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t\tBNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}\n \t\t}\n \t},\n \t/* class_tid: 1, stingray, table: profile_tcam.0 */\n@@ -1280,580 +1246,684 @@ struct bnxt_ulp_mapper_key_info ulp_stingray_class_key_info_list[] = {\n \t.field_info_mask = {\n \t\t.description = \"l4_hdr_is_udp_tcp\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l4_hdr_is_udp_tcp\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l4_hdr_type\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l4_hdr_type\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,\n+\t\t.field_cond_opr = {\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,\n+\t\t\t(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\tULP_SR_SYM_L4_HDR_TYPE_TCP},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr2 = {\n+\t\t\tULP_SR_SYM_L4_HDR_TYPE_UDP}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l4_hdr_error\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l4_hdr_error\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l4_hdr_valid\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l4_hdr_valid\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {\n-\t\t\tBNXT_ULP_STINGRAY_SYM_L4_HDR_VALID_YES,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\tULP_SR_SYM_L4_HDR_VALID_YES}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l3_ipv6_cmp_dst\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l3_ipv6_cmp_dst\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l3_ipv6_cmp_src\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l3_ipv6_cmp_src\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l3_hdr_isIP\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l3_hdr_isIP\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l3_hdr_type\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l3_hdr_type\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,\n+\t\t.field_cond_opr = {\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,\n+\t\t\t(uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\tULP_SR_SYM_L3_HDR_TYPE_IPV4},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr2 = {\n+\t\t\tULP_SR_SYM_L3_HDR_TYPE_IPV6}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l3_hdr_error\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l3_hdr_error\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l3_hdr_valid\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l3_hdr_valid\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {\n-\t\t\tBNXT_ULP_STINGRAY_SYM_L3_HDR_VALID_YES,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\tULP_SR_SYM_L3_HDR_VALID_YES}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l2_two_vtags\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l2_two_vtags\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l2_vtag_present\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l2_vtag_present\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,\n-\t\t.field_operand = {\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n \t\t\t(BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff,\n-\t\t\tBNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t\tBNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l2_uc_mc_bc\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l2_uc_mc_bc\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l2_hdr_type\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l2_hdr_type\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l2_hdr_error\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l2_hdr_error\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l2_hdr_valid\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l2_hdr_valid\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {\n-\t\t\tBNXT_ULP_STINGRAY_SYM_L2_HDR_VALID_YES,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\tULP_SR_SYM_L2_HDR_VALID_YES}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tun_hdr_flags\",\n \t\t.field_bit_size = 3,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tun_hdr_flags\",\n \t\t.field_bit_size = 3,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tun_hdr_type\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tun_hdr_type\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tun_hdr_err\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tun_hdr_err\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tun_hdr_valid\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tun_hdr_valid\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl4_hdr_is_udp_tcp\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl4_hdr_is_udp_tcp\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl4_hdr_type\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl4_hdr_type\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl4_hdr_error\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl4_hdr_error\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl4_hdr_valid\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl4_hdr_valid\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl3_ipv6_cmp_dst\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl3_ipv6_cmp_dst\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl3_ipv6_cmp_src\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl3_ipv6_cmp_src\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl3_hdr_isIP\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl3_hdr_isIP\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl3_hdr_type\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl3_hdr_type\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl3_hdr_error\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl3_hdr_error\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl3_hdr_valid\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl3_hdr_valid\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl2_two_vtags\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl2_two_vtags\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl2_vtag_present\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl2_vtag_present\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl2_uc_mc_bc\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl2_uc_mc_bc\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl2_hdr_type\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl2_hdr_type\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl2_hdr_valid\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl2_hdr_valid\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"hrec_next\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"hrec_next\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"reserved\",\n \t\t.field_bit_size = 9,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"reserved\",\n \t\t.field_bit_size = 9,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"prof_func_id\",\n \t\t.field_bit_size = 7,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"prof_func_id\",\n \t\t.field_bit_size = 7,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE,\n-\t\t.field_operand = {\n-\t\t(BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"agg_error\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"agg_error\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"recycle_cnt\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"recycle_cnt\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"pkt_type_0\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"pkt_type_0\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"pkt_type_1\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"pkt_type_1\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"valid\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"valid\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t1}\n \t\t}\n \t},\n \t/* class_tid: 1, stingray, table: profile_tcam_cache.wr */\n@@ -1861,3165 +1931,2188 @@ struct bnxt_ulp_mapper_key_info ulp_stingray_class_key_info_list[] = {\n \t.field_info_mask = {\n \t\t.description = \"recycle_cnt\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"recycle_cnt\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"prof_func_id\",\n \t\t.field_bit_size = 7,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"prof_func_id\",\n \t\t.field_bit_size = 7,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE,\n-\t\t.field_operand = {\n-\t\t(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"hdr_sig_id\",\n \t\t.field_bit_size = 5,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"hdr_sig_id\",\n \t\t.field_bit_size = 5,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,\n-\t\t.field_operand = {\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n \t\t\t(BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,\n-\t\t\tBNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t\tBNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}\n \t\t}\n \t},\n-\t/* class_tid: 1, stingray, table: eem.ext_0 */\n+\t/* class_tid: 1, stingray, table: em.int_0 */\n \t{\n \t.field_info_mask = {\n \t\t.description = \"spare\",\n-\t\t.field_bit_size = 275,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_bit_size = 3,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"spare\",\n-\t\t.field_bit_size = 275,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_bit_size = 3,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"local_cos\",\n \t\t.field_bit_size = 3,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"local_cos\",\n \t\t.field_bit_size = 3,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"o_l4.dport\",\n \t\t.field_bit_size = 16,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_GLB_HF_O_TCP_DST_PORT >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_O_TCP_DST_PORT & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"o_l4.dport\",\n \t\t.field_bit_size = 16,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_GLB_HF_O_TCP_DST_PORT >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_O_TCP_DST_PORT & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,\n+\t\t.field_cond_opr = {\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,\n+\t\t\t(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"o_l4.sport\",\n \t\t.field_bit_size = 16,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_GLB_HF_O_TCP_SRC_PORT >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_O_TCP_SRC_PORT & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"o_l4.sport\",\n \t\t.field_bit_size = 16,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_GLB_HF_O_TCP_SRC_PORT >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_O_TCP_SRC_PORT & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,\n+\t\t.field_cond_opr = {\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,\n+\t\t\t(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"o_ipv4.ip_proto\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"o_ipv4.ip_proto\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {\n-\t\t\tBNXT_ULP_STINGRAY_SYM_IP_PROTO_TCP,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,\n+\t\t.field_cond_opr = {\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,\n+\t\t\t(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\tULP_SR_SYM_IP_PROTO_TCP},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr2 = {\n+\t\t\tULP_SR_SYM_IP_PROTO_UDP}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"o_ipv4.dst\",\n \t\t.field_bit_size = 32,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_O_IPV4_DST_ADDR & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"o_ipv4.dst\",\n \t\t.field_bit_size = 32,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_O_IPV4_DST_ADDR & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"o_ipv4.src\",\n \t\t.field_bit_size = 32,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_GLB_HF_O_IPV4_SRC_ADDR >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_O_IPV4_SRC_ADDR & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"o_ipv4.src\",\n \t\t.field_bit_size = 32,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_GLB_HF_O_IPV4_SRC_ADDR >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_O_IPV4_SRC_ADDR & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"o_eth.smac\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff,\n+\t\t\t0xff,\n+\t\t\t0xff,\n+\t\t\t0xff,\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"o_eth.smac\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l2_cntxt_id\",\n \t\t.field_bit_size = 10,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l2_cntxt_id\",\n \t\t.field_bit_size = 10,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t\t.field_operand = {\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t\t.field_opr1 = {\n \t\t\t(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,\n-\t\t\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"em_profile_id\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"em_profile_id\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t\t.field_operand = {\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t\t.field_opr1 = {\n \t\t\t(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,\n-\t\t\tBNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t\tBNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}\n \t\t}\n \t},\n-\t/* class_tid: 1, stingray, table: em.int_0 */\n+\t/* class_tid: 1, stingray, table: eem.ext_0 */\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"spare\",\n-\t\t.field_bit_size = 3,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"spare\",\n-\t\t.field_bit_size = 3,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"local_cos\",\n-\t\t.field_bit_size = 3,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"local_cos\",\n-\t\t.field_bit_size = 3,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"o_l4.dport\",\n-\t\t.field_bit_size = 16,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_GLB_HF_O_TCP_DST_PORT >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_O_TCP_DST_PORT & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"o_l4.dport\",\n-\t\t.field_bit_size = 16,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_GLB_HF_O_TCP_DST_PORT >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_O_TCP_DST_PORT & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"o_l4.sport\",\n-\t\t.field_bit_size = 16,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_GLB_HF_O_TCP_SRC_PORT >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_O_TCP_SRC_PORT & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"o_l4.sport\",\n-\t\t.field_bit_size = 16,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_GLB_HF_O_TCP_SRC_PORT >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_O_TCP_SRC_PORT & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"o_ipv4.ip_proto\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"o_ipv4.ip_proto\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {\n-\t\t\tBNXT_ULP_STINGRAY_SYM_IP_PROTO_TCP,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"o_ipv4.dst\",\n-\t\t.field_bit_size = 32,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_O_IPV4_DST_ADDR & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"o_ipv4.dst\",\n-\t\t.field_bit_size = 32,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_O_IPV4_DST_ADDR & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"o_ipv4.src\",\n-\t\t.field_bit_size = 32,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_GLB_HF_O_IPV4_SRC_ADDR >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_O_IPV4_SRC_ADDR & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"o_ipv4.src\",\n-\t\t.field_bit_size = 32,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_GLB_HF_O_IPV4_SRC_ADDR >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_O_IPV4_SRC_ADDR & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"o_eth.smac\",\n-\t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"o_eth.smac\",\n-\t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"l2_cntxt_id\",\n-\t\t.field_bit_size = 10,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l2_cntxt_id\",\n-\t\t.field_bit_size = 10,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,\n-\t\t\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"em_profile_id\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"em_profile_id\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,\n-\t\t\tBNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t\t}\n-\t},\n-\t/* class_tid: 2, stingray, table: l2_cntxt_tcam.0 */\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"l2_ivlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_GLB_HF_OO_VLAN_VID >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_OO_VLAN_VID & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l2_ivlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_GLB_HF_OO_VLAN_VID >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_OO_VLAN_VID & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"l2_ovlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l2_ovlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"mac0_addr\",\n-\t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_GLB_HF_O_ETH_DMAC >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_O_ETH_DMAC & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"mac0_addr\",\n-\t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_GLB_HF_O_ETH_DMAC >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_O_ETH_DMAC & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"svif\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_GLB_HF_SVIF_INDEX >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_SVIF_INDEX & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"svif\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_GLB_HF_SVIF_INDEX >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_SVIF_INDEX & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"sparif\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"sparif\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"tl2_ivlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tl2_ivlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"tl2_ovlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tl2_ovlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"mac1_addr\",\n-\t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"mac1_addr\",\n-\t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"l2_num_vtags\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l2_num_vtags\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff,\n-\t\t\tBNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"tl2_num_vtags\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tl2_num_vtags\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"tun_hdr_type\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tun_hdr_type\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"key_type\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"key_type\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"valid\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"valid\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t\t}\n-\t},\n-\t/* class_tid: 2, stingray, table: profile_tcam_cache.rd */\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"recycle_cnt\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"recycle_cnt\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"prof_func_id\",\n-\t\t.field_bit_size = 7,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"prof_func_id\",\n-\t\t.field_bit_size = 7,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE,\n-\t\t.field_operand = {\n-\t\t(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"hdr_sig_id\",\n-\t\t.field_bit_size = 5,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"hdr_sig_id\",\n-\t\t.field_bit_size = 5,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,\n-\t\t\tBNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t\t}\n-\t},\n-\t/* class_tid: 2, stingray, table: profile_tcam.0 */\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"l4_hdr_is_udp_tcp\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l4_hdr_is_udp_tcp\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"l4_hdr_type\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l4_hdr_type\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"l4_hdr_error\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l4_hdr_error\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"l4_hdr_valid\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l4_hdr_valid\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {\n-\t\t\tBNXT_ULP_STINGRAY_SYM_L4_HDR_VALID_YES,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"l3_ipv6_cmp_dst\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l3_ipv6_cmp_dst\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"l3_ipv6_cmp_src\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l3_ipv6_cmp_src\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"l3_hdr_isIP\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l3_hdr_isIP\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"l3_hdr_type\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l3_hdr_type\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"l3_hdr_error\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l3_hdr_error\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"l3_hdr_valid\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l3_hdr_valid\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {\n-\t\t\tBNXT_ULP_STINGRAY_SYM_L3_HDR_VALID_YES,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"l2_two_vtags\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l2_two_vtags\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"l2_vtag_present\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l2_vtag_present\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff,\n-\t\t\tBNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"l2_uc_mc_bc\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l2_uc_mc_bc\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"l2_hdr_type\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l2_hdr_type\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"l2_hdr_error\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l2_hdr_error\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"l2_hdr_valid\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l2_hdr_valid\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {\n-\t\t\tBNXT_ULP_STINGRAY_SYM_L2_HDR_VALID_YES,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"tun_hdr_flags\",\n-\t\t.field_bit_size = 3,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tun_hdr_flags\",\n-\t\t.field_bit_size = 3,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"tun_hdr_type\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tun_hdr_type\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"tun_hdr_err\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tun_hdr_err\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"tun_hdr_valid\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tun_hdr_valid\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"tl4_hdr_is_udp_tcp\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tl4_hdr_is_udp_tcp\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"tl4_hdr_type\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tl4_hdr_type\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"tl4_hdr_error\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tl4_hdr_error\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"tl4_hdr_valid\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tl4_hdr_valid\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"tl3_ipv6_cmp_dst\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tl3_ipv6_cmp_dst\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"tl3_ipv6_cmp_src\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tl3_ipv6_cmp_src\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"tl3_hdr_isIP\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tl3_hdr_isIP\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"tl3_hdr_type\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tl3_hdr_type\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"tl3_hdr_error\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tl3_hdr_error\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"tl3_hdr_valid\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tl3_hdr_valid\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"tl2_two_vtags\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tl2_two_vtags\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"tl2_vtag_present\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tl2_vtag_present\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"tl2_uc_mc_bc\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tl2_uc_mc_bc\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"tl2_hdr_type\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tl2_hdr_type\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"tl2_hdr_valid\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tl2_hdr_valid\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"hrec_next\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"hrec_next\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"reserved\",\n-\t\t.field_bit_size = 9,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"reserved\",\n-\t\t.field_bit_size = 9,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"prof_func_id\",\n-\t\t.field_bit_size = 7,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"prof_func_id\",\n-\t\t.field_bit_size = 7,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE,\n-\t\t.field_operand = {\n-\t\t(BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"agg_error\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"agg_error\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"recycle_cnt\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"recycle_cnt\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"pkt_type_0\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"pkt_type_0\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"pkt_type_1\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"pkt_type_1\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"valid\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"valid\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t\t}\n-\t},\n-\t/* class_tid: 2, stingray, table: profile_tcam_cache.wr */\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"recycle_cnt\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"recycle_cnt\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"prof_func_id\",\n-\t\t.field_bit_size = 7,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"prof_func_id\",\n-\t\t.field_bit_size = 7,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE,\n-\t\t.field_operand = {\n-\t\t(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"hdr_sig_id\",\n-\t\t.field_bit_size = 5,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"hdr_sig_id\",\n-\t\t.field_bit_size = 5,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,\n-\t\t\tBNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t\t}\n-\t},\n-\t/* class_tid: 2, stingray, table: eem.ext_0 */\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"spare\",\n-\t\t.field_bit_size = 275,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n \t\t.description = \"spare\",\n \t\t.field_bit_size = 275,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"local_cos\",\n-\t\t.field_bit_size = 3,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"local_cos\",\n-\t\t.field_bit_size = 3,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"o_l4.dport\",\n-\t\t.field_bit_size = 16,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_GLB_HF_O_TCP_DST_PORT >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_O_TCP_DST_PORT & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"o_l4.dport\",\n-\t\t.field_bit_size = 16,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_GLB_HF_O_TCP_DST_PORT >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_O_TCP_DST_PORT & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"o_l4.sport\",\n-\t\t.field_bit_size = 16,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_GLB_HF_O_TCP_SRC_PORT >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_O_TCP_SRC_PORT & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"o_l4.sport\",\n-\t\t.field_bit_size = 16,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_GLB_HF_O_TCP_SRC_PORT >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_O_TCP_SRC_PORT & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"o_ipv4.ip_proto\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"o_ipv4.ip_proto\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {\n-\t\t\tBNXT_ULP_STINGRAY_SYM_IP_PROTO_TCP,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"o_ipv4.dst\",\n-\t\t.field_bit_size = 32,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_O_IPV4_DST_ADDR & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"o_ipv4.dst\",\n-\t\t.field_bit_size = 32,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_O_IPV4_DST_ADDR & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"o_ipv4.src\",\n-\t\t.field_bit_size = 32,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"o_ipv4.src\",\n-\t\t.field_bit_size = 32,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"o_eth.smac\",\n-\t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"o_eth.smac\",\n-\t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"l2_cntxt_id\",\n-\t\t.field_bit_size = 10,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l2_cntxt_id\",\n-\t\t.field_bit_size = 10,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,\n-\t\t\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"em_profile_id\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"em_profile_id\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,\n-\t\t\tBNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t\t}\n-\t},\n-\t/* class_tid: 2, stingray, table: em.int_0 */\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"spare\",\n-\t\t.field_bit_size = 3,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"spare\",\n-\t\t.field_bit_size = 3,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_bit_size = 275,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"local_cos\",\n \t\t.field_bit_size = 3,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"local_cos\",\n \t\t.field_bit_size = 3,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"o_l4.dport\",\n \t\t.field_bit_size = 16,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_GLB_HF_O_TCP_DST_PORT >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_O_TCP_DST_PORT & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"o_l4.dport\",\n \t\t.field_bit_size = 16,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_GLB_HF_O_TCP_DST_PORT >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_O_TCP_DST_PORT & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,\n+\t\t.field_cond_opr = {\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,\n+\t\t\t(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"o_l4.sport\",\n \t\t.field_bit_size = 16,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_GLB_HF_O_TCP_SRC_PORT >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_O_TCP_SRC_PORT & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"o_l4.sport\",\n \t\t.field_bit_size = 16,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_GLB_HF_O_TCP_SRC_PORT >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_O_TCP_SRC_PORT & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,\n+\t\t.field_cond_opr = {\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,\n+\t\t\t(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"o_ipv4.ip_proto\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"o_ipv4.ip_proto\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {\n-\t\t\tBNXT_ULP_STINGRAY_SYM_IP_PROTO_TCP,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,\n+\t\t.field_cond_opr = {\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,\n+\t\t\t(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\tULP_SR_SYM_IP_PROTO_TCP},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr2 = {\n+\t\t\tULP_SR_SYM_IP_PROTO_UDP}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"o_ipv4.dst\",\n \t\t.field_bit_size = 32,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_O_IPV4_DST_ADDR & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"o_ipv4.dst\",\n \t\t.field_bit_size = 32,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_O_IPV4_DST_ADDR & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"o_ipv4.src\",\n \t\t.field_bit_size = 32,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"o_ipv4.src\",\n \t\t.field_bit_size = 32,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"o_eth.smac\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff,\n+\t\t\t0xff,\n+\t\t\t0xff,\n+\t\t\t0xff,\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"o_eth.smac\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l2_cntxt_id\",\n \t\t.field_bit_size = 10,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l2_cntxt_id\",\n \t\t.field_bit_size = 10,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t\t.field_operand = {\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t\t.field_opr1 = {\n \t\t\t(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,\n-\t\t\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"em_profile_id\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"em_profile_id\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t\t.field_operand = {\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t\t.field_opr1 = {\n \t\t\t(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,\n-\t\t\tBNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t\tBNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}\n \t\t}\n \t},\n-\t/* class_tid: 3, stingray, table: l2_cntxt_tcam.0 */\n+\t/* class_tid: 2, stingray, table: l2_cntxt_tcam.0 */\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l2_ivlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l2_ivlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l2_ovlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l2_ovlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"mac0_addr\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"mac0_addr\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"svif\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"svif\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,\n-\t\t.field_operand = {\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n \t\t\t(BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff,\n-\t\t\tBNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t\tBNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"sparif\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"sparif\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl2_ivlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl2_ivlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl2_ovlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl2_ovlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"mac1_addr\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"mac1_addr\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l2_num_vtags\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l2_num_vtags\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl2_num_vtags\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl2_num_vtags\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tun_hdr_type\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tun_hdr_type\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"key_type\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"key_type\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"valid\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"valid\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t1}\n \t\t}\n \t},\n-\t/* class_tid: 3, stingray, table: l2_cntxt_tcam_cache.wr */\n+\t/* class_tid: 2, stingray, table: l2_cntxt_tcam_cache.wr */\n \t{\n \t.field_info_mask = {\n \t\t.description = \"svif\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"svif\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,\n-\t\t.field_operand = {\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n \t\t\t(BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff,\n-\t\t\tBNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t\tBNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}\n \t\t}\n \t},\n-\t/* class_tid: 4, stingray, table: l2_cntxt_tcam_bypass.vfr_0 */\n+\t/* class_tid: 3, stingray, table: l2_cntxt_tcam_bypass.vfr_0 */\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l2_ivlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l2_ivlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l2_ovlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l2_ovlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"mac0_addr\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"mac0_addr\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"svif\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"svif\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,\n-\t\t.field_operand = {\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n \t\t\t(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,\n-\t\t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"sparif\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"sparif\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl2_ivlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl2_ivlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl2_ovlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl2_ovlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"mac1_addr\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"mac1_addr\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l2_num_vtags\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l2_num_vtags\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl2_num_vtags\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl2_num_vtags\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tun_hdr_type\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tun_hdr_type\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"key_type\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"key_type\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"valid\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"valid\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t1}\n \t\t}\n \t},\n-\t/* class_tid: 4, stingray, table: l2_cntxt_tcam_cache.rd */\n+\t/* class_tid: 3, stingray, table: l2_cntxt_tcam_cache.rd */\n \t{\n \t.field_info_mask = {\n \t\t.description = \"svif\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"svif\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,\n-\t\t.field_operand = {\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n \t\t\t(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,\n-\t\t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}\n \t\t}\n \t},\n-\t/* class_tid: 4, stingray, table: l2_cntxt_tcam.0 */\n+\t/* class_tid: 3, stingray, table: l2_cntxt_tcam.0 */\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l2_ivlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l2_ivlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l2_ovlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l2_ovlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"mac0_addr\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"mac0_addr\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"svif\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"svif\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,\n-\t\t.field_operand = {\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n \t\t\t(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,\n-\t\t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"sparif\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"sparif\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl2_ivlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl2_ivlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl2_ovlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl2_ovlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"mac1_addr\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"mac1_addr\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l2_num_vtags\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l2_num_vtags\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl2_num_vtags\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl2_num_vtags\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tun_hdr_type\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tun_hdr_type\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"key_type\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"key_type\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"valid\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"valid\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t1}\n \t\t}\n \t},\n-\t/* class_tid: 4, stingray, table: l2_cntxt_tcam_cache.wr */\n+\t/* class_tid: 3, stingray, table: l2_cntxt_tcam_cache.wr */\n \t{\n \t.field_info_mask = {\n \t\t.description = \"svif\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"svif\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,\n-\t\t.field_operand = {\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n \t\t\t(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,\n-\t\t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}\n \t\t}\n \t},\n-\t/* class_tid: 5, stingray, table: l2_cntxt_tcam_bypass.egr0 */\n+\t/* class_tid: 4, stingray, table: l2_cntxt_tcam_bypass.egr0 */\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l2_ivlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l2_ivlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l2_ovlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l2_ovlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"mac0_addr\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"mac0_addr\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"svif\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"svif\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,\n-\t\t.field_operand = {\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n \t\t\t(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,\n-\t\t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"sparif\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"sparif\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl2_ivlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl2_ivlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl2_ovlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl2_ovlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"mac1_addr\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"mac1_addr\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l2_num_vtags\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l2_num_vtags\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl2_num_vtags\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl2_num_vtags\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tun_hdr_type\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tun_hdr_type\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"key_type\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"key_type\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"valid\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"valid\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t1}\n \t\t}\n \t},\n-\t/* class_tid: 5, stingray, table: l2_cntxt_tcam_cache.wr_egr0 */\n+\t/* class_tid: 4, stingray, table: l2_cntxt_tcam_cache.wr_egr0 */\n \t{\n \t.field_info_mask = {\n \t\t.description = \"svif\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"svif\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,\n-\t\t.field_operand = {\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n \t\t\t(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,\n-\t\t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}\n \t\t}\n \t},\n-\t/* class_tid: 5, stingray, table: l2_cntxt_tcam_bypass.dtagged_ing0 */\n+\t/* class_tid: 4, stingray, table: l2_cntxt_tcam_bypass.dtagged_ing0 */\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l2_ivlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l2_ivlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l2_ovlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l2_ovlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,\n-\t\t.field_operand = {\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n \t\t\t(BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,\n-\t\t\tBNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t\tBNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"mac0_addr\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"mac0_addr\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"svif\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"svif\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,\n-\t\t.field_operand = {\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n \t\t\t(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,\n-\t\t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"sparif\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"sparif\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl2_ivlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl2_ivlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl2_ovlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl2_ovlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"mac1_addr\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"mac1_addr\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l2_num_vtags\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l2_num_vtags\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t2}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl2_num_vtags\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl2_num_vtags\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tun_hdr_type\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tun_hdr_type\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {\n-\t\t\tBNXT_ULP_STINGRAY_SYM_TUN_HDR_TYPE_NONE,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\tULP_SR_SYM_TUN_HDR_TYPE_NONE}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"key_type\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"key_type\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"valid\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"valid\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t1}\n \t\t}\n \t},\n-\t/* class_tid: 5, stingray, table: l2_cntxt_tcam_bypass.stagged_ing0 */\n+\t/* class_tid: 4, stingray, table: l2_cntxt_tcam_bypass.stagged_ing0 */\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l2_ivlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l2_ivlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,\n-\t\t.field_operand = {\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n \t\t\t(BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,\n-\t\t\tBNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t\tBNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l2_ovlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l2_ovlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"mac0_addr\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"mac0_addr\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"svif\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"svif\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,\n-\t\t.field_operand = {\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n \t\t\t(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,\n-\t\t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"sparif\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"sparif\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl2_ivlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl2_ivlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl2_ovlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl2_ovlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"mac1_addr\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"mac1_addr\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l2_num_vtags\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l2_num_vtags\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t1}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl2_num_vtags\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl2_num_vtags\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tun_hdr_type\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tun_hdr_type\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {\n-\t\t\tBNXT_ULP_STINGRAY_SYM_TUN_HDR_TYPE_NONE,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\tULP_SR_SYM_TUN_HDR_TYPE_NONE}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"key_type\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"key_type\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"valid\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"valid\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t1}\n \t\t}\n \t},\n-\t/* class_tid: 6, stingray, table: l2_cntxt_tcam.egr */\n+\t/* class_tid: 5, stingray, table: l2_cntxt_tcam.egr */\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l2_ivlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l2_ivlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l2_ovlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l2_ovlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"mac0_addr\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"mac0_addr\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"svif\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"svif\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,\n-\t\t.field_operand = {\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n \t\t\t(BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,\n-\t\t\tBNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t\tBNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"sparif\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"sparif\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl2_ivlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl2_ivlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl2_ovlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl2_ovlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"mac1_addr\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"mac1_addr\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l2_num_vtags\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l2_num_vtags\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl2_num_vtags\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl2_num_vtags\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tun_hdr_type\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tun_hdr_type\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"key_type\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"key_type\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"valid\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"valid\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t1}\n \t\t}\n \t},\n-\t/* class_tid: 6, stingray, table: l2_cntxt_tcam_cache.egr_wr */\n+\t/* class_tid: 5, stingray, table: l2_cntxt_tcam_cache.egr_wr */\n \t{\n \t.field_info_mask = {\n \t\t.description = \"svif\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"svif\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,\n-\t\t.field_operand = {\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n \t\t\t(BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,\n-\t\t\tBNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t\tBNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}\n \t\t}\n \t},\n-\t/* class_tid: 6, stingray, table: l2_cntxt_tcam_bypass.ing */\n+\t/* class_tid: 5, stingray, table: l2_cntxt_tcam_bypass.ing */\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l2_ivlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l2_ivlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l2_ovlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l2_ovlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"mac0_addr\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"mac0_addr\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"svif\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"svif\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,\n-\t\t.field_operand = {\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n \t\t\t(BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,\n-\t\t\tBNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t\tBNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"sparif\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"sparif\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl2_ivlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl2_ivlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl2_ovlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl2_ovlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"mac1_addr\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"mac1_addr\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l2_num_vtags\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l2_num_vtags\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl2_num_vtags\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl2_num_vtags\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tun_hdr_type\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tun_hdr_type\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"key_type\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"key_type\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"valid\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"valid\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t1}\n \t\t}\n \t}\n };\n@@ -5029,2372 +4122,2300 @@ struct bnxt_ulp_mapper_field_info ulp_stingray_class_result_field_list[] = {\n \t{\n \t.description = \"l2_cntxt_id\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}\n \t},\n \t{\n \t.description = \"prof_func_id\",\n \t.field_bit_size = 7,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}\n \t},\n \t{\n \t.description = \"l2_byp_lkup_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"parif\",\n \t.field_bit_size = 4,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}\n \t},\n \t{\n \t.description = \"allowed_pri\",\n \t.field_bit_size = 8,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"default_pri\",\n \t.field_bit_size = 3,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"allowed_tpid\",\n \t.field_bit_size = 6,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"default_tpid\",\n \t.field_bit_size = 3,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"bd_act_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"sp_rec_ptr\",\n \t.field_bit_size = 16,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"byp_sp_lkup\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t1}\n \t},\n \t{\n \t.description = \"pri_anti_spoof_ctl\",\n \t.field_bit_size = 2,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tpid_anti_spoof_ctl\",\n \t.field_bit_size = 2,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t/* class_tid: 1, stingray, table: profile_tcam.0 */\n \t{\n \t.description = \"wc_key_id\",\n \t.field_bit_size = 4,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t3}\n \t},\n \t{\n \t.description = \"wc_profile_id\",\n \t.field_bit_size = 8,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"wc_search_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"em_key_mask\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {\n-\t\t(0x007d >> 8) & 0xff,\n-\t\t0x007d & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t(125 >> 8) & 0xff,\n+\t\t125 & 0xff}\n \t},\n \t{\n \t.description = \"em_key_id\",\n \t.field_bit_size = 5,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t3}\n \t},\n \t{\n \t.description = \"em_profile_id\",\n \t.field_bit_size = 8,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}\n \t},\n \t{\n \t.description = \"em_search_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t1}\n \t},\n \t{\n \t.description = \"pl_byp_lkup_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t/* class_tid: 1, stingray, table: profile_tcam_cache.wr */\n \t{\n \t.description = \"rid\",\n \t.field_bit_size = 32,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_RF_IDX_RID >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_RID & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_RF_IDX_RID & 0xff}\n \t},\n \t{\n \t.description = \"profile_tcam_index\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff}\n \t},\n \t{\n \t.description = \"em_profile_id\",\n \t.field_bit_size = 8,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}\n \t},\n \t{\n \t.description = \"wm_profile_id\",\n \t.field_bit_size = 8,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"flow_sig_id\",\n \t.field_bit_size = 8,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t},\n-\t/* class_tid: 1, stingray, table: eem.ext_0 */\n-\t{\n-\t.description = \"act_rec_ptr\",\n-\t.field_bit_size = 33,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n-\t\t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t},\n-\t{\n-\t.description = \"ext_flow_cntr\",\n-\t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {\n-\t\tBNXT_ULP_STINGRAY_SYM_EEM_EXT_FLOW_CNTR,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t},\n-\t{\n-\t.description = \"act_rec_int\",\n-\t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t},\n-\t{\n-\t.description = \"act_rec_size\",\n-\t.field_bit_size = 5,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n-\t\t(BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t},\n-\t{\n-\t.description = \"key_size\",\n-\t.field_bit_size = 9,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {\n-\t\t(0x00ad >> 8) & 0xff,\n-\t\t0x00ad & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t},\n-\t{\n-\t.description = \"reserved\",\n-\t.field_bit_size = 11,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t},\n-\t{\n-\t.description = \"strength\",\n-\t.field_bit_size = 2,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t},\n-\t{\n-\t.description = \"l1_cacheable\",\n-\t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t},\n-\t{\n-\t.description = \"valid\",\n-\t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}\n \t},\n \t/* class_tid: 1, stingray, table: em.int_0 */\n \t{\n \t.description = \"act_rec_ptr\",\n \t.field_bit_size = 33,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n \t},\n \t{\n \t.description = \"ext_flow_cntr\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"act_rec_int\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"act_rec_size\",\n \t.field_bit_size = 5,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"key_size\",\n \t.field_bit_size = 9,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"reserved\",\n \t.field_bit_size = 11,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"strength\",\n \t.field_bit_size = 2,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t3}\n \t},\n \t{\n \t.description = \"l1_cacheable\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"valid\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t},\n-\t/* class_tid: 2, stingray, table: l2_cntxt_tcam.0 */\n-\t{\n-\t.description = \"l2_cntxt_id\",\n-\t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n-\t\t(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t},\n-\t{\n-\t.description = \"prof_func_id\",\n-\t.field_bit_size = 7,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE,\n-\t.field_operand = {\n-\t\t(BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t},\n-\t{\n-\t.description = \"l2_byp_lkup_en\",\n-\t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t},\n-\t{\n-\t.description = \"parif\",\n-\t.field_bit_size = 4,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,\n-\t.field_operand = {\n-\t\t(BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t},\n-\t{\n-\t.description = \"allowed_pri\",\n-\t.field_bit_size = 8,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t},\n-\t{\n-\t.description = \"default_pri\",\n-\t.field_bit_size = 3,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t},\n-\t{\n-\t.description = \"allowed_tpid\",\n-\t.field_bit_size = 6,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t},\n-\t{\n-\t.description = \"default_tpid\",\n-\t.field_bit_size = 3,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t},\n-\t{\n-\t.description = \"bd_act_en\",\n-\t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t},\n-\t{\n-\t.description = \"sp_rec_ptr\",\n-\t.field_bit_size = 16,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t},\n-\t{\n-\t.description = \"byp_sp_lkup\",\n-\t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t},\n-\t{\n-\t.description = \"pri_anti_spoof_ctl\",\n-\t.field_bit_size = 2,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t},\n-\t{\n-\t.description = \"tpid_anti_spoof_ctl\",\n-\t.field_bit_size = 2,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t},\n-\t/* class_tid: 2, stingray, table: profile_tcam.0 */\n-\t{\n-\t.description = \"wc_key_id\",\n-\t.field_bit_size = 4,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t},\n-\t{\n-\t.description = \"wc_profile_id\",\n-\t.field_bit_size = 8,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t},\n-\t{\n-\t.description = \"wc_search_en\",\n-\t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t},\n-\t{\n-\t.description = \"em_key_mask\",\n-\t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {\n-\t\t(0x0079 >> 8) & 0xff,\n-\t\t0x0079 & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t},\n-\t{\n-\t.description = \"em_key_id\",\n-\t.field_bit_size = 5,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t},\n-\t{\n-\t.description = \"em_profile_id\",\n-\t.field_bit_size = 8,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n-\t\t(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t},\n-\t{\n-\t.description = \"em_search_en\",\n-\t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t},\n-\t{\n-\t.description = \"pl_byp_lkup_en\",\n-\t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t},\n-\t/* class_tid: 2, stingray, table: profile_tcam_cache.wr */\n-\t{\n-\t.description = \"rid\",\n-\t.field_bit_size = 32,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n-\t\t(BNXT_ULP_RF_IDX_RID >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_RID & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t},\n-\t{\n-\t.description = \"profile_tcam_index\",\n-\t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n-\t\t(BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t},\n-\t{\n-\t.description = \"em_profile_id\",\n-\t.field_bit_size = 8,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n-\t\t(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t},\n-\t{\n-\t.description = \"wm_profile_id\",\n-\t.field_bit_size = 8,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t},\n-\t{\n-\t.description = \"flow_sig_id\",\n-\t.field_bit_size = 8,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,\n-\t.field_operand = {\n-\t\t(BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t1}\n \t},\n-\t/* class_tid: 2, stingray, table: eem.ext_0 */\n+\t/* class_tid: 1, stingray, table: eem.ext_0 */\n \t{\n \t.description = \"act_rec_ptr\",\n \t.field_bit_size = 33,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n \t},\n \t{\n \t.description = \"ext_flow_cntr\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {\n-\t\tBNXT_ULP_STINGRAY_SYM_EEM_EXT_FLOW_CNTR,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\tULP_SR_SYM_EEM_EXT_FLOW_CNTR}\n \t},\n \t{\n \t.description = \"act_rec_int\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"act_rec_size\",\n \t.field_bit_size = 5,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t},\n-\t{\n-\t.description = \"key_size\",\n-\t.field_bit_size = 9,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {\n-\t\t(0x00ad >> 8) & 0xff,\n-\t\t0x00ad & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t},\n-\t{\n-\t.description = \"reserved\",\n-\t.field_bit_size = 11,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t},\n-\t{\n-\t.description = \"strength\",\n-\t.field_bit_size = 2,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t},\n-\t{\n-\t.description = \"l1_cacheable\",\n-\t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t},\n-\t{\n-\t.description = \"valid\",\n-\t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t},\n-\t/* class_tid: 2, stingray, table: em.int_0 */\n-\t{\n-\t.description = \"act_rec_ptr\",\n-\t.field_bit_size = 33,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n-\t\t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t},\n-\t{\n-\t.description = \"ext_flow_cntr\",\n-\t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t},\n-\t{\n-\t.description = \"act_rec_int\",\n-\t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t},\n-\t{\n-\t.description = \"act_rec_size\",\n-\t.field_bit_size = 5,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\tBNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff}\n \t},\n \t{\n \t.description = \"key_size\",\n \t.field_bit_size = 9,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t(173 >> 8) & 0xff,\n+\t\t173 & 0xff}\n \t},\n \t{\n \t.description = \"reserved\",\n \t.field_bit_size = 11,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"strength\",\n \t.field_bit_size = 2,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t3}\n \t},\n \t{\n \t.description = \"l1_cacheable\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"valid\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t1}\n \t},\n-\t/* class_tid: 3, stingray, table: int_full_act_record.0 */\n+\t/* class_tid: 2, stingray, table: int_full_act_record.0 */\n \t{\n \t.description = \"flow_cntr_ptr\",\n \t.field_bit_size = 14,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"age_enable\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"agg_cntr_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"rate_cntr_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"flow_cntr_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tcpflags_key\",\n \t.field_bit_size = 8,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tcpflags_mir\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tcpflags_match\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"encap_ptr\",\n \t.field_bit_size = 11,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"dst_ip_ptr\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tcp_dst_port\",\n \t.field_bit_size = 16,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"src_ip_ptr\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tcp_src_port\",\n \t.field_bit_size = 16,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"meter_id\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"l3_rdir\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tl3_rdir\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"l3_ttl_dec\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tl3_ttl_dec\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"decap_func\",\n \t.field_bit_size = 4,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"vnic_or_vport\",\n \t.field_bit_size = 12,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_CF_IDX_DRV_FUNC_VNIC >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff}\n \t},\n \t{\n \t.description = \"pop_vlan\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"meter\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"mirror\",\n \t.field_bit_size = 2,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"drop\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"hit\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"type\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 3, stingray, table: l2_cntxt_tcam.0 */\n+\t/* class_tid: 2, stingray, table: l2_cntxt_tcam.0 */\n \t{\n \t.description = \"l2_cntxt_id\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}\n \t},\n \t{\n \t.description = \"prof_func_id\",\n \t.field_bit_size = 7,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}\n \t},\n \t{\n \t.description = \"l2_byp_lkup_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"parif\",\n \t.field_bit_size = 4,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}\n \t},\n \t{\n \t.description = \"allowed_pri\",\n \t.field_bit_size = 8,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"default_pri\",\n \t.field_bit_size = 3,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"allowed_tpid\",\n \t.field_bit_size = 6,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"default_tpid\",\n \t.field_bit_size = 3,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"bd_act_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"sp_rec_ptr\",\n \t.field_bit_size = 16,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"byp_sp_lkup\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t1}\n \t},\n \t{\n \t.description = \"pri_anti_spoof_ctl\",\n \t.field_bit_size = 2,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tpid_anti_spoof_ctl\",\n \t.field_bit_size = 2,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 3, stingray, table: l2_cntxt_tcam_cache.wr */\n+\t/* class_tid: 2, stingray, table: l2_cntxt_tcam_cache.wr */\n \t{\n \t.description = \"rid\",\n \t.field_bit_size = 32,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_RF_IDX_RID >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_RID & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_RF_IDX_RID & 0xff}\n \t},\n \t{\n \t.description = \"l2_cntxt_tcam_index\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff}\n \t},\n \t{\n \t.description = \"l2_cntxt_id\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}\n \t},\n \t{\n \t.description = \"src_property_ptr\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 3, stingray, table: parif_def_lkup_arec_ptr.0 */\n+\t/* class_tid: 2, stingray, table: parif_def_lkup_arec_ptr.0 */\n \t{\n \t.description = \"act_rec_ptr\",\n \t.field_bit_size = 32,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n \t},\n-\t/* class_tid: 3, stingray, table: parif_def_arec_ptr.0 */\n+\t/* class_tid: 2, stingray, table: parif_def_arec_ptr.0 */\n \t{\n \t.description = \"act_rec_ptr\",\n \t.field_bit_size = 32,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n \t},\n-\t/* class_tid: 3, stingray, table: parif_def_err_arec_ptr.0 */\n+\t/* class_tid: 2, stingray, table: parif_def_err_arec_ptr.0 */\n \t{\n \t.description = \"act_rec_ptr\",\n \t.field_bit_size = 32,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n \t},\n-\t/* class_tid: 4, stingray, table: int_full_act_record.0 */\n+\t/* class_tid: 3, stingray, table: int_full_act_record.0 */\n \t{\n \t.description = \"flow_cntr_ptr\",\n \t.field_bit_size = 14,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"age_enable\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"agg_cntr_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"rate_cntr_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"flow_cntr_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tcpflags_key\",\n \t.field_bit_size = 8,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tcpflags_mir\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tcpflags_match\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"encap_ptr\",\n \t.field_bit_size = 11,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"dst_ip_ptr\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tcp_dst_port\",\n \t.field_bit_size = 16,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"src_ip_ptr\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tcp_src_port\",\n \t.field_bit_size = 16,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"meter_id\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"l3_rdir\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tl3_rdir\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"l3_ttl_dec\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tl3_ttl_dec\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"decap_func\",\n \t.field_bit_size = 4,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"vnic_or_vport\",\n \t.field_bit_size = 12,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_CF_IDX_PHY_PORT_VPORT >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_PHY_PORT_VPORT & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_CF_IDX_PHY_PORT_VPORT & 0xff}\n \t},\n \t{\n \t.description = \"pop_vlan\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"meter\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"mirror\",\n \t.field_bit_size = 2,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"drop\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"hit\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"type\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 4, stingray, table: l2_cntxt_tcam_bypass.vfr_0 */\n+\t/* class_tid: 3, stingray, table: l2_cntxt_tcam_bypass.vfr_0 */\n \t{\n \t.description = \"act_record_ptr\",\n \t.field_bit_size = 16,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"reserved\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"l2_byp_lkup_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"parif\",\n \t.field_bit_size = 4,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff}\n \t},\n \t{\n \t.description = \"allowed_pri\",\n \t.field_bit_size = 8,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"default_pri\",\n \t.field_bit_size = 3,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"allowed_tpid\",\n \t.field_bit_size = 6,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"default_tpid\",\n \t.field_bit_size = 3,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"bd_act_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t1}\n \t},\n \t{\n \t.description = \"sp_rec_ptr\",\n \t.field_bit_size = 16,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"byp_sp_lkup\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t1}\n \t},\n \t{\n \t.description = \"pri_anti_spoof_ctl\",\n \t.field_bit_size = 2,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tpid_anti_spoof_ctl\",\n \t.field_bit_size = 2,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 4, stingray, table: l2_cntxt_tcam.0 */\n+\t/* class_tid: 3, stingray, table: l2_cntxt_tcam.0 */\n \t{\n \t.description = \"l2_cntxt_id\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}\n \t},\n \t{\n \t.description = \"prof_func_id\",\n \t.field_bit_size = 7,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}\n \t},\n \t{\n \t.description = \"l2_byp_lkup_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"parif\",\n \t.field_bit_size = 4,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff}\n \t},\n \t{\n \t.description = \"allowed_pri\",\n \t.field_bit_size = 8,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"default_pri\",\n \t.field_bit_size = 3,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"allowed_tpid\",\n \t.field_bit_size = 6,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"default_tpid\",\n \t.field_bit_size = 3,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"bd_act_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"sp_rec_ptr\",\n \t.field_bit_size = 16,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"byp_sp_lkup\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t1}\n \t},\n \t{\n \t.description = \"pri_anti_spoof_ctl\",\n \t.field_bit_size = 2,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tpid_anti_spoof_ctl\",\n \t.field_bit_size = 2,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 4, stingray, table: l2_cntxt_tcam_cache.wr */\n+\t/* class_tid: 3, stingray, table: l2_cntxt_tcam_cache.wr */\n \t{\n \t.description = \"rid\",\n \t.field_bit_size = 32,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_RF_IDX_RID >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_RID & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_RF_IDX_RID & 0xff}\n \t},\n \t{\n \t.description = \"l2_cntxt_tcam_index\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff}\n \t},\n \t{\n \t.description = \"l2_cntxt_id\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}\n \t},\n \t{\n \t.description = \"src_property_ptr\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 4, stingray, table: parif_def_lkup_arec_ptr.0 */\n+\t/* class_tid: 3, stingray, table: parif_def_lkup_arec_ptr.0 */\n \t{\n \t.description = \"act_rec_ptr\",\n \t.field_bit_size = 32,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n \t},\n-\t/* class_tid: 4, stingray, table: parif_def_arec_ptr.0 */\n+\t/* class_tid: 3, stingray, table: parif_def_arec_ptr.0 */\n \t{\n \t.description = \"act_rec_ptr\",\n \t.field_bit_size = 32,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n \t},\n-\t/* class_tid: 4, stingray, table: parif_def_err_arec_ptr.0 */\n+\t/* class_tid: 3, stingray, table: parif_def_err_arec_ptr.0 */\n \t{\n \t.description = \"act_rec_ptr\",\n \t.field_bit_size = 32,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n \t},\n-\t/* class_tid: 5, stingray, table: int_vtag_encap_record.egr0 */\n+\t/* class_tid: 4, stingray, table: int_vtag_encap_record.egr0 */\n \t{\n \t.description = \"ecv_tun_type\",\n \t.field_bit_size = 3,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"ecv_l4_type\",\n \t.field_bit_size = 3,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"ecv_l3_type\",\n \t.field_bit_size = 3,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"ecv_l2_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"ecv_vtag_type\",\n \t.field_bit_size = 4,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {\n-\t\tBNXT_ULP_STINGRAY_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\tULP_SR_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI}\n \t},\n \t{\n \t.description = \"ecv_custom_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"ecv_valid\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t1}\n \t},\n \t{\n \t.description = \"vtag_tpid\",\n \t.field_bit_size = 16,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {0x81, 0x00}\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t0x81,\n+\t\t0x00}\n \t},\n \t{\n \t.description = \"vtag_vid\",\n \t.field_bit_size = 12,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}\n \t},\n \t{\n \t.description = \"vtag_de\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"vtag_pcp\",\n \t.field_bit_size = 3,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"spare\",\n \t.field_bit_size = 80,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 5, stingray, table: int_full_act_record.egr0 */\n+\t/* class_tid: 4, stingray, table: int_full_act_record.egr0 */\n \t{\n \t.description = \"flow_cntr_ptr\",\n \t.field_bit_size = 14,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"age_enable\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"agg_cntr_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"rate_cntr_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"flow_cntr_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tcpflags_key\",\n \t.field_bit_size = 8,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tcpflags_mir\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tcpflags_match\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"encap_ptr\",\n \t.field_bit_size = 11,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff}\n \t},\n \t{\n \t.description = \"dst_ip_ptr\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tcp_dst_port\",\n \t.field_bit_size = 16,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"src_ip_ptr\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tcp_src_port\",\n \t.field_bit_size = 16,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"meter_id\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"l3_rdir\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tl3_rdir\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"l3_ttl_dec\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tl3_ttl_dec\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"decap_func\",\n \t.field_bit_size = 4,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"vnic_or_vport\",\n \t.field_bit_size = 12,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {\n-\t\t(BNXT_ULP_STINGRAY_SYM_LOOPBACK_PORT >> 8) & 0xff,\n-\t\tBNXT_ULP_STINGRAY_SYM_LOOPBACK_PORT & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t(ULP_SR_SYM_LOOPBACK_PORT >> 8) & 0xff,\n+\t\tULP_SR_SYM_LOOPBACK_PORT & 0xff}\n \t},\n \t{\n \t.description = \"pop_vlan\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"meter\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"mirror\",\n \t.field_bit_size = 2,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"drop\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"hit\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"type\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 5, stingray, table: l2_cntxt_tcam_bypass.egr0 */\n+\t/* class_tid: 4, stingray, table: l2_cntxt_tcam_bypass.egr0 */\n \t{\n \t.description = \"act_record_ptr\",\n \t.field_bit_size = 16,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"reserved\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"l2_byp_lkup_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"parif\",\n \t.field_bit_size = 4,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"allowed_pri\",\n \t.field_bit_size = 8,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"default_pri\",\n \t.field_bit_size = 3,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"allowed_tpid\",\n \t.field_bit_size = 6,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"default_tpid\",\n \t.field_bit_size = 3,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"bd_act_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t1}\n \t},\n \t{\n \t.description = \"sp_rec_ptr\",\n \t.field_bit_size = 16,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"byp_sp_lkup\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t1}\n \t},\n \t{\n \t.description = \"pri_anti_spoof_ctl\",\n \t.field_bit_size = 2,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tpid_anti_spoof_ctl\",\n \t.field_bit_size = 2,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 5, stingray, table: l2_cntxt_tcam_cache.wr_egr0 */\n+\t/* class_tid: 4, stingray, table: l2_cntxt_tcam_cache.wr_egr0 */\n \t{\n \t.description = \"rid\",\n \t.field_bit_size = 32,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_RF_IDX_RID >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_RID & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_RF_IDX_RID & 0xff}\n \t},\n \t{\n \t.description = \"l2_cntxt_tcam_index\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff}\n \t},\n \t{\n \t.description = \"l2_cntxt_id\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"src_property_ptr\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 5, stingray, table: int_full_act_record.ing0 */\n+\t/* class_tid: 4, stingray, table: int_full_act_record.ing0 */\n \t{\n \t.description = \"flow_cntr_ptr\",\n \t.field_bit_size = 14,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"age_enable\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"agg_cntr_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"rate_cntr_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"flow_cntr_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tcpflags_key\",\n \t.field_bit_size = 8,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tcpflags_mir\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tcpflags_match\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"encap_ptr\",\n \t.field_bit_size = 11,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"dst_ip_ptr\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tcp_dst_port\",\n \t.field_bit_size = 16,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"src_ip_ptr\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tcp_src_port\",\n \t.field_bit_size = 16,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"meter_id\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"l3_rdir\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tl3_rdir\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"l3_ttl_dec\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tl3_ttl_dec\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"decap_func\",\n \t.field_bit_size = 4,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"vnic_or_vport\",\n \t.field_bit_size = 12,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_CF_IDX_VF_FUNC_VNIC >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_VF_FUNC_VNIC & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_CF_IDX_VF_FUNC_VNIC & 0xff}\n \t},\n \t{\n \t.description = \"pop_vlan\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t1}\n \t},\n \t{\n \t.description = \"meter\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"mirror\",\n \t.field_bit_size = 2,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"drop\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"hit\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"type\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 5, stingray, table: l2_cntxt_tcam_bypass.dtagged_ing0 */\n+\t/* class_tid: 4, stingray, table: l2_cntxt_tcam_bypass.dtagged_ing0 */\n \t{\n \t.description = \"act_record_ptr\",\n \t.field_bit_size = 16,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n \t},\n \t{\n \t.description = \"reserved\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"l2_byp_lkup_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"parif\",\n \t.field_bit_size = 4,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"allowed_pri\",\n \t.field_bit_size = 8,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"default_pri\",\n \t.field_bit_size = 3,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"allowed_tpid\",\n \t.field_bit_size = 6,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"default_tpid\",\n \t.field_bit_size = 3,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"bd_act_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"sp_rec_ptr\",\n \t.field_bit_size = 16,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"byp_sp_lkup\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t1}\n \t},\n \t{\n \t.description = \"pri_anti_spoof_ctl\",\n \t.field_bit_size = 2,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tpid_anti_spoof_ctl\",\n \t.field_bit_size = 2,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 5, stingray, table: l2_cntxt_tcam_bypass.stagged_ing0 */\n+\t/* class_tid: 4, stingray, table: l2_cntxt_tcam_bypass.stagged_ing0 */\n \t{\n \t.description = \"act_record_ptr\",\n \t.field_bit_size = 16,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n \t},\n \t{\n \t.description = \"reserved\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"l2_byp_lkup_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"parif\",\n \t.field_bit_size = 4,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"allowed_pri\",\n \t.field_bit_size = 8,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"default_pri\",\n \t.field_bit_size = 3,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"allowed_tpid\",\n \t.field_bit_size = 6,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"default_tpid\",\n \t.field_bit_size = 3,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"bd_act_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"sp_rec_ptr\",\n \t.field_bit_size = 16,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"byp_sp_lkup\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t1}\n \t},\n \t{\n \t.description = \"pri_anti_spoof_ctl\",\n \t.field_bit_size = 2,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tpid_anti_spoof_ctl\",\n \t.field_bit_size = 2,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 6, stingray, table: l2_cntxt_tcam.egr */\n+\t/* class_tid: 5, stingray, table: l2_cntxt_tcam.egr */\n \t{\n \t.description = \"l2_cntxt_id\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}\n \t},\n \t{\n \t.description = \"prof_func_id\",\n \t.field_bit_size = 7,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}\n \t},\n \t{\n \t.description = \"l2_byp_lkup_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"parif\",\n \t.field_bit_size = 4,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_CF_IDX_VF_FUNC_PARIF >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_VF_FUNC_PARIF & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_CF_IDX_VF_FUNC_PARIF & 0xff}\n \t},\n \t{\n \t.description = \"allowed_pri\",\n \t.field_bit_size = 8,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"default_pri\",\n \t.field_bit_size = 3,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"allowed_tpid\",\n \t.field_bit_size = 6,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"default_tpid\",\n \t.field_bit_size = 3,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"bd_act_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"sp_rec_ptr\",\n \t.field_bit_size = 16,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"byp_sp_lkup\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t1}\n \t},\n \t{\n \t.description = \"pri_anti_spoof_ctl\",\n \t.field_bit_size = 2,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tpid_anti_spoof_ctl\",\n \t.field_bit_size = 2,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 6, stingray, table: l2_cntxt_tcam_cache.egr_wr */\n+\t/* class_tid: 5, stingray, table: l2_cntxt_tcam_cache.egr_wr */\n \t{\n \t.description = \"rid\",\n \t.field_bit_size = 32,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_RF_IDX_RID >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_RID & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_RF_IDX_RID & 0xff}\n \t},\n \t{\n \t.description = \"l2_cntxt_tcam_index\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff}\n \t},\n \t{\n \t.description = \"l2_cntxt_id\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}\n \t},\n \t{\n \t.description = \"src_property_ptr\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 6, stingray, table: parif_def_lkup_arec_ptr.egr */\n+\t/* class_tid: 5, stingray, table: parif_def_lkup_arec_ptr.egr */\n \t{\n \t.description = \"act_rec_ptr\",\n \t.field_bit_size = 32,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}\n \t},\n-\t/* class_tid: 6, stingray, table: parif_def_arec_ptr.egr */\n+\t/* class_tid: 5, stingray, table: parif_def_arec_ptr.egr */\n \t{\n \t.description = \"act_rec_ptr\",\n \t.field_bit_size = 32,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}\n \t},\n-\t/* class_tid: 6, stingray, table: parif_def_err_arec_ptr.egr */\n+\t/* class_tid: 5, stingray, table: parif_def_err_arec_ptr.egr */\n \t{\n \t.description = \"act_rec_ptr\",\n \t.field_bit_size = 32,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}\n \t},\n-\t/* class_tid: 6, stingray, table: int_full_act_record.ing */\n+\t/* class_tid: 5, stingray, table: int_full_act_record.ing */\n \t{\n \t.description = \"flow_cntr_ptr\",\n \t.field_bit_size = 14,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"age_enable\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"agg_cntr_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"rate_cntr_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"flow_cntr_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tcpflags_key\",\n \t.field_bit_size = 8,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tcpflags_mir\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tcpflags_match\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"encap_ptr\",\n \t.field_bit_size = 11,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"dst_ip_ptr\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tcp_dst_port\",\n \t.field_bit_size = 16,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"src_ip_ptr\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tcp_src_port\",\n \t.field_bit_size = 16,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"meter_id\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"l3_rdir\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tl3_rdir\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"l3_ttl_dec\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tl3_ttl_dec\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"decap_func\",\n \t.field_bit_size = 4,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"vnic_or_vport\",\n \t.field_bit_size = 12,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_CF_IDX_DRV_FUNC_VNIC >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff}\n \t},\n \t{\n \t.description = \"pop_vlan\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"meter\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"mirror\",\n \t.field_bit_size = 2,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"drop\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"hit\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"type\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 6, stingray, table: l2_cntxt_tcam_bypass.ing */\n+\t/* class_tid: 5, stingray, table: l2_cntxt_tcam_bypass.ing */\n \t{\n \t.description = \"act_record_ptr\",\n \t.field_bit_size = 16,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n \t},\n \t{\n \t.description = \"reserved\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"l2_byp_lkup_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"parif\",\n \t.field_bit_size = 4,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"allowed_pri\",\n \t.field_bit_size = 8,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"default_pri\",\n \t.field_bit_size = 3,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"allowed_tpid\",\n \t.field_bit_size = 6,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"default_tpid\",\n \t.field_bit_size = 3,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"bd_act_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"sp_rec_ptr\",\n \t.field_bit_size = 16,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"byp_sp_lkup\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t1}\n \t},\n \t{\n \t.description = \"pri_anti_spoof_ctl\",\n \t.field_bit_size = 2,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tpid_anti_spoof_ctl\",\n \t.field_bit_size = 2,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 7, stingray, table: int_full_act_record.0 */\n+\t/* class_tid: 6, stingray, table: int_full_act_record.0 */\n \t{\n \t.description = \"flow_cntr_ptr\",\n \t.field_bit_size = 14,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"age_enable\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"agg_cntr_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"rate_cntr_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"flow_cntr_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tcpflags_key\",\n \t.field_bit_size = 8,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tcpflags_mir\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tcpflags_match\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"encap_ptr\",\n \t.field_bit_size = 11,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"dst_ip_ptr\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tcp_dst_port\",\n \t.field_bit_size = 16,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"src_ip_ptr\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tcp_src_port\",\n \t.field_bit_size = 16,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"meter_id\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"l3_rdir\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tl3_rdir\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"l3_ttl_dec\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tl3_ttl_dec\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"decap_func\",\n \t.field_bit_size = 4,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"vnic_or_vport\",\n \t.field_bit_size = 12,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {\n-\t\t(BNXT_ULP_STINGRAY_SYM_LOOPBACK_PORT >> 8) & 0xff,\n-\t\tBNXT_ULP_STINGRAY_SYM_LOOPBACK_PORT & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t(ULP_SR_SYM_LOOPBACK_PORT >> 8) & 0xff,\n+\t\tULP_SR_SYM_LOOPBACK_PORT & 0xff}\n \t},\n \t{\n \t.description = \"pop_vlan\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"meter\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"mirror\",\n \t.field_bit_size = 2,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"drop\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"hit\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"type\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t}\n };\n \n struct bnxt_ulp_mapper_ident_info ulp_stingray_class_ident_list[] = {\n+\t/* class_tid: 1, stingray, table: l2_cntxt_tcam_cache.rd */\n+\t{\n+\t.description = \"l2_cntxt_id\",\n+\t.regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,\n+\t.ident_bit_size = 10,\n+\t.ident_bit_pos = 42\n+\t},\n \t/* class_tid: 1, stingray, table: l2_cntxt_tcam.0 */\n \t{\n \t.description = \"l2_cntxt_id\",\n@@ -7406,12 +6427,6 @@ struct bnxt_ulp_mapper_ident_info ulp_stingray_class_ident_list[] = {\n \t},\n \t/* class_tid: 1, stingray, table: profile_tcam_cache.rd */\n \t{\n-\t.description = \"flow_sig_id\",\n-\t.regfile_idx = BNXT_ULP_RF_IDX_FLOW_SIG_ID,\n-\t.ident_bit_size = 8,\n-\t.ident_bit_pos = 58\n-\t},\n-\t{\n \t.description = \"profile_tcam_index\",\n \t.regfile_idx = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,\n \t.ident_bit_size = 10,\n@@ -7423,44 +6438,13 @@ struct bnxt_ulp_mapper_ident_info ulp_stingray_class_ident_list[] = {\n \t.ident_bit_size = 8,\n \t.ident_bit_pos = 42\n \t},\n-\t/* class_tid: 1, stingray, table: profile_tcam.0 */\n-\t{\n-\t.description = \"em_profile_id\",\n-\t.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n-\t.ident_type = TF_IDENT_TYPE_EM_PROF,\n-\t.regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0,\n-\t.ident_bit_size = 8,\n-\t.ident_bit_pos = 28\n-\t},\n-\t/* class_tid: 2, stingray, table: l2_cntxt_tcam.0 */\n-\t{\n-\t.description = \"l2_cntxt_id\",\n-\t.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n-\t.ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH,\n-\t.regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,\n-\t.ident_bit_size = 10,\n-\t.ident_bit_pos = 0\n-\t},\n-\t/* class_tid: 2, stingray, table: profile_tcam_cache.rd */\n-\t{\n-\t.description = \"profile_tcam_index\",\n-\t.regfile_idx = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,\n-\t.ident_bit_size = 10,\n-\t.ident_bit_pos = 32\n-\t},\n \t{\n \t.description = \"flow_sig_id\",\n \t.regfile_idx = BNXT_ULP_RF_IDX_FLOW_SIG_ID,\n \t.ident_bit_size = 8,\n \t.ident_bit_pos = 58\n \t},\n-\t{\n-\t.description = \"em_profile_id\",\n-\t.regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0,\n-\t.ident_bit_size = 8,\n-\t.ident_bit_pos = 42\n-\t},\n-\t/* class_tid: 2, stingray, table: profile_tcam.0 */\n+\t/* class_tid: 1, stingray, table: profile_tcam.0 */\n \t{\n \t.description = \"em_profile_id\",\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n@@ -7469,7 +6453,7 @@ struct bnxt_ulp_mapper_ident_info ulp_stingray_class_ident_list[] = {\n \t.ident_bit_size = 8,\n \t.ident_bit_pos = 28\n \t},\n-\t/* class_tid: 3, stingray, table: l2_cntxt_tcam.0 */\n+\t/* class_tid: 2, stingray, table: l2_cntxt_tcam.0 */\n \t{\n \t.description = \"l2_cntxt_id\",\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n@@ -7478,14 +6462,14 @@ struct bnxt_ulp_mapper_ident_info ulp_stingray_class_ident_list[] = {\n \t.ident_bit_size = 10,\n \t.ident_bit_pos = 0\n \t},\n-\t/* class_tid: 4, stingray, table: l2_cntxt_tcam_cache.rd */\n+\t/* class_tid: 3, stingray, table: l2_cntxt_tcam_cache.rd */\n \t{\n \t.description = \"l2_cntxt_id\",\n \t.regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,\n \t.ident_bit_size = 10,\n \t.ident_bit_pos = 42\n \t},\n-\t/* class_tid: 4, stingray, table: l2_cntxt_tcam.0 */\n+\t/* class_tid: 3, stingray, table: l2_cntxt_tcam.0 */\n \t{\n \t.description = \"l2_cntxt_id\",\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n@@ -7494,7 +6478,7 @@ struct bnxt_ulp_mapper_ident_info ulp_stingray_class_ident_list[] = {\n \t.ident_bit_size = 10,\n \t.ident_bit_pos = 0\n \t},\n-\t/* class_tid: 6, stingray, table: l2_cntxt_tcam.egr */\n+\t/* class_tid: 5, stingray, table: l2_cntxt_tcam.egr */\n \t{\n \t.description = \"l2_cntxt_id\",\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\ndiff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c\nindex 30a71def95..ff003b2ebd 100644\n--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c\n+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c\n@@ -3,7 +3,7 @@\n  * All rights reserved.\n  */\n \n-/* date: Mon Nov 23 17:33:02 2020 */\n+/* date: Tue Dec  1 10:17:11 2020 */\n \n #include \"ulp_template_db_enum.h\"\n #include \"ulp_template_db_field.h\"\n@@ -209,11 +209,11 @@ uint32_t ulp_glb_template_tbl[] = {\n struct bnxt_ulp_shared_act_info ulp_shared_act_info[] = {\n \t[BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MIRROR_TBL << 1 |\n \t\tBNXT_ULP_DIRECTION_INGRESS] = {\n-\t.act_bitmask             = BNXT_ULP_ACTION_BIT_SHARED_SAMPLE\n+\t.act_bitmask             = BNXT_ULP_ACT_BIT_SHARED_SAMPLE\n \t},\n \t[BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_MIRROR_TBL << 1 |\n \t\tBNXT_ULP_DIRECTION_EGRESS] = {\n-\t.act_bitmask             = BNXT_ULP_ACTION_BIT_SHARED_SAMPLE\n+\t.act_bitmask             = BNXT_ULP_ACT_BIT_SHARED_SAMPLE\n \t}\n };\n \n@@ -312,78 +312,176 @@ uint8_t ulp_glb_field_tbl[] = {\n \t[2050] = 2,\n \t[2052] = 3,\n \t[2054] = 4,\n-\t[2056] = 5,\n-\t[2058] = 6,\n-\t[2060] = 7,\n-\t[2062] = 8,\n-\t[2064] = 9,\n-\t[2066] = 10,\n-\t[2068] = 11,\n-\t[2070] = 12,\n-\t[2072] = 13,\n-\t[2074] = 14,\n-\t[2102] = 15,\n-\t[2104] = 16,\n-\t[2106] = 17,\n-\t[2108] = 18,\n-\t[2110] = 19,\n-\t[2112] = 20,\n-\t[2114] = 21,\n-\t[2116] = 22,\n-\t[2118] = 23,\n+\t[2076] = 5,\n+\t[2078] = 6,\n+\t[2080] = 7,\n+\t[2082] = 8,\n+\t[2084] = 9,\n+\t[2086] = 10,\n+\t[2088] = 11,\n+\t[2090] = 12,\n+\t[2102] = 13,\n+\t[2104] = 14,\n+\t[2106] = 15,\n+\t[2108] = 16,\n+\t[2110] = 17,\n+\t[2112] = 18,\n+\t[2114] = 19,\n+\t[2116] = 20,\n+\t[2118] = 21,\n \t[2176] = 0,\n \t[2177] = 1,\n \t[2178] = 2,\n \t[2180] = 3,\n \t[2182] = 4,\n-\t[2184] = 8,\n-\t[2186] = 9,\n-\t[2188] = 10,\n-\t[2190] = 11,\n-\t[2192] = 12,\n-\t[2194] = 13,\n-\t[2196] = 14,\n-\t[2198] = 15,\n-\t[2200] = 16,\n-\t[2202] = 17,\n-\t[2230] = 18,\n-\t[2232] = 19,\n-\t[2234] = 20,\n-\t[2236] = 21,\n-\t[2238] = 22,\n-\t[2240] = 23,\n-\t[2242] = 24,\n-\t[2244] = 25,\n-\t[2246] = 26,\n+\t[2204] = 8,\n+\t[2206] = 9,\n+\t[2208] = 10,\n+\t[2210] = 11,\n+\t[2212] = 12,\n+\t[2214] = 13,\n+\t[2216] = 14,\n+\t[2218] = 15,\n+\t[2230] = 16,\n+\t[2232] = 17,\n+\t[2234] = 18,\n+\t[2236] = 19,\n+\t[2238] = 20,\n+\t[2240] = 21,\n+\t[2242] = 22,\n+\t[2244] = 23,\n+\t[2246] = 24,\n \t[2256] = 5,\n \t[2260] = 6,\n \t[2264] = 7,\n-\t[4352] = 0,\n-\t[4353] = 1,\n-\t[4354] = 2,\n-\t[4356] = 3,\n-\t[4358] = 4,\n-\t[4360] = 8,\n-\t[4362] = 9,\n-\t[4364] = 10,\n-\t[4366] = 11,\n-\t[4368] = 12,\n-\t[4370] = 13,\n-\t[4372] = 14,\n-\t[4374] = 15,\n-\t[4376] = 16,\n-\t[4378] = 17,\n-\t[4406] = 18,\n-\t[4408] = 19,\n-\t[4410] = 20,\n-\t[4412] = 21,\n-\t[4414] = 22,\n-\t[4416] = 23,\n-\t[4418] = 24,\n-\t[4420] = 25,\n-\t[4422] = 26,\n-\t[4432] = 5,\n-\t[4436] = 6,\n-\t[4440] = 7\n+\t[2304] = 0,\n+\t[2305] = 1,\n+\t[2306] = 2,\n+\t[2308] = 3,\n+\t[2310] = 4,\n+\t[2312] = 5,\n+\t[2314] = 6,\n+\t[2316] = 7,\n+\t[2318] = 8,\n+\t[2320] = 9,\n+\t[2322] = 10,\n+\t[2324] = 11,\n+\t[2326] = 12,\n+\t[2328] = 13,\n+\t[2330] = 14,\n+\t[2358] = 15,\n+\t[2360] = 16,\n+\t[2362] = 17,\n+\t[2364] = 18,\n+\t[2366] = 19,\n+\t[2368] = 20,\n+\t[2370] = 21,\n+\t[2372] = 22,\n+\t[2374] = 23,\n+\t[2432] = 0,\n+\t[2433] = 1,\n+\t[2434] = 2,\n+\t[2436] = 3,\n+\t[2438] = 4,\n+\t[2460] = 5,\n+\t[2462] = 6,\n+\t[2464] = 7,\n+\t[2466] = 8,\n+\t[2468] = 9,\n+\t[2470] = 10,\n+\t[2472] = 11,\n+\t[2474] = 12,\n+\t[2504] = 13,\n+\t[2506] = 14,\n+\t[2508] = 15,\n+\t[2510] = 16,\n+\t[2560] = 0,\n+\t[2561] = 1,\n+\t[2562] = 2,\n+\t[2564] = 3,\n+\t[2566] = 4,\n+\t[2568] = 8,\n+\t[2570] = 9,\n+\t[2572] = 10,\n+\t[2574] = 11,\n+\t[2576] = 12,\n+\t[2578] = 13,\n+\t[2580] = 14,\n+\t[2582] = 15,\n+\t[2584] = 16,\n+\t[2586] = 17,\n+\t[2614] = 18,\n+\t[2616] = 19,\n+\t[2618] = 20,\n+\t[2620] = 21,\n+\t[2622] = 22,\n+\t[2624] = 23,\n+\t[2626] = 24,\n+\t[2628] = 25,\n+\t[2630] = 26,\n+\t[2640] = 5,\n+\t[2644] = 6,\n+\t[2648] = 7,\n+\t[2688] = 0,\n+\t[2689] = 1,\n+\t[2690] = 2,\n+\t[2692] = 3,\n+\t[2694] = 4,\n+\t[2716] = 8,\n+\t[2718] = 9,\n+\t[2720] = 10,\n+\t[2722] = 11,\n+\t[2724] = 12,\n+\t[2726] = 13,\n+\t[2728] = 14,\n+\t[2730] = 15,\n+\t[2760] = 16,\n+\t[2762] = 17,\n+\t[2764] = 18,\n+\t[2766] = 19,\n+\t[2768] = 5,\n+\t[2772] = 6,\n+\t[2776] = 7,\n+\t[2816] = 0,\n+\t[2817] = 1,\n+\t[2818] = 2,\n+\t[2820] = 3,\n+\t[2822] = 4,\n+\t[2824] = 5,\n+\t[2826] = 6,\n+\t[2828] = 7,\n+\t[2830] = 8,\n+\t[2832] = 9,\n+\t[2834] = 10,\n+\t[2836] = 11,\n+\t[2838] = 12,\n+\t[2840] = 13,\n+\t[2842] = 14,\n+\t[2888] = 15,\n+\t[2890] = 16,\n+\t[2892] = 17,\n+\t[2894] = 18,\n+\t[2944] = 0,\n+\t[2945] = 1,\n+\t[2946] = 2,\n+\t[2948] = 3,\n+\t[2950] = 4,\n+\t[2952] = 8,\n+\t[2954] = 9,\n+\t[2956] = 10,\n+\t[2958] = 11,\n+\t[2960] = 12,\n+\t[2962] = 13,\n+\t[2964] = 14,\n+\t[2966] = 15,\n+\t[2968] = 16,\n+\t[2970] = 17,\n+\t[3016] = 18,\n+\t[3018] = 19,\n+\t[3020] = 20,\n+\t[3022] = 21,\n+\t[3024] = 5,\n+\t[3028] = 6,\n+\t[3032] = 7\n };\n \ndiff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c\nindex 69cc7f33f9..5b098cff37 100644\n--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c\n+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c\n@@ -3,7 +3,7 @@\n  * All rights reserved.\n  */\n \n-/* date: Wed Nov 18 12:19:40 2020 */\n+/* date: Tue Dec  1 17:07:12 2020 */\n \n #include \"ulp_template_db_enum.h\"\n #include \"ulp_template_db_field.h\"\n@@ -32,6 +32,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {\n \t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT,\n \t.direction = TF_DIR_RX,\n \t.execute_info = {\n+\t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n \t\t.cond_start_idx = 0,\n \t\t.cond_nums = 1 },\n@@ -53,6 +54,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {\n \t.direction = TF_DIR_RX,\n \t.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT,\n \t.execute_info = {\n+\t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n \t\t.cond_start_idx = 1,\n \t\t.cond_nums = 1 },\n@@ -74,6 +76,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {\n \t.direction = TF_DIR_RX,\n \t.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT,\n \t.execute_info = {\n+\t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 2,\n \t\t.cond_nums = 0 },\n@@ -95,6 +98,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {\n \t.direction = TF_DIR_RX,\n \t.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT,\n \t.execute_info = {\n+\t\t.cond_goto = 0,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 2,\n \t\t.cond_nums = 0 },\n@@ -112,12 +116,12 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {\n \n struct bnxt_ulp_mapper_cond_info ulp_wh_plus_act_cond_list[] = {\n \t{\n-\t.cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET,\n-\t.cond_operand = BNXT_ULP_ACTION_BIT_COUNT\n+\t.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,\n+\t.cond_operand = BNXT_ULP_ACT_BIT_COUNT\n \t},\n \t{\n-\t.cond_opcode = BNXT_ULP_COND_OPC_ACTION_BIT_IS_SET,\n-\t.cond_operand = BNXT_ULP_ACTION_BIT_PUSH_VLAN\n+\t.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,\n+\t.cond_operand = BNXT_ULP_ACT_BIT_PUSH_VLAN\n \t}\n };\n \n@@ -126,557 +130,578 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_act_result_field_list[] = {\n \t{\n \t.description = \"count\",\n \t.field_bit_size = 64,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t/* act_tid: 1, wh_plus, table: int_vtag_encap_record.0 */\n \t{\n \t.description = \"ecv_tun_type\",\n \t.field_bit_size = 3,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"ecv_l4_type\",\n \t.field_bit_size = 3,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"ecv_l3_type\",\n \t.field_bit_size = 3,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"ecv_l2_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"ecv_vtag_type\",\n \t.field_bit_size = 4,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {\n-\t\tBNXT_ULP_WH_PLUS_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\tULP_WP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI}\n \t},\n \t{\n \t.description = \"ecv_custom_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"ecv_valid\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"vtag_tpid\",\n \t.field_bit_size = 16,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_PROP,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN >> 8) & 0xff,\n-\t\tBNXT_ULP_ACT_PROP_IDX_PUSH_VLAN & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_ACT_PROP_IDX_PUSH_VLAN & 0xff}\n \t},\n \t{\n \t.description = \"vtag_vid\",\n \t.field_bit_size = 12,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_PROP,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID >> 8) & 0xff,\n-\t\tBNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID & 0xff}\n \t},\n \t{\n \t.description = \"vtag_de\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"vtag_pcp\",\n \t.field_bit_size = 3,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_PROP,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff,\n-\t\tBNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff}\n \t},\n \t{\n \t.description = \"spare\",\n \t.field_bit_size = 80,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t/* act_tid: 1, wh_plus, table: int_full_act_record.0 */\n \t{\n \t.description = \"flow_cntr_ptr\",\n \t.field_bit_size = 14,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}\n \t},\n \t{\n \t.description = \"age_enable\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"agg_cntr_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"rate_cntr_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"flow_cntr_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_BIT,\n-\t.field_operand = {\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 56) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 48) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 40) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 32) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 24) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 16) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 8) & 0xff,\n-\t\t(uint64_t)BNXT_ULP_ACTION_BIT_COUNT & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,\n+\t.field_opr1 = {\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff,\n+\t\t(uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff}\n \t},\n \t{\n \t.description = \"tcpflags_key\",\n \t.field_bit_size = 8,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tcpflags_mir\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tcpflags_match\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"encap_ptr\",\n \t.field_bit_size = 11,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff}\n \t},\n \t{\n \t.description = \"dst_ip_ptr\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 & 0xff}\n \t},\n \t{\n \t.description = \"tcp_dst_port\",\n \t.field_bit_size = 16,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST,\n-\t.field_operand = {\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 56) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 48) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 40) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 32) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 24) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 16) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 8) & 0xff,\n-\t\t(uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},\n-\t.field_operand_true = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT,\n+\t.field_cond_opr = {\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff,\n+\t\t(uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff},\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff,\n-\t\tBNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff},\n+\t.field_src2 = BNXT_ULP_FIELD_SRC_CONST\n \t},\n \t{\n \t.description = \"src_ip_ptr\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 & 0xff}\n \t},\n \t{\n \t.description = \"tcp_src_port\",\n \t.field_bit_size = 16,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST,\n-\t.field_operand = {\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 56) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 48) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 40) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 32) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 24) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 16) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 8) & 0xff,\n-\t\t(uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},\n-\t.field_operand_true = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT,\n+\t.field_cond_opr = {\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff,\n+\t\t(uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff},\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff,\n-\t\tBNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff},\n+\t.field_src2 = BNXT_ULP_FIELD_SRC_CONST\n \t},\n \t{\n \t.description = \"meter_id\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"l3_rdir\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tl3_rdir\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"l3_ttl_dec\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff}\n \t},\n \t{\n \t.description = \"tl3_ttl_dec\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff}\n \t},\n \t{\n \t.description = \"decap_func\",\n \t.field_bit_size = 4,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_IF_ACT_BIT_THEN_CONST_ELSE_CONST,\n-\t.field_operand = {\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 56) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 48) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 40) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 32) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 24) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 16) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 8) & 0xff,\n-\t\t(uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},\n-\t.field_operand_true = {0x0a, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT,\n+\t.field_cond_opr = {\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 56) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 48) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 40) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 32) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 24) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 16) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 8) & 0xff,\n+\t\t(uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP & 0xff},\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\tULP_WP_SYM_DECAP_FUNC_THRU_TUN},\n+\t.field_src2 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr2 = {\n+\t\tULP_WP_SYM_DECAP_FUNC_NONE}\n \t},\n \t{\n \t.description = \"vnic_or_vport\",\n \t.field_bit_size = 12,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_PROP,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,\n-\t\tBNXT_ULP_ACT_PROP_IDX_VNIC & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_ACT_PROP_IDX_VNIC & 0xff}\n \t},\n \t{\n \t.description = \"pop_vlan\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_BIT,\n-\t.field_operand = {\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 56) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 48) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 40) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 32) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 24) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 16) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 8) & 0xff,\n-\t\t(uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,\n+\t.field_opr1 = {\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 56) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 48) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 40) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 32) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 24) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 16) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 8) & 0xff,\n+\t\t(uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN & 0xff}\n \t},\n \t{\n \t.description = \"meter\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"mirror\",\n \t.field_bit_size = 2,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"drop\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_BIT,\n-\t.field_operand = {\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 56) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 48) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 40) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 32) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 24) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 16) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 8) & 0xff,\n-\t\t(uint64_t)BNXT_ULP_ACTION_BIT_DROP & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,\n+\t.field_opr1 = {\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff,\n+\t\t(uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff}\n \t},\n \t{\n \t.description = \"hit\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"type\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t/* act_tid: 1, wh_plus, table: ext_full_act_record.0 */\n \t{\n \t.description = \"flow_cntr_ptr\",\n \t.field_bit_size = 14,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}\n \t},\n \t{\n \t.description = \"age_enable\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"agg_cntr_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"rate_cntr_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"flow_cntr_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_BIT,\n-\t.field_operand = {\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 56) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 48) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 40) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 32) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 24) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 16) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 8) & 0xff,\n-\t\t(uint64_t)BNXT_ULP_ACTION_BIT_COUNT & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,\n+\t.field_opr1 = {\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff,\n+\t\t(uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff}\n \t},\n \t{\n \t.description = \"flow_cntr_ext\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tcpflags_key\",\n \t.field_bit_size = 8,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tcpflags_mir\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tcpflags_match\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"encap_ptr\",\n \t.field_bit_size = 11,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"encap_rec_int\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"dst_ip_ptr\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 & 0xff}\n \t},\n \t{\n \t.description = \"tcp_dst_port\",\n \t.field_bit_size = 16,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST,\n-\t.field_operand = {\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 56) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 48) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 40) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 32) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 24) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 16) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST >> 8) & 0xff,\n-\t\t(uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_DST & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},\n-\t.field_operand_true = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT,\n+\t.field_cond_opr = {\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff,\n+\t\t(uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff},\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff,\n-\t\tBNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff},\n+\t.field_src2 = BNXT_ULP_FIELD_SRC_CONST\n \t},\n \t{\n \t.description = \"src_ip_ptr\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 & 0xff}\n \t},\n \t{\n \t.description = \"tcp_src_port\",\n \t.field_bit_size = 16,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_IF_ACT_BIT_THEN_ACT_PROP_ELSE_CONST,\n-\t.field_operand = {\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 56) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 48) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 40) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 32) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 24) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 16) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC >> 8) & 0xff,\n-\t\t(uint64_t)BNXT_ULP_ACTION_BIT_SET_TP_SRC & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},\n-\t.field_operand_true = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT,\n+\t.field_cond_opr = {\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff,\n+\t\t(uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff},\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff,\n-\t\tBNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff},\n+\t.field_src2 = BNXT_ULP_FIELD_SRC_CONST\n \t},\n \t{\n \t.description = \"meter_id\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"l3_rdir\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tl3_rdir\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"l3_ttl_dec\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff}\n \t},\n \t{\n \t.description = \"tl3_ttl_dec\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff}\n \t},\n \t{\n \t.description = \"decap_func\",\n \t.field_bit_size = 4,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_IF_ACT_BIT_THEN_CONST_ELSE_CONST,\n-\t.field_operand = {\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 56) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 48) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 40) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 32) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 24) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 16) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP >> 8) & 0xff,\n-\t\t(uint64_t)BNXT_ULP_ACTION_BIT_VXLAN_DECAP & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},\n-\t.field_operand_true = {0x0a, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT,\n+\t.field_cond_opr = {\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 56) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 48) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 40) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 32) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 24) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 16) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 8) & 0xff,\n+\t\t(uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP & 0xff},\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\tULP_WP_SYM_DECAP_FUNC_THRU_TUN},\n+\t.field_src2 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr2 = {\n+\t\tULP_WP_SYM_DECAP_FUNC_NONE}\n \t},\n \t{\n \t.description = \"vnic_or_vport\",\n \t.field_bit_size = 12,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_PROP,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,\n-\t\tBNXT_ULP_ACT_PROP_IDX_VNIC & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_ACT_PROP_IDX_VNIC & 0xff}\n \t},\n \t{\n \t.description = \"pop_vlan\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_BIT,\n-\t.field_operand = {\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 56) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 48) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 40) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 32) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 24) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 16) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 8) & 0xff,\n-\t\t(uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,\n+\t.field_opr1 = {\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 56) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 48) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 40) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 32) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 24) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 16) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 8) & 0xff,\n+\t\t(uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN & 0xff}\n \t},\n \t{\n \t.description = \"meter\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"mirror\",\n \t.field_bit_size = 2,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"drop\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ACT_BIT,\n-\t.field_operand = {\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 56) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 48) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 40) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 32) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 24) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 16) & 0xff,\n-\t\t((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 8) & 0xff,\n-\t\t(uint64_t)BNXT_ULP_ACTION_BIT_DROP & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,\n+\t.field_opr1 = {\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff,\n+\t\t((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff,\n+\t\t(uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff}\n \t}\n };\ndiff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c\nindex 0bce60d4e3..52eab7a715 100644\n--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c\n+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c\n@@ -3,7 +3,7 @@\n  * All rights reserved.\n  */\n \n-/* date: Mon Nov 23 17:33:02 2020 */\n+/* date: Wed Dec  2 12:05:11 2020 */\n \n #include \"ulp_template_db_enum.h\"\n #include \"ulp_template_db_field.h\"\n@@ -15,7 +15,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_class_tmpl_list[] = {\n \t/* class_tid: 1, wh_plus, ingress */\n \t[1] = {\n \t.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,\n-\t.num_tbls = 6,\n+\t.num_tbls = 9,\n \t.start_tbl_idx = 0,\n \t.reject_info = {\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,\n@@ -26,17 +26,17 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_class_tmpl_list[] = {\n \t[2] = {\n \t.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.num_tbls = 6,\n-\t.start_tbl_idx = 6,\n+\t.start_tbl_idx = 9,\n \t.reject_info = {\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,\n-\t\t.cond_start_idx = 2,\n+\t\t.cond_start_idx = 4,\n \t\t.cond_nums = 0 }\n \t},\n-\t/* class_tid: 3, wh_plus, ingress */\n+\t/* class_tid: 3, wh_plus, egress */\n \t[3] = {\n \t.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,\n-\t.num_tbls = 6,\n-\t.start_tbl_idx = 12,\n+\t.num_tbls = 8,\n+\t.start_tbl_idx = 15,\n \t.reject_info = {\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,\n \t\t.cond_start_idx = 4,\n@@ -45,18 +45,18 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_class_tmpl_list[] = {\n \t/* class_tid: 4, wh_plus, egress */\n \t[4] = {\n \t.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,\n-\t.num_tbls = 8,\n-\t.start_tbl_idx = 18,\n+\t.num_tbls = 7,\n+\t.start_tbl_idx = 23,\n \t.reject_info = {\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,\n-\t\t.cond_start_idx = 4,\n+\t\t.cond_start_idx = 10,\n \t\t.cond_nums = 0 }\n \t},\n \t/* class_tid: 5, wh_plus, egress */\n \t[5] = {\n \t.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.num_tbls = 7,\n-\t.start_tbl_idx = 26,\n+\t.start_tbl_idx = 30,\n \t.reject_info = {\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,\n \t\t.cond_start_idx = 10,\n@@ -65,18 +65,8 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_class_tmpl_list[] = {\n \t/* class_tid: 6, wh_plus, egress */\n \t[6] = {\n \t.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,\n-\t.num_tbls = 7,\n-\t.start_tbl_idx = 33,\n-\t.reject_info = {\n-\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,\n-\t\t.cond_start_idx = 10,\n-\t\t.cond_nums = 0 }\n-\t},\n-\t/* class_tid: 7, wh_plus, egress */\n-\t[7] = {\n-\t.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,\n \t.num_tbls = 1,\n-\t.start_tbl_idx = 40,\n+\t.start_tbl_idx = 37,\n \t.reject_info = {\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,\n \t\t.cond_start_idx = 10,\n@@ -85,13 +75,35 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_class_tmpl_list[] = {\n };\n \n struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n+\t{ /* class_tid: 1, wh_plus, table: l2_cntxt_tcam_cache.rd */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,\n+\t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,\n+\t.resource_sub_type =\n+\t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,\n+\t.direction = TF_DIR_RX,\n+\t.execute_info = {\n+\t\t.cond_goto = 2,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n+\t\t.cond_start_idx = 0,\n+\t\t.cond_nums = 1 },\n+\t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,\n+\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n+\t.key_start_idx = 0,\n+\t.blob_key_bit_size = 8,\n+\t.key_bit_size = 8,\n+\t.key_num_fields = 1,\n+\t.ident_start_idx = 0,\n+\t.ident_nums = 1\n+\t},\n \t{ /* class_tid: 1, wh_plus, table: l2_cntxt_tcam.0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n \t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,\n \t.direction = TF_DIR_RX,\n \t.execute_info = {\n+\t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 0,\n+\t\t.cond_start_idx = 1,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_SRCH_ALLOC_WR_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,\n@@ -99,7 +111,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n \t.pri_opcode  = BNXT_ULP_PRI_OPC_CONST,\n \t.pri_operand = 0,\n-\t.key_start_idx = 0,\n+\t.key_start_idx = 1,\n \t.blob_key_bit_size = 167,\n \t.key_bit_size = 167,\n \t.key_num_fields = 13,\n@@ -107,7 +119,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t.result_bit_size = 64,\n \t.result_num_fields = 13,\n \t.encap_num_fields = 0,\n-\t.ident_start_idx = 0,\n+\t.ident_start_idx = 1,\n \t.ident_nums = 1\n \t},\n \t{ /* class_tid: 1, wh_plus, table: profile_tcam_cache.rd */\n@@ -117,27 +129,40 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,\n \t.direction = TF_DIR_RX,\n \t.execute_info = {\n+\t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 0,\n+\t\t.cond_start_idx = 1,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_FLOW_SIG_ID_MATCH,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.key_start_idx = 13,\n+\t.key_start_idx = 14,\n \t.blob_key_bit_size = 14,\n \t.key_bit_size = 14,\n \t.key_num_fields = 3,\n-\t.ident_start_idx = 1,\n+\t.ident_start_idx = 2,\n \t.ident_nums = 3\n \t},\n+\t{ /* class_tid: 1, wh_plus, table: branch.0 */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_BRANCH_TABLE,\n+\t.direction = TF_DIR_RX,\n+\t.execute_info = {\n+\t\t.cond_goto = 3,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n+\t\t.cond_start_idx = 1,\n+\t\t.cond_nums = 1 },\n+\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH\n+\t},\n \t{ /* class_tid: 1, wh_plus, table: profile_tcam.0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n \t.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,\n \t.direction = TF_DIR_RX,\n \t.execute_info = {\n-\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n-\t\t.cond_start_idx = 0,\n-\t\t.cond_nums = 1 },\n+\t\t.cond_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n+\t\t.cond_start_idx = 2,\n+\t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,\n \t.tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n@@ -145,7 +170,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t.fdb_operand = BNXT_ULP_RF_IDX_RID,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n \t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,\n-\t.key_start_idx = 16,\n+\t.key_start_idx = 17,\n \t.blob_key_bit_size = 81,\n \t.key_bit_size = 81,\n \t.key_num_fields = 43,\n@@ -153,7 +178,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t.result_bit_size = 38,\n \t.result_num_fields = 8,\n \t.encap_num_fields = 0,\n-\t.ident_start_idx = 4,\n+\t.ident_start_idx = 5,\n \t.ident_nums = 1\n \t},\n \t{ /* class_tid: 1, wh_plus, table: profile_tcam_cache.wr */\n@@ -163,13 +188,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,\n \t.direction = TF_DIR_RX,\n \t.execute_info = {\n-\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n-\t\t.cond_start_idx = 1,\n-\t\t.cond_nums = 1 },\n+\t\t.cond_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n+\t\t.cond_start_idx = 2,\n+\t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.key_start_idx = 59,\n+\t.key_start_idx = 60,\n \t.blob_key_bit_size = 14,\n \t.key_bit_size = 14,\n \t.key_num_fields = 3,\n@@ -178,194 +204,71 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t.result_num_fields = 5,\n \t.encap_num_fields = 0\n \t},\n-\t{ /* class_tid: 1, wh_plus, table: eem.ext_0 */\n-\t.resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE,\n-\t.resource_type = TF_MEM_EXTERNAL,\n-\t.direction = TF_DIR_RX,\n-\t.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT,\n-\t.execute_info = {\n-\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 2,\n-\t\t.cond_nums = 0 },\n-\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,\n-\t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,\n-\t.key_start_idx = 62,\n-\t.blob_key_bit_size = 448,\n-\t.key_bit_size = 448,\n-\t.key_num_fields = 10,\n-\t.result_start_idx = 26,\n-\t.result_bit_size = 64,\n-\t.result_num_fields = 9,\n-\t.encap_num_fields = 0\n-\t},\n \t{ /* class_tid: 1, wh_plus, table: em.int_0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE,\n \t.resource_type = TF_MEM_INTERNAL,\n \t.direction = TF_DIR_RX,\n \t.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT,\n \t.execute_info = {\n-\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n+\t\t.cond_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n \t\t.cond_start_idx = 2,\n-\t\t.cond_nums = 0 },\n+\t\t.cond_nums = 1 },\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,\n \t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,\n-\t.key_start_idx = 72,\n+\t.key_start_idx = 63,\n \t.blob_key_bit_size = 176,\n \t.key_bit_size = 176,\n \t.key_num_fields = 10,\n-\t.result_start_idx = 35,\n+\t.result_start_idx = 26,\n \t.result_bit_size = 64,\n \t.result_num_fields = 9,\n \t.encap_num_fields = 0\n \t},\n-\t{ /* class_tid: 2, wh_plus, table: l2_cntxt_tcam.0 */\n-\t.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n-\t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,\n-\t.direction = TF_DIR_RX,\n-\t.execute_info = {\n-\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 2,\n-\t\t.cond_nums = 0 },\n-\t.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_SRCH_ALLOC_WR_REGFILE,\n-\t.tbl_operand = BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0,\n-\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.pri_opcode  = BNXT_ULP_PRI_OPC_CONST,\n-\t.pri_operand = 0,\n-\t.key_start_idx = 82,\n-\t.blob_key_bit_size = 167,\n-\t.key_bit_size = 167,\n-\t.key_num_fields = 13,\n-\t.result_start_idx = 44,\n-\t.result_bit_size = 64,\n-\t.result_num_fields = 13,\n-\t.encap_num_fields = 0,\n-\t.ident_start_idx = 5,\n-\t.ident_nums = 1\n-\t},\n-\t{ /* class_tid: 2, wh_plus, table: profile_tcam_cache.rd */\n-\t.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,\n-\t.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,\n-\t.resource_sub_type =\n-\t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,\n-\t.direction = TF_DIR_RX,\n-\t.execute_info = {\n-\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 2,\n-\t\t.cond_nums = 0 },\n-\t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,\n-\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_FLOW_SIG_ID_MATCH,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.key_start_idx = 95,\n-\t.blob_key_bit_size = 14,\n-\t.key_bit_size = 14,\n-\t.key_num_fields = 3,\n-\t.ident_start_idx = 6,\n-\t.ident_nums = 3\n-\t},\n-\t{ /* class_tid: 2, wh_plus, table: profile_tcam.0 */\n-\t.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n-\t.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,\n-\t.direction = TF_DIR_RX,\n-\t.execute_info = {\n-\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n-\t\t.cond_start_idx = 2,\n-\t\t.cond_nums = 1 },\n-\t.tbl_opcode = BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE,\n-\t.tbl_operand = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,\n-\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_PUSH_REGFILE,\n-\t.fdb_operand = BNXT_ULP_RF_IDX_RID,\n-\t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n-\t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,\n-\t.key_start_idx = 98,\n-\t.blob_key_bit_size = 81,\n-\t.key_bit_size = 81,\n-\t.key_num_fields = 43,\n-\t.result_start_idx = 57,\n-\t.result_bit_size = 38,\n-\t.result_num_fields = 8,\n-\t.encap_num_fields = 0,\n-\t.ident_start_idx = 9,\n-\t.ident_nums = 1\n-\t},\n-\t{ /* class_tid: 2, wh_plus, table: profile_tcam_cache.wr */\n-\t.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,\n-\t.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,\n-\t.resource_sub_type =\n-\t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PROFILE_TCAM,\n-\t.direction = TF_DIR_RX,\n-\t.execute_info = {\n-\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n-\t\t.cond_start_idx = 3,\n-\t\t.cond_nums = 1 },\n-\t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,\n-\t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.key_start_idx = 141,\n-\t.blob_key_bit_size = 14,\n-\t.key_bit_size = 14,\n-\t.key_num_fields = 3,\n-\t.result_start_idx = 65,\n-\t.result_bit_size = 66,\n-\t.result_num_fields = 5,\n-\t.encap_num_fields = 0\n-\t},\n-\t{ /* class_tid: 2, wh_plus, table: eem.ext_0 */\n+\t{ /* class_tid: 1, wh_plus, table: eem.ext_0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE,\n \t.resource_type = TF_MEM_EXTERNAL,\n \t.direction = TF_DIR_RX,\n \t.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT,\n \t.execute_info = {\n-\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n-\t\t.cond_start_idx = 4,\n-\t\t.cond_nums = 0 },\n+\t\t.cond_goto = 1,\n+\t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n+\t\t.cond_start_idx = 3,\n+\t\t.cond_nums = 1 },\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,\n \t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,\n-\t.key_start_idx = 144,\n+\t.key_start_idx = 73,\n \t.blob_key_bit_size = 448,\n \t.key_bit_size = 448,\n \t.key_num_fields = 10,\n-\t.result_start_idx = 70,\n+\t.result_start_idx = 35,\n \t.result_bit_size = 64,\n \t.result_num_fields = 9,\n \t.encap_num_fields = 0\n \t},\n-\t{ /* class_tid: 2, wh_plus, table: em.int_0 */\n-\t.resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE,\n-\t.resource_type = TF_MEM_INTERNAL,\n+\t{ /* class_tid: 1, wh_plus, table: last */\n+\t.resource_func = BNXT_ULP_RESOURCE_FUNC_BRANCH_TABLE,\n \t.direction = TF_DIR_RX,\n-\t.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT,\n \t.execute_info = {\n+\t\t.cond_goto = 0,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 4,\n \t\t.cond_nums = 0 },\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n-\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_IF_MARK_ACTION,\n-\t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,\n-\t.key_start_idx = 154,\n-\t.blob_key_bit_size = 176,\n-\t.key_bit_size = 176,\n-\t.key_num_fields = 10,\n-\t.result_start_idx = 79,\n-\t.result_bit_size = 64,\n-\t.result_num_fields = 9,\n-\t.encap_num_fields = 0\n+\t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH\n \t},\n-\t{ /* class_tid: 3, wh_plus, table: int_full_act_record.0 */\n+\t{ /* class_tid: 2, wh_plus, table: int_full_act_record.0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n \t.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,\n \t.resource_sub_type =\n \t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,\n \t.direction = TF_DIR_RX,\n \t.execute_info = {\n+\t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 4,\n \t\t.cond_nums = 0 },\n@@ -374,16 +277,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n-\t.result_start_idx = 88,\n+\t.result_start_idx = 44,\n \t.result_bit_size = 128,\n \t.result_num_fields = 26,\n \t.encap_num_fields = 0\n \t},\n-\t{ /* class_tid: 3, wh_plus, table: l2_cntxt_tcam.0 */\n+\t{ /* class_tid: 2, wh_plus, table: l2_cntxt_tcam.0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n \t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,\n \t.direction = TF_DIR_RX,\n \t.execute_info = {\n+\t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 4,\n \t\t.cond_nums = 0 },\n@@ -396,44 +300,46 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t.pri_operand = 0,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n \t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,\n-\t.key_start_idx = 164,\n+\t.key_start_idx = 83,\n \t.blob_key_bit_size = 167,\n \t.key_bit_size = 167,\n \t.key_num_fields = 13,\n-\t.result_start_idx = 114,\n+\t.result_start_idx = 70,\n \t.result_bit_size = 64,\n \t.result_num_fields = 13,\n \t.encap_num_fields = 0,\n-\t.ident_start_idx = 10,\n+\t.ident_start_idx = 6,\n \t.ident_nums = 1\n \t},\n-\t{ /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.wr */\n+\t{ /* class_tid: 2, wh_plus, table: l2_cntxt_tcam_cache.wr */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,\n \t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,\n \t.resource_sub_type =\n \t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,\n \t.direction = TF_DIR_RX,\n \t.execute_info = {\n+\t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 4,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.key_start_idx = 177,\n+\t.key_start_idx = 96,\n \t.blob_key_bit_size = 8,\n \t.key_bit_size = 8,\n \t.key_num_fields = 1,\n-\t.result_start_idx = 127,\n+\t.result_start_idx = 83,\n \t.result_bit_size = 62,\n \t.result_num_fields = 4,\n \t.encap_num_fields = 0\n \t},\n-\t{ /* class_tid: 3, wh_plus, table: parif_def_lkup_arec_ptr.0 */\n+\t{ /* class_tid: 2, wh_plus, table: parif_def_lkup_arec_ptr.0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,\n \t.resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR,\n \t.direction = TF_DIR_RX,\n \t.execute_info = {\n+\t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 4,\n \t\t.cond_nums = 0 },\n@@ -441,16 +347,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t.tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.result_start_idx = 131,\n+\t.result_start_idx = 87,\n \t.result_bit_size = 32,\n \t.result_num_fields = 1,\n \t.encap_num_fields = 0\n \t},\n-\t{ /* class_tid: 3, wh_plus, table: parif_def_arec_ptr.0 */\n+\t{ /* class_tid: 2, wh_plus, table: parif_def_arec_ptr.0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,\n \t.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,\n \t.direction = TF_DIR_RX,\n \t.execute_info = {\n+\t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 4,\n \t\t.cond_nums = 0 },\n@@ -458,16 +365,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t.tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.result_start_idx = 132,\n+\t.result_start_idx = 88,\n \t.result_bit_size = 32,\n \t.result_num_fields = 1,\n \t.encap_num_fields = 0\n \t},\n-\t{ /* class_tid: 3, wh_plus, table: parif_def_err_arec_ptr.0 */\n+\t{ /* class_tid: 2, wh_plus, table: parif_def_err_arec_ptr.0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,\n \t.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,\n \t.direction = TF_DIR_RX,\n \t.execute_info = {\n+\t\t.cond_goto = 0,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 4,\n \t\t.cond_nums = 0 },\n@@ -475,18 +383,19 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t.tbl_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.result_start_idx = 133,\n+\t.result_start_idx = 89,\n \t.result_bit_size = 32,\n \t.result_num_fields = 1,\n \t.encap_num_fields = 0\n \t},\n-\t{ /* class_tid: 4, wh_plus, table: int_full_act_record.0 */\n+\t{ /* class_tid: 3, wh_plus, table: int_full_act_record.0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n \t.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,\n \t.resource_sub_type =\n \t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,\n \t.direction = TF_DIR_TX,\n \t.execute_info = {\n+\t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 4,\n \t\t.cond_nums = 0 },\n@@ -495,16 +404,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n-\t.result_start_idx = 134,\n+\t.result_start_idx = 90,\n \t.result_bit_size = 128,\n \t.result_num_fields = 26,\n \t.encap_num_fields = 0\n \t},\n-\t{ /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.vfr_0 */\n+\t{ /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_bypass.vfr_0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n \t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,\n \t.direction = TF_DIR_TX,\n \t.execute_info = {\n+\t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n \t\t.cond_start_idx = 4,\n \t\t.cond_nums = 1 },\n@@ -516,42 +426,44 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t.pri_operand = 0,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n \t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,\n-\t.key_start_idx = 178,\n+\t.key_start_idx = 97,\n \t.blob_key_bit_size = 167,\n \t.key_bit_size = 167,\n \t.key_num_fields = 13,\n-\t.result_start_idx = 160,\n+\t.result_start_idx = 116,\n \t.result_bit_size = 64,\n \t.result_num_fields = 13,\n \t.encap_num_fields = 0,\n-\t.ident_start_idx = 11,\n+\t.ident_start_idx = 7,\n \t.ident_nums = 0\n \t},\n-\t{ /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.rd */\n+\t{ /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.rd */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,\n \t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,\n \t.resource_sub_type =\n \t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,\n \t.direction = TF_DIR_TX,\n \t.execute_info = {\n+\t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,\n \t\t.cond_start_idx = 5,\n \t\t.cond_nums = 1 },\n \t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.key_start_idx = 191,\n+\t.key_start_idx = 110,\n \t.blob_key_bit_size = 8,\n \t.key_bit_size = 8,\n \t.key_num_fields = 1,\n-\t.ident_start_idx = 11,\n+\t.ident_start_idx = 7,\n \t.ident_nums = 1\n \t},\n-\t{ /* class_tid: 4, wh_plus, table: l2_cntxt_tcam.0 */\n+\t{ /* class_tid: 3, wh_plus, table: l2_cntxt_tcam.0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n \t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,\n \t.direction = TF_DIR_TX,\n \t.execute_info = {\n+\t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,\n \t\t.cond_start_idx = 6,\n \t\t.cond_nums = 2 },\n@@ -562,44 +474,46 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t.fdb_operand = BNXT_ULP_RF_IDX_RID,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n \t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,\n-\t.key_start_idx = 192,\n+\t.key_start_idx = 111,\n \t.blob_key_bit_size = 167,\n \t.key_bit_size = 167,\n \t.key_num_fields = 13,\n-\t.result_start_idx = 173,\n+\t.result_start_idx = 129,\n \t.result_bit_size = 64,\n \t.result_num_fields = 13,\n \t.encap_num_fields = 0,\n-\t.ident_start_idx = 12,\n+\t.ident_start_idx = 8,\n \t.ident_nums = 1\n \t},\n-\t{ /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.wr */\n+\t{ /* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.wr */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,\n \t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,\n \t.resource_sub_type =\n \t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,\n \t.direction = TF_DIR_TX,\n \t.execute_info = {\n+\t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,\n \t\t.cond_start_idx = 8,\n \t\t.cond_nums = 2 },\n \t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.key_start_idx = 205,\n+\t.key_start_idx = 124,\n \t.blob_key_bit_size = 8,\n \t.key_bit_size = 8,\n \t.key_num_fields = 1,\n-\t.result_start_idx = 186,\n+\t.result_start_idx = 142,\n \t.result_bit_size = 62,\n \t.result_num_fields = 4,\n \t.encap_num_fields = 0\n \t},\n-\t{ /* class_tid: 4, wh_plus, table: parif_def_lkup_arec_ptr.0 */\n+\t{ /* class_tid: 3, wh_plus, table: parif_def_lkup_arec_ptr.0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,\n \t.resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR,\n \t.direction = TF_DIR_TX,\n \t.execute_info = {\n+\t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 10,\n \t\t.cond_nums = 0 },\n@@ -607,16 +521,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t.tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.result_start_idx = 190,\n+\t.result_start_idx = 146,\n \t.result_bit_size = 32,\n \t.result_num_fields = 1,\n \t.encap_num_fields = 0\n \t},\n-\t{ /* class_tid: 4, wh_plus, table: parif_def_arec_ptr.0 */\n+\t{ /* class_tid: 3, wh_plus, table: parif_def_arec_ptr.0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,\n \t.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,\n \t.direction = TF_DIR_TX,\n \t.execute_info = {\n+\t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 10,\n \t\t.cond_nums = 0 },\n@@ -624,16 +539,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t.tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.result_start_idx = 191,\n+\t.result_start_idx = 147,\n \t.result_bit_size = 32,\n \t.result_num_fields = 1,\n \t.encap_num_fields = 0\n \t},\n-\t{ /* class_tid: 4, wh_plus, table: parif_def_err_arec_ptr.0 */\n+\t{ /* class_tid: 3, wh_plus, table: parif_def_err_arec_ptr.0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,\n \t.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,\n \t.direction = TF_DIR_TX,\n \t.execute_info = {\n+\t\t.cond_goto = 0,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 10,\n \t\t.cond_nums = 0 },\n@@ -641,18 +557,19 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t.tbl_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.result_start_idx = 192,\n+\t.result_start_idx = 148,\n \t.result_bit_size = 32,\n \t.result_num_fields = 1,\n \t.encap_num_fields = 0\n \t},\n-\t{ /* class_tid: 5, wh_plus, table: int_vtag_encap_record.egr0 */\n+\t{ /* class_tid: 4, wh_plus, table: int_vtag_encap_record.egr0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n \t.resource_type = TF_TBL_TYPE_ACT_ENCAP_8B,\n \t.resource_sub_type =\n \t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,\n \t.direction = TF_DIR_TX,\n \t.execute_info = {\n+\t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 10,\n \t\t.cond_nums = 0 },\n@@ -661,18 +578,19 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n-\t.result_start_idx = 193,\n+\t.result_start_idx = 149,\n \t.result_bit_size = 0,\n \t.result_num_fields = 0,\n \t.encap_num_fields = 12\n \t},\n-\t{ /* class_tid: 5, wh_plus, table: int_full_act_record.egr0 */\n+\t{ /* class_tid: 4, wh_plus, table: int_full_act_record.egr0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n \t.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,\n \t.resource_sub_type =\n \t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,\n \t.direction = TF_DIR_TX,\n \t.execute_info = {\n+\t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 10,\n \t\t.cond_nums = 0 },\n@@ -681,16 +599,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n-\t.result_start_idx = 205,\n+\t.result_start_idx = 161,\n \t.result_bit_size = 128,\n \t.result_num_fields = 26,\n \t.encap_num_fields = 0\n \t},\n-\t{ /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.egr0 */\n+\t{ /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.egr0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n \t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,\n \t.direction = TF_DIR_TX,\n \t.execute_info = {\n+\t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 10,\n \t\t.cond_nums = 0 },\n@@ -701,48 +620,50 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t.fdb_operand = BNXT_ULP_RF_IDX_RID,\n \t.pri_opcode  = BNXT_ULP_PRI_OPC_CONST,\n \t.pri_operand = 0,\n-\t.key_start_idx = 206,\n+\t.key_start_idx = 125,\n \t.blob_key_bit_size = 167,\n \t.key_bit_size = 167,\n \t.key_num_fields = 13,\n-\t.result_start_idx = 231,\n+\t.result_start_idx = 187,\n \t.result_bit_size = 64,\n \t.result_num_fields = 13,\n \t.encap_num_fields = 0,\n-\t.ident_start_idx = 13,\n+\t.ident_start_idx = 9,\n \t.ident_nums = 0\n \t},\n-\t{ /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_cache.wr_egr0 */\n+\t{ /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.wr_egr0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,\n \t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,\n \t.resource_sub_type =\n \t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,\n \t.direction = TF_DIR_TX,\n \t.execute_info = {\n+\t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 10,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.key_start_idx = 219,\n+\t.key_start_idx = 138,\n \t.blob_key_bit_size = 8,\n \t.key_bit_size = 8,\n \t.key_num_fields = 1,\n-\t.result_start_idx = 244,\n+\t.result_start_idx = 200,\n \t.result_bit_size = 62,\n \t.result_num_fields = 4,\n \t.encap_num_fields = 0,\n-\t.ident_start_idx = 13,\n+\t.ident_start_idx = 9,\n \t.ident_nums = 0\n \t},\n-\t{ /* class_tid: 5, wh_plus, table: int_full_act_record.ing0 */\n+\t{ /* class_tid: 4, wh_plus, table: int_full_act_record.ing0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n \t.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,\n \t.resource_sub_type =\n \t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,\n \t.direction = TF_DIR_RX,\n \t.execute_info = {\n+\t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 10,\n \t\t.cond_nums = 0 },\n@@ -751,16 +672,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n-\t.result_start_idx = 248,\n+\t.result_start_idx = 204,\n \t.result_bit_size = 128,\n \t.result_num_fields = 26,\n \t.encap_num_fields = 0\n \t},\n-\t{ /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.dtagged_ing0 */\n+\t{ /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.dtagged_ing0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n \t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,\n \t.direction = TF_DIR_RX,\n \t.execute_info = {\n+\t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 10,\n \t\t.cond_nums = 0 },\n@@ -772,22 +694,23 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t.pri_operand = 0,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n \t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,\n-\t.key_start_idx = 220,\n+\t.key_start_idx = 139,\n \t.blob_key_bit_size = 167,\n \t.key_bit_size = 167,\n \t.key_num_fields = 13,\n-\t.result_start_idx = 274,\n+\t.result_start_idx = 230,\n \t.result_bit_size = 64,\n \t.result_num_fields = 13,\n \t.encap_num_fields = 0,\n-\t.ident_start_idx = 13,\n+\t.ident_start_idx = 9,\n \t.ident_nums = 0\n \t},\n-\t{ /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.stagged_ing0 */\n+\t{ /* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.stagged_ing0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n \t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,\n \t.direction = TF_DIR_RX,\n \t.execute_info = {\n+\t\t.cond_goto = 0,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 10,\n \t\t.cond_nums = 0 },\n@@ -799,22 +722,23 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t.pri_operand = 0,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n \t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,\n-\t.key_start_idx = 233,\n+\t.key_start_idx = 152,\n \t.blob_key_bit_size = 167,\n \t.key_bit_size = 167,\n \t.key_num_fields = 13,\n-\t.result_start_idx = 287,\n+\t.result_start_idx = 243,\n \t.result_bit_size = 64,\n \t.result_num_fields = 13,\n \t.encap_num_fields = 0,\n-\t.ident_start_idx = 13,\n+\t.ident_start_idx = 9,\n \t.ident_nums = 0\n \t},\n-\t{ /* class_tid: 6, wh_plus, table: l2_cntxt_tcam.egr */\n+\t{ /* class_tid: 5, wh_plus, table: l2_cntxt_tcam.egr */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n \t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,\n \t.direction = TF_DIR_TX,\n \t.execute_info = {\n+\t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 10,\n \t\t.cond_nums = 0 },\n@@ -825,44 +749,46 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t.fdb_operand = BNXT_ULP_RF_IDX_RID,\n \t.pri_opcode  = BNXT_ULP_PRI_OPC_CONST,\n \t.pri_operand = 0,\n-\t.key_start_idx = 246,\n+\t.key_start_idx = 165,\n \t.blob_key_bit_size = 167,\n \t.key_bit_size = 167,\n \t.key_num_fields = 13,\n-\t.result_start_idx = 300,\n+\t.result_start_idx = 256,\n \t.result_bit_size = 64,\n \t.result_num_fields = 13,\n \t.encap_num_fields = 0,\n-\t.ident_start_idx = 13,\n+\t.ident_start_idx = 9,\n \t.ident_nums = 1\n \t},\n-\t{ /* class_tid: 6, wh_plus, table: l2_cntxt_tcam_cache.egr_wr */\n+\t{ /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_cache.egr_wr */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_GENERIC_TABLE,\n \t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,\n \t.resource_sub_type =\n \t\tBNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_L2_CNTXT_TCAM,\n \t.direction = TF_DIR_TX,\n \t.execute_info = {\n+\t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 10,\n \t\t.cond_nums = 0 },\n \t.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_WRITE,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.key_start_idx = 259,\n+\t.key_start_idx = 178,\n \t.blob_key_bit_size = 8,\n \t.key_bit_size = 8,\n \t.key_num_fields = 1,\n-\t.result_start_idx = 313,\n+\t.result_start_idx = 269,\n \t.result_bit_size = 62,\n \t.result_num_fields = 4,\n \t.encap_num_fields = 0\n \t},\n-\t{ /* class_tid: 6, wh_plus, table: parif_def_lkup_arec_ptr.egr */\n+\t{ /* class_tid: 5, wh_plus, table: parif_def_lkup_arec_ptr.egr */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,\n \t.resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR,\n \t.direction = TF_DIR_TX,\n \t.execute_info = {\n+\t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 10,\n \t\t.cond_nums = 0 },\n@@ -870,16 +796,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t.tbl_operand = BNXT_ULP_CF_IDX_VF_FUNC_PARIF,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.result_start_idx = 317,\n+\t.result_start_idx = 273,\n \t.result_bit_size = 32,\n \t.result_num_fields = 1,\n \t.encap_num_fields = 0\n \t},\n-\t{ /* class_tid: 6, wh_plus, table: parif_def_arec_ptr.egr */\n+\t{ /* class_tid: 5, wh_plus, table: parif_def_arec_ptr.egr */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,\n \t.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,\n \t.direction = TF_DIR_TX,\n \t.execute_info = {\n+\t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 10,\n \t\t.cond_nums = 0 },\n@@ -887,16 +814,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t.tbl_operand = BNXT_ULP_CF_IDX_VF_FUNC_PARIF,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.result_start_idx = 318,\n+\t.result_start_idx = 274,\n \t.result_bit_size = 32,\n \t.result_num_fields = 1,\n \t.encap_num_fields = 0\n \t},\n-\t{ /* class_tid: 6, wh_plus, table: parif_def_err_arec_ptr.egr */\n+\t{ /* class_tid: 5, wh_plus, table: parif_def_err_arec_ptr.egr */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,\n \t.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,\n \t.direction = TF_DIR_TX,\n \t.execute_info = {\n+\t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 10,\n \t\t.cond_nums = 0 },\n@@ -904,18 +832,19 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t.tbl_operand = BNXT_ULP_CF_IDX_VF_FUNC_PARIF,\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n-\t.result_start_idx = 319,\n+\t.result_start_idx = 275,\n \t.result_bit_size = 32,\n \t.result_num_fields = 1,\n \t.encap_num_fields = 0\n \t},\n-\t{ /* class_tid: 6, wh_plus, table: int_full_act_record.ing */\n+\t{ /* class_tid: 5, wh_plus, table: int_full_act_record.ing */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n \t.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,\n \t.resource_sub_type =\n \t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,\n \t.direction = TF_DIR_RX,\n \t.execute_info = {\n+\t\t.cond_goto = 1,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 10,\n \t\t.cond_nums = 0 },\n@@ -924,16 +853,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_PUSH_AND_SET_VFR_FLAG,\n-\t.result_start_idx = 320,\n+\t.result_start_idx = 276,\n \t.result_bit_size = 128,\n \t.result_num_fields = 26,\n \t.encap_num_fields = 0\n \t},\n-\t{ /* class_tid: 6, wh_plus, table: l2_cntxt_tcam_bypass.ing */\n+\t{ /* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.ing */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,\n \t.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,\n \t.direction = TF_DIR_RX,\n \t.execute_info = {\n+\t\t.cond_goto = 0,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 10,\n \t\t.cond_nums = 0 },\n@@ -945,24 +875,25 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t.pri_operand = 0,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n \t.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,\n-\t.key_start_idx = 260,\n+\t.key_start_idx = 179,\n \t.blob_key_bit_size = 167,\n \t.key_bit_size = 167,\n \t.key_num_fields = 13,\n-\t.result_start_idx = 346,\n+\t.result_start_idx = 302,\n \t.result_bit_size = 64,\n \t.result_num_fields = 13,\n \t.encap_num_fields = 0,\n-\t.ident_start_idx = 14,\n+\t.ident_start_idx = 10,\n \t.ident_nums = 0\n \t},\n-\t{ /* class_tid: 7, wh_plus, table: int_full_act_record.0 */\n+\t{ /* class_tid: 6, wh_plus, table: int_full_act_record.0 */\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,\n \t.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,\n \t.resource_sub_type =\n \t\tBNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_VFR_CFA_ACTION,\n \t.direction = TF_DIR_TX,\n \t.execute_info = {\n+\t\t.cond_goto = 0,\n \t\t.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,\n \t\t.cond_start_idx = 10,\n \t\t.cond_nums = 0 },\n@@ -971,7 +902,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \t.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,\n \t.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,\n \t.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,\n-\t.result_start_idx = 359,\n+\t.result_start_idx = 315,\n \t.result_bit_size = 128,\n \t.result_num_fields = 26,\n \t.encap_num_fields = 0\n@@ -980,246 +911,279 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {\n \n struct bnxt_ulp_mapper_cond_info ulp_wh_plus_class_cond_list[] = {\n \t{\n-\t.cond_opcode = BNXT_ULP_COND_OPC_REGFILE_NOT_SET,\n-\t.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT\n+\t.cond_opcode = BNXT_ULP_COND_OPC_FIELD_BIT_NOT_SET,\n+\t.cond_operand = BNXT_ULP_GLB_HF_ID_O_ETH_DMAC\n \t},\n \t{\n-\t.cond_opcode = BNXT_ULP_COND_OPC_REGFILE_NOT_SET,\n+\t.cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,\n \t.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT\n \t},\n \t{\n-\t.cond_opcode = BNXT_ULP_COND_OPC_REGFILE_NOT_SET,\n-\t.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT\n+\t.cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,\n+\t.cond_operand = BNXT_ULP_HDR_BIT_O_IPV4\n \t},\n \t{\n-\t.cond_opcode = BNXT_ULP_COND_OPC_REGFILE_NOT_SET,\n-\t.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT\n+\t.cond_opcode = BNXT_ULP_COND_OPC_HDR_BIT_IS_SET,\n+\t.cond_operand = BNXT_ULP_HDR_BIT_O_IPV4\n \t},\n \t{\n-\t.cond_opcode = BNXT_ULP_COND_OPC_COMP_FIELD_IS_SET,\n+\t.cond_opcode = BNXT_ULP_COND_OPC_CF_IS_SET,\n \t.cond_operand = BNXT_ULP_CF_IDX_VFR_MODE\n \t},\n \t{\n-\t.cond_opcode = BNXT_ULP_COND_OPC_COMP_FIELD_NOT_SET,\n+\t.cond_opcode = BNXT_ULP_COND_OPC_CF_NOT_SET,\n \t.cond_operand = BNXT_ULP_CF_IDX_VFR_MODE\n \t},\n \t{\n-\t.cond_opcode = BNXT_ULP_COND_OPC_COMP_FIELD_NOT_SET,\n+\t.cond_opcode = BNXT_ULP_COND_OPC_CF_NOT_SET,\n \t.cond_operand = BNXT_ULP_CF_IDX_VFR_MODE\n \t},\n \t{\n-\t.cond_opcode = BNXT_ULP_COND_OPC_REGFILE_NOT_SET,\n+\t.cond_opcode = BNXT_ULP_COND_OPC_RF_NOT_SET,\n \t.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT\n \t},\n \t{\n-\t.cond_opcode = BNXT_ULP_COND_OPC_COMP_FIELD_NOT_SET,\n+\t.cond_opcode = BNXT_ULP_COND_OPC_CF_NOT_SET,\n \t.cond_operand = BNXT_ULP_CF_IDX_VFR_MODE\n \t},\n \t{\n-\t.cond_opcode = BNXT_ULP_COND_OPC_REGFILE_NOT_SET,\n+\t.cond_opcode = BNXT_ULP_COND_OPC_RF_NOT_SET,\n \t.cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_HIT\n \t}\n };\n \n struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n+\t/* class_tid: 1, wh_plus, table: l2_cntxt_tcam_cache.rd */\n+\t{\n+\t.field_info_mask = {\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}\n+\t\t},\n+\t.field_info_spec = {\n+\t\t.description = \"svif\",\n+\t\t.field_bit_size = 8,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}\n+\t\t}\n+\t},\n \t/* class_tid: 1, wh_plus, table: l2_cntxt_tcam.0 */\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l2_ivlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_GLB_HF_OO_VLAN_VID >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_OO_VLAN_VID & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l2_ivlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_GLB_HF_OO_VLAN_VID >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_OO_VLAN_VID & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_OO_VLAN_VID >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_OO_VLAN_VID & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l2_ovlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l2_ovlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"mac0_addr\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_GLB_HF_O_ETH_DMAC >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_O_ETH_DMAC & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"mac0_addr\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_GLB_HF_O_ETH_DMAC >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_O_ETH_DMAC & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_ETH_DMAC >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_ETH_DMAC & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"svif\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_GLB_HF_SVIF_INDEX >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_SVIF_INDEX & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"svif\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_GLB_HF_SVIF_INDEX >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_SVIF_INDEX & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_SVIF_INDEX >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_SVIF_INDEX & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"sparif\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"sparif\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl2_ivlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl2_ivlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl2_ovlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl2_ovlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"mac1_addr\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"mac1_addr\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l2_num_vtags\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l2_num_vtags\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,\n-\t\t.field_operand = {\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n \t\t\t(BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff,\n-\t\t\tBNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t\tBNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl2_num_vtags\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl2_num_vtags\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tun_hdr_type\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tun_hdr_type\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"key_type\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"key_type\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"valid\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"valid\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t1}\n \t\t}\n \t},\n \t/* class_tid: 1, wh_plus, table: profile_tcam_cache.rd */\n@@ -1227,52 +1191,54 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t.field_info_mask = {\n \t\t.description = \"recycle_cnt\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"recycle_cnt\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"prof_func_id\",\n \t\t.field_bit_size = 7,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"prof_func_id\",\n \t\t.field_bit_size = 7,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE,\n-\t\t.field_operand = {\n-\t\t(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"hdr_sig_id\",\n \t\t.field_bit_size = 5,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"hdr_sig_id\",\n \t\t.field_bit_size = 5,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,\n-\t\t.field_operand = {\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n \t\t\t(BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,\n-\t\t\tBNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t\tBNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}\n \t\t}\n \t},\n \t/* class_tid: 1, wh_plus, table: profile_tcam.0 */\n@@ -1280,580 +1246,684 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t.field_info_mask = {\n \t\t.description = \"l4_hdr_is_udp_tcp\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l4_hdr_is_udp_tcp\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l4_hdr_type\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l4_hdr_type\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,\n+\t\t.field_cond_opr = {\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,\n+\t\t\t(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\tULP_WP_SYM_L4_HDR_TYPE_TCP},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr2 = {\n+\t\t\tULP_WP_SYM_L4_HDR_TYPE_UDP}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l4_hdr_error\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l4_hdr_error\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l4_hdr_valid\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l4_hdr_valid\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {\n-\t\t\tBNXT_ULP_WH_PLUS_SYM_L4_HDR_VALID_YES,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\tULP_WP_SYM_L4_HDR_VALID_YES}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l3_ipv6_cmp_dst\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l3_ipv6_cmp_dst\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l3_ipv6_cmp_src\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l3_ipv6_cmp_src\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l3_hdr_isIP\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l3_hdr_isIP\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l3_hdr_type\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l3_hdr_type\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,\n+\t\t.field_cond_opr = {\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 56) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 48) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 40) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 32) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 24) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 16) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 >> 8) & 0xff,\n+\t\t\t(uint64_t)BNXT_ULP_HDR_BIT_O_IPV4 & 0xff},\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\tULP_WP_SYM_L3_HDR_TYPE_IPV4},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr2 = {\n+\t\t\tULP_WP_SYM_L3_HDR_TYPE_IPV6}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l3_hdr_error\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l3_hdr_error\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l3_hdr_valid\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l3_hdr_valid\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {\n-\t\t\tBNXT_ULP_WH_PLUS_SYM_L3_HDR_VALID_YES,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\tULP_WP_SYM_L3_HDR_VALID_YES}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l2_two_vtags\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l2_two_vtags\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l2_vtag_present\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l2_vtag_present\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,\n-\t\t.field_operand = {\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n \t\t\t(BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff,\n-\t\t\tBNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t\tBNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l2_uc_mc_bc\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l2_uc_mc_bc\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l2_hdr_type\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l2_hdr_type\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l2_hdr_error\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l2_hdr_error\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l2_hdr_valid\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l2_hdr_valid\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {\n-\t\t\tBNXT_ULP_WH_PLUS_SYM_L2_HDR_VALID_YES,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\tULP_WP_SYM_L2_HDR_VALID_YES}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tun_hdr_flags\",\n \t\t.field_bit_size = 3,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tun_hdr_flags\",\n \t\t.field_bit_size = 3,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tun_hdr_type\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tun_hdr_type\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tun_hdr_err\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tun_hdr_err\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tun_hdr_valid\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tun_hdr_valid\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl4_hdr_is_udp_tcp\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl4_hdr_is_udp_tcp\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl4_hdr_type\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl4_hdr_type\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl4_hdr_error\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl4_hdr_error\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl4_hdr_valid\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl4_hdr_valid\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl3_ipv6_cmp_dst\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl3_ipv6_cmp_dst\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl3_ipv6_cmp_src\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl3_ipv6_cmp_src\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl3_hdr_isIP\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl3_hdr_isIP\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl3_hdr_type\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl3_hdr_type\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl3_hdr_error\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl3_hdr_error\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl3_hdr_valid\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl3_hdr_valid\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl2_two_vtags\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl2_two_vtags\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl2_vtag_present\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl2_vtag_present\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl2_uc_mc_bc\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl2_uc_mc_bc\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl2_hdr_type\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl2_hdr_type\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl2_hdr_valid\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl2_hdr_valid\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"hrec_next\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"hrec_next\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"reserved\",\n \t\t.field_bit_size = 9,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"reserved\",\n \t\t.field_bit_size = 9,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"prof_func_id\",\n \t\t.field_bit_size = 7,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"prof_func_id\",\n \t\t.field_bit_size = 7,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE,\n-\t\t.field_operand = {\n-\t\t(BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"agg_error\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"agg_error\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"recycle_cnt\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"recycle_cnt\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"pkt_type_0\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"pkt_type_0\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"pkt_type_1\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"pkt_type_1\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"valid\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"valid\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t1}\n \t\t}\n \t},\n \t/* class_tid: 1, wh_plus, table: profile_tcam_cache.wr */\n@@ -1861,3165 +1931,2188 @@ struct bnxt_ulp_mapper_key_info ulp_wh_plus_class_key_info_list[] = {\n \t.field_info_mask = {\n \t\t.description = \"recycle_cnt\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"recycle_cnt\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"prof_func_id\",\n \t\t.field_bit_size = 7,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"prof_func_id\",\n \t\t.field_bit_size = 7,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE,\n-\t\t.field_operand = {\n-\t\t(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"hdr_sig_id\",\n \t\t.field_bit_size = 5,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"hdr_sig_id\",\n \t\t.field_bit_size = 5,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,\n-\t\t.field_operand = {\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n \t\t\t(BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,\n-\t\t\tBNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t\tBNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff}\n \t\t}\n \t},\n-\t/* class_tid: 1, wh_plus, table: eem.ext_0 */\n+\t/* class_tid: 1, wh_plus, table: em.int_0 */\n \t{\n \t.field_info_mask = {\n \t\t.description = \"spare\",\n-\t\t.field_bit_size = 275,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_bit_size = 3,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"spare\",\n-\t\t.field_bit_size = 275,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_bit_size = 3,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"local_cos\",\n \t\t.field_bit_size = 3,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"local_cos\",\n \t\t.field_bit_size = 3,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"o_l4.dport\",\n \t\t.field_bit_size = 16,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_GLB_HF_O_TCP_DST_PORT >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_O_TCP_DST_PORT & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"o_l4.dport\",\n \t\t.field_bit_size = 16,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_GLB_HF_O_TCP_DST_PORT >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_O_TCP_DST_PORT & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,\n+\t\t.field_cond_opr = {\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,\n+\t\t\t(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"o_l4.sport\",\n \t\t.field_bit_size = 16,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_GLB_HF_O_TCP_SRC_PORT >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_O_TCP_SRC_PORT & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"o_l4.sport\",\n \t\t.field_bit_size = 16,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_GLB_HF_O_TCP_SRC_PORT >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_O_TCP_SRC_PORT & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,\n+\t\t.field_cond_opr = {\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,\n+\t\t\t(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"o_ipv4.ip_proto\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"o_ipv4.ip_proto\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {\n-\t\t\tBNXT_ULP_WH_PLUS_SYM_IP_PROTO_TCP,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,\n+\t\t.field_cond_opr = {\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,\n+\t\t\t(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\tULP_WP_SYM_IP_PROTO_TCP},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr2 = {\n+\t\t\tULP_WP_SYM_IP_PROTO_UDP}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"o_ipv4.dst\",\n \t\t.field_bit_size = 32,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_O_IPV4_DST_ADDR & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"o_ipv4.dst\",\n \t\t.field_bit_size = 32,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_O_IPV4_DST_ADDR & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"o_ipv4.src\",\n \t\t.field_bit_size = 32,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_GLB_HF_O_IPV4_SRC_ADDR >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_O_IPV4_SRC_ADDR & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"o_ipv4.src\",\n \t\t.field_bit_size = 32,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_GLB_HF_O_IPV4_SRC_ADDR >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_O_IPV4_SRC_ADDR & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"o_eth.smac\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff,\n+\t\t\t0xff,\n+\t\t\t0xff,\n+\t\t\t0xff,\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"o_eth.smac\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l2_cntxt_id\",\n \t\t.field_bit_size = 10,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l2_cntxt_id\",\n \t\t.field_bit_size = 10,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t\t.field_operand = {\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t\t.field_opr1 = {\n \t\t\t(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,\n-\t\t\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"em_profile_id\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"em_profile_id\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t\t.field_operand = {\n-\t\t(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,\n-\t\t\tBNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,\n+\t\t\tBNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}\n \t\t}\n \t},\n-\t/* class_tid: 1, wh_plus, table: em.int_0 */\n+\t/* class_tid: 1, wh_plus, table: eem.ext_0 */\n \t{\n \t.field_info_mask = {\n-\t\t.description = \"spare\",\n-\t\t.field_bit_size = 3,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"spare\",\n-\t\t.field_bit_size = 3,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"local_cos\",\n-\t\t.field_bit_size = 3,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"local_cos\",\n-\t\t.field_bit_size = 3,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"o_l4.dport\",\n-\t\t.field_bit_size = 16,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_GLB_HF_O_TCP_DST_PORT >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_O_TCP_DST_PORT & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"o_l4.dport\",\n-\t\t.field_bit_size = 16,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_GLB_HF_O_TCP_DST_PORT >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_O_TCP_DST_PORT & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"o_l4.sport\",\n-\t\t.field_bit_size = 16,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_GLB_HF_O_TCP_SRC_PORT >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_O_TCP_SRC_PORT & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"o_l4.sport\",\n-\t\t.field_bit_size = 16,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_GLB_HF_O_TCP_SRC_PORT >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_O_TCP_SRC_PORT & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"o_ipv4.ip_proto\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"o_ipv4.ip_proto\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {\n-\t\t\tBNXT_ULP_WH_PLUS_SYM_IP_PROTO_TCP,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"o_ipv4.dst\",\n-\t\t.field_bit_size = 32,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_O_IPV4_DST_ADDR & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"o_ipv4.dst\",\n-\t\t.field_bit_size = 32,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_O_IPV4_DST_ADDR & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"o_ipv4.src\",\n-\t\t.field_bit_size = 32,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_GLB_HF_O_IPV4_SRC_ADDR >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_O_IPV4_SRC_ADDR & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"o_ipv4.src\",\n-\t\t.field_bit_size = 32,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_GLB_HF_O_IPV4_SRC_ADDR >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_O_IPV4_SRC_ADDR & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"o_eth.smac\",\n-\t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"o_eth.smac\",\n-\t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"l2_cntxt_id\",\n-\t\t.field_bit_size = 10,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l2_cntxt_id\",\n-\t\t.field_bit_size = 10,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,\n-\t\t\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"em_profile_id\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"em_profile_id\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,\n-\t\t\tBNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t\t}\n-\t},\n-\t/* class_tid: 2, wh_plus, table: l2_cntxt_tcam.0 */\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"l2_ivlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_GLB_HF_OO_VLAN_VID >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_OO_VLAN_VID & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l2_ivlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_GLB_HF_OO_VLAN_VID >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_OO_VLAN_VID & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"l2_ovlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l2_ovlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"mac0_addr\",\n-\t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_GLB_HF_O_ETH_DMAC >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_O_ETH_DMAC & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"mac0_addr\",\n-\t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_GLB_HF_O_ETH_DMAC >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_O_ETH_DMAC & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"svif\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_GLB_HF_SVIF_INDEX >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_SVIF_INDEX & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"svif\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_GLB_HF_SVIF_INDEX >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_SVIF_INDEX & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"sparif\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"sparif\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"tl2_ivlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tl2_ivlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"tl2_ovlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tl2_ovlan_vid\",\n-\t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"mac1_addr\",\n-\t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"mac1_addr\",\n-\t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"l2_num_vtags\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l2_num_vtags\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff,\n-\t\t\tBNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"tl2_num_vtags\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tl2_num_vtags\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"tun_hdr_type\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tun_hdr_type\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"key_type\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"key_type\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"valid\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"valid\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t\t}\n-\t},\n-\t/* class_tid: 2, wh_plus, table: profile_tcam_cache.rd */\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"recycle_cnt\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"recycle_cnt\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"prof_func_id\",\n-\t\t.field_bit_size = 7,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"prof_func_id\",\n-\t\t.field_bit_size = 7,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE,\n-\t\t.field_operand = {\n-\t\t(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"hdr_sig_id\",\n-\t\t.field_bit_size = 5,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"hdr_sig_id\",\n-\t\t.field_bit_size = 5,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,\n-\t\t\tBNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t\t}\n-\t},\n-\t/* class_tid: 2, wh_plus, table: profile_tcam.0 */\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"l4_hdr_is_udp_tcp\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l4_hdr_is_udp_tcp\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"l4_hdr_type\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l4_hdr_type\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"l4_hdr_error\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l4_hdr_error\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"l4_hdr_valid\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l4_hdr_valid\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {\n-\t\t\tBNXT_ULP_WH_PLUS_SYM_L4_HDR_VALID_YES,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"l3_ipv6_cmp_dst\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l3_ipv6_cmp_dst\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"l3_ipv6_cmp_src\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l3_ipv6_cmp_src\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"l3_hdr_isIP\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l3_hdr_isIP\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"l3_hdr_type\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l3_hdr_type\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"l3_hdr_error\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l3_hdr_error\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"l3_hdr_valid\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l3_hdr_valid\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {\n-\t\t\tBNXT_ULP_WH_PLUS_SYM_L3_HDR_VALID_YES,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"l2_two_vtags\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l2_two_vtags\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"l2_vtag_present\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l2_vtag_present\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_CF_IDX_O_ONE_VTAG >> 8) & 0xff,\n-\t\t\tBNXT_ULP_CF_IDX_O_ONE_VTAG & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"l2_uc_mc_bc\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l2_uc_mc_bc\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"l2_hdr_type\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l2_hdr_type\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"l2_hdr_error\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l2_hdr_error\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"l2_hdr_valid\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l2_hdr_valid\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {\n-\t\t\tBNXT_ULP_WH_PLUS_SYM_L2_HDR_VALID_YES,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"tun_hdr_flags\",\n-\t\t.field_bit_size = 3,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tun_hdr_flags\",\n-\t\t.field_bit_size = 3,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"tun_hdr_type\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tun_hdr_type\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"tun_hdr_err\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tun_hdr_err\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"tun_hdr_valid\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tun_hdr_valid\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"tl4_hdr_is_udp_tcp\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tl4_hdr_is_udp_tcp\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"tl4_hdr_type\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tl4_hdr_type\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"tl4_hdr_error\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tl4_hdr_error\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"tl4_hdr_valid\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tl4_hdr_valid\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"tl3_ipv6_cmp_dst\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tl3_ipv6_cmp_dst\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"tl3_ipv6_cmp_src\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tl3_ipv6_cmp_src\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"tl3_hdr_isIP\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tl3_hdr_isIP\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"tl3_hdr_type\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tl3_hdr_type\",\n-\t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"tl3_hdr_error\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tl3_hdr_error\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"tl3_hdr_valid\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tl3_hdr_valid\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"tl2_two_vtags\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tl2_two_vtags\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"tl2_vtag_present\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tl2_vtag_present\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"tl2_uc_mc_bc\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tl2_uc_mc_bc\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"tl2_hdr_type\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tl2_hdr_type\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"tl2_hdr_valid\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"tl2_hdr_valid\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"hrec_next\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"hrec_next\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"reserved\",\n-\t\t.field_bit_size = 9,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"reserved\",\n-\t\t.field_bit_size = 9,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"prof_func_id\",\n-\t\t.field_bit_size = 7,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"prof_func_id\",\n-\t\t.field_bit_size = 7,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE,\n-\t\t.field_operand = {\n-\t\t(BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"agg_error\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"agg_error\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"recycle_cnt\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"recycle_cnt\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"pkt_type_0\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"pkt_type_0\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"pkt_type_1\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"pkt_type_1\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"valid\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"valid\",\n-\t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t\t}\n-\t},\n-\t/* class_tid: 2, wh_plus, table: profile_tcam_cache.wr */\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"recycle_cnt\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"recycle_cnt\",\n-\t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"prof_func_id\",\n-\t\t.field_bit_size = 7,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"prof_func_id\",\n-\t\t.field_bit_size = 7,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE,\n-\t\t.field_operand = {\n-\t\t(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"hdr_sig_id\",\n-\t\t.field_bit_size = 5,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"hdr_sig_id\",\n-\t\t.field_bit_size = 5,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_CF_IDX_HDR_SIG_ID >> 8) & 0xff,\n-\t\t\tBNXT_ULP_CF_IDX_HDR_SIG_ID & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t\t}\n-\t},\n-\t/* class_tid: 2, wh_plus, table: eem.ext_0 */\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"spare\",\n-\t\t.field_bit_size = 275,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n \t\t.description = \"spare\",\n \t\t.field_bit_size = 275,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"local_cos\",\n-\t\t.field_bit_size = 3,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"local_cos\",\n-\t\t.field_bit_size = 3,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"o_l4.dport\",\n-\t\t.field_bit_size = 16,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_GLB_HF_O_TCP_DST_PORT >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_O_TCP_DST_PORT & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"o_l4.dport\",\n-\t\t.field_bit_size = 16,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_GLB_HF_O_TCP_DST_PORT >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_O_TCP_DST_PORT & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"o_l4.sport\",\n-\t\t.field_bit_size = 16,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_GLB_HF_O_TCP_SRC_PORT >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_O_TCP_SRC_PORT & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"o_l4.sport\",\n-\t\t.field_bit_size = 16,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_GLB_HF_O_TCP_SRC_PORT >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_O_TCP_SRC_PORT & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"o_ipv4.ip_proto\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"o_ipv4.ip_proto\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {\n-\t\t\tBNXT_ULP_WH_PLUS_SYM_IP_PROTO_TCP,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"o_ipv4.dst\",\n-\t\t.field_bit_size = 32,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_O_IPV4_DST_ADDR & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"o_ipv4.dst\",\n-\t\t.field_bit_size = 32,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_O_IPV4_DST_ADDR & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"o_ipv4.src\",\n-\t\t.field_bit_size = 32,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"o_ipv4.src\",\n-\t\t.field_bit_size = 32,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"o_eth.smac\",\n-\t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"o_eth.smac\",\n-\t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"l2_cntxt_id\",\n-\t\t.field_bit_size = 10,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"l2_cntxt_id\",\n-\t\t.field_bit_size = 10,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,\n-\t\t\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t\t}\n-\t},\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"em_profile_id\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n-\t\t},\n-\t.field_info_spec = {\n-\t\t.description = \"em_profile_id\",\n-\t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,\n-\t\t\tBNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t\t}\n-\t},\n-\t/* class_tid: 2, wh_plus, table: em.int_0 */\n-\t{\n-\t.field_info_mask = {\n-\t\t.description = \"spare\",\n-\t\t.field_bit_size = 3,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"spare\",\n-\t\t.field_bit_size = 3,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_bit_size = 275,\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"local_cos\",\n \t\t.field_bit_size = 3,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"local_cos\",\n \t\t.field_bit_size = 3,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"o_l4.dport\",\n \t\t.field_bit_size = 16,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_GLB_HF_O_TCP_DST_PORT >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_O_TCP_DST_PORT & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"o_l4.dport\",\n \t\t.field_bit_size = 16,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_GLB_HF_O_TCP_DST_PORT >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_O_TCP_DST_PORT & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,\n+\t\t.field_cond_opr = {\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,\n+\t\t\t(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_UDP_DST_PORT & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"o_l4.sport\",\n \t\t.field_bit_size = 16,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_GLB_HF_O_TCP_SRC_PORT >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_O_TCP_SRC_PORT & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"o_l4.sport\",\n \t\t.field_bit_size = 16,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_GLB_HF_O_TCP_SRC_PORT >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_O_TCP_SRC_PORT & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,\n+\t\t.field_cond_opr = {\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,\n+\t\t\t(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT & 0xff},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr2 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_UDP_SRC_PORT & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"o_ipv4.ip_proto\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"o_ipv4.ip_proto\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {\n-\t\t\tBNXT_ULP_WH_PLUS_SYM_IP_PROTO_TCP,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_HDR_BIT,\n+\t\t.field_cond_opr = {\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 56) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 48) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 40) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 32) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 24) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 16) & 0xff,\n+\t\t\t((uint64_t)BNXT_ULP_HDR_BIT_O_TCP >> 8) & 0xff,\n+\t\t\t(uint64_t)BNXT_ULP_HDR_BIT_O_TCP & 0xff},\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\tULP_WP_SYM_IP_PROTO_TCP},\n+\t\t.field_src2 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr2 = {\n+\t\t\tULP_WP_SYM_IP_PROTO_UDP}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"o_ipv4.dst\",\n \t\t.field_bit_size = 32,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_O_IPV4_DST_ADDR & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"o_ipv4.dst\",\n \t\t.field_bit_size = 32,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_HDR_FIELD,\n-\t\t.field_operand = {\n-\t\t\t(BNXT_ULP_GLB_HF_O_IPV4_DST_ADDR >> 8) & 0xff,\n-\t\t\tBNXT_ULP_GLB_HF_O_IPV4_DST_ADDR & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV4_DST_ADDR & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"o_ipv4.src\",\n \t\t.field_bit_size = 32,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"o_ipv4.src\",\n \t\t.field_bit_size = 32,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_HF,\n+\t\t.field_opr1 = {\n+\t\t\t(BNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR >> 8) & 0xff,\n+\t\t\tBNXT_ULP_GLB_HF_ID_O_IPV4_SRC_ADDR & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"o_eth.smac\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff,\n+\t\t\t0xff,\n+\t\t\t0xff,\n+\t\t\t0xff,\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"o_eth.smac\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l2_cntxt_id\",\n \t\t.field_bit_size = 10,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l2_cntxt_id\",\n \t\t.field_bit_size = 10,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t\t.field_operand = {\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t\t.field_opr1 = {\n \t\t\t(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,\n-\t\t\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"em_profile_id\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"em_profile_id\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t\t.field_operand = {\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t\t.field_opr1 = {\n \t\t\t(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,\n-\t\t\tBNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t\tBNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}\n \t\t}\n \t},\n-\t/* class_tid: 3, wh_plus, table: l2_cntxt_tcam.0 */\n+\t/* class_tid: 2, wh_plus, table: l2_cntxt_tcam.0 */\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l2_ivlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l2_ivlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l2_ovlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l2_ovlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"mac0_addr\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"mac0_addr\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"svif\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"svif\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,\n-\t\t.field_operand = {\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n \t\t\t(BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff,\n-\t\t\tBNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t\tBNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"sparif\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"sparif\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl2_ivlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl2_ivlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl2_ovlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl2_ovlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"mac1_addr\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"mac1_addr\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l2_num_vtags\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l2_num_vtags\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl2_num_vtags\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl2_num_vtags\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tun_hdr_type\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tun_hdr_type\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"key_type\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"key_type\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"valid\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"valid\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t1}\n \t\t}\n \t},\n-\t/* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.wr */\n+\t/* class_tid: 2, wh_plus, table: l2_cntxt_tcam_cache.wr */\n \t{\n \t.field_info_mask = {\n \t\t.description = \"svif\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"svif\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,\n-\t\t.field_operand = {\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n \t\t\t(BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff,\n-\t\t\tBNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t\tBNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff}\n \t\t}\n \t},\n-\t/* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.vfr_0 */\n+\t/* class_tid: 3, wh_plus, table: l2_cntxt_tcam_bypass.vfr_0 */\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l2_ivlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l2_ivlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l2_ovlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l2_ovlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"mac0_addr\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"mac0_addr\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"svif\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"svif\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,\n-\t\t.field_operand = {\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n \t\t\t(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,\n-\t\t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"sparif\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"sparif\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl2_ivlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl2_ivlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl2_ovlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl2_ovlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"mac1_addr\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"mac1_addr\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l2_num_vtags\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l2_num_vtags\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl2_num_vtags\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl2_num_vtags\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tun_hdr_type\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tun_hdr_type\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"key_type\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"key_type\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"valid\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"valid\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t1}\n \t\t}\n \t},\n-\t/* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.rd */\n+\t/* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.rd */\n \t{\n \t.field_info_mask = {\n \t\t.description = \"svif\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"svif\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,\n-\t\t.field_operand = {\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n \t\t\t(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,\n-\t\t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}\n \t\t}\n \t},\n-\t/* class_tid: 4, wh_plus, table: l2_cntxt_tcam.0 */\n+\t/* class_tid: 3, wh_plus, table: l2_cntxt_tcam.0 */\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l2_ivlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l2_ivlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l2_ovlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l2_ovlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"mac0_addr\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"mac0_addr\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"svif\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"svif\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,\n-\t\t.field_operand = {\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n \t\t\t(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,\n-\t\t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"sparif\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"sparif\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl2_ivlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl2_ivlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl2_ovlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl2_ovlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"mac1_addr\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"mac1_addr\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l2_num_vtags\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l2_num_vtags\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl2_num_vtags\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl2_num_vtags\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tun_hdr_type\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tun_hdr_type\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"key_type\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"key_type\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"valid\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"valid\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t1}\n \t\t}\n \t},\n-\t/* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.wr */\n+\t/* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.wr */\n \t{\n \t.field_info_mask = {\n \t\t.description = \"svif\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"svif\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,\n-\t\t.field_operand = {\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n \t\t\t(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,\n-\t\t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}\n \t\t}\n \t},\n-\t/* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.egr0 */\n+\t/* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.egr0 */\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l2_ivlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l2_ivlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l2_ovlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l2_ovlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"mac0_addr\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"mac0_addr\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"svif\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"svif\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,\n-\t\t.field_operand = {\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n \t\t\t(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,\n-\t\t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"sparif\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"sparif\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl2_ivlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl2_ivlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl2_ovlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl2_ovlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"mac1_addr\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"mac1_addr\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l2_num_vtags\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l2_num_vtags\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl2_num_vtags\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl2_num_vtags\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tun_hdr_type\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tun_hdr_type\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"key_type\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"key_type\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"valid\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"valid\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t1}\n \t\t}\n \t},\n-\t/* class_tid: 5, wh_plus, table: l2_cntxt_tcam_cache.wr_egr0 */\n+\t/* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.wr_egr0 */\n \t{\n \t.field_info_mask = {\n \t\t.description = \"svif\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"svif\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,\n-\t\t.field_operand = {\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n \t\t\t(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,\n-\t\t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}\n \t\t}\n \t},\n-\t/* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.dtagged_ing0 */\n+\t/* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.dtagged_ing0 */\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l2_ivlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l2_ivlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l2_ovlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l2_ovlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,\n-\t\t.field_operand = {\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n \t\t\t(BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,\n-\t\t\tBNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t\tBNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"mac0_addr\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"mac0_addr\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"svif\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"svif\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,\n-\t\t.field_operand = {\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n \t\t\t(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,\n-\t\t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"sparif\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"sparif\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl2_ivlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl2_ivlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl2_ovlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl2_ovlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"mac1_addr\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"mac1_addr\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l2_num_vtags\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l2_num_vtags\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t2}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl2_num_vtags\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl2_num_vtags\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tun_hdr_type\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tun_hdr_type\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {\n-\t\t\tBNXT_ULP_WH_PLUS_SYM_TUN_HDR_TYPE_NONE,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\tULP_WP_SYM_TUN_HDR_TYPE_NONE}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"key_type\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"key_type\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"valid\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"valid\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t1}\n \t\t}\n \t},\n-\t/* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.stagged_ing0 */\n+\t/* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.stagged_ing0 */\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l2_ivlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff,\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l2_ivlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,\n-\t\t.field_operand = {\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n \t\t\t(BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,\n-\t\t\tBNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t\tBNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l2_ovlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l2_ovlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"mac0_addr\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"mac0_addr\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"svif\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"svif\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,\n-\t\t.field_operand = {\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n \t\t\t(BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,\n-\t\t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t\tBNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"sparif\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"sparif\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl2_ivlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl2_ivlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl2_ovlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl2_ovlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"mac1_addr\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"mac1_addr\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l2_num_vtags\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l2_num_vtags\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t1}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl2_num_vtags\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl2_num_vtags\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tun_hdr_type\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tun_hdr_type\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {\n-\t\t\tBNXT_ULP_WH_PLUS_SYM_TUN_HDR_TYPE_NONE,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\tULP_WP_SYM_TUN_HDR_TYPE_NONE}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"key_type\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"key_type\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"valid\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"valid\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t1}\n \t\t}\n \t},\n-\t/* class_tid: 6, wh_plus, table: l2_cntxt_tcam.egr */\n+\t/* class_tid: 5, wh_plus, table: l2_cntxt_tcam.egr */\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l2_ivlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l2_ivlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l2_ovlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l2_ovlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"mac0_addr\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"mac0_addr\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"svif\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"svif\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,\n-\t\t.field_operand = {\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n \t\t\t(BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,\n-\t\t\tBNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t\tBNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"sparif\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"sparif\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl2_ivlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl2_ivlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl2_ovlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl2_ovlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"mac1_addr\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"mac1_addr\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l2_num_vtags\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l2_num_vtags\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl2_num_vtags\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl2_num_vtags\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tun_hdr_type\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tun_hdr_type\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"key_type\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"key_type\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"valid\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"valid\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t1}\n \t\t}\n \t},\n-\t/* class_tid: 6, wh_plus, table: l2_cntxt_tcam_cache.egr_wr */\n+\t/* class_tid: 5, wh_plus, table: l2_cntxt_tcam_cache.egr_wr */\n \t{\n \t.field_info_mask = {\n \t\t.description = \"svif\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"svif\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,\n-\t\t.field_operand = {\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n \t\t\t(BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,\n-\t\t\tBNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t\tBNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}\n \t\t}\n \t},\n-\t/* class_tid: 6, wh_plus, table: l2_cntxt_tcam_bypass.ing */\n+\t/* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.ing */\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l2_ivlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l2_ivlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l2_ovlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l2_ovlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"mac0_addr\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"mac0_addr\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"svif\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"svif\",\n \t\t.field_bit_size = 8,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,\n-\t\t.field_operand = {\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t\t.field_opr1 = {\n \t\t\t(BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,\n-\t\t\tBNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t\tBNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff}\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"sparif\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"sparif\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl2_ivlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl2_ivlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl2_ovlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl2_ovlan_vid\",\n \t\t.field_bit_size = 12,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"mac1_addr\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"mac1_addr\",\n \t\t.field_bit_size = 48,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"l2_num_vtags\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"l2_num_vtags\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tl2_num_vtags\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tl2_num_vtags\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"tun_hdr_type\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"tun_hdr_type\",\n \t\t.field_bit_size = 4,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"key_type\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"key_type\",\n \t\t.field_bit_size = 2,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t\t}\n \t},\n \t{\n \t.field_info_mask = {\n \t\t.description = \"valid\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n-\t\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t0xff}\n \t\t},\n \t.field_info_spec = {\n \t\t.description = \"valid\",\n \t\t.field_bit_size = 1,\n-\t\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t\t.field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t\t.field_opr1 = {\n+\t\t\t1}\n \t\t}\n \t}\n };\n@@ -5029,2380 +4122,2308 @@ struct bnxt_ulp_mapper_field_info ulp_wh_plus_class_result_field_list[] = {\n \t{\n \t.description = \"l2_cntxt_id\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}\n \t},\n \t{\n \t.description = \"prof_func_id\",\n \t.field_bit_size = 7,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff}\n \t},\n \t{\n \t.description = \"l2_byp_lkup_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"parif\",\n \t.field_bit_size = 4,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}\n \t},\n \t{\n \t.description = \"allowed_pri\",\n \t.field_bit_size = 8,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"default_pri\",\n \t.field_bit_size = 3,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"allowed_tpid\",\n \t.field_bit_size = 6,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"default_tpid\",\n \t.field_bit_size = 3,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"bd_act_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"sp_rec_ptr\",\n \t.field_bit_size = 16,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"byp_sp_lkup\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t1}\n \t},\n \t{\n \t.description = \"pri_anti_spoof_ctl\",\n \t.field_bit_size = 2,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tpid_anti_spoof_ctl\",\n \t.field_bit_size = 2,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t/* class_tid: 1, wh_plus, table: profile_tcam.0 */\n \t{\n \t.description = \"wc_key_id\",\n \t.field_bit_size = 4,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t3}\n \t},\n \t{\n \t.description = \"wc_profile_id\",\n \t.field_bit_size = 8,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"wc_search_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"em_key_mask\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {\n-\t\t(0x007d >> 8) & 0xff,\n-\t\t0x007d & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t(125 >> 8) & 0xff,\n+\t\t125 & 0xff}\n \t},\n \t{\n \t.description = \"em_key_id\",\n \t.field_bit_size = 5,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t3}\n \t},\n \t{\n \t.description = \"em_profile_id\",\n \t.field_bit_size = 8,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}\n \t},\n \t{\n \t.description = \"em_search_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t1}\n \t},\n \t{\n \t.description = \"pl_byp_lkup_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t/* class_tid: 1, wh_plus, table: profile_tcam_cache.wr */\n \t{\n \t.description = \"rid\",\n \t.field_bit_size = 32,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_RF_IDX_RID >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_RID & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_RF_IDX_RID & 0xff}\n \t},\n \t{\n \t.description = \"profile_tcam_index\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff}\n \t},\n \t{\n \t.description = \"em_profile_id\",\n \t.field_bit_size = 8,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff}\n \t},\n \t{\n \t.description = \"wm_profile_id\",\n \t.field_bit_size = 8,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"flow_sig_id\",\n \t.field_bit_size = 8,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t},\n-\t/* class_tid: 1, wh_plus, table: eem.ext_0 */\n-\t{\n-\t.description = \"act_rec_ptr\",\n-\t.field_bit_size = 33,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n-\t\t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t},\n-\t{\n-\t.description = \"ext_flow_cntr\",\n-\t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t},\n-\t{\n-\t.description = \"act_rec_int\",\n-\t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {\n-\t\tBNXT_ULP_WH_PLUS_SYM_EEM_ACT_REC_INT,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t},\n-\t{\n-\t.description = \"act_rec_size\",\n-\t.field_bit_size = 5,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n-\t\t(BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t},\n-\t{\n-\t.description = \"key_size\",\n-\t.field_bit_size = 9,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {\n-\t\t(0x00ad >> 8) & 0xff,\n-\t\t0x00ad & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t},\n-\t{\n-\t.description = \"reserved\",\n-\t.field_bit_size = 11,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t},\n-\t{\n-\t.description = \"strength\",\n-\t.field_bit_size = 2,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t},\n-\t{\n-\t.description = \"l1_cacheable\",\n-\t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t},\n-\t{\n-\t.description = \"valid\",\n-\t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff}\n \t},\n \t/* class_tid: 1, wh_plus, table: em.int_0 */\n \t{\n \t.description = \"act_rec_ptr\",\n \t.field_bit_size = 33,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n \t},\n \t{\n \t.description = \"ext_flow_cntr\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"act_rec_int\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"act_rec_size\",\n \t.field_bit_size = 5,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"key_size\",\n \t.field_bit_size = 9,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"reserved\",\n \t.field_bit_size = 11,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"strength\",\n \t.field_bit_size = 2,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t3}\n \t},\n \t{\n \t.description = \"l1_cacheable\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"valid\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t},\n-\t/* class_tid: 2, wh_plus, table: l2_cntxt_tcam.0 */\n-\t{\n-\t.description = \"l2_cntxt_id\",\n-\t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n-\t\t(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t},\n-\t{\n-\t.description = \"prof_func_id\",\n-\t.field_bit_size = 7,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE,\n-\t.field_operand = {\n-\t\t(BNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_RF_IDX_L2_PROF_FUNC_ID & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t},\n-\t{\n-\t.description = \"l2_byp_lkup_en\",\n-\t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t},\n-\t{\n-\t.description = \"parif\",\n-\t.field_bit_size = 4,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,\n-\t.field_operand = {\n-\t\t(BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t},\n-\t{\n-\t.description = \"allowed_pri\",\n-\t.field_bit_size = 8,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t},\n-\t{\n-\t.description = \"default_pri\",\n-\t.field_bit_size = 3,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t},\n-\t{\n-\t.description = \"allowed_tpid\",\n-\t.field_bit_size = 6,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t},\n-\t{\n-\t.description = \"default_tpid\",\n-\t.field_bit_size = 3,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t},\n-\t{\n-\t.description = \"bd_act_en\",\n-\t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t},\n-\t{\n-\t.description = \"sp_rec_ptr\",\n-\t.field_bit_size = 16,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t},\n-\t{\n-\t.description = \"byp_sp_lkup\",\n-\t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t},\n-\t{\n-\t.description = \"pri_anti_spoof_ctl\",\n-\t.field_bit_size = 2,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t},\n-\t{\n-\t.description = \"tpid_anti_spoof_ctl\",\n-\t.field_bit_size = 2,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t},\n-\t/* class_tid: 2, wh_plus, table: profile_tcam.0 */\n-\t{\n-\t.description = \"wc_key_id\",\n-\t.field_bit_size = 4,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t},\n-\t{\n-\t.description = \"wc_profile_id\",\n-\t.field_bit_size = 8,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t},\n-\t{\n-\t.description = \"wc_search_en\",\n-\t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t},\n-\t{\n-\t.description = \"em_key_mask\",\n-\t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {\n-\t\t(0x0079 >> 8) & 0xff,\n-\t\t0x0079 & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t},\n-\t{\n-\t.description = \"em_key_id\",\n-\t.field_bit_size = 5,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t},\n-\t{\n-\t.description = \"em_profile_id\",\n-\t.field_bit_size = 8,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n-\t\t(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t},\n-\t{\n-\t.description = \"em_search_en\",\n-\t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t},\n-\t{\n-\t.description = \"pl_byp_lkup_en\",\n-\t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t},\n-\t/* class_tid: 2, wh_plus, table: profile_tcam_cache.wr */\n-\t{\n-\t.description = \"rid\",\n-\t.field_bit_size = 32,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n-\t\t(BNXT_ULP_RF_IDX_RID >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_RID & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t},\n-\t{\n-\t.description = \"profile_tcam_index\",\n-\t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n-\t\t(BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0 & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t},\n-\t{\n-\t.description = \"em_profile_id\",\n-\t.field_bit_size = 8,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n-\t\t(BNXT_ULP_RF_IDX_EM_PROFILE_ID_0 >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_EM_PROFILE_ID_0 & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t},\n-\t{\n-\t.description = \"wm_profile_id\",\n-\t.field_bit_size = 8,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t},\n-\t{\n-\t.description = \"flow_sig_id\",\n-\t.field_bit_size = 8,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,\n-\t.field_operand = {\n-\t\t(BNXT_ULP_CF_IDX_FLOW_SIG_ID >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_FLOW_SIG_ID & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t1}\n \t},\n-\t/* class_tid: 2, wh_plus, table: eem.ext_0 */\n+\t/* class_tid: 1, wh_plus, table: eem.ext_0 */\n \t{\n \t.description = \"act_rec_ptr\",\n \t.field_bit_size = 33,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n \t},\n \t{\n \t.description = \"ext_flow_cntr\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"act_rec_int\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {\n-\t\tBNXT_ULP_WH_PLUS_SYM_EEM_ACT_REC_INT,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\tULP_WP_SYM_EEM_ACT_REC_INT}\n \t},\n \t{\n \t.description = \"act_rec_size\",\n \t.field_bit_size = 5,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_RF_IDX_ACTION_REC_SIZE >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t},\n-\t{\n-\t.description = \"key_size\",\n-\t.field_bit_size = 9,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {\n-\t\t(0x00ad >> 8) & 0xff,\n-\t\t0x00ad & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t},\n-\t{\n-\t.description = \"reserved\",\n-\t.field_bit_size = 11,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t},\n-\t{\n-\t.description = \"strength\",\n-\t.field_bit_size = 2,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t},\n-\t{\n-\t.description = \"l1_cacheable\",\n-\t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t},\n-\t{\n-\t.description = \"valid\",\n-\t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t},\n-\t/* class_tid: 2, wh_plus, table: em.int_0 */\n-\t{\n-\t.description = \"act_rec_ptr\",\n-\t.field_bit_size = 33,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n-\t\t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n-\t},\n-\t{\n-\t.description = \"ext_flow_cntr\",\n-\t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t},\n-\t{\n-\t.description = \"act_rec_int\",\n-\t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n-\t},\n-\t{\n-\t.description = \"act_rec_size\",\n-\t.field_bit_size = 5,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t\tBNXT_ULP_RF_IDX_ACTION_REC_SIZE & 0xff}\n \t},\n \t{\n \t.description = \"key_size\",\n \t.field_bit_size = 9,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t(173 >> 8) & 0xff,\n+\t\t173 & 0xff}\n \t},\n \t{\n \t.description = \"reserved\",\n \t.field_bit_size = 11,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"strength\",\n \t.field_bit_size = 2,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t3}\n \t},\n \t{\n \t.description = \"l1_cacheable\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"valid\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t1}\n \t},\n-\t/* class_tid: 3, wh_plus, table: int_full_act_record.0 */\n+\t/* class_tid: 2, wh_plus, table: int_full_act_record.0 */\n \t{\n \t.description = \"flow_cntr_ptr\",\n \t.field_bit_size = 14,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"age_enable\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"agg_cntr_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"rate_cntr_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"flow_cntr_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tcpflags_key\",\n \t.field_bit_size = 8,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tcpflags_mir\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tcpflags_match\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"encap_ptr\",\n \t.field_bit_size = 11,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"dst_ip_ptr\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tcp_dst_port\",\n \t.field_bit_size = 16,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"src_ip_ptr\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tcp_src_port\",\n \t.field_bit_size = 16,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"meter_id\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"l3_rdir\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tl3_rdir\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"l3_ttl_dec\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tl3_ttl_dec\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"decap_func\",\n \t.field_bit_size = 4,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"vnic_or_vport\",\n \t.field_bit_size = 12,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_CF_IDX_DRV_FUNC_VNIC >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff}\n \t},\n \t{\n \t.description = \"pop_vlan\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"meter\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"mirror\",\n \t.field_bit_size = 2,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"drop\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"hit\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"type\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 3, wh_plus, table: l2_cntxt_tcam.0 */\n+\t/* class_tid: 2, wh_plus, table: l2_cntxt_tcam.0 */\n \t{\n \t.description = \"l2_cntxt_id\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}\n \t},\n \t{\n \t.description = \"prof_func_id\",\n \t.field_bit_size = 7,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}\n \t},\n \t{\n \t.description = \"l2_byp_lkup_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"parif\",\n \t.field_bit_size = 4,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff}\n \t},\n \t{\n \t.description = \"allowed_pri\",\n \t.field_bit_size = 8,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"default_pri\",\n \t.field_bit_size = 3,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"allowed_tpid\",\n \t.field_bit_size = 6,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"default_tpid\",\n \t.field_bit_size = 3,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"bd_act_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"sp_rec_ptr\",\n \t.field_bit_size = 16,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"byp_sp_lkup\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t1}\n \t},\n \t{\n \t.description = \"pri_anti_spoof_ctl\",\n \t.field_bit_size = 2,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tpid_anti_spoof_ctl\",\n \t.field_bit_size = 2,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.wr */\n+\t/* class_tid: 2, wh_plus, table: l2_cntxt_tcam_cache.wr */\n \t{\n \t.description = \"rid\",\n \t.field_bit_size = 32,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_RF_IDX_RID >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_RID & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_RF_IDX_RID & 0xff}\n \t},\n \t{\n \t.description = \"l2_cntxt_tcam_index\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff}\n \t},\n \t{\n \t.description = \"l2_cntxt_id\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}\n \t},\n \t{\n \t.description = \"src_property_ptr\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 3, wh_plus, table: parif_def_lkup_arec_ptr.0 */\n+\t/* class_tid: 2, wh_plus, table: parif_def_lkup_arec_ptr.0 */\n \t{\n \t.description = \"act_rec_ptr\",\n \t.field_bit_size = 32,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n \t},\n-\t/* class_tid: 3, wh_plus, table: parif_def_arec_ptr.0 */\n+\t/* class_tid: 2, wh_plus, table: parif_def_arec_ptr.0 */\n \t{\n \t.description = \"act_rec_ptr\",\n \t.field_bit_size = 32,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n \t},\n-\t/* class_tid: 3, wh_plus, table: parif_def_err_arec_ptr.0 */\n+\t/* class_tid: 2, wh_plus, table: parif_def_err_arec_ptr.0 */\n \t{\n \t.description = \"act_rec_ptr\",\n \t.field_bit_size = 32,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n \t},\n-\t/* class_tid: 4, wh_plus, table: int_full_act_record.0 */\n+\t/* class_tid: 3, wh_plus, table: int_full_act_record.0 */\n \t{\n \t.description = \"flow_cntr_ptr\",\n \t.field_bit_size = 14,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"age_enable\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"agg_cntr_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"rate_cntr_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"flow_cntr_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tcpflags_key\",\n \t.field_bit_size = 8,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tcpflags_mir\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tcpflags_match\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"encap_ptr\",\n \t.field_bit_size = 11,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"dst_ip_ptr\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tcp_dst_port\",\n \t.field_bit_size = 16,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"src_ip_ptr\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tcp_src_port\",\n \t.field_bit_size = 16,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"meter_id\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"l3_rdir\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tl3_rdir\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"l3_ttl_dec\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tl3_ttl_dec\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"decap_func\",\n \t.field_bit_size = 4,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"vnic_or_vport\",\n \t.field_bit_size = 12,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_CF_IDX_PHY_PORT_VPORT >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_PHY_PORT_VPORT & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_CF_IDX_PHY_PORT_VPORT & 0xff}\n \t},\n \t{\n \t.description = \"pop_vlan\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"meter\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"mirror\",\n \t.field_bit_size = 2,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"drop\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"hit\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"type\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.vfr_0 */\n+\t/* class_tid: 3, wh_plus, table: l2_cntxt_tcam_bypass.vfr_0 */\n \t{\n \t.description = \"act_record_ptr\",\n \t.field_bit_size = 16,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"reserved\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"l2_byp_lkup_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t1}\n \t},\n \t{\n \t.description = \"parif\",\n \t.field_bit_size = 4,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff}\n \t},\n \t{\n \t.description = \"allowed_pri\",\n \t.field_bit_size = 8,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"default_pri\",\n \t.field_bit_size = 3,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"allowed_tpid\",\n \t.field_bit_size = 6,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"default_tpid\",\n \t.field_bit_size = 3,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"bd_act_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t1}\n \t},\n \t{\n \t.description = \"sp_rec_ptr\",\n \t.field_bit_size = 16,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"byp_sp_lkup\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t1}\n \t},\n \t{\n \t.description = \"pri_anti_spoof_ctl\",\n \t.field_bit_size = 2,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tpid_anti_spoof_ctl\",\n \t.field_bit_size = 2,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 4, wh_plus, table: l2_cntxt_tcam.0 */\n+\t/* class_tid: 3, wh_plus, table: l2_cntxt_tcam.0 */\n \t{\n \t.description = \"l2_cntxt_id\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}\n \t},\n \t{\n \t.description = \"prof_func_id\",\n \t.field_bit_size = 7,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}\n \t},\n \t{\n \t.description = \"l2_byp_lkup_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"parif\",\n \t.field_bit_size = 4,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_CF_IDX_DRV_FUNC_PARIF >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_CF_IDX_DRV_FUNC_PARIF & 0xff}\n \t},\n \t{\n \t.description = \"allowed_pri\",\n \t.field_bit_size = 8,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"default_pri\",\n \t.field_bit_size = 3,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"allowed_tpid\",\n \t.field_bit_size = 6,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"default_tpid\",\n \t.field_bit_size = 3,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"bd_act_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"sp_rec_ptr\",\n \t.field_bit_size = 16,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"byp_sp_lkup\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t1}\n \t},\n \t{\n \t.description = \"pri_anti_spoof_ctl\",\n \t.field_bit_size = 2,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tpid_anti_spoof_ctl\",\n \t.field_bit_size = 2,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.wr */\n+\t/* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.wr */\n \t{\n \t.description = \"rid\",\n \t.field_bit_size = 32,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_RF_IDX_RID >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_RID & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_RF_IDX_RID & 0xff}\n \t},\n \t{\n \t.description = \"l2_cntxt_tcam_index\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff}\n \t},\n \t{\n \t.description = \"l2_cntxt_id\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}\n \t},\n \t{\n \t.description = \"src_property_ptr\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 4, wh_plus, table: parif_def_lkup_arec_ptr.0 */\n+\t/* class_tid: 3, wh_plus, table: parif_def_lkup_arec_ptr.0 */\n \t{\n \t.description = \"act_rec_ptr\",\n \t.field_bit_size = 32,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n \t},\n-\t/* class_tid: 4, wh_plus, table: parif_def_arec_ptr.0 */\n+\t/* class_tid: 3, wh_plus, table: parif_def_arec_ptr.0 */\n \t{\n \t.description = \"act_rec_ptr\",\n \t.field_bit_size = 32,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n \t},\n-\t/* class_tid: 4, wh_plus, table: parif_def_err_arec_ptr.0 */\n+\t/* class_tid: 3, wh_plus, table: parif_def_err_arec_ptr.0 */\n \t{\n \t.description = \"act_rec_ptr\",\n \t.field_bit_size = 32,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n \t},\n-\t/* class_tid: 5, wh_plus, table: int_vtag_encap_record.egr0 */\n+\t/* class_tid: 4, wh_plus, table: int_vtag_encap_record.egr0 */\n \t{\n \t.description = \"ecv_tun_type\",\n \t.field_bit_size = 3,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"ecv_l4_type\",\n \t.field_bit_size = 3,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"ecv_l3_type\",\n \t.field_bit_size = 3,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"ecv_l2_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"ecv_vtag_type\",\n \t.field_bit_size = 4,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {\n-\t\tBNXT_ULP_WH_PLUS_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\tULP_WP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI}\n \t},\n \t{\n \t.description = \"ecv_custom_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"ecv_valid\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"vtag_tpid\",\n \t.field_bit_size = 16,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {0x81, 0x00}\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t0x81,\n+\t\t0x00}\n \t},\n \t{\n \t.description = \"vtag_vid\",\n \t.field_bit_size = 12,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff}\n \t},\n \t{\n \t.description = \"vtag_de\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"vtag_pcp\",\n \t.field_bit_size = 3,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"spare\",\n \t.field_bit_size = 80,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 5, wh_plus, table: int_full_act_record.egr0 */\n+\t/* class_tid: 4, wh_plus, table: int_full_act_record.egr0 */\n \t{\n \t.description = \"flow_cntr_ptr\",\n \t.field_bit_size = 14,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"age_enable\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"agg_cntr_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"rate_cntr_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"flow_cntr_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tcpflags_key\",\n \t.field_bit_size = 8,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tcpflags_mir\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tcpflags_match\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"encap_ptr\",\n \t.field_bit_size = 11,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff}\n \t},\n \t{\n \t.description = \"dst_ip_ptr\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tcp_dst_port\",\n \t.field_bit_size = 16,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"src_ip_ptr\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tcp_src_port\",\n \t.field_bit_size = 16,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"meter_id\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"l3_rdir\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tl3_rdir\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"l3_ttl_dec\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tl3_ttl_dec\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"decap_func\",\n \t.field_bit_size = 4,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"vnic_or_vport\",\n \t.field_bit_size = 12,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {\n-\t\t(BNXT_ULP_WH_PLUS_SYM_LOOPBACK_PORT >> 8) & 0xff,\n-\t\tBNXT_ULP_WH_PLUS_SYM_LOOPBACK_PORT & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t(ULP_WP_SYM_LOOPBACK_PORT >> 8) & 0xff,\n+\t\tULP_WP_SYM_LOOPBACK_PORT & 0xff}\n \t},\n \t{\n \t.description = \"pop_vlan\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"meter\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"mirror\",\n \t.field_bit_size = 2,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"drop\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"hit\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"type\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.egr0 */\n+\t/* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.egr0 */\n \t{\n \t.description = \"act_record_ptr\",\n \t.field_bit_size = 16,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"reserved\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"l2_byp_lkup_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t1}\n \t},\n \t{\n \t.description = \"parif\",\n \t.field_bit_size = 4,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"allowed_pri\",\n \t.field_bit_size = 8,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"default_pri\",\n \t.field_bit_size = 3,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"allowed_tpid\",\n \t.field_bit_size = 6,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"default_tpid\",\n \t.field_bit_size = 3,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"bd_act_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t1}\n \t},\n \t{\n \t.description = \"sp_rec_ptr\",\n \t.field_bit_size = 16,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"byp_sp_lkup\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t1}\n \t},\n \t{\n \t.description = \"pri_anti_spoof_ctl\",\n \t.field_bit_size = 2,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tpid_anti_spoof_ctl\",\n \t.field_bit_size = 2,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 5, wh_plus, table: l2_cntxt_tcam_cache.wr_egr0 */\n+\t/* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.wr_egr0 */\n \t{\n \t.description = \"rid\",\n \t.field_bit_size = 32,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_RF_IDX_RID >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_RID & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_RF_IDX_RID & 0xff}\n \t},\n \t{\n \t.description = \"l2_cntxt_tcam_index\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff}\n \t},\n \t{\n \t.description = \"l2_cntxt_id\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"src_property_ptr\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 5, wh_plus, table: int_full_act_record.ing0 */\n+\t/* class_tid: 4, wh_plus, table: int_full_act_record.ing0 */\n \t{\n \t.description = \"flow_cntr_ptr\",\n \t.field_bit_size = 14,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"age_enable\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"agg_cntr_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"rate_cntr_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"flow_cntr_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tcpflags_key\",\n \t.field_bit_size = 8,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tcpflags_mir\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tcpflags_match\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"encap_ptr\",\n \t.field_bit_size = 11,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"dst_ip_ptr\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tcp_dst_port\",\n \t.field_bit_size = 16,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"src_ip_ptr\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tcp_src_port\",\n \t.field_bit_size = 16,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"meter_id\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"l3_rdir\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tl3_rdir\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"l3_ttl_dec\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tl3_ttl_dec\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"decap_func\",\n \t.field_bit_size = 4,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"vnic_or_vport\",\n \t.field_bit_size = 12,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_CF_IDX_VF_FUNC_VNIC >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_VF_FUNC_VNIC & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_CF_IDX_VF_FUNC_VNIC & 0xff}\n \t},\n \t{\n \t.description = \"pop_vlan\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t1}\n \t},\n \t{\n \t.description = \"meter\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"mirror\",\n \t.field_bit_size = 2,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"drop\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"hit\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"type\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.dtagged_ing0 */\n+\t/* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.dtagged_ing0 */\n \t{\n \t.description = \"act_record_ptr\",\n \t.field_bit_size = 16,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n \t},\n \t{\n \t.description = \"reserved\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"l2_byp_lkup_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t1}\n \t},\n \t{\n \t.description = \"parif\",\n \t.field_bit_size = 4,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"allowed_pri\",\n \t.field_bit_size = 8,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"default_pri\",\n \t.field_bit_size = 3,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"allowed_tpid\",\n \t.field_bit_size = 6,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"default_tpid\",\n \t.field_bit_size = 3,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"bd_act_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"sp_rec_ptr\",\n \t.field_bit_size = 16,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"byp_sp_lkup\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t1}\n \t},\n \t{\n \t.description = \"pri_anti_spoof_ctl\",\n \t.field_bit_size = 2,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tpid_anti_spoof_ctl\",\n \t.field_bit_size = 2,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.stagged_ing0 */\n+\t/* class_tid: 4, wh_plus, table: l2_cntxt_tcam_bypass.stagged_ing0 */\n \t{\n \t.description = \"act_record_ptr\",\n \t.field_bit_size = 16,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n \t},\n \t{\n \t.description = \"reserved\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"l2_byp_lkup_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t1}\n \t},\n \t{\n \t.description = \"parif\",\n \t.field_bit_size = 4,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"allowed_pri\",\n \t.field_bit_size = 8,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"default_pri\",\n \t.field_bit_size = 3,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"allowed_tpid\",\n \t.field_bit_size = 6,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"default_tpid\",\n \t.field_bit_size = 3,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"bd_act_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"sp_rec_ptr\",\n \t.field_bit_size = 16,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"byp_sp_lkup\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t1}\n \t},\n \t{\n \t.description = \"pri_anti_spoof_ctl\",\n \t.field_bit_size = 2,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tpid_anti_spoof_ctl\",\n \t.field_bit_size = 2,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 6, wh_plus, table: l2_cntxt_tcam.egr */\n+\t/* class_tid: 5, wh_plus, table: l2_cntxt_tcam.egr */\n \t{\n \t.description = \"l2_cntxt_id\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}\n \t},\n \t{\n \t.description = \"prof_func_id\",\n \t.field_bit_size = 7,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_GLB_RF_IDX_GLB_PROF_FUNC_ID & 0xff}\n \t},\n \t{\n \t.description = \"l2_byp_lkup_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"parif\",\n \t.field_bit_size = 4,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_CF_IDX_VF_FUNC_PARIF >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_VF_FUNC_PARIF & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_CF_IDX_VF_FUNC_PARIF & 0xff}\n \t},\n \t{\n \t.description = \"allowed_pri\",\n \t.field_bit_size = 8,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"default_pri\",\n \t.field_bit_size = 3,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"allowed_tpid\",\n \t.field_bit_size = 6,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"default_tpid\",\n \t.field_bit_size = 3,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"bd_act_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"sp_rec_ptr\",\n \t.field_bit_size = 16,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"byp_sp_lkup\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t1}\n \t},\n \t{\n \t.description = \"pri_anti_spoof_ctl\",\n \t.field_bit_size = 2,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tpid_anti_spoof_ctl\",\n \t.field_bit_size = 2,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 6, wh_plus, table: l2_cntxt_tcam_cache.egr_wr */\n+\t/* class_tid: 5, wh_plus, table: l2_cntxt_tcam_cache.egr_wr */\n \t{\n \t.description = \"rid\",\n \t.field_bit_size = 32,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_RF_IDX_RID >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_RID & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_RF_IDX_RID & 0xff}\n \t},\n \t{\n \t.description = \"l2_cntxt_tcam_index\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_RF_IDX_L2_CNTXT_TCAM_INDEX_0 & 0xff}\n \t},\n \t{\n \t.description = \"l2_cntxt_id\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_RF_IDX_L2_CNTXT_ID_0 >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_RF_IDX_L2_CNTXT_ID_0 & 0xff}\n \t},\n \t{\n \t.description = \"src_property_ptr\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 6, wh_plus, table: parif_def_lkup_arec_ptr.egr */\n+\t/* class_tid: 5, wh_plus, table: parif_def_lkup_arec_ptr.egr */\n \t{\n \t.description = \"act_rec_ptr\",\n \t.field_bit_size = 32,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}\n \t},\n-\t/* class_tid: 6, wh_plus, table: parif_def_arec_ptr.egr */\n+\t/* class_tid: 5, wh_plus, table: parif_def_arec_ptr.egr */\n \t{\n \t.description = \"act_rec_ptr\",\n \t.field_bit_size = 32,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}\n \t},\n-\t/* class_tid: 6, wh_plus, table: parif_def_err_arec_ptr.egr */\n+\t/* class_tid: 5, wh_plus, table: parif_def_err_arec_ptr.egr */\n \t{\n \t.description = \"act_rec_ptr\",\n \t.field_bit_size = 32,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_GLB_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_GLB_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR >> 8) & 0xff,\n-\t\tBNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_GLB_RF_IDX_GLB_LB_AREC_PTR & 0xff}\n \t},\n-\t/* class_tid: 6, wh_plus, table: int_full_act_record.ing */\n+\t/* class_tid: 5, wh_plus, table: int_full_act_record.ing */\n \t{\n \t.description = \"flow_cntr_ptr\",\n \t.field_bit_size = 14,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"age_enable\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"agg_cntr_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"rate_cntr_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"flow_cntr_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tcpflags_key\",\n \t.field_bit_size = 8,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tcpflags_mir\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tcpflags_match\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"encap_ptr\",\n \t.field_bit_size = 11,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"dst_ip_ptr\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tcp_dst_port\",\n \t.field_bit_size = 16,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"src_ip_ptr\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tcp_src_port\",\n \t.field_bit_size = 16,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"meter_id\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"l3_rdir\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tl3_rdir\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"l3_ttl_dec\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tl3_ttl_dec\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"decap_func\",\n \t.field_bit_size = 4,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"vnic_or_vport\",\n \t.field_bit_size = 12,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_COMP_FIELD,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_CF_IDX_DRV_FUNC_VNIC >> 8) & 0xff,\n-\t\tBNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff}\n \t},\n \t{\n \t.description = \"pop_vlan\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"meter\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"mirror\",\n \t.field_bit_size = 2,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"drop\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"hit\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"type\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 6, wh_plus, table: l2_cntxt_tcam_bypass.ing */\n+\t/* class_tid: 5, wh_plus, table: l2_cntxt_tcam_bypass.ing */\n \t{\n \t.description = \"act_record_ptr\",\n \t.field_bit_size = 16,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_REGFILE,\n-\t.field_operand = {\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_RF,\n+\t.field_opr1 = {\n \t\t(BNXT_ULP_RF_IDX_MAIN_ACTION_PTR >> 8) & 0xff,\n-\t\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t\tBNXT_ULP_RF_IDX_MAIN_ACTION_PTR & 0xff}\n \t},\n \t{\n \t.description = \"reserved\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"l2_byp_lkup_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t1}\n \t},\n \t{\n \t.description = \"parif\",\n \t.field_bit_size = 4,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"allowed_pri\",\n \t.field_bit_size = 8,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"default_pri\",\n \t.field_bit_size = 3,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"allowed_tpid\",\n \t.field_bit_size = 6,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"default_tpid\",\n \t.field_bit_size = 3,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"bd_act_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"sp_rec_ptr\",\n \t.field_bit_size = 16,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"byp_sp_lkup\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t1}\n \t},\n \t{\n \t.description = \"pri_anti_spoof_ctl\",\n \t.field_bit_size = 2,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tpid_anti_spoof_ctl\",\n \t.field_bit_size = 2,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n-\t/* class_tid: 7, wh_plus, table: int_full_act_record.0 */\n+\t/* class_tid: 6, wh_plus, table: int_full_act_record.0 */\n \t{\n \t.description = \"flow_cntr_ptr\",\n \t.field_bit_size = 14,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"age_enable\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"agg_cntr_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"rate_cntr_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"flow_cntr_en\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tcpflags_key\",\n \t.field_bit_size = 8,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tcpflags_mir\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tcpflags_match\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"encap_ptr\",\n \t.field_bit_size = 11,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"dst_ip_ptr\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tcp_dst_port\",\n \t.field_bit_size = 16,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"src_ip_ptr\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tcp_src_port\",\n \t.field_bit_size = 16,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"meter_id\",\n \t.field_bit_size = 10,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"l3_rdir\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tl3_rdir\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"l3_ttl_dec\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"tl3_ttl_dec\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"decap_func\",\n \t.field_bit_size = 4,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"vnic_or_vport\",\n \t.field_bit_size = 12,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_CONSTANT,\n-\t.field_operand = {\n-\t\t(BNXT_ULP_WH_PLUS_SYM_LOOPBACK_PORT >> 8) & 0xff,\n-\t\tBNXT_ULP_WH_PLUS_SYM_LOOPBACK_PORT & 0xff,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n-\t\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_CONST,\n+\t.field_opr1 = {\n+\t\t(ULP_WP_SYM_LOOPBACK_PORT >> 8) & 0xff,\n+\t\tULP_WP_SYM_LOOPBACK_PORT & 0xff}\n \t},\n \t{\n \t.description = \"pop_vlan\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"meter\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"mirror\",\n \t.field_bit_size = 2,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"drop\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"hit\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t},\n \t{\n \t.description = \"type\",\n \t.field_bit_size = 1,\n-\t.field_opcode = BNXT_ULP_FIELD_OPC_SET_TO_ZERO\n+\t.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,\n+\t.field_src1 = BNXT_ULP_FIELD_SRC_ZERO\n \t}\n };\n \n struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = {\n+\t/* class_tid: 1, wh_plus, table: l2_cntxt_tcam_cache.rd */\n+\t{\n+\t.description = \"l2_cntxt_id\",\n+\t.regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,\n+\t.ident_bit_size = 10,\n+\t.ident_bit_pos = 42\n+\t},\n \t/* class_tid: 1, wh_plus, table: l2_cntxt_tcam.0 */\n \t{\n \t.description = \"l2_cntxt_id\",\n@@ -7414,12 +6435,6 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = {\n \t},\n \t/* class_tid: 1, wh_plus, table: profile_tcam_cache.rd */\n \t{\n-\t.description = \"flow_sig_id\",\n-\t.regfile_idx = BNXT_ULP_RF_IDX_FLOW_SIG_ID,\n-\t.ident_bit_size = 8,\n-\t.ident_bit_pos = 58\n-\t},\n-\t{\n \t.description = \"profile_tcam_index\",\n \t.regfile_idx = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,\n \t.ident_bit_size = 10,\n@@ -7431,44 +6446,13 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = {\n \t.ident_bit_size = 8,\n \t.ident_bit_pos = 42\n \t},\n-\t/* class_tid: 1, wh_plus, table: profile_tcam.0 */\n-\t{\n-\t.description = \"em_profile_id\",\n-\t.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n-\t.ident_type = TF_IDENT_TYPE_EM_PROF,\n-\t.regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0,\n-\t.ident_bit_size = 8,\n-\t.ident_bit_pos = 28\n-\t},\n-\t/* class_tid: 2, wh_plus, table: l2_cntxt_tcam.0 */\n-\t{\n-\t.description = \"l2_cntxt_id\",\n-\t.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n-\t.ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH,\n-\t.regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,\n-\t.ident_bit_size = 10,\n-\t.ident_bit_pos = 0\n-\t},\n-\t/* class_tid: 2, wh_plus, table: profile_tcam_cache.rd */\n-\t{\n-\t.description = \"profile_tcam_index\",\n-\t.regfile_idx = BNXT_ULP_RF_IDX_PROFILE_TCAM_INDEX_0,\n-\t.ident_bit_size = 10,\n-\t.ident_bit_pos = 32\n-\t},\n \t{\n \t.description = \"flow_sig_id\",\n \t.regfile_idx = BNXT_ULP_RF_IDX_FLOW_SIG_ID,\n \t.ident_bit_size = 8,\n \t.ident_bit_pos = 58\n \t},\n-\t{\n-\t.description = \"em_profile_id\",\n-\t.regfile_idx = BNXT_ULP_RF_IDX_EM_PROFILE_ID_0,\n-\t.ident_bit_size = 8,\n-\t.ident_bit_pos = 42\n-\t},\n-\t/* class_tid: 2, wh_plus, table: profile_tcam.0 */\n+\t/* class_tid: 1, wh_plus, table: profile_tcam.0 */\n \t{\n \t.description = \"em_profile_id\",\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n@@ -7477,7 +6461,7 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = {\n \t.ident_bit_size = 8,\n \t.ident_bit_pos = 28\n \t},\n-\t/* class_tid: 3, wh_plus, table: l2_cntxt_tcam.0 */\n+\t/* class_tid: 2, wh_plus, table: l2_cntxt_tcam.0 */\n \t{\n \t.description = \"l2_cntxt_id\",\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n@@ -7486,14 +6470,14 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = {\n \t.ident_bit_size = 10,\n \t.ident_bit_pos = 0\n \t},\n-\t/* class_tid: 4, wh_plus, table: l2_cntxt_tcam_cache.rd */\n+\t/* class_tid: 3, wh_plus, table: l2_cntxt_tcam_cache.rd */\n \t{\n \t.description = \"l2_cntxt_id\",\n \t.regfile_idx = BNXT_ULP_RF_IDX_L2_CNTXT_ID_0,\n \t.ident_bit_size = 10,\n \t.ident_bit_pos = 42\n \t},\n-\t/* class_tid: 4, wh_plus, table: l2_cntxt_tcam.0 */\n+\t/* class_tid: 3, wh_plus, table: l2_cntxt_tcam.0 */\n \t{\n \t.description = \"l2_cntxt_id\",\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\n@@ -7502,7 +6486,7 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = {\n \t.ident_bit_size = 10,\n \t.ident_bit_pos = 0\n \t},\n-\t/* class_tid: 6, wh_plus, table: l2_cntxt_tcam.egr */\n+\t/* class_tid: 5, wh_plus, table: l2_cntxt_tcam.egr */\n \t{\n \t.description = \"l2_cntxt_id\",\n \t.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,\ndiff --git a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h\nindex b06b1b12d3..16802fb89a 100644\n--- a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h\n+++ b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h\n@@ -160,6 +160,7 @@ struct bnxt_ulp_mapper_cond_list_info {\n \tenum bnxt_ulp_cond_list_opc cond_list_opcode;\n \tuint32_t cond_start_idx;\n \tuint32_t cond_nums;\n+\tuint32_t cond_goto;\n };\n \n struct bnxt_ulp_template_device_tbls {\n@@ -252,12 +253,15 @@ struct bnxt_ulp_mapper_tbl_info {\n };\n \n struct bnxt_ulp_mapper_field_info {\n-\tuint8_t\t\t\tdescription[64];\n-\tenum bnxt_ulp_field_opc\tfield_opcode;\n-\tuint16_t\t\tfield_bit_size;\n-\tuint8_t\t\t\tfield_operand[16];\n-\tuint8_t\t\t\tfield_operand_true[16];\n-\tuint8_t\t\t\tfield_operand_false[16];\n+\tuint8_t\t\t\t\tdescription[64];\n+\tuint16_t\t\t\tfield_bit_size;\n+\tenum bnxt_ulp_field_cond_src\tfield_cond_src;\n+\tuint8_t\t\t\t\tfield_cond_opr[16];\n+\tenum bnxt_ulp_field_src\t\tfield_src1;\n+\tuint8_t\t\t\t\tfield_opr1[16];\n+\tenum bnxt_ulp_field_src\t\tfield_src2;\n+\tuint8_t\t\t\t\tfield_opr2[16];\n+\n };\n \n struct bnxt_ulp_mapper_key_info {\ndiff --git a/drivers/net/bnxt/tf_ulp/ulp_tun.c b/drivers/net/bnxt/tf_ulp/ulp_tun.c\nindex e8d2861880..dd3d8703fb 100644\n--- a/drivers/net/bnxt/tf_ulp/ulp_tun.c\n+++ b/drivers/net/bnxt/tf_ulp/ulp_tun.c\n@@ -25,7 +25,7 @@ ulp_install_outer_tun_flow(struct ulp_rte_parser_params *params,\n \t/* Reset the JUMP action bit in the action bitmap as we don't\n \t * offload this action.\n \t */\n-\tULP_BITMAP_RESET(params->act_bitmap.bits, BNXT_ULP_ACTION_BIT_JUMP);\n+\tULP_BITMAP_RESET(params->act_bitmap.bits, BNXT_ULP_ACT_BIT_JUMP);\n \n \tULP_BITMAP_SET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_F1);\n \ndiff --git a/drivers/net/bnxt/tf_ulp/ulp_tun.h b/drivers/net/bnxt/tf_ulp/ulp_tun.h\nindex ad70ae6164..763138218b 100644\n--- a/drivers/net/bnxt/tf_ulp/ulp_tun.h\n+++ b/drivers/net/bnxt/tf_ulp/ulp_tun.h\n@@ -18,7 +18,7 @@\n #define\tBNXT_OUTER_TUN_SIGNATURE(l3_tun, params)\t\t\\\n \t((l3_tun) &&\t\t\t\t\t\\\n \t ULP_BITMAP_ISSET((params)->act_bitmap.bits,\t\\\n-\t\t\t  BNXT_ULP_ACTION_BIT_JUMP))\n+\t\t\t  BNXT_ULP_ACT_BIT_JUMP))\n #define\tBNXT_INNER_TUN_SIGNATURE(l3_tun, l3_tun_decap, params)\t\t\\\n \t((l3_tun) && (l3_tun_decap) &&\t\t\t\t\t\\\n \t !ULP_BITMAP_ISSET((params)->hdr_bitmap.bits,\t\t\t\\\n",
    "prefixes": [
        "35/58"
    ]
}