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{
    "id": 93550,
    "url": "http://patches.dpdk.org/api/patches/93550/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210530085929.29695-2-venkatkumar.duvvuru@broadcom.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20210530085929.29695-2-venkatkumar.duvvuru@broadcom.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20210530085929.29695-2-venkatkumar.duvvuru@broadcom.com",
    "date": "2021-05-30T08:58:32",
    "name": "[01/58] net/bnxt: add CFA folder to HCAPI directory",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "4adf08fc6c7d86e89a64bf06afee15708bd0e768",
    "submitter": {
        "id": 1635,
        "url": "http://patches.dpdk.org/api/people/1635/?format=api",
        "name": "Venkat Duvvuru",
        "email": "venkatkumar.duvvuru@broadcom.com"
    },
    "delegate": {
        "id": 1766,
        "url": "http://patches.dpdk.org/api/users/1766/?format=api",
        "username": "ajitkhaparde",
        "first_name": "Ajit",
        "last_name": "Khaparde",
        "email": "ajit.khaparde@broadcom.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210530085929.29695-2-venkatkumar.duvvuru@broadcom.com/mbox/",
    "series": [
        {
            "id": 17161,
            "url": "http://patches.dpdk.org/api/series/17161/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=17161",
            "date": "2021-05-30T08:58:31",
            "name": "enhancements to host based flow table management",
            "version": 1,
            "mbox": "http://patches.dpdk.org/series/17161/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/93550/comments/",
    "check": "success",
    "checks": "http://patches.dpdk.org/api/patches/93550/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 3F649A0524;\n\tSun, 30 May 2021 11:00:35 +0200 (CEST)",
            "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 57EF240E01;\n\tSun, 30 May 2021 11:00:29 +0200 (CEST)",
            "from relay.smtp-ext.broadcom.com (saphodev.broadcom.com\n [192.19.11.229]) by mails.dpdk.org (Postfix) with ESMTP id 93CCE40DFB\n for <dev@dpdk.org>; Sun, 30 May 2021 11:00:27 +0200 (CEST)",
            "from S60.dhcp.broadcom.net (unknown [10.123.66.170])\n (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits))\n (No client certificate requested)\n by relay.smtp-ext.broadcom.com (Postfix) with ESMTPS id AB5387DC2;\n Sun, 30 May 2021 02:00:25 -0700 (PDT)"
        ],
        "DKIM-Filter": "OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com AB5387DC2",
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com;\n s=dkimrelay; t=1622365227;\n bh=OqtPpkxyU4mSMDSEMtVlCAOWrPrtK6kml+9jr5yFTRg=;\n h=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n b=IPn/ycyWsPgtmM2OEKWaDDOS0wZofTd2JVbU4z4P0GtUVRm+CgaXLWRfyFo99Ilk9\n c4BF8vNrydS/QhS03N0or8WAq4iJDDc1t0YepPDIu/GjnE5aIjy0qBED6lU7M0Y4cl\n ug7eBuJGyQkgUQeRbv9sEoAXR8lKeQA5CYCkwhL8=",
        "From": "Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>",
        "To": "dev@dpdk.org",
        "Cc": "Jeffrey Huang <jeffrey.huang@broadcom.com>,\n Randy Schacher <stuart.schacher@broadcom.com>,\n Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>",
        "Date": "Sun, 30 May 2021 14:28:32 +0530",
        "Message-Id": "<20210530085929.29695-2-venkatkumar.duvvuru@broadcom.com>",
        "X-Mailer": "git-send-email 2.17.1",
        "In-Reply-To": "<20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com>",
        "References": "<20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com>",
        "Subject": "[dpdk-dev] [PATCH 01/58] net/bnxt: add CFA folder to HCAPI directory",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "From: Jeffrey Huang <jeffrey.huang@broadcom.com>\n\nBefore introducing more HCAPI components to DPDK, the CFA code needs\nto be organized into a dedicated folder so it is separated from\nother new HCAPI components\n\nSigned-off-by: Jeffrey Huang <jeffrey.huang@broadcom.com>\nSigned-off-by: Randy Schacher <stuart.schacher@broadcom.com>\nSigned-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>\nReviewed-by: Farah Smith <farah.smith@broadcom.com>\n---\n drivers/net/bnxt/hcapi/{ => cfa}/hcapi_cfa.h  |  14 -\n .../net/bnxt/hcapi/{ => cfa}/hcapi_cfa_defs.h |   8 +-\n .../net/bnxt/hcapi/{ => cfa}/hcapi_cfa_p4.c   |   0\n .../net/bnxt/hcapi/{ => cfa}/hcapi_cfa_p4.h   |   2 -\n drivers/net/bnxt/hcapi/cfa/meson.build        |  10 +\n drivers/net/bnxt/hcapi/cfa_p40_hw.h           | 781 ------------------\n drivers/net/bnxt/hcapi/cfa_p40_tbl.h          | 303 -------\n drivers/net/bnxt/meson.build                  |  65 +-\n drivers/net/bnxt/tf_core/meson.build          |  33 +\n drivers/net/bnxt/tf_core/tf_core.h            |   2 +-\n drivers/net/bnxt/tf_core/tf_em.h              |   2 +-\n drivers/net/bnxt/tf_ulp/meson.build           |  28 +\n 12 files changed, 89 insertions(+), 1159 deletions(-)\n rename drivers/net/bnxt/hcapi/{ => cfa}/hcapi_cfa.h (96%)\n rename drivers/net/bnxt/hcapi/{ => cfa}/hcapi_cfa_defs.h (98%)\n rename drivers/net/bnxt/hcapi/{ => cfa}/hcapi_cfa_p4.c (100%)\n rename drivers/net/bnxt/hcapi/{ => cfa}/hcapi_cfa_p4.h (99%)\n create mode 100644 drivers/net/bnxt/hcapi/cfa/meson.build\n delete mode 100644 drivers/net/bnxt/hcapi/cfa_p40_hw.h\n delete mode 100644 drivers/net/bnxt/hcapi/cfa_p40_tbl.h\n create mode 100644 drivers/net/bnxt/tf_core/meson.build\n create mode 100644 drivers/net/bnxt/tf_ulp/meson.build",
    "diff": "diff --git a/drivers/net/bnxt/hcapi/hcapi_cfa.h b/drivers/net/bnxt/hcapi/cfa/hcapi_cfa.h\nsimilarity index 96%\nrename from drivers/net/bnxt/hcapi/hcapi_cfa.h\nrename to drivers/net/bnxt/hcapi/cfa/hcapi_cfa.h\nindex c58092e72d..b8c85a0fca 100644\n--- a/drivers/net/bnxt/hcapi/hcapi_cfa.h\n+++ b/drivers/net/bnxt/hcapi/cfa/hcapi_cfa.h\n@@ -14,20 +14,6 @@\n \n #include \"hcapi_cfa_defs.h\"\n \n-#if CHIP_CFG == SR_A\n-#define SUPPORT_CFA_HW_P45  1\n-#undef SUPPORT_CFA_HW_P4\n-#define SUPPORT_CFA_HW_P4   0\n-#elif CHIP_CFG == CMB_A\n-#define SUPPORT_CFA_HW_P4  1\n-#else\n-#error \"Chip not supported\"\n-#endif\n-\n-#if SUPPORT_CFA_HW_P4 && SUPPORT_CFA_HW_P58 && SUPPORT_CFA_HW_P59\n-#define SUPPORT_CFA_HW_ALL  1\n-#endif\n-\n /**\n  * Index used for the sram_entries field\n  */\ndiff --git a/drivers/net/bnxt/hcapi/hcapi_cfa_defs.h b/drivers/net/bnxt/hcapi/cfa/hcapi_cfa_defs.h\nsimilarity index 98%\nrename from drivers/net/bnxt/hcapi/hcapi_cfa_defs.h\nrename to drivers/net/bnxt/hcapi/cfa/hcapi_cfa_defs.h\nindex b3d6892b0b..08f098ec86 100644\n--- a/drivers/net/bnxt/hcapi/hcapi_cfa_defs.h\n+++ b/drivers/net/bnxt/hcapi/cfa/hcapi_cfa_defs.h\n@@ -17,11 +17,6 @@\n #include <stdint.h>\n #include <stddef.h>\n \n-#define SUPPORT_CFA_HW_ALL 0\n-#define SUPPORT_CFA_HW_P4  1\n-#define SUPPORT_CFA_HW_P58 0\n-#define SUPPORT_CFA_HW_P59 0\n-\n #define CFA_BITS_PER_BYTE (8)\n #define __CFA_ALIGN_MASK(x, mask) (((x) + (mask)) & ~(mask))\n #define CFA_ALIGN(x, a) __CFA_ALIGN_MASK(x, (a) - 1)\n@@ -49,8 +44,7 @@ enum hcapi_cfa_ver {\n \tHCAPI_CFA_P40 = 0, /**< CFA phase 4.0 */\n \tHCAPI_CFA_P45 = 1, /**< CFA phase 4.5 */\n \tHCAPI_CFA_P58 = 2, /**< CFA phase 5.8 */\n-\tHCAPI_CFA_P59 = 3, /**< CFA phase 5.9 */\n-\tHCAPI_CFA_PMAX = 4\n+\tHCAPI_CFA_PMAX = 3\n };\n \n /**\ndiff --git a/drivers/net/bnxt/hcapi/hcapi_cfa_p4.c b/drivers/net/bnxt/hcapi/cfa/hcapi_cfa_p4.c\nsimilarity index 100%\nrename from drivers/net/bnxt/hcapi/hcapi_cfa_p4.c\nrename to drivers/net/bnxt/hcapi/cfa/hcapi_cfa_p4.c\ndiff --git a/drivers/net/bnxt/hcapi/hcapi_cfa_p4.h b/drivers/net/bnxt/hcapi/cfa/hcapi_cfa_p4.h\nsimilarity index 99%\nrename from drivers/net/bnxt/hcapi/hcapi_cfa_p4.h\nrename to drivers/net/bnxt/hcapi/cfa/hcapi_cfa_p4.h\nindex 305c83bc9f..74a5483c0b 100644\n--- a/drivers/net/bnxt/hcapi/hcapi_cfa_p4.h\n+++ b/drivers/net/bnxt/hcapi/cfa/hcapi_cfa_p4.h\n@@ -6,8 +6,6 @@\n #ifndef _HCAPI_CFA_P4_H_\n #define _HCAPI_CFA_P4_H_\n \n-#include \"cfa_p40_hw.h\"\n-\n /** CFA phase 4 fix formatted table(layout) ID definition\n  *\n  */\ndiff --git a/drivers/net/bnxt/hcapi/cfa/meson.build b/drivers/net/bnxt/hcapi/cfa/meson.build\nnew file mode 100644\nindex 0000000000..8b70d273f4\n--- /dev/null\n+++ b/drivers/net/bnxt/hcapi/cfa/meson.build\n@@ -0,0 +1,10 @@\n+# SPDX-License-Identifier: BSD-3-Clause\n+# Copyright(c) 2018 Intel Corporation\n+# Copyright(c) 2021 Broadcom\n+\n+#Include the folder for headers\n+includes += include_directories('.')\n+\n+#Add the source files\n+sources += files(\n+        'hcapi_cfa_p4.c')\ndiff --git a/drivers/net/bnxt/hcapi/cfa_p40_hw.h b/drivers/net/bnxt/hcapi/cfa_p40_hw.h\ndeleted file mode 100644\nindex 5e32529886..0000000000\n--- a/drivers/net/bnxt/hcapi/cfa_p40_hw.h\n+++ /dev/null\n@@ -1,781 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(c) 2019-2021 Broadcom\n- * All rights reserved.\n- */\n-/*\n- * Name:  cfa_p40_hw.h\n- *\n- * Description: header for SWE based on Truflow\n- *\n- * Date:  taken from 12/16/19 17:18:12\n- *\n- * Note:  This file was first generated using  tflib_decode.py.\n- *\n- *        Changes have been made due to lack of availability of xml for\n- *        additional tables at this time (EEM Record and union table fields)\n- *        Changes not autogenerated are noted in comments.\n- */\n-\n-#ifndef _CFA_P40_HW_H_\n-#define _CFA_P40_HW_H_\n-\n-/**\n- * Valid TCAM entry. (for idx 5 ...)\n- */\n-#define CFA_P40_PROF_L2_CTXT_TCAM_VALID_BITPOS   166\n-#define CFA_P40_PROF_L2_CTXT_TCAM_VALID_NUM_BITS 1\n-/**\n- * Key type (pass). (for idx 5 ...)\n- */\n-#define CFA_P40_PROF_L2_CTXT_TCAM_KEY_TYPE_BITPOS 164\n-#define CFA_P40_PROF_L2_CTXT_TCAM_KEY_TYPE_NUM_BITS 2\n-/**\n- * Tunnel HDR type. (for idx 5 ...)\n- */\n-#define CFA_P40_PROF_L2_CTXT_TCAM_TUN_HDR_TYPE_BITPOS 160\n-#define CFA_P40_PROF_L2_CTXT_TCAM_TUN_HDR_TYPE_NUM_BITS 4\n-/**\n- * Number of VLAN tags in tunnel l2 header. (for idx 4 ...)\n- */\n-#define CFA_P40_PROF_L2_CTXT_TCAM_T_L2_NUMTAGS_BITPOS 158\n-#define CFA_P40_PROF_L2_CTXT_TCAM_T_L2_NUMTAGS_NUM_BITS 2\n-/**\n- * Number of VLAN tags in l2 header. (for idx 4 ...)\n- */\n-#define CFA_P40_PROF_L2_CTXT_TCAM_L2_NUMTAGS_BITPOS 156\n-#define CFA_P40_PROF_L2_CTXT_TCAM_L2_NUMTAGS_NUM_BITS 2\n-/**\n- * Tunnel/Inner Source/Dest. MAC Address.\n- */\n-#define CFA_P40_PROF_L2_CTXT_TCAM_MAC1_BITPOS    108\n-#define CFA_P40_PROF_L2_CTXT_TCAM_MAC1_NUM_BITS  48\n-/**\n- * Tunnel Outer VLAN Tag ID. (for idx 3 ...)\n- */\n-#define CFA_P40_PROF_L2_CTXT_TCAM_T_OVID_BITPOS  96\n-#define CFA_P40_PROF_L2_CTXT_TCAM_T_OVID_NUM_BITS 12\n-/**\n- * Tunnel Inner VLAN Tag ID. (for idx 2 ...)\n- */\n-#define CFA_P40_PROF_L2_CTXT_TCAM_T_IVID_BITPOS  84\n-#define CFA_P40_PROF_L2_CTXT_TCAM_T_IVID_NUM_BITS 12\n-/**\n- * Source Partition. (for idx 2 ...)\n- */\n-#define CFA_P40_PROF_L2_CTXT_TCAM_SPARIF_BITPOS  80\n-#define CFA_P40_PROF_L2_CTXT_TCAM_SPARIF_NUM_BITS 4\n-/**\n- * Source Virtual I/F. (for idx 2 ...)\n- */\n-#define CFA_P40_PROF_L2_CTXT_TCAM_SVIF_BITPOS    72\n-#define CFA_P40_PROF_L2_CTXT_TCAM_SVIF_NUM_BITS  8\n-/**\n- * Tunnel/Inner Source/Dest. MAC Address.\n- */\n-#define CFA_P40_PROF_L2_CTXT_TCAM_MAC0_BITPOS    24\n-#define CFA_P40_PROF_L2_CTXT_TCAM_MAC0_NUM_BITS  48\n-/**\n- * Outer VLAN Tag ID.\n- */\n-#define CFA_P40_PROF_L2_CTXT_TCAM_OVID_BITPOS    12\n-#define CFA_P40_PROF_L2_CTXT_TCAM_OVID_NUM_BITS  12\n-/**\n- * Inner VLAN Tag ID.\n- */\n-#define CFA_P40_PROF_L2_CTXT_TCAM_IVID_BITPOS    0\n-#define CFA_P40_PROF_L2_CTXT_TCAM_IVID_NUM_BITS  12\n-\n-enum cfa_p40_prof_l2_ctxt_tcam_flds {\n-\tCFA_P40_PROF_L2_CTXT_TCAM_VALID_FLD = 0,\n-\tCFA_P40_PROF_L2_CTXT_TCAM_KEY_TYPE_FLD = 1,\n-\tCFA_P40_PROF_L2_CTXT_TCAM_TUN_HDR_TYPE_FLD = 2,\n-\tCFA_P40_PROF_L2_CTXT_TCAM_T_L2_NUMTAGS_FLD = 3,\n-\tCFA_P40_PROF_L2_CTXT_TCAM_L2_NUMTAGS_FLD = 4,\n-\tCFA_P40_PROF_L2_CTXT_TCAM_MAC1_FLD = 5,\n-\tCFA_P40_PROF_L2_CTXT_TCAM_T_OVID_FLD = 6,\n-\tCFA_P40_PROF_L2_CTXT_TCAM_T_IVID_FLD = 7,\n-\tCFA_P40_PROF_L2_CTXT_TCAM_SPARIF_FLD = 8,\n-\tCFA_P40_PROF_L2_CTXT_TCAM_SVIF_FLD = 9,\n-\tCFA_P40_PROF_L2_CTXT_TCAM_MAC0_FLD = 10,\n-\tCFA_P40_PROF_L2_CTXT_TCAM_OVID_FLD = 11,\n-\tCFA_P40_PROF_L2_CTXT_TCAM_IVID_FLD = 12,\n-\tCFA_P40_PROF_L2_CTXT_TCAM_MAX_FLD\n-};\n-\n-#define CFA_P40_PROF_L2_CTXT_TCAM_TOTAL_NUM_BITS 167\n-\n-/**\n- * Valid entry. (for idx 2 ...)\n- */\n-#define CFA_P40_ACT_VEB_TCAM_VALID_BITPOS        79\n-#define CFA_P40_ACT_VEB_TCAM_VALID_NUM_BITS      1\n-/**\n- * reserved program to 0. (for idx 2 ...)\n- */\n-#define CFA_P40_ACT_VEB_TCAM_RESERVED_BITPOS     78\n-#define CFA_P40_ACT_VEB_TCAM_RESERVED_NUM_BITS   1\n-/**\n- * PF Parif Number. (for idx 2 ...)\n- */\n-#define CFA_P40_ACT_VEB_TCAM_PARIF_IN_BITPOS     74\n-#define CFA_P40_ACT_VEB_TCAM_PARIF_IN_NUM_BITS   4\n-/**\n- * Number of VLAN Tags. (for idx 2 ...)\n- */\n-#define CFA_P40_ACT_VEB_TCAM_NUM_VTAGS_BITPOS    72\n-#define CFA_P40_ACT_VEB_TCAM_NUM_VTAGS_NUM_BITS  2\n-/**\n- * Dest. MAC Address.\n- */\n-#define CFA_P40_ACT_VEB_TCAM_MAC_BITPOS          24\n-#define CFA_P40_ACT_VEB_TCAM_MAC_NUM_BITS        48\n-/**\n- * Outer VLAN Tag ID.\n- */\n-#define CFA_P40_ACT_VEB_TCAM_OVID_BITPOS         12\n-#define CFA_P40_ACT_VEB_TCAM_OVID_NUM_BITS       12\n-/**\n- * Inner VLAN Tag ID.\n- */\n-#define CFA_P40_ACT_VEB_TCAM_IVID_BITPOS         0\n-#define CFA_P40_ACT_VEB_TCAM_IVID_NUM_BITS       12\n-\n-enum cfa_p40_act_veb_tcam_flds {\n-\tCFA_P40_ACT_VEB_TCAM_VALID_FLD = 0,\n-\tCFA_P40_ACT_VEB_TCAM_RESERVED_FLD = 1,\n-\tCFA_P40_ACT_VEB_TCAM_PARIF_IN_FLD = 2,\n-\tCFA_P40_ACT_VEB_TCAM_NUM_VTAGS_FLD = 3,\n-\tCFA_P40_ACT_VEB_TCAM_MAC_FLD = 4,\n-\tCFA_P40_ACT_VEB_TCAM_OVID_FLD = 5,\n-\tCFA_P40_ACT_VEB_TCAM_IVID_FLD = 6,\n-\tCFA_P40_ACT_VEB_TCAM_MAX_FLD\n-};\n-\n-#define CFA_P40_ACT_VEB_TCAM_TOTAL_NUM_BITS 80\n-\n-/**\n- * Entry is valid.\n- */\n-#define CFA_P40_LKUP_TCAM_RECORD_MEM_VALID_BITPOS 18\n-#define CFA_P40_LKUP_TCAM_RECORD_MEM_VALID_NUM_BITS 1\n-/**\n- * Action Record Pointer\n- */\n-#define CFA_P40_LKUP_TCAM_RECORD_MEM_ACT_REC_PTR_BITPOS 2\n-#define CFA_P40_LKUP_TCAM_RECORD_MEM_ACT_REC_PTR_NUM_BITS 16\n-/**\n- * for resolving TCAM/EM conflicts\n- */\n-#define CFA_P40_LKUP_TCAM_RECORD_MEM_STRENGTH_BITPOS 0\n-#define CFA_P40_LKUP_TCAM_RECORD_MEM_STRENGTH_NUM_BITS 2\n-\n-enum cfa_p40_lkup_tcam_record_mem_flds {\n-\tCFA_P40_LKUP_TCAM_RECORD_MEM_VALID_FLD = 0,\n-\tCFA_P40_LKUP_TCAM_RECORD_MEM_ACT_REC_PTR_FLD = 1,\n-\tCFA_P40_LKUP_TCAM_RECORD_MEM_STRENGTH_FLD = 2,\n-\tCFA_P40_LKUP_TCAM_RECORD_MEM_MAX_FLD\n-};\n-\n-#define CFA_P40_LKUP_TCAM_RECORD_MEM_TOTAL_NUM_BITS 19\n-\n-/**\n- * (for idx 1 ...)\n- */\n-#define CFA_P40_PROF_CTXT_REMAP_MEM_TPID_ANTI_SPOOF_CTL_BITPOS 62\n-#define CFA_P40_PROF_CTXT_REMAP_MEM_TPID_ANTI_SPOOF_CTL_NUM_BITS 2\n-enum cfa_p40_prof_ctxt_remap_mem_tpid_anti_spoof_ctl {\n-\tCFA_P40_PROF_CTXT_REMAP_MEM_TPID_IGNORE = 0x0UL,\n-\n-\tCFA_P40_PROF_CTXT_REMAP_MEM_TPID_DROP = 0x1UL,\n-\n-\tCFA_P40_PROF_CTXT_REMAP_MEM_TPID_DEFAULT = 0x2UL,\n-\n-\tCFA_P40_PROF_CTXT_REMAP_MEM_TPID_SPIF = 0x3UL,\n-\tCFA_P40_PROF_CTXT_REMAP_MEM_TPID_MAX = 0x3UL\n-};\n-/**\n- * (for idx 1 ...)\n- */\n-#define CFA_P40_PROF_CTXT_REMAP_MEM_PRI_ANTI_SPOOF_CTL_BITPOS 60\n-#define CFA_P40_PROF_CTXT_REMAP_MEM_PRI_ANTI_SPOOF_CTL_NUM_BITS 2\n-enum cfa_p40_prof_ctxt_remap_mem_pri_anti_spoof_ctl {\n-\tCFA_P40_PROF_CTXT_REMAP_MEM_PRI_IGNORE = 0x0UL,\n-\n-\tCFA_P40_PROF_CTXT_REMAP_MEM_PRI_DROP = 0x1UL,\n-\n-\tCFA_P40_PROF_CTXT_REMAP_MEM_PRI_DEFAULT = 0x2UL,\n-\n-\tCFA_P40_PROF_CTXT_REMAP_MEM_PRI_SPIF = 0x3UL,\n-\tCFA_P40_PROF_CTXT_REMAP_MEM_PRI_MAX = 0x3UL\n-};\n-/**\n- * Bypass Source Properties Lookup. (for idx 1 ...)\n- */\n-#define CFA_P40_PROF_CTXT_REMAP_MEM_BYP_SP_LKUP_BITPOS 59\n-#define CFA_P40_PROF_CTXT_REMAP_MEM_BYP_SP_LKUP_NUM_BITS 1\n-/**\n- * SP Record Pointer. (for idx 1 ...)\n- */\n-#define CFA_P40_PROF_CTXT_REMAP_MEM_SP_REC_PTR_BITPOS 43\n-#define CFA_P40_PROF_CTXT_REMAP_MEM_SP_REC_PTR_NUM_BITS 16\n-/**\n- * BD Action pointer passing enable. (for idx 1 ...)\n- */\n-#define CFA_P40_PROF_CTXT_REMAP_MEM_BD_ACT_EN_BITPOS 42\n-#define CFA_P40_PROF_CTXT_REMAP_MEM_BD_ACT_EN_NUM_BITS 1\n-/**\n- * Default VLAN TPID. (for idx 1 ...)\n- */\n-#define CFA_P40_PROF_CTXT_REMAP_MEM_DEFAULT_TPID_BITPOS 39\n-#define CFA_P40_PROF_CTXT_REMAP_MEM_DEFAULT_TPID_NUM_BITS 3\n-/**\n- * Allowed VLAN TPIDs. (for idx 1 ...)\n- */\n-#define CFA_P40_PROF_CTXT_REMAP_MEM_ALLOWED_TPID_BITPOS 33\n-#define CFA_P40_PROF_CTXT_REMAP_MEM_ALLOWED_TPID_NUM_BITS 6\n-/**\n- * Default VLAN PRI.\n- */\n-#define CFA_P40_PROF_CTXT_REMAP_MEM_DEFAULT_PRI_BITPOS 30\n-#define CFA_P40_PROF_CTXT_REMAP_MEM_DEFAULT_PRI_NUM_BITS 3\n-/**\n- * Allowed VLAN PRIs.\n- */\n-#define CFA_P40_PROF_CTXT_REMAP_MEM_ALLOWED_PRI_BITPOS 22\n-#define CFA_P40_PROF_CTXT_REMAP_MEM_ALLOWED_PRI_NUM_BITS 8\n-/**\n- * Partition.\n- */\n-#define CFA_P40_PROF_CTXT_REMAP_MEM_PARIF_BITPOS 18\n-#define CFA_P40_PROF_CTXT_REMAP_MEM_PARIF_NUM_BITS 4\n-/**\n- * Bypass Lookup.\n- */\n-#define CFA_P40_PROF_CTXT_REMAP_MEM_BYP_LKUP_EN_BITPOS 17\n-#define CFA_P40_PROF_CTXT_REMAP_MEM_BYP_LKUP_EN_NUM_BITS 1\n-\n-/**\n- * L2 Context Remap Data. Action bypass mode (1) {7'd0,prof_vnic[9:0]} Note:\n- * should also set byp_lkup_en. Action bypass mode (0) byp_lkup_en(0) -\n- * {prof_func[6:0],l2_context[9:0]} byp_lkup_en(1) - {1'b0,act_rec_ptr[15:0]}\n- */\n-\n-#define CFA_P40_PROF_CTXT_REMAP_MEM_PROF_VNIC_BITPOS 0\n-#define CFA_P40_PROF_CTXT_REMAP_MEM_PROF_VNIC_NUM_BITS 12\n-\n-#define CFA_P40_PROF_CTXT_REMAP_MEM_PROF_FUNC_BITPOS 10\n-#define CFA_P40_PROF_CTXT_REMAP_MEM_PROF_FUNC_NUM_BITS 7\n-\n-#define CFA_P40_PROF_CTXT_REMAP_MEM_L2_CTXT_BITPOS 0\n-#define CFA_P40_PROF_CTXT_REMAP_MEM_L2_CTXT_NUM_BITS 10\n-\n-#define CFA_P40_PROF_CTXT_REMAP_MEM_ARP_BITPOS 0\n-#define CFA_P40_PROF_CTXT_REMAP_MEM_ARP_NUM_BITS 16\n-\n-enum cfa_p40_prof_ctxt_remap_mem_flds {\n-\tCFA_P40_PROF_CTXT_REMAP_MEM_TPID_ANTI_SPOOF_CTL_FLD = 0,\n-\tCFA_P40_PROF_CTXT_REMAP_MEM_PRI_ANTI_SPOOF_CTL_FLD = 1,\n-\tCFA_P40_PROF_CTXT_REMAP_MEM_BYP_SP_LKUP_FLD = 2,\n-\tCFA_P40_PROF_CTXT_REMAP_MEM_SP_REC_PTR_FLD = 3,\n-\tCFA_P40_PROF_CTXT_REMAP_MEM_BD_ACT_EN_FLD = 4,\n-\tCFA_P40_PROF_CTXT_REMAP_MEM_DEFAULT_TPID_FLD = 5,\n-\tCFA_P40_PROF_CTXT_REMAP_MEM_ALLOWED_TPID_FLD = 6,\n-\tCFA_P40_PROF_CTXT_REMAP_MEM_DEFAULT_PRI_FLD = 7,\n-\tCFA_P40_PROF_CTXT_REMAP_MEM_ALLOWED_PRI_FLD = 8,\n-\tCFA_P40_PROF_CTXT_REMAP_MEM_PARIF_FLD = 9,\n-\tCFA_P40_PROF_CTXT_REMAP_MEM_BYP_LKUP_EN_FLD = 10,\n-\tCFA_P40_PROF_CTXT_REMAP_MEM_PROF_VNIC_FLD = 11,\n-\tCFA_P40_PROF_CTXT_REMAP_MEM_PROF_FUNC_FLD = 12,\n-\tCFA_P40_PROF_CTXT_REMAP_MEM_L2_CTXT_FLD = 13,\n-\tCFA_P40_PROF_CTXT_REMAP_MEM_ARP_FLD = 14,\n-\tCFA_P40_PROF_CTXT_REMAP_MEM_MAX_FLD\n-};\n-\n-#define CFA_P40_PROF_CTXT_REMAP_MEM_TOTAL_NUM_BITS 64\n-\n-/**\n- * Bypass action pointer look up (for idx 1 ...)\n- */\n-#define CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_PL_BYP_LKUP_EN_BITPOS 37\n-#define CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_PL_BYP_LKUP_EN_NUM_BITS 1\n-/**\n- * Exact match search enable (for idx 1 ...)\n- */\n-#define CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_EM_SEARCH_ENB_BITPOS 36\n-#define CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_EM_SEARCH_ENB_NUM_BITS 1\n-/**\n- * Exact match profile\n- */\n-#define CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_EM_PROFILE_ID_BITPOS 28\n-#define CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_EM_PROFILE_ID_NUM_BITS 8\n-/**\n- * Exact match key format\n- */\n-#define CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_EM_KEY_ID_BITPOS 23\n-#define CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_EM_KEY_ID_NUM_BITS 5\n-/**\n- * Exact match key mask\n- */\n-#define CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_EM_KEY_MASK_BITPOS 13\n-#define CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_EM_KEY_MASK_NUM_BITS 10\n-/**\n- * TCAM search enable\n- */\n-#define CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_TCAM_SEARCH_ENB_BITPOS 12\n-#define CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_TCAM_SEARCH_ENB_NUM_BITS 1\n-/**\n- * TCAM profile\n- */\n-#define CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_TCAM_PROFILE_ID_BITPOS 4\n-#define CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_TCAM_PROFILE_ID_NUM_BITS 8\n-/**\n- * TCAM key format\n- */\n-#define CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_TCAM_KEY_ID_BITPOS 0\n-#define CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_TCAM_KEY_ID_NUM_BITS 4\n-\n-#define CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_BYPASS_OPT_BITPOS 16\n-#define CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_BYPASS_OPT_NUM_BITS 2\n-\n-#define CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_ACT_REC_PTR_BITPOS 0\n-#define CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_ACT_REC_PTR_NUM_BITS 16\n-\n-enum cfa_p40_prof_profile_tcam_remap_mem_flds {\n-\tCFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_PL_BYP_LKUP_EN_FLD = 0,\n-\tCFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_EM_SEARCH_ENB_FLD = 1,\n-\tCFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_EM_PROFILE_ID_FLD = 2,\n-\tCFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_EM_KEY_ID_FLD = 3,\n-\tCFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_EM_KEY_MASK_FLD = 4,\n-\tCFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_TCAM_SEARCH_ENB_FLD = 5,\n-\tCFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_TCAM_PROFILE_ID_FLD = 6,\n-\tCFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_TCAM_KEY_ID_FLD = 7,\n-\tCFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_BYPASS_OPT_FLD = 8,\n-\tCFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_ACT_REC_PTR_FLD = 9,\n-\tCFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_MAX_FLD\n-};\n-\n-#define CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_TOTAL_NUM_BITS 38\n-\n-/**\n- * Valid TCAM entry (for idx 2 ...)\n- */\n-#define CFA_P40_PROF_PROFILE_TCAM_VALID_BITPOS   80\n-#define CFA_P40_PROF_PROFILE_TCAM_VALID_NUM_BITS 1\n-/**\n- * Packet type (for idx 2 ...)\n- */\n-#define CFA_P40_PROF_PROFILE_TCAM_PKT_TYPE_BITPOS 76\n-#define CFA_P40_PROF_PROFILE_TCAM_PKT_TYPE_NUM_BITS 4\n-/**\n- * Pass through CFA (for idx 2 ...)\n- */\n-#define CFA_P40_PROF_PROFILE_TCAM_RECYCLE_CNT_BITPOS 74\n-#define CFA_P40_PROF_PROFILE_TCAM_RECYCLE_CNT_NUM_BITS 2\n-/**\n- * Aggregate error (for idx 2 ...)\n- */\n-#define CFA_P40_PROF_PROFILE_TCAM_AGG_ERROR_BITPOS 73\n-#define CFA_P40_PROF_PROFILE_TCAM_AGG_ERROR_NUM_BITS 1\n-/**\n- * Profile function (for idx 2 ...)\n- */\n-#define CFA_P40_PROF_PROFILE_TCAM_PROF_FUNC_BITPOS 66\n-#define CFA_P40_PROF_PROFILE_TCAM_PROF_FUNC_NUM_BITS 7\n-/**\n- * Reserved for future use. Set to 0.\n- */\n-#define CFA_P40_PROF_PROFILE_TCAM_RESERVED_BITPOS 57\n-#define CFA_P40_PROF_PROFILE_TCAM_RESERVED_NUM_BITS 9\n-/**\n- * non-tunnel(0)/tunneled(1) packet (for idx 1 ...)\n- */\n-#define CFA_P40_PROF_PROFILE_TCAM_HREC_NEXT_BITPOS 56\n-#define CFA_P40_PROF_PROFILE_TCAM_HREC_NEXT_NUM_BITS 1\n-/**\n- * Tunnel L2 tunnel valid (for idx 1 ...)\n- */\n-#define CFA_P40_PROF_PROFILE_TCAM_TL2_HDR_VALID_BITPOS 55\n-#define CFA_P40_PROF_PROFILE_TCAM_TL2_HDR_VALID_NUM_BITS 1\n-/**\n- * Tunnel L2 header type (for idx 1 ...)\n- */\n-#define CFA_P40_PROF_PROFILE_TCAM_TL2_HDR_TYPE_BITPOS 53\n-#define CFA_P40_PROF_PROFILE_TCAM_TL2_HDR_TYPE_NUM_BITS 2\n-/**\n- * Remapped tunnel L2 dest_type UC(0)/MC(2)/BC(3) (for idx 1 ...)\n- */\n-#define CFA_P40_PROF_PROFILE_TCAM_TL2_UC_MC_BC_BITPOS 51\n-#define CFA_P40_PROF_PROFILE_TCAM_TL2_UC_MC_BC_NUM_BITS 2\n-/**\n- * Tunnel L2 1+ VLAN tags present (for idx 1 ...)\n- */\n-#define CFA_P40_PROF_PROFILE_TCAM_TL2_VTAG_PRESENT_BITPOS 50\n-#define CFA_P40_PROF_PROFILE_TCAM_TL2_VTAG_PRESENT_NUM_BITS 1\n-/**\n- * Tunnel L2 2 VLAN tags present (for idx 1 ...)\n- */\n-#define CFA_P40_PROF_PROFILE_TCAM_TL2_TWO_VTAGS_BITPOS 49\n-#define CFA_P40_PROF_PROFILE_TCAM_TL2_TWO_VTAGS_NUM_BITS 1\n-/**\n- * Tunnel L3 valid (for idx 1 ...)\n- */\n-#define CFA_P40_PROF_PROFILE_TCAM_TL3_VALID_BITPOS 48\n-#define CFA_P40_PROF_PROFILE_TCAM_TL3_VALID_NUM_BITS 1\n-/**\n- * Tunnel L3 error (for idx 1 ...)\n- */\n-#define CFA_P40_PROF_PROFILE_TCAM_TL3_ERROR_BITPOS 47\n-#define CFA_P40_PROF_PROFILE_TCAM_TL3_ERROR_NUM_BITS 1\n-/**\n- * Tunnel L3 header type (for idx 1 ...)\n- */\n-#define CFA_P40_PROF_PROFILE_TCAM_TL3_HDR_TYPE_BITPOS 43\n-#define CFA_P40_PROF_PROFILE_TCAM_TL3_HDR_TYPE_NUM_BITS 4\n-/**\n- * Tunnel L3 header is IPV4 or IPV6. (for idx 1 ...)\n- */\n-#define CFA_P40_PROF_PROFILE_TCAM_TL3_HDR_ISIP_BITPOS 42\n-#define CFA_P40_PROF_PROFILE_TCAM_TL3_HDR_ISIP_NUM_BITS 1\n-/**\n- * Tunnel L3 IPV6 src address is compressed (for idx 1 ...)\n- */\n-#define CFA_P40_PROF_PROFILE_TCAM_TL3_IPV6_CMP_SRC_BITPOS 41\n-#define CFA_P40_PROF_PROFILE_TCAM_TL3_IPV6_CMP_SRC_NUM_BITS 1\n-/**\n- * Tunnel L3 IPV6 dest address is compressed (for idx 1 ...)\n- */\n-#define CFA_P40_PROF_PROFILE_TCAM_TL3_IPV6_CMP_DEST_BITPOS 40\n-#define CFA_P40_PROF_PROFILE_TCAM_TL3_IPV6_CMP_DEST_NUM_BITS 1\n-/**\n- * Tunnel L4 valid (for idx 1 ...)\n- */\n-#define CFA_P40_PROF_PROFILE_TCAM_TL4_HDR_VALID_BITPOS 39\n-#define CFA_P40_PROF_PROFILE_TCAM_TL4_HDR_VALID_NUM_BITS 1\n-/**\n- * Tunnel L4 error (for idx 1 ...)\n- */\n-#define CFA_P40_PROF_PROFILE_TCAM_TL4_HDR_ERROR_BITPOS 38\n-#define CFA_P40_PROF_PROFILE_TCAM_TL4_HDR_ERROR_NUM_BITS 1\n-/**\n- * Tunnel L4 header type (for idx 1 ...)\n- */\n-#define CFA_P40_PROF_PROFILE_TCAM_TL4_HDR_TYPE_BITPOS 34\n-#define CFA_P40_PROF_PROFILE_TCAM_TL4_HDR_TYPE_NUM_BITS 4\n-/**\n- * Tunnel L4 header is UDP or TCP (for idx 1 ...)\n- */\n-#define CFA_P40_PROF_PROFILE_TCAM_TL4_HDR_IS_UDP_TCP_BITPOS 33\n-#define CFA_P40_PROF_PROFILE_TCAM_TL4_HDR_IS_UDP_TCP_NUM_BITS 1\n-/**\n- * Tunnel valid (for idx 1 ...)\n- */\n-#define CFA_P40_PROF_PROFILE_TCAM_TUN_HDR_VALID_BITPOS 32\n-#define CFA_P40_PROF_PROFILE_TCAM_TUN_HDR_VALID_NUM_BITS 1\n-/**\n- * Tunnel error\n- */\n-#define CFA_P40_PROF_PROFILE_TCAM_TUN_HDR_ERR_BITPOS 31\n-#define CFA_P40_PROF_PROFILE_TCAM_TUN_HDR_ERR_NUM_BITS 1\n-/**\n- * Tunnel header type\n- */\n-#define CFA_P40_PROF_PROFILE_TCAM_TUN_HDR_TYPE_BITPOS 27\n-#define CFA_P40_PROF_PROFILE_TCAM_TUN_HDR_TYPE_NUM_BITS 4\n-/**\n- * Tunnel header flags\n- */\n-#define CFA_P40_PROF_PROFILE_TCAM_TUN_HDR_FLAGS_BITPOS 24\n-#define CFA_P40_PROF_PROFILE_TCAM_TUN_HDR_FLAGS_NUM_BITS 3\n-/**\n- * L2 header valid\n- */\n-#define CFA_P40_PROF_PROFILE_TCAM_L2_HDR_VALID_BITPOS 23\n-#define CFA_P40_PROF_PROFILE_TCAM_L2_HDR_VALID_NUM_BITS 1\n-/**\n- * L2 header error\n- */\n-#define CFA_P40_PROF_PROFILE_TCAM_L2_HDR_ERROR_BITPOS 22\n-#define CFA_P40_PROF_PROFILE_TCAM_L2_HDR_ERROR_NUM_BITS 1\n-/**\n- * L2 header type\n- */\n-#define CFA_P40_PROF_PROFILE_TCAM_L2_HDR_TYPE_BITPOS 20\n-#define CFA_P40_PROF_PROFILE_TCAM_L2_HDR_TYPE_NUM_BITS 2\n-/**\n- * Remapped L2 dest_type UC(0)/MC(2)/BC(3)\n- */\n-#define CFA_P40_PROF_PROFILE_TCAM_L2_UC_MC_BC_BITPOS 18\n-#define CFA_P40_PROF_PROFILE_TCAM_L2_UC_MC_BC_NUM_BITS 2\n-/**\n- * L2 header 1+ VLAN tags present\n- */\n-#define CFA_P40_PROF_PROFILE_TCAM_L2_VTAG_PRESENT_BITPOS 17\n-#define CFA_P40_PROF_PROFILE_TCAM_L2_VTAG_PRESENT_NUM_BITS 1\n-/**\n- * L2 header 2 VLAN tags present\n- */\n-#define CFA_P40_PROF_PROFILE_TCAM_L2_TWO_VTAGS_BITPOS 16\n-#define CFA_P40_PROF_PROFILE_TCAM_L2_TWO_VTAGS_NUM_BITS 1\n-/**\n- * L3 header valid\n- */\n-#define CFA_P40_PROF_PROFILE_TCAM_L3_VALID_BITPOS 15\n-#define CFA_P40_PROF_PROFILE_TCAM_L3_VALID_NUM_BITS 1\n-/**\n- * L3 header error\n- */\n-#define CFA_P40_PROF_PROFILE_TCAM_L3_ERROR_BITPOS 14\n-#define CFA_P40_PROF_PROFILE_TCAM_L3_ERROR_NUM_BITS 1\n-/**\n- * L3 header type\n- */\n-#define CFA_P40_PROF_PROFILE_TCAM_L3_HDR_TYPE_BITPOS 10\n-#define CFA_P40_PROF_PROFILE_TCAM_L3_HDR_TYPE_NUM_BITS 4\n-/**\n- * L3 header is IPV4 or IPV6.\n- */\n-#define CFA_P40_PROF_PROFILE_TCAM_L3_HDR_ISIP_BITPOS 9\n-#define CFA_P40_PROF_PROFILE_TCAM_L3_HDR_ISIP_NUM_BITS 1\n-/**\n- * L3 header IPV6 src address is compressed\n- */\n-#define CFA_P40_PROF_PROFILE_TCAM_L3_IPV6_CMP_SRC_BITPOS 8\n-#define CFA_P40_PROF_PROFILE_TCAM_L3_IPV6_CMP_SRC_NUM_BITS 1\n-/**\n- * L3 header IPV6 dest address is compressed\n- */\n-#define CFA_P40_PROF_PROFILE_TCAM_L3_IPV6_CMP_DEST_BITPOS 7\n-#define CFA_P40_PROF_PROFILE_TCAM_L3_IPV6_CMP_DEST_NUM_BITS 1\n-/**\n- * L4 header valid\n- */\n-#define CFA_P40_PROF_PROFILE_TCAM_L4_HDR_VALID_BITPOS 6\n-#define CFA_P40_PROF_PROFILE_TCAM_L4_HDR_VALID_NUM_BITS 1\n-/**\n- * L4 header error\n- */\n-#define CFA_P40_PROF_PROFILE_TCAM_L4_HDR_ERROR_BITPOS 5\n-#define CFA_P40_PROF_PROFILE_TCAM_L4_HDR_ERROR_NUM_BITS 1\n-/**\n- * L4 header type\n- */\n-#define CFA_P40_PROF_PROFILE_TCAM_L4_HDR_TYPE_BITPOS 1\n-#define CFA_P40_PROF_PROFILE_TCAM_L4_HDR_TYPE_NUM_BITS 4\n-/**\n- * L4 header is UDP or TCP\n- */\n-#define CFA_P40_PROF_PROFILE_TCAM_L4_HDR_IS_UDP_TCP_BITPOS 0\n-#define CFA_P40_PROF_PROFILE_TCAM_L4_HDR_IS_UDP_TCP_NUM_BITS 1\n-\n-enum cfa_p40_prof_profile_tcam_flds {\n-\tCFA_P40_PROF_PROFILE_TCAM_VALID_FLD = 0,\n-\tCFA_P40_PROF_PROFILE_TCAM_PKT_TYPE_FLD = 1,\n-\tCFA_P40_PROF_PROFILE_TCAM_RECYCLE_CNT_FLD = 2,\n-\tCFA_P40_PROF_PROFILE_TCAM_AGG_ERROR_FLD = 3,\n-\tCFA_P40_PROF_PROFILE_TCAM_PROF_FUNC_FLD = 4,\n-\tCFA_P40_PROF_PROFILE_TCAM_RESERVED_FLD = 5,\n-\tCFA_P40_PROF_PROFILE_TCAM_HREC_NEXT_FLD = 6,\n-\tCFA_P40_PROF_PROFILE_TCAM_TL2_HDR_VALID_FLD = 7,\n-\tCFA_P40_PROF_PROFILE_TCAM_TL2_HDR_TYPE_FLD = 8,\n-\tCFA_P40_PROF_PROFILE_TCAM_TL2_UC_MC_BC_FLD = 9,\n-\tCFA_P40_PROF_PROFILE_TCAM_TL2_VTAG_PRESENT_FLD = 10,\n-\tCFA_P40_PROF_PROFILE_TCAM_TL2_TWO_VTAGS_FLD = 11,\n-\tCFA_P40_PROF_PROFILE_TCAM_TL3_VALID_FLD = 12,\n-\tCFA_P40_PROF_PROFILE_TCAM_TL3_ERROR_FLD = 13,\n-\tCFA_P40_PROF_PROFILE_TCAM_TL3_HDR_TYPE_FLD = 14,\n-\tCFA_P40_PROF_PROFILE_TCAM_TL3_HDR_ISIP_FLD = 15,\n-\tCFA_P40_PROF_PROFILE_TCAM_TL3_IPV6_CMP_SRC_FLD = 16,\n-\tCFA_P40_PROF_PROFILE_TCAM_TL3_IPV6_CMP_DEST_FLD = 17,\n-\tCFA_P40_PROF_PROFILE_TCAM_TL4_HDR_VALID_FLD = 18,\n-\tCFA_P40_PROF_PROFILE_TCAM_TL4_HDR_ERROR_FLD = 19,\n-\tCFA_P40_PROF_PROFILE_TCAM_TL4_HDR_TYPE_FLD = 20,\n-\tCFA_P40_PROF_PROFILE_TCAM_TL4_HDR_IS_UDP_TCP_FLD = 21,\n-\tCFA_P40_PROF_PROFILE_TCAM_TUN_HDR_VALID_FLD = 22,\n-\tCFA_P40_PROF_PROFILE_TCAM_TUN_HDR_ERR_FLD = 23,\n-\tCFA_P40_PROF_PROFILE_TCAM_TUN_HDR_TYPE_FLD = 24,\n-\tCFA_P40_PROF_PROFILE_TCAM_TUN_HDR_FLAGS_FLD = 25,\n-\tCFA_P40_PROF_PROFILE_TCAM_L2_HDR_VALID_FLD = 26,\n-\tCFA_P40_PROF_PROFILE_TCAM_L2_HDR_ERROR_FLD = 27,\n-\tCFA_P40_PROF_PROFILE_TCAM_L2_HDR_TYPE_FLD = 28,\n-\tCFA_P40_PROF_PROFILE_TCAM_L2_UC_MC_BC_FLD = 29,\n-\tCFA_P40_PROF_PROFILE_TCAM_L2_VTAG_PRESENT_FLD = 30,\n-\tCFA_P40_PROF_PROFILE_TCAM_L2_TWO_VTAGS_FLD = 31,\n-\tCFA_P40_PROF_PROFILE_TCAM_L3_VALID_FLD = 32,\n-\tCFA_P40_PROF_PROFILE_TCAM_L3_ERROR_FLD = 33,\n-\tCFA_P40_PROF_PROFILE_TCAM_L3_HDR_TYPE_FLD = 34,\n-\tCFA_P40_PROF_PROFILE_TCAM_L3_HDR_ISIP_FLD = 35,\n-\tCFA_P40_PROF_PROFILE_TCAM_L3_IPV6_CMP_SRC_FLD = 36,\n-\tCFA_P40_PROF_PROFILE_TCAM_L3_IPV6_CMP_DEST_FLD = 37,\n-\tCFA_P40_PROF_PROFILE_TCAM_L4_HDR_VALID_FLD = 38,\n-\tCFA_P40_PROF_PROFILE_TCAM_L4_HDR_ERROR_FLD = 39,\n-\tCFA_P40_PROF_PROFILE_TCAM_L4_HDR_TYPE_FLD = 40,\n-\tCFA_P40_PROF_PROFILE_TCAM_L4_HDR_IS_UDP_TCP_FLD = 41,\n-\tCFA_P40_PROF_PROFILE_TCAM_MAX_FLD\n-};\n-\n-#define CFA_P40_PROF_PROFILE_TCAM_TOTAL_NUM_BITS 81\n-\n-/**\n- * CFA flexible key layout definition\n- */\n-enum cfa_p40_key_fld_id {\n-\tCFA_P40_KEY_FLD_ID_MAX\n-};\n-\n-/**************************************************************************/\n-/**\n- * Non-autogenerated fields\n- */\n-\n-/**\n- * Valid\n- */\n-#define CFA_P40_EEM_KEY_TBL_VALID_BITPOS 0\n-#define CFA_P40_EEM_KEY_TBL_VALID_NUM_BITS 1\n-\n-/**\n- * L1 Cacheable\n- */\n-#define CFA_P40_EEM_KEY_TBL_L1_CACHEABLE_BITPOS 1\n-#define CFA_P40_EEM_KEY_TBL_L1_CACHEABLE_NUM_BITS 1\n-\n-/**\n- * Strength\n- */\n-#define CFA_P40_EEM_KEY_TBL_STRENGTH_BITPOS 2\n-#define CFA_P40_EEM_KEY_TBL_STRENGTH_NUM_BITS 2\n-\n-/**\n- * Key Size\n- */\n-#define CFA_P40_EEM_KEY_TBL_KEY_SZ_BITPOS 15\n-#define CFA_P40_EEM_KEY_TBL_KEY_SZ_NUM_BITS 9\n-\n-/**\n- * Record Size\n- */\n-#define CFA_P40_EEM_KEY_TBL_REC_SZ_BITPOS 24\n-#define CFA_P40_EEM_KEY_TBL_REC_SZ_NUM_BITS 5\n-\n-/**\n- * Action Record Internal\n- */\n-#define CFA_P40_EEM_KEY_TBL_ACT_REC_INT_BITPOS 29\n-#define CFA_P40_EEM_KEY_TBL_ACT_REC_INT_NUM_BITS 1\n-\n-/**\n- * External Flow Counter\n- */\n-#define CFA_P40_EEM_KEY_TBL_EXT_FLOW_CTR_BITPOS 30\n-#define CFA_P40_EEM_KEY_TBL_EXT_FLOW_CTR_NUM_BITS 1\n-\n-/**\n- * Action Record Pointer\n- */\n-#define CFA_P40_EEM_KEY_TBL_AR_PTR_BITPOS 31\n-#define CFA_P40_EEM_KEY_TBL_AR_PTR_NUM_BITS 33\n-\n-/**\n- * EEM Key omitted - create using keybuilder\n- * Fields here cannot be larger than a uint64_t\n- */\n-\n-#define CFA_P40_EEM_KEY_TBL_TOTAL_NUM_BITS 64\n-\n-enum cfa_p40_eem_key_tbl_flds {\n-\tCFA_P40_EEM_KEY_TBL_VALID_FLD = 0,\n-\tCFA_P40_EEM_KEY_TBL_L1_CACHEABLE_FLD = 1,\n-\tCFA_P40_EEM_KEY_TBL_STRENGTH_FLD = 2,\n-\tCFA_P40_EEM_KEY_TBL_KEY_SZ_FLD = 3,\n-\tCFA_P40_EEM_KEY_TBL_REC_SZ_FLD = 4,\n-\tCFA_P40_EEM_KEY_TBL_ACT_REC_INT_FLD = 5,\n-\tCFA_P40_EEM_KEY_TBL_EXT_FLOW_CTR_FLD = 6,\n-\tCFA_P40_EEM_KEY_TBL_AR_PTR_FLD = 7,\n-\tCFA_P40_EEM_KEY_TBL_MAX_FLD\n-};\n-\n-/**\n- * Mirror Destination 0 Source Property Record Pointer\n- */\n-#define CFA_P40_MIRROR_TBL_SP_PTR_BITPOS 0\n-#define CFA_P40_MIRROR_TBL_SP_PTR_NUM_BITS 11\n-\n-/**\n- * ignore or honor drop\n- */\n-#define CFA_P40_MIRROR_TBL_IGN_DROP_BITPOS 13\n-#define CFA_P40_MIRROR_TBL_IGN_DROP_NUM_BITS 1\n-\n-/**\n- * ingress or egress copy\n- */\n-#define CFA_P40_MIRROR_TBL_COPY_BITPOS 14\n-#define CFA_P40_MIRROR_TBL_COPY_NUM_BITS 1\n-\n-/**\n- * Mirror Destination enable.\n- */\n-#define CFA_P40_MIRROR_TBL_EN_BITPOS 15\n-#define CFA_P40_MIRROR_TBL_EN_NUM_BITS 1\n-\n-/**\n- * Action Record Pointer\n- */\n-#define CFA_P40_MIRROR_TBL_AR_PTR_BITPOS 16\n-#define CFA_P40_MIRROR_TBL_AR_PTR_NUM_BITS 16\n-\n-#define CFA_P40_MIRROR_TBL_TOTAL_NUM_BITS 32\n-\n-enum cfa_p40_mirror_tbl_flds {\n-\tCFA_P40_MIRROR_TBL_SP_PTR_FLD = 0,\n-\tCFA_P40_MIRROR_TBL_IGN_DROP_FLD = 1,\n-\tCFA_P40_MIRROR_TBL_COPY_FLD = 2,\n-\tCFA_P40_MIRROR_TBL_EN_FLD = 3,\n-\tCFA_P40_MIRROR_TBL_AR_PTR_FLD = 4,\n-\tCFA_P40_MIRROR_TBL_MAX_FLD\n-};\n-\n-/**\n- * P45 Specific Updates (SR) - Non-autogenerated\n- */\n-/**\n- * Valid TCAM entry.\n- */\n-#define CFA_P45_PROF_L2_CTXT_TCAM_VALID_BITPOS   166\n-#define CFA_P45_PROF_L2_CTXT_TCAM_VALID_NUM_BITS 1\n-/**\n- * Source Partition.\n- */\n-#define CFA_P45_PROF_L2_CTXT_TCAM_SPARIF_BITPOS  166\n-#define CFA_P45_PROF_L2_CTXT_TCAM_SPARIF_NUM_BITS 4\n-\n-/**\n- * Source Virtual I/F.\n- */\n-#define CFA_P45_PROF_L2_CTXT_TCAM_SVIF_BITPOS    72\n-#define CFA_P45_PROF_L2_CTXT_TCAM_SVIF_NUM_BITS  12\n-\n-\n-/* The SR layout of the l2 ctxt key is different from the Wh+.  Switch to\n- * cfa_p45_hw.h definition when available.\n- */\n-enum cfa_p45_prof_l2_ctxt_tcam_flds {\n-\tCFA_P45_PROF_L2_CTXT_TCAM_VALID_FLD = 0,\n-\tCFA_P45_PROF_L2_CTXT_TCAM_SPARIF_FLD = 1,\n-\tCFA_P45_PROF_L2_CTXT_TCAM_KEY_TYPE_FLD = 2,\n-\tCFA_P45_PROF_L2_CTXT_TCAM_TUN_HDR_TYPE_FLD = 3,\n-\tCFA_P45_PROF_L2_CTXT_TCAM_T_L2_NUMTAGS_FLD = 4,\n-\tCFA_P45_PROF_L2_CTXT_TCAM_L2_NUMTAGS_FLD = 5,\n-\tCFA_P45_PROF_L2_CTXT_TCAM_MAC1_FLD = 6,\n-\tCFA_P45_PROF_L2_CTXT_TCAM_T_OVID_FLD = 7,\n-\tCFA_P45_PROF_L2_CTXT_TCAM_T_IVID_FLD = 8,\n-\tCFA_P45_PROF_L2_CTXT_TCAM_SVIF_FLD = 9,\n-\tCFA_P45_PROF_L2_CTXT_TCAM_MAC0_FLD = 10,\n-\tCFA_P45_PROF_L2_CTXT_TCAM_OVID_FLD = 11,\n-\tCFA_P45_PROF_L2_CTXT_TCAM_IVID_FLD = 12,\n-\tCFA_P45_PROF_L2_CTXT_TCAM_MAX_FLD\n-};\n-\n-#define CFA_P45_PROF_L2_CTXT_TCAM_TOTAL_NUM_BITS 171\n-\n-#endif /* _CFA_P40_HW_H_ */\ndiff --git a/drivers/net/bnxt/hcapi/cfa_p40_tbl.h b/drivers/net/bnxt/hcapi/cfa_p40_tbl.h\ndeleted file mode 100644\nindex 539241ad0e..0000000000\n--- a/drivers/net/bnxt/hcapi/cfa_p40_tbl.h\n+++ /dev/null\n@@ -1,303 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(c) 2019-2021 Broadcom\n- * All rights reserved.\n- */\n-/*\n- * Name:  cfa_p40_tbl.h\n- *\n- * Description: header for SWE based on Truflow\n- *\n- * Date:  12/16/19 17:18:12\n- *\n- * Note:  This file was originally generated by tflib_decode.py.\n- *        Remainder is hand coded due to lack of availability of xml for\n- *        additional tables at this time (EEM Record and union fields)\n- *\n- **/\n-#ifndef _CFA_P40_TBL_H_\n-#define _CFA_P40_TBL_H_\n-\n-#include \"cfa_p40_hw.h\"\n-\n-#include \"hcapi_cfa_defs.h\"\n-\n-const struct hcapi_cfa_field cfa_p40_prof_l2_ctxt_tcam_layout[] = {\n-\t{CFA_P40_PROF_L2_CTXT_TCAM_VALID_BITPOS,\n-\t CFA_P40_PROF_L2_CTXT_TCAM_VALID_NUM_BITS},\n-\t{CFA_P40_PROF_L2_CTXT_TCAM_KEY_TYPE_BITPOS,\n-\t CFA_P40_PROF_L2_CTXT_TCAM_KEY_TYPE_NUM_BITS},\n-\t{CFA_P40_PROF_L2_CTXT_TCAM_TUN_HDR_TYPE_BITPOS,\n-\t CFA_P40_PROF_L2_CTXT_TCAM_TUN_HDR_TYPE_NUM_BITS},\n-\t{CFA_P40_PROF_L2_CTXT_TCAM_T_L2_NUMTAGS_BITPOS,\n-\t CFA_P40_PROF_L2_CTXT_TCAM_T_L2_NUMTAGS_NUM_BITS},\n-\t{CFA_P40_PROF_L2_CTXT_TCAM_L2_NUMTAGS_BITPOS,\n-\t CFA_P40_PROF_L2_CTXT_TCAM_L2_NUMTAGS_NUM_BITS},\n-\t{CFA_P40_PROF_L2_CTXT_TCAM_MAC1_BITPOS,\n-\t CFA_P40_PROF_L2_CTXT_TCAM_MAC1_NUM_BITS},\n-\t{CFA_P40_PROF_L2_CTXT_TCAM_T_OVID_BITPOS,\n-\t CFA_P40_PROF_L2_CTXT_TCAM_T_OVID_NUM_BITS},\n-\t{CFA_P40_PROF_L2_CTXT_TCAM_T_IVID_BITPOS,\n-\t CFA_P40_PROF_L2_CTXT_TCAM_T_IVID_NUM_BITS},\n-\t{CFA_P40_PROF_L2_CTXT_TCAM_SPARIF_BITPOS,\n-\t CFA_P40_PROF_L2_CTXT_TCAM_SPARIF_NUM_BITS},\n-\t{CFA_P40_PROF_L2_CTXT_TCAM_SVIF_BITPOS,\n-\t CFA_P40_PROF_L2_CTXT_TCAM_SVIF_NUM_BITS},\n-\t{CFA_P40_PROF_L2_CTXT_TCAM_MAC0_BITPOS,\n-\t CFA_P40_PROF_L2_CTXT_TCAM_MAC0_NUM_BITS},\n-\t{CFA_P40_PROF_L2_CTXT_TCAM_OVID_BITPOS,\n-\t CFA_P40_PROF_L2_CTXT_TCAM_OVID_NUM_BITS},\n-\t{CFA_P40_PROF_L2_CTXT_TCAM_IVID_BITPOS,\n-\t CFA_P40_PROF_L2_CTXT_TCAM_IVID_NUM_BITS},\n-};\n-\n-const struct hcapi_cfa_field cfa_p40_act_veb_tcam_layout[] = {\n-\t{CFA_P40_ACT_VEB_TCAM_VALID_BITPOS,\n-\t CFA_P40_ACT_VEB_TCAM_VALID_NUM_BITS},\n-\t{CFA_P40_ACT_VEB_TCAM_RESERVED_BITPOS,\n-\t CFA_P40_ACT_VEB_TCAM_RESERVED_NUM_BITS},\n-\t{CFA_P40_ACT_VEB_TCAM_PARIF_IN_BITPOS,\n-\t CFA_P40_ACT_VEB_TCAM_PARIF_IN_NUM_BITS},\n-\t{CFA_P40_ACT_VEB_TCAM_NUM_VTAGS_BITPOS,\n-\t CFA_P40_ACT_VEB_TCAM_NUM_VTAGS_NUM_BITS},\n-\t{CFA_P40_ACT_VEB_TCAM_MAC_BITPOS,\n-\t CFA_P40_ACT_VEB_TCAM_MAC_NUM_BITS},\n-\t{CFA_P40_ACT_VEB_TCAM_OVID_BITPOS,\n-\t CFA_P40_ACT_VEB_TCAM_OVID_NUM_BITS},\n-\t{CFA_P40_ACT_VEB_TCAM_IVID_BITPOS,\n-\t CFA_P40_ACT_VEB_TCAM_IVID_NUM_BITS},\n-};\n-\n-const struct hcapi_cfa_field cfa_p40_lkup_tcam_record_mem_layout[] = {\n-\t{CFA_P40_LKUP_TCAM_RECORD_MEM_VALID_BITPOS,\n-\t CFA_P40_LKUP_TCAM_RECORD_MEM_VALID_NUM_BITS},\n-\t{CFA_P40_LKUP_TCAM_RECORD_MEM_ACT_REC_PTR_BITPOS,\n-\t CFA_P40_LKUP_TCAM_RECORD_MEM_ACT_REC_PTR_NUM_BITS},\n-\t{CFA_P40_LKUP_TCAM_RECORD_MEM_STRENGTH_BITPOS,\n-\t CFA_P40_LKUP_TCAM_RECORD_MEM_STRENGTH_NUM_BITS},\n-};\n-\n-const struct hcapi_cfa_field cfa_p40_prof_ctxt_remap_mem_layout[] = {\n-\t{CFA_P40_PROF_CTXT_REMAP_MEM_TPID_ANTI_SPOOF_CTL_BITPOS,\n-\t CFA_P40_PROF_CTXT_REMAP_MEM_TPID_ANTI_SPOOF_CTL_NUM_BITS},\n-\t{CFA_P40_PROF_CTXT_REMAP_MEM_PRI_ANTI_SPOOF_CTL_BITPOS,\n-\t CFA_P40_PROF_CTXT_REMAP_MEM_PRI_ANTI_SPOOF_CTL_NUM_BITS},\n-\t{CFA_P40_PROF_CTXT_REMAP_MEM_BYP_SP_LKUP_BITPOS,\n-\t CFA_P40_PROF_CTXT_REMAP_MEM_BYP_SP_LKUP_NUM_BITS},\n-\t{CFA_P40_PROF_CTXT_REMAP_MEM_SP_REC_PTR_BITPOS,\n-\t CFA_P40_PROF_CTXT_REMAP_MEM_SP_REC_PTR_NUM_BITS},\n-\t{CFA_P40_PROF_CTXT_REMAP_MEM_BD_ACT_EN_BITPOS,\n-\t CFA_P40_PROF_CTXT_REMAP_MEM_BD_ACT_EN_NUM_BITS},\n-\t{CFA_P40_PROF_CTXT_REMAP_MEM_DEFAULT_TPID_BITPOS,\n-\t CFA_P40_PROF_CTXT_REMAP_MEM_DEFAULT_TPID_NUM_BITS},\n-\t{CFA_P40_PROF_CTXT_REMAP_MEM_ALLOWED_TPID_BITPOS,\n-\t CFA_P40_PROF_CTXT_REMAP_MEM_ALLOWED_TPID_NUM_BITS},\n-\t{CFA_P40_PROF_CTXT_REMAP_MEM_DEFAULT_PRI_BITPOS,\n-\t CFA_P40_PROF_CTXT_REMAP_MEM_DEFAULT_PRI_NUM_BITS},\n-\t{CFA_P40_PROF_CTXT_REMAP_MEM_ALLOWED_PRI_BITPOS,\n-\t CFA_P40_PROF_CTXT_REMAP_MEM_ALLOWED_PRI_NUM_BITS},\n-\t{CFA_P40_PROF_CTXT_REMAP_MEM_PARIF_BITPOS,\n-\t CFA_P40_PROF_CTXT_REMAP_MEM_PARIF_NUM_BITS},\n-\t{CFA_P40_PROF_CTXT_REMAP_MEM_BYP_LKUP_EN_BITPOS,\n-\t CFA_P40_PROF_CTXT_REMAP_MEM_BYP_LKUP_EN_NUM_BITS},\n-\t/* Fields below not generated through automation */\n-\t{CFA_P40_PROF_CTXT_REMAP_MEM_PROF_VNIC_BITPOS,\n-\t CFA_P40_PROF_CTXT_REMAP_MEM_PROF_VNIC_NUM_BITS},\n-\t{CFA_P40_PROF_CTXT_REMAP_MEM_PROF_FUNC_BITPOS,\n-\t CFA_P40_PROF_CTXT_REMAP_MEM_PROF_FUNC_NUM_BITS},\n-\t{CFA_P40_PROF_CTXT_REMAP_MEM_L2_CTXT_BITPOS,\n-\t CFA_P40_PROF_CTXT_REMAP_MEM_L2_CTXT_NUM_BITS},\n-\t{CFA_P40_PROF_CTXT_REMAP_MEM_ARP_BITPOS,\n-\t CFA_P40_PROF_CTXT_REMAP_MEM_ARP_NUM_BITS},\n-};\n-\n-const struct hcapi_cfa_field cfa_p40_prof_profile_tcam_remap_mem_layout[] = {\n-\t{CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_PL_BYP_LKUP_EN_BITPOS,\n-\t CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_PL_BYP_LKUP_EN_NUM_BITS},\n-\t{CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_EM_SEARCH_ENB_BITPOS,\n-\t CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_EM_SEARCH_ENB_NUM_BITS},\n-\t{CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_EM_PROFILE_ID_BITPOS,\n-\t CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_EM_PROFILE_ID_NUM_BITS},\n-\t{CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_EM_KEY_ID_BITPOS,\n-\t CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_EM_KEY_ID_NUM_BITS},\n-\t{CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_EM_KEY_MASK_BITPOS,\n-\t CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_EM_KEY_MASK_NUM_BITS},\n-\t{CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_TCAM_SEARCH_ENB_BITPOS,\n-\t CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_TCAM_SEARCH_ENB_NUM_BITS},\n-\t{CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_TCAM_PROFILE_ID_BITPOS,\n-\t CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_TCAM_PROFILE_ID_NUM_BITS},\n-\t{CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_TCAM_KEY_ID_BITPOS,\n-\t CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_TCAM_KEY_ID_NUM_BITS},\n-\t/* Fields below not generated through automation */\n-\t{CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_BYPASS_OPT_BITPOS,\n-\t CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_BYPASS_OPT_NUM_BITS},\n-\t{CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_ACT_REC_PTR_BITPOS,\n-\t CFA_P40_PROF_PROFILE_TCAM_REMAP_MEM_ACT_REC_PTR_NUM_BITS},\n-};\n-\n-const struct hcapi_cfa_field cfa_p40_prof_profile_tcam_layout[] = {\n-\t{CFA_P40_PROF_PROFILE_TCAM_VALID_BITPOS,\n-\t CFA_P40_PROF_PROFILE_TCAM_VALID_NUM_BITS},\n-\t{CFA_P40_PROF_PROFILE_TCAM_PKT_TYPE_BITPOS,\n-\t CFA_P40_PROF_PROFILE_TCAM_PKT_TYPE_NUM_BITS},\n-\t{CFA_P40_PROF_PROFILE_TCAM_RECYCLE_CNT_BITPOS,\n-\t CFA_P40_PROF_PROFILE_TCAM_RECYCLE_CNT_NUM_BITS},\n-\t{CFA_P40_PROF_PROFILE_TCAM_AGG_ERROR_BITPOS,\n-\t CFA_P40_PROF_PROFILE_TCAM_AGG_ERROR_NUM_BITS},\n-\t{CFA_P40_PROF_PROFILE_TCAM_PROF_FUNC_BITPOS,\n-\t CFA_P40_PROF_PROFILE_TCAM_PROF_FUNC_NUM_BITS},\n-\t{CFA_P40_PROF_PROFILE_TCAM_RESERVED_BITPOS,\n-\t CFA_P40_PROF_PROFILE_TCAM_RESERVED_NUM_BITS},\n-\t{CFA_P40_PROF_PROFILE_TCAM_HREC_NEXT_BITPOS,\n-\t CFA_P40_PROF_PROFILE_TCAM_HREC_NEXT_NUM_BITS},\n-\t{CFA_P40_PROF_PROFILE_TCAM_TL2_HDR_VALID_BITPOS,\n-\t CFA_P40_PROF_PROFILE_TCAM_TL2_HDR_VALID_NUM_BITS},\n-\t{CFA_P40_PROF_PROFILE_TCAM_TL2_HDR_TYPE_BITPOS,\n-\t CFA_P40_PROF_PROFILE_TCAM_TL2_HDR_TYPE_NUM_BITS},\n-\t{CFA_P40_PROF_PROFILE_TCAM_TL2_UC_MC_BC_BITPOS,\n-\t CFA_P40_PROF_PROFILE_TCAM_TL2_UC_MC_BC_NUM_BITS},\n-\t{CFA_P40_PROF_PROFILE_TCAM_TL2_VTAG_PRESENT_BITPOS,\n-\t CFA_P40_PROF_PROFILE_TCAM_TL2_VTAG_PRESENT_NUM_BITS},\n-\t{CFA_P40_PROF_PROFILE_TCAM_TL2_TWO_VTAGS_BITPOS,\n-\t CFA_P40_PROF_PROFILE_TCAM_TL2_TWO_VTAGS_NUM_BITS},\n-\t{CFA_P40_PROF_PROFILE_TCAM_TL3_VALID_BITPOS,\n-\t CFA_P40_PROF_PROFILE_TCAM_TL3_VALID_NUM_BITS},\n-\t{CFA_P40_PROF_PROFILE_TCAM_TL3_ERROR_BITPOS,\n-\t CFA_P40_PROF_PROFILE_TCAM_TL3_ERROR_NUM_BITS},\n-\t{CFA_P40_PROF_PROFILE_TCAM_TL3_HDR_TYPE_BITPOS,\n-\t CFA_P40_PROF_PROFILE_TCAM_TL3_HDR_TYPE_NUM_BITS},\n-\t{CFA_P40_PROF_PROFILE_TCAM_TL3_HDR_ISIP_BITPOS,\n-\t CFA_P40_PROF_PROFILE_TCAM_TL3_HDR_ISIP_NUM_BITS},\n-\t{CFA_P40_PROF_PROFILE_TCAM_TL3_IPV6_CMP_SRC_BITPOS,\n-\t CFA_P40_PROF_PROFILE_TCAM_TL3_IPV6_CMP_SRC_NUM_BITS},\n-\t{CFA_P40_PROF_PROFILE_TCAM_TL3_IPV6_CMP_DEST_BITPOS,\n-\t CFA_P40_PROF_PROFILE_TCAM_TL3_IPV6_CMP_DEST_NUM_BITS},\n-\t{CFA_P40_PROF_PROFILE_TCAM_TL4_HDR_VALID_BITPOS,\n-\t CFA_P40_PROF_PROFILE_TCAM_TL4_HDR_VALID_NUM_BITS},\n-\t{CFA_P40_PROF_PROFILE_TCAM_TL4_HDR_ERROR_BITPOS,\n-\t CFA_P40_PROF_PROFILE_TCAM_TL4_HDR_ERROR_NUM_BITS},\n-\t{CFA_P40_PROF_PROFILE_TCAM_TL4_HDR_TYPE_BITPOS,\n-\t CFA_P40_PROF_PROFILE_TCAM_TL4_HDR_TYPE_NUM_BITS},\n-\t{CFA_P40_PROF_PROFILE_TCAM_TL4_HDR_IS_UDP_TCP_BITPOS,\n-\t CFA_P40_PROF_PROFILE_TCAM_TL4_HDR_IS_UDP_TCP_NUM_BITS},\n-\t{CFA_P40_PROF_PROFILE_TCAM_TUN_HDR_VALID_BITPOS,\n-\t CFA_P40_PROF_PROFILE_TCAM_TUN_HDR_VALID_NUM_BITS},\n-\t{CFA_P40_PROF_PROFILE_TCAM_TUN_HDR_ERR_BITPOS,\n-\t CFA_P40_PROF_PROFILE_TCAM_TUN_HDR_ERR_NUM_BITS},\n-\t{CFA_P40_PROF_PROFILE_TCAM_TUN_HDR_TYPE_BITPOS,\n-\t CFA_P40_PROF_PROFILE_TCAM_TUN_HDR_TYPE_NUM_BITS},\n-\t{CFA_P40_PROF_PROFILE_TCAM_TUN_HDR_FLAGS_BITPOS,\n-\t CFA_P40_PROF_PROFILE_TCAM_TUN_HDR_FLAGS_NUM_BITS},\n-\t{CFA_P40_PROF_PROFILE_TCAM_L2_HDR_VALID_BITPOS,\n-\t CFA_P40_PROF_PROFILE_TCAM_L2_HDR_VALID_NUM_BITS},\n-\t{CFA_P40_PROF_PROFILE_TCAM_L2_HDR_ERROR_BITPOS,\n-\t CFA_P40_PROF_PROFILE_TCAM_L2_HDR_ERROR_NUM_BITS},\n-\t{CFA_P40_PROF_PROFILE_TCAM_L2_HDR_TYPE_BITPOS,\n-\t CFA_P40_PROF_PROFILE_TCAM_L2_HDR_TYPE_NUM_BITS},\n-\t{CFA_P40_PROF_PROFILE_TCAM_L2_UC_MC_BC_BITPOS,\n-\t CFA_P40_PROF_PROFILE_TCAM_L2_UC_MC_BC_NUM_BITS},\n-\t{CFA_P40_PROF_PROFILE_TCAM_L2_VTAG_PRESENT_BITPOS,\n-\t CFA_P40_PROF_PROFILE_TCAM_L2_VTAG_PRESENT_NUM_BITS},\n-\t{CFA_P40_PROF_PROFILE_TCAM_L2_TWO_VTAGS_BITPOS,\n-\t CFA_P40_PROF_PROFILE_TCAM_L2_TWO_VTAGS_NUM_BITS},\n-\t{CFA_P40_PROF_PROFILE_TCAM_L3_VALID_BITPOS,\n-\t CFA_P40_PROF_PROFILE_TCAM_L3_VALID_NUM_BITS},\n-\t{CFA_P40_PROF_PROFILE_TCAM_L3_ERROR_BITPOS,\n-\t CFA_P40_PROF_PROFILE_TCAM_L3_ERROR_NUM_BITS},\n-\t{CFA_P40_PROF_PROFILE_TCAM_L3_HDR_TYPE_BITPOS,\n-\t CFA_P40_PROF_PROFILE_TCAM_L3_HDR_TYPE_NUM_BITS},\n-\t{CFA_P40_PROF_PROFILE_TCAM_L3_HDR_ISIP_BITPOS,\n-\t CFA_P40_PROF_PROFILE_TCAM_L3_HDR_ISIP_NUM_BITS},\n-\t{CFA_P40_PROF_PROFILE_TCAM_L3_IPV6_CMP_SRC_BITPOS,\n-\t CFA_P40_PROF_PROFILE_TCAM_L3_IPV6_CMP_SRC_NUM_BITS},\n-\t{CFA_P40_PROF_PROFILE_TCAM_L3_IPV6_CMP_DEST_BITPOS,\n-\t CFA_P40_PROF_PROFILE_TCAM_L3_IPV6_CMP_DEST_NUM_BITS},\n-\t{CFA_P40_PROF_PROFILE_TCAM_L4_HDR_VALID_BITPOS,\n-\t CFA_P40_PROF_PROFILE_TCAM_L4_HDR_VALID_NUM_BITS},\n-\t{CFA_P40_PROF_PROFILE_TCAM_L4_HDR_ERROR_BITPOS,\n-\t CFA_P40_PROF_PROFILE_TCAM_L4_HDR_ERROR_NUM_BITS},\n-\t{CFA_P40_PROF_PROFILE_TCAM_L4_HDR_TYPE_BITPOS,\n-\t CFA_P40_PROF_PROFILE_TCAM_L4_HDR_TYPE_NUM_BITS},\n-\t{CFA_P40_PROF_PROFILE_TCAM_L4_HDR_IS_UDP_TCP_BITPOS,\n-\t CFA_P40_PROF_PROFILE_TCAM_L4_HDR_IS_UDP_TCP_NUM_BITS},\n-};\n-\n-/**************************************************************************/\n-/**\n- * Non-autogenerated fields\n- */\n-\n-const struct hcapi_cfa_field cfa_p40_eem_key_tbl_layout[] = {\n-\t{CFA_P40_EEM_KEY_TBL_VALID_BITPOS,\n-\t CFA_P40_EEM_KEY_TBL_VALID_NUM_BITS},\n-\n-\t{CFA_P40_EEM_KEY_TBL_L1_CACHEABLE_BITPOS,\n-\t CFA_P40_EEM_KEY_TBL_L1_CACHEABLE_NUM_BITS},\n-\n-\t{CFA_P40_EEM_KEY_TBL_STRENGTH_BITPOS,\n-\t CFA_P40_EEM_KEY_TBL_STRENGTH_NUM_BITS},\n-\n-\t{CFA_P40_EEM_KEY_TBL_KEY_SZ_BITPOS,\n-\t CFA_P40_EEM_KEY_TBL_KEY_SZ_NUM_BITS},\n-\n-\t{CFA_P40_EEM_KEY_TBL_REC_SZ_BITPOS,\n-\t CFA_P40_EEM_KEY_TBL_REC_SZ_NUM_BITS},\n-\n-\t{CFA_P40_EEM_KEY_TBL_ACT_REC_INT_BITPOS,\n-\t CFA_P40_EEM_KEY_TBL_ACT_REC_INT_NUM_BITS},\n-\n-\t{CFA_P40_EEM_KEY_TBL_EXT_FLOW_CTR_BITPOS,\n-\t CFA_P40_EEM_KEY_TBL_EXT_FLOW_CTR_NUM_BITS},\n-\n-\t{CFA_P40_EEM_KEY_TBL_AR_PTR_BITPOS,\n-\t CFA_P40_EEM_KEY_TBL_AR_PTR_NUM_BITS},\n-\n-};\n-\n-const struct hcapi_cfa_field cfa_p40_mirror_tbl_layout[] = {\n-\t{CFA_P40_MIRROR_TBL_SP_PTR_BITPOS,\n-\t CFA_P40_MIRROR_TBL_SP_PTR_NUM_BITS},\n-\n-\t{CFA_P40_MIRROR_TBL_IGN_DROP_BITPOS,\n-\t CFA_P40_MIRROR_TBL_IGN_DROP_NUM_BITS},\n-\n-\t{CFA_P40_MIRROR_TBL_COPY_BITPOS,\n-\t CFA_P40_MIRROR_TBL_COPY_NUM_BITS},\n-\n-\t{CFA_P40_MIRROR_TBL_EN_BITPOS,\n-\t CFA_P40_MIRROR_TBL_EN_NUM_BITS},\n-\n-\t{CFA_P40_MIRROR_TBL_AR_PTR_BITPOS,\n-\t CFA_P40_MIRROR_TBL_AR_PTR_NUM_BITS},\n-};\n-\n-/* P45 Defines */\n-\n-const struct hcapi_cfa_field cfa_p45_prof_l2_ctxt_tcam_layout[] = {\n-\t{CFA_P45_PROF_L2_CTXT_TCAM_VALID_BITPOS,\n-\t CFA_P45_PROF_L2_CTXT_TCAM_VALID_NUM_BITS},\n-\t{CFA_P45_PROF_L2_CTXT_TCAM_SPARIF_BITPOS,\n-\t CFA_P45_PROF_L2_CTXT_TCAM_SPARIF_NUM_BITS},\n-\t{CFA_P40_PROF_L2_CTXT_TCAM_KEY_TYPE_BITPOS,\n-\t CFA_P40_PROF_L2_CTXT_TCAM_KEY_TYPE_NUM_BITS},\n-\t{CFA_P40_PROF_L2_CTXT_TCAM_TUN_HDR_TYPE_BITPOS,\n-\t CFA_P40_PROF_L2_CTXT_TCAM_TUN_HDR_TYPE_NUM_BITS},\n-\t{CFA_P40_PROF_L2_CTXT_TCAM_T_L2_NUMTAGS_BITPOS,\n-\t CFA_P40_PROF_L2_CTXT_TCAM_T_L2_NUMTAGS_NUM_BITS},\n-\t{CFA_P40_PROF_L2_CTXT_TCAM_L2_NUMTAGS_BITPOS,\n-\t CFA_P40_PROF_L2_CTXT_TCAM_L2_NUMTAGS_NUM_BITS},\n-\t{CFA_P40_PROF_L2_CTXT_TCAM_MAC1_BITPOS,\n-\t CFA_P40_PROF_L2_CTXT_TCAM_MAC1_NUM_BITS},\n-\t{CFA_P40_PROF_L2_CTXT_TCAM_T_OVID_BITPOS,\n-\t CFA_P40_PROF_L2_CTXT_TCAM_T_OVID_NUM_BITS},\n-\t{CFA_P40_PROF_L2_CTXT_TCAM_T_IVID_BITPOS,\n-\t CFA_P40_PROF_L2_CTXT_TCAM_T_IVID_NUM_BITS},\n-\t{CFA_P45_PROF_L2_CTXT_TCAM_SVIF_BITPOS,\n-\t CFA_P45_PROF_L2_CTXT_TCAM_SVIF_NUM_BITS},\n-\t{CFA_P40_PROF_L2_CTXT_TCAM_MAC0_BITPOS,\n-\t CFA_P40_PROF_L2_CTXT_TCAM_MAC0_NUM_BITS},\n-\t{CFA_P40_PROF_L2_CTXT_TCAM_OVID_BITPOS,\n-\t CFA_P40_PROF_L2_CTXT_TCAM_OVID_NUM_BITS},\n-\t{CFA_P40_PROF_L2_CTXT_TCAM_IVID_BITPOS,\n-\t CFA_P40_PROF_L2_CTXT_TCAM_IVID_NUM_BITS},\n-};\n-#endif /* _CFA_P40_TBL_H_ */\ndiff --git a/drivers/net/bnxt/meson.build b/drivers/net/bnxt/meson.build\nindex 117c753489..f7a4e7a013 100644\n--- a/drivers/net/bnxt/meson.build\n+++ b/drivers/net/bnxt/meson.build\n@@ -8,10 +8,17 @@ if is_windows\n     subdir_done()\n endif\n \n-headers = files('rte_pmd_bnxt.h')\n+cflags_options = [\n+        '-DSUPPORT_CFA_HW_ALL=1',\n+]\n+\n+foreach option:cflags_options\n+        if cc.has_argument(option)\n+                cflags += option\n+        endif\n+endforeach\n \n-includes += include_directories('tf_ulp')\n-includes += include_directories('tf_core')\n+headers = files('rte_pmd_bnxt.h')\n \n sources = files(\n         'bnxt_cpr.c',\n@@ -30,53 +37,6 @@ sources = files(\n         'bnxt_vnic.c',\n         'bnxt_reps.c',\n \n-        'tf_core/tf_core.c',\n-        'tf_core/bitalloc.c',\n-        'tf_core/tf_msg.c',\n-        'tf_core/rand.c',\n-        'tf_core/stack.c',\n-        'tf_core/tf_em_common.c',\n-        'tf_core/tf_em_internal.c',\n-        'tf_core/tf_rm.c',\n-        'tf_core/tf_tbl.c',\n-        'tf_core/tfp.c',\n-        'tf_core/tf_session.c',\n-        'tf_core/tf_device.c',\n-        'tf_core/tf_device_p4.c',\n-        'tf_core/tf_identifier.c',\n-        'tf_core/tf_shadow_tbl.c',\n-        'tf_core/tf_shadow_tcam.c',\n-        'tf_core/tf_tcam.c',\n-        'tf_core/tf_util.c',\n-        'tf_core/tf_if_tbl.c',\n-        'tf_core/ll.c',\n-        'tf_core/tf_global_cfg.c',\n-        'tf_core/tf_em_host.c',\n-        'tf_core/tf_shadow_identifier.c',\n-        'tf_core/tf_hash.c',\n-\n-        'hcapi/hcapi_cfa_p4.c',\n-\n-        'tf_ulp/bnxt_ulp.c',\n-        'tf_ulp/ulp_mark_mgr.c',\n-        'tf_ulp/ulp_flow_db.c',\n-        'tf_ulp/ulp_template_db_tbl.c',\n-        'tf_ulp/ulp_template_db_class.c',\n-        'tf_ulp/ulp_template_db_act.c',\n-        'tf_ulp/ulp_utils.c',\n-        'tf_ulp/ulp_mapper.c',\n-        'tf_ulp/ulp_matcher.c',\n-        'tf_ulp/ulp_rte_parser.c',\n-        'tf_ulp/bnxt_ulp_flow.c',\n-        'tf_ulp/ulp_port_db.c',\n-        'tf_ulp/ulp_def_rules.c',\n-        'tf_ulp/ulp_fc_mgr.c',\n-        'tf_ulp/ulp_tun.c',\n-        'tf_ulp/ulp_template_db_wh_plus_act.c',\n-        'tf_ulp/ulp_template_db_wh_plus_class.c',\n-        'tf_ulp/ulp_template_db_stingray_act.c',\n-        'tf_ulp/ulp_template_db_stingray_class.c',\n-\n         'rte_pmd_bnxt.c',\n )\n \n@@ -85,3 +45,8 @@ if arch_subdir == 'x86'\n elif arch_subdir == 'arm' and host_machine.cpu_family().startswith('aarch64')\n     sources += files('bnxt_rxtx_vec_neon.c')\n endif\n+\n+#Add the subdirectories that need to be compiled\n+subdir('tf_ulp')\n+subdir('tf_core')\n+subdir('hcapi/cfa')\ndiff --git a/drivers/net/bnxt/tf_core/meson.build b/drivers/net/bnxt/tf_core/meson.build\nnew file mode 100644\nindex 0000000000..b23e0fbe70\n--- /dev/null\n+++ b/drivers/net/bnxt/tf_core/meson.build\n@@ -0,0 +1,33 @@\n+# SPDX-License-Identifier: BSD-3-Clause\n+# Copyright(c) 2018 Intel Corporation\n+# Copyright(c) 2021 Broadcom\n+\n+#Include the folder for headers\n+includes += include_directories('.')\n+\n+#Add the source files\n+sources += files(\n+        'tf_core.c',\n+        'bitalloc.c',\n+        'tf_msg.c',\n+        'rand.c',\n+        'stack.c',\n+        'tf_em_common.c',\n+        'tf_em_internal.c',\n+        'tf_rm.c',\n+        'tf_tbl.c',\n+        'tfp.c',\n+        'tf_session.c',\n+        'tf_device.c',\n+        'tf_device_p4.c',\n+        'tf_identifier.c',\n+        'tf_shadow_tbl.c',\n+        'tf_shadow_tcam.c',\n+        'tf_tcam.c',\n+        'tf_util.c',\n+        'tf_if_tbl.c',\n+        'll.c',\n+        'tf_global_cfg.c',\n+        'tf_em_host.c',\n+        'tf_shadow_identifier.c',\n+        'tf_hash.c')\ndiff --git a/drivers/net/bnxt/tf_core/tf_core.h b/drivers/net/bnxt/tf_core/tf_core.h\nindex a47edff1e3..5e458c58fb 100644\n--- a/drivers/net/bnxt/tf_core/tf_core.h\n+++ b/drivers/net/bnxt/tf_core/tf_core.h\n@@ -10,7 +10,7 @@\n #include <stdlib.h>\n #include <stdbool.h>\n #include <stdio.h>\n-#include \"hcapi/hcapi_cfa_defs.h\"\n+#include \"hcapi/cfa/hcapi_cfa_defs.h\"\n #include \"tf_project.h\"\n \n /**\ndiff --git a/drivers/net/bnxt/tf_core/tf_em.h b/drivers/net/bnxt/tf_core/tf_em.h\nindex 23591272bd..b5c3acb09a 100644\n--- a/drivers/net/bnxt/tf_core/tf_em.h\n+++ b/drivers/net/bnxt/tf_core/tf_em.h\n@@ -9,7 +9,7 @@\n #include \"tf_core.h\"\n #include \"tf_session.h\"\n \n-#include \"hcapi/hcapi_cfa_defs.h\"\n+#include \"hcapi/cfa/hcapi_cfa_defs.h\"\n \n #define TF_EM_MIN_ENTRIES     (1 << 15) /* 32K */\n #define TF_EM_MAX_ENTRIES     (1 << 27) /* 128M */\ndiff --git a/drivers/net/bnxt/tf_ulp/meson.build b/drivers/net/bnxt/tf_ulp/meson.build\nnew file mode 100644\nindex 0000000000..98cbdf3177\n--- /dev/null\n+++ b/drivers/net/bnxt/tf_ulp/meson.build\n@@ -0,0 +1,28 @@\n+# SPDX-License-Identifier: BSD-3-Clause\n+# Copyright(c) 2018 Intel Corporation\n+# Copyright(c) 2021 Broadcom\n+\n+#Include the folder for headers\n+includes += include_directories('.')\n+\n+#Add the source files\n+sources += files(\n+        'bnxt_ulp.c',\n+        'ulp_mark_mgr.c',\n+        'ulp_flow_db.c',\n+        'ulp_template_db_tbl.c',\n+        'ulp_template_db_class.c',\n+        'ulp_template_db_act.c',\n+        'ulp_utils.c',\n+        'ulp_mapper.c',\n+        'ulp_matcher.c',\n+        'ulp_rte_parser.c',\n+        'bnxt_ulp_flow.c',\n+        'ulp_port_db.c',\n+        'ulp_def_rules.c',\n+        'ulp_fc_mgr.c',\n+        'ulp_tun.c',\n+        'ulp_template_db_wh_plus_act.c',\n+        'ulp_template_db_wh_plus_class.c',\n+        'ulp_template_db_stingray_act.c',\n+        'ulp_template_db_stingray_class.c')\n",
    "prefixes": [
        "01/58"
    ]
}