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GET /api/patches/93007/?format=api
{ "id": 93007, "url": "http://patches.dpdk.org/api/patches/93007/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210506142526.28245-3-mk@semihalf.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210506142526.28245-3-mk@semihalf.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210506142526.28245-3-mk@semihalf.com", "date": "2021-05-06T14:25:06", "name": "[v3,02/22] net/ena/base: unify arg names for the functions", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "5ae8d96523361287b797b2e36d6c925dd9098348", "submitter": { "id": 786, "url": "http://patches.dpdk.org/api/people/786/?format=api", "name": "Michal Krawczyk", "email": "mk@semihalf.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210506142526.28245-3-mk@semihalf.com/mbox/", "series": [ { "id": 16861, "url": "http://patches.dpdk.org/api/series/16861/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=16861", "date": "2021-05-06T14:25:04", "name": "net/ena: update ENA PMD to v2.3.0", "version": 3, "mbox": "http://patches.dpdk.org/series/16861/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/93007/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/93007/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 20C07A0524;\n\tThu, 6 May 2021 16:25:58 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id F400C410FF;\n\tThu, 6 May 2021 16:25:46 +0200 (CEST)", "from mail-lj1-f171.google.com (mail-lj1-f171.google.com\n [209.85.208.171])\n by mails.dpdk.org (Postfix) with ESMTP id 448E0410F9\n for <dev@dpdk.org>; Thu, 6 May 2021 16:25:45 +0200 (CEST)", "by mail-lj1-f171.google.com with SMTP id u20so7253818lja.13\n for <dev@dpdk.org>; Thu, 06 May 2021 07:25:45 -0700 (PDT)", "from DESKTOP-U5LNN3J.localdomain (89-79-189-199.dynamic.chello.pl.\n [89.79.189.199])\n by smtp.gmail.com with ESMTPSA id b40sm892908ljr.101.2021.05.06.07.25.43\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Thu, 06 May 2021 07:25:43 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=semihalf-com.20150623.gappssmtp.com; s=20150623;\n h=from:to:cc:subject:date:message-id:in-reply-to:references\n :mime-version:content-transfer-encoding;\n bh=eD9i65pBbnphpAjWSmo42fdxLdI0C6CvXTcwXD/pSEg=;\n b=DqVXWksEJimuyKdxBvkUd+B2ankbROIVRpN51Kb9Wwwl5nXGGQQ1Gf8wxu5wSJCpVl\n STJTKm8ha8u8izXsVcokx5FUNjLg3HPYqQxAuAq3uYZc370+3LQraGfVM2wDt5+jLU05\n FaVQPMUzGM97hVFCXnRCTJsU2zSF+ZFfIJ+g+UQswC5PwfLmkfgLmP1XZVfSVtS3WrbW\n IkL5cey7oKpsz7lTxpWrpklxF8xD1qqp6vf9XoxoN7Xk5dO2rpzsy+V1vPvr8O9OJPFM\n jsHGpBmklz45lQlzhErszklnM8byqhQaomdQehhxIOt9E2vblT9/aH8O5PKx8vNqBf0n\n nTjA==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20161025;\n h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n :references:mime-version:content-transfer-encoding;\n bh=eD9i65pBbnphpAjWSmo42fdxLdI0C6CvXTcwXD/pSEg=;\n b=qfWUxm7nJlDmQsTUc4Hg4kKB/mrj26W9x3t1a510ujhHLbiIAWI4uOYzWATDAIDG9F\n sf0UxiHwGmutdeuI65MjR+qMEIKRttMHa/MVcPfJrnTJe2dYB3scOqsTBahqqe5jS6rs\n 0tQYI73ivzdcaZLoSk4veQ8ZroWAeX9VmRxXUOWAj/FSPO3Leoxkgp/j/A8xhD9XbYcn\n c4lANsQQKDPmG5x+EYN6alXZVjhUlW6zwTqiWjMcBcEbHxQz4p8cooQxGjwrk2OIXBPN\n 8Gu5IKCz3uLLLQqQjjZl5Slij94LhY7qYn7T23KIfNJrcnx5NXtJNYb/8A903r3yic9C\n mAHQ==", "X-Gm-Message-State": "AOAM533Mi00LjKTdQE8sjegvTmjrOeV8xZba98eeaulmc9UiNuKm/IZJ\n BVyjMtoS37NSsUR2iak67lgr63HvpOmzCtfE", "X-Google-Smtp-Source": "\n ABdhPJx11zcPLVE9FN1iEn7UU1jf2T/QdCNaGB3lBr7Wx39ZLKwT7QN0YWDMCcqv9TyFw7CLM90XYg==", "X-Received": "by 2002:a2e:9152:: with SMTP id q18mr3687316ljg.188.1620311144505;\n Thu, 06 May 2021 07:25:44 -0700 (PDT)", "From": "Michal Krawczyk <mk@semihalf.com>", "To": "dev@dpdk.org", "Cc": "ndagan@amazon.com, gtzalik@amazon.com, igorch@amazon.com,\n upstream@semihalf.com, Michal Krawczyk <mk@semihalf.com>", "Date": "Thu, 6 May 2021 16:25:06 +0200", "Message-Id": "<20210506142526.28245-3-mk@semihalf.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20210506142526.28245-1-mk@semihalf.com>", "References": "<20210505073348.6394-1-mk@semihalf.com>\n <20210506142526.28245-1-mk@semihalf.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH v3 02/22] net/ena/base: unify arg names for the\n functions", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Instead of using 'queue' for struct ena_com_admin_queue and 'dev' for\nstruct ena_com_dev variables, use more descriptive 'admin_queue' and\n'ena_dev'.\n\nThis also unifies the names of variables of the type struct ena_com_dev\nin the driver.\n\nSigned-off-by: Michal Krawczyk <mk@semihalf.com>\nReviewed-by: Igor Chauskin <igorch@amazon.com>\nReviewed-by: Guy Tzalik <gtzalik@amazon.com>\n---\nv3:\n* Fix typo in the commit log of the version upgrade patch.\n\n drivers/net/ena/base/ena_com.c | 74 +++++++++++++++++-----------------\n drivers/net/ena/base/ena_com.h | 2 +-\n 2 files changed, 38 insertions(+), 38 deletions(-)", "diff": "diff --git a/drivers/net/ena/base/ena_com.c b/drivers/net/ena/base/ena_com.c\nindex aae68721fb..f7258254a5 100644\n--- a/drivers/net/ena/base/ena_com.c\n+++ b/drivers/net/ena/base/ena_com.c\n@@ -80,12 +80,12 @@ static int ena_com_mem_addr_set(struct ena_com_dev *ena_dev,\n \treturn 0;\n }\n \n-static int ena_com_admin_init_sq(struct ena_com_admin_queue *queue)\n+static int ena_com_admin_init_sq(struct ena_com_admin_queue *admin_queue)\n {\n-\tstruct ena_com_admin_sq *sq = &queue->sq;\n-\tu16 size = ADMIN_SQ_SIZE(queue->q_depth);\n+\tstruct ena_com_admin_sq *sq = &admin_queue->sq;\n+\tu16 size = ADMIN_SQ_SIZE(admin_queue->q_depth);\n \n-\tENA_MEM_ALLOC_COHERENT(queue->q_dmadev, size, sq->entries, sq->dma_addr,\n+\tENA_MEM_ALLOC_COHERENT(admin_queue->q_dmadev, size, sq->entries, sq->dma_addr,\n \t\t\t sq->mem_handle);\n \n \tif (!sq->entries) {\n@@ -102,12 +102,12 @@ static int ena_com_admin_init_sq(struct ena_com_admin_queue *queue)\n \treturn 0;\n }\n \n-static int ena_com_admin_init_cq(struct ena_com_admin_queue *queue)\n+static int ena_com_admin_init_cq(struct ena_com_admin_queue *admin_queue)\n {\n-\tstruct ena_com_admin_cq *cq = &queue->cq;\n-\tu16 size = ADMIN_CQ_SIZE(queue->q_depth);\n+\tstruct ena_com_admin_cq *cq = &admin_queue->cq;\n+\tu16 size = ADMIN_CQ_SIZE(admin_queue->q_depth);\n \n-\tENA_MEM_ALLOC_COHERENT(queue->q_dmadev, size, cq->entries, cq->dma_addr,\n+\tENA_MEM_ALLOC_COHERENT(admin_queue->q_dmadev, size, cq->entries, cq->dma_addr,\n \t\t\t cq->mem_handle);\n \n \tif (!cq->entries) {\n@@ -121,16 +121,16 @@ static int ena_com_admin_init_cq(struct ena_com_admin_queue *queue)\n \treturn 0;\n }\n \n-static int ena_com_admin_init_aenq(struct ena_com_dev *dev,\n+static int ena_com_admin_init_aenq(struct ena_com_dev *ena_dev,\n \t\t\t\t struct ena_aenq_handlers *aenq_handlers)\n {\n-\tstruct ena_com_aenq *aenq = &dev->aenq;\n+\tstruct ena_com_aenq *aenq = &ena_dev->aenq;\n \tu32 addr_low, addr_high, aenq_caps;\n \tu16 size;\n \n-\tdev->aenq.q_depth = ENA_ASYNC_QUEUE_DEPTH;\n+\tena_dev->aenq.q_depth = ENA_ASYNC_QUEUE_DEPTH;\n \tsize = ADMIN_AENQ_SIZE(ENA_ASYNC_QUEUE_DEPTH);\n-\tENA_MEM_ALLOC_COHERENT(dev->dmadev, size,\n+\tENA_MEM_ALLOC_COHERENT(ena_dev->dmadev, size,\n \t\t\taenq->entries,\n \t\t\taenq->dma_addr,\n \t\t\taenq->mem_handle);\n@@ -146,15 +146,15 @@ static int ena_com_admin_init_aenq(struct ena_com_dev *dev,\n \taddr_low = ENA_DMA_ADDR_TO_UINT32_LOW(aenq->dma_addr);\n \taddr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(aenq->dma_addr);\n \n-\tENA_REG_WRITE32(dev->bus, addr_low, dev->reg_bar + ENA_REGS_AENQ_BASE_LO_OFF);\n-\tENA_REG_WRITE32(dev->bus, addr_high, dev->reg_bar + ENA_REGS_AENQ_BASE_HI_OFF);\n+\tENA_REG_WRITE32(ena_dev->bus, addr_low, ena_dev->reg_bar + ENA_REGS_AENQ_BASE_LO_OFF);\n+\tENA_REG_WRITE32(ena_dev->bus, addr_high, ena_dev->reg_bar + ENA_REGS_AENQ_BASE_HI_OFF);\n \n \taenq_caps = 0;\n-\taenq_caps |= dev->aenq.q_depth & ENA_REGS_AENQ_CAPS_AENQ_DEPTH_MASK;\n+\taenq_caps |= ena_dev->aenq.q_depth & ENA_REGS_AENQ_CAPS_AENQ_DEPTH_MASK;\n \taenq_caps |= (sizeof(struct ena_admin_aenq_entry) <<\n \t\tENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_SHIFT) &\n \t\tENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_MASK;\n-\tENA_REG_WRITE32(dev->bus, aenq_caps, dev->reg_bar + ENA_REGS_AENQ_CAPS_OFF);\n+\tENA_REG_WRITE32(ena_dev->bus, aenq_caps, ena_dev->reg_bar + ENA_REGS_AENQ_CAPS_OFF);\n \n \tif (unlikely(!aenq_handlers)) {\n \t\tena_trc_err(\"aenq handlers pointer is NULL\\n\");\n@@ -173,31 +173,31 @@ static void comp_ctxt_release(struct ena_com_admin_queue *queue,\n \tATOMIC32_DEC(&queue->outstanding_cmds);\n }\n \n-static struct ena_comp_ctx *get_comp_ctxt(struct ena_com_admin_queue *queue,\n+static struct ena_comp_ctx *get_comp_ctxt(struct ena_com_admin_queue *admin_queue,\n \t\t\t\t\t u16 command_id, bool capture)\n {\n-\tif (unlikely(command_id >= queue->q_depth)) {\n+\tif (unlikely(command_id >= admin_queue->q_depth)) {\n \t\tena_trc_err(\"command id is larger than the queue size. cmd_id: %u queue size %d\\n\",\n-\t\t\t command_id, queue->q_depth);\n+\t\t\t command_id, admin_queue->q_depth);\n \t\treturn NULL;\n \t}\n \n-\tif (unlikely(!queue->comp_ctx)) {\n+\tif (unlikely(!admin_queue->comp_ctx)) {\n \t\tena_trc_err(\"Completion context is NULL\\n\");\n \t\treturn NULL;\n \t}\n \n-\tif (unlikely(queue->comp_ctx[command_id].occupied && capture)) {\n+\tif (unlikely(admin_queue->comp_ctx[command_id].occupied && capture)) {\n \t\tena_trc_err(\"Completion context is occupied\\n\");\n \t\treturn NULL;\n \t}\n \n \tif (capture) {\n-\t\tATOMIC32_INC(&queue->outstanding_cmds);\n-\t\tqueue->comp_ctx[command_id].occupied = true;\n+\t\tATOMIC32_INC(&admin_queue->outstanding_cmds);\n+\t\tadmin_queue->comp_ctx[command_id].occupied = true;\n \t}\n \n-\treturn &queue->comp_ctx[command_id];\n+\treturn &admin_queue->comp_ctx[command_id];\n }\n \n static struct ena_comp_ctx *__ena_com_submit_admin_cmd(struct ena_com_admin_queue *admin_queue,\n@@ -260,20 +260,20 @@ static struct ena_comp_ctx *__ena_com_submit_admin_cmd(struct ena_com_admin_queu\n \treturn comp_ctx;\n }\n \n-static int ena_com_init_comp_ctxt(struct ena_com_admin_queue *queue)\n+static int ena_com_init_comp_ctxt(struct ena_com_admin_queue *admin_queue)\n {\n-\tsize_t size = queue->q_depth * sizeof(struct ena_comp_ctx);\n+\tsize_t size = admin_queue->q_depth * sizeof(struct ena_comp_ctx);\n \tstruct ena_comp_ctx *comp_ctx;\n \tu16 i;\n \n-\tqueue->comp_ctx = ENA_MEM_ALLOC(queue->q_dmadev, size);\n-\tif (unlikely(!queue->comp_ctx)) {\n+\tadmin_queue->comp_ctx = ENA_MEM_ALLOC(admin_queue->q_dmadev, size);\n+\tif (unlikely(!admin_queue->comp_ctx)) {\n \t\tena_trc_err(\"memory allocation failed\\n\");\n \t\treturn ENA_COM_NO_MEM;\n \t}\n \n-\tfor (i = 0; i < queue->q_depth; i++) {\n-\t\tcomp_ctx = get_comp_ctxt(queue, i, false);\n+\tfor (i = 0; i < admin_queue->q_depth; i++) {\n+\t\tcomp_ctx = get_comp_ctxt(admin_queue, i, false);\n \t\tif (comp_ctx)\n \t\t\tENA_WAIT_EVENT_INIT(comp_ctx->wait_event);\n \t}\n@@ -2049,10 +2049,10 @@ void ena_com_admin_q_comp_intr_handler(struct ena_com_dev *ena_dev)\n /* ena_handle_specific_aenq_event:\n * return the handler that is relevant to the specific event group\n */\n-static ena_aenq_handler ena_com_get_specific_aenq_cb(struct ena_com_dev *dev,\n+static ena_aenq_handler ena_com_get_specific_aenq_cb(struct ena_com_dev *ena_dev,\n \t\t\t\t\t\t u16 group)\n {\n-\tstruct ena_aenq_handlers *aenq_handlers = dev->aenq.aenq_handlers;\n+\tstruct ena_aenq_handlers *aenq_handlers = ena_dev->aenq.aenq_handlers;\n \n \tif ((group < ENA_MAX_HANDLERS) && aenq_handlers->handlers[group])\n \t\treturn aenq_handlers->handlers[group];\n@@ -2064,11 +2064,11 @@ static ena_aenq_handler ena_com_get_specific_aenq_cb(struct ena_com_dev *dev,\n * handles the aenq incoming events.\n * pop events from the queue and apply the specific handler\n */\n-void ena_com_aenq_intr_handler(struct ena_com_dev *dev, void *data)\n+void ena_com_aenq_intr_handler(struct ena_com_dev *ena_dev, void *data)\n {\n \tstruct ena_admin_aenq_entry *aenq_e;\n \tstruct ena_admin_aenq_common_desc *aenq_common;\n-\tstruct ena_com_aenq *aenq = &dev->aenq;\n+\tstruct ena_com_aenq *aenq = &ena_dev->aenq;\n \tu64 timestamp;\n \tena_aenq_handler handler_cb;\n \tu16 masked_head, processed = 0;\n@@ -2096,7 +2096,7 @@ void ena_com_aenq_intr_handler(struct ena_com_dev *dev, void *data)\n \t\t\t timestamp);\n \n \t\t/* Handle specific event*/\n-\t\thandler_cb = ena_com_get_specific_aenq_cb(dev,\n+\t\thandler_cb = ena_com_get_specific_aenq_cb(ena_dev,\n \t\t\t\t\t\t\t aenq_common->group);\n \t\thandler_cb(data, aenq_e); /* call the actual event handler*/\n \n@@ -2121,8 +2121,8 @@ void ena_com_aenq_intr_handler(struct ena_com_dev *dev, void *data)\n \n \t/* write the aenq doorbell after all AENQ descriptors were read */\n \tmb();\n-\tENA_REG_WRITE32_RELAXED(dev->bus, (u32)aenq->head,\n-\t\t\t\tdev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF);\n+\tENA_REG_WRITE32_RELAXED(ena_dev->bus, (u32)aenq->head,\n+\t\t\t\tena_dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF);\n \tmmiowb();\n }\n \ndiff --git a/drivers/net/ena/base/ena_com.h b/drivers/net/ena/base/ena_com.h\nindex 64d8f247cb..e9601b1a8e 100644\n--- a/drivers/net/ena/base/ena_com.h\n+++ b/drivers/net/ena/base/ena_com.h\n@@ -522,7 +522,7 @@ void ena_com_admin_q_comp_intr_handler(struct ena_com_dev *ena_dev);\n * This method goes over the async event notification queue and calls the proper\n * aenq handler.\n */\n-void ena_com_aenq_intr_handler(struct ena_com_dev *dev, void *data);\n+void ena_com_aenq_intr_handler(struct ena_com_dev *ena_dev, void *data);\n \n /* ena_com_abort_admin_commands - Abort all the outstanding admin commands.\n * @ena_dev: ENA communication layer struct\n", "prefixes": [ "v3", "02/22" ] }