From patchwork Thu May 6 14:25:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Krawczyk X-Patchwork-Id: 93006 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5F94DA0524; Thu, 6 May 2021 16:25:51 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id CE704410FA; Thu, 6 May 2021 16:25:45 +0200 (CEST) Received: from mail-lf1-f48.google.com (mail-lf1-f48.google.com [209.85.167.48]) by mails.dpdk.org (Postfix) with ESMTP id B2E8F410F3 for ; Thu, 6 May 2021 16:25:43 +0200 (CEST) Received: by mail-lf1-f48.google.com with SMTP id x19so8080210lfa.2 for ; Thu, 06 May 2021 07:25:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2XqtNgVNFW+3cuq3W34xXDy9JZdCaLxVkH9dYbjPK7Y=; b=jNDDvAwDnzUfKct8+rsrTy2egXMKhm4ZUm2WPOwdatf97l5REdMMNUm/lEogcYQXRx G6sLaZ3ncpGJR6DAIbxOY64Hd5E/AP1UYsPweC8XTZvFPOI5CLZVkbvoZO76Flv24srI 5RFaDZHn+dYC4Ajc7HdoxHEhePeCTD1wv9xqVPGV8WHsLZnMVTxtWpeB0hLMYbKXCyhS AWWvlV9mQX8nAvIlHn20QwjmtYmygtEMLbyxhqJ0FlyawNXfYvKDzZMqMDzFw5QBM36I Y4AKge7/NCWT5moj6ZdbqVOsKQQx09myc12hGE6kYliSYOmg0G3KCYCkiU7cV9M/hvVS 8vHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2XqtNgVNFW+3cuq3W34xXDy9JZdCaLxVkH9dYbjPK7Y=; b=LHxyGRrHTXUvwairPNJH7sRSpt6A/K1e2pn4NNYQLlb0Yv8VTG6dFzrPcXxBoimvhi BDrGGwstpshnOm+2sVWtPCMo3u2MMQGBC5qOP7rCIrkQLogvq5LOVTFNR2zidrYL6CCK CmIEATJrLwxOsPxngMGYuKvbtb1y0WaeAb2T/7AUwLauwwH5r5HrRFrqjG1+EDSMrYJD 43ll3G1nBzWVrdYnqJ12Xyh31RzeZ7xgc4goAS9wm6ukFoaSCdi+Ua/6gJ42cvTDX5n/ PzeZZf+EdXXN1sGIqZaInVfnl5XEVnoomhOkrx/y+GczLGjFeyIAMf7yT3KPdAZgRhpC hwXA== X-Gm-Message-State: AOAM5334WUgCLDsi8/qAplA3dmpYpjca5WMJdXNWdAGi67kCuMdg6vW2 6GsNyXxQ1JgZbi2bv/w0wVGLAvgSAMMMT8HC X-Google-Smtp-Source: ABdhPJwCgY3I+3hBfLhvyiKi5BMggoWcRglX6dlDCYk/YcateOGmcySrI80s1XTKS87Iubgx9na4Dw== X-Received: by 2002:a05:6512:10c9:: with SMTP id k9mr3028451lfg.273.1620311143005; Thu, 06 May 2021 07:25:43 -0700 (PDT) Received: from DESKTOP-U5LNN3J.localdomain (89-79-189-199.dynamic.chello.pl. [89.79.189.199]) by smtp.gmail.com with ESMTPSA id b40sm892908ljr.101.2021.05.06.07.25.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 May 2021 07:25:42 -0700 (PDT) From: Michal Krawczyk To: dev@dpdk.org Cc: ndagan@amazon.com, gtzalik@amazon.com, igorch@amazon.com, upstream@semihalf.com, stable@dpdk.org, Michal Krawczyk , Artur Rojek Date: Thu, 6 May 2021 16:25:05 +0200 Message-Id: <20210506142526.28245-2-mk@semihalf.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210506142526.28245-1-mk@semihalf.com> References: <20210505073348.6394-1-mk@semihalf.com> <20210506142526.28245-1-mk@semihalf.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v3 01/22] net/ena: switch memcpy to dpdk-optimized version X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Igor Chauskin memcpy is now mapped to rte_memcpy macro on x86 architectures. Fixes: 9ba7981ec992 ("ena: add communication layer for DPDK") Cc: stable@dpdk.org Signed-off-by: Igor Chauskin Reviewed-by: Michal Krawczyk Reviewed-by: Artur Rojek --- v2: * Fix nested declaration of the rte_memcpy on arm64 architecture. drivers/net/ena/base/ena_plat_dpdk.h | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/net/ena/base/ena_plat_dpdk.h b/drivers/net/ena/base/ena_plat_dpdk.h index a1d749f83f..ae68f860a5 100644 --- a/drivers/net/ena/base/ena_plat_dpdk.h +++ b/drivers/net/ena/base/ena_plat_dpdk.h @@ -25,6 +25,7 @@ #include #include +#include typedef uint64_t u64; typedef uint32_t u32; @@ -62,7 +63,11 @@ typedef uint64_t dma_addr_t; #define ENA_UDELAY(x) rte_delay_us_block(x) #define ENA_TOUCH(x) ((void)(x)) -#define memcpy_toio memcpy +/* Avoid nested declaration on arm64, as it may define rte_memcpy as memcpy. */ +#if defined(RTE_ARCH_X86) +#undef memcpy +#define memcpy rte_memcpy +#endif #define wmb rte_wmb #define rmb rte_rmb #define mb rte_mb From patchwork Thu May 6 14:25:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Krawczyk X-Patchwork-Id: 93007 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 20C07A0524; Thu, 6 May 2021 16:25:58 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id F400C410FF; Thu, 6 May 2021 16:25:46 +0200 (CEST) Received: from mail-lj1-f171.google.com (mail-lj1-f171.google.com [209.85.208.171]) by mails.dpdk.org (Postfix) with ESMTP id 448E0410F9 for ; Thu, 6 May 2021 16:25:45 +0200 (CEST) Received: by mail-lj1-f171.google.com with SMTP id u20so7253818lja.13 for ; Thu, 06 May 2021 07:25:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=eD9i65pBbnphpAjWSmo42fdxLdI0C6CvXTcwXD/pSEg=; b=DqVXWksEJimuyKdxBvkUd+B2ankbROIVRpN51Kb9Wwwl5nXGGQQ1Gf8wxu5wSJCpVl STJTKm8ha8u8izXsVcokx5FUNjLg3HPYqQxAuAq3uYZc370+3LQraGfVM2wDt5+jLU05 FaVQPMUzGM97hVFCXnRCTJsU2zSF+ZFfIJ+g+UQswC5PwfLmkfgLmP1XZVfSVtS3WrbW IkL5cey7oKpsz7lTxpWrpklxF8xD1qqp6vf9XoxoN7Xk5dO2rpzsy+V1vPvr8O9OJPFM jsHGpBmklz45lQlzhErszklnM8byqhQaomdQehhxIOt9E2vblT9/aH8O5PKx8vNqBf0n nTjA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=eD9i65pBbnphpAjWSmo42fdxLdI0C6CvXTcwXD/pSEg=; b=qfWUxm7nJlDmQsTUc4Hg4kKB/mrj26W9x3t1a510ujhHLbiIAWI4uOYzWATDAIDG9F sf0UxiHwGmutdeuI65MjR+qMEIKRttMHa/MVcPfJrnTJe2dYB3scOqsTBahqqe5jS6rs 0tQYI73ivzdcaZLoSk4veQ8ZroWAeX9VmRxXUOWAj/FSPO3Leoxkgp/j/A8xhD9XbYcn c4lANsQQKDPmG5x+EYN6alXZVjhUlW6zwTqiWjMcBcEbHxQz4p8cooQxGjwrk2OIXBPN 8Gu5IKCz3uLLLQqQjjZl5Slij94LhY7qYn7T23KIfNJrcnx5NXtJNYb/8A903r3yic9C mAHQ== X-Gm-Message-State: AOAM533Mi00LjKTdQE8sjegvTmjrOeV8xZba98eeaulmc9UiNuKm/IZJ BVyjMtoS37NSsUR2iak67lgr63HvpOmzCtfE X-Google-Smtp-Source: ABdhPJx11zcPLVE9FN1iEn7UU1jf2T/QdCNaGB3lBr7Wx39ZLKwT7QN0YWDMCcqv9TyFw7CLM90XYg== X-Received: by 2002:a2e:9152:: with SMTP id q18mr3687316ljg.188.1620311144505; Thu, 06 May 2021 07:25:44 -0700 (PDT) Received: from DESKTOP-U5LNN3J.localdomain (89-79-189-199.dynamic.chello.pl. [89.79.189.199]) by smtp.gmail.com with ESMTPSA id b40sm892908ljr.101.2021.05.06.07.25.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 May 2021 07:25:43 -0700 (PDT) From: Michal Krawczyk To: dev@dpdk.org Cc: ndagan@amazon.com, gtzalik@amazon.com, igorch@amazon.com, upstream@semihalf.com, Michal Krawczyk Date: Thu, 6 May 2021 16:25:06 +0200 Message-Id: <20210506142526.28245-3-mk@semihalf.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210506142526.28245-1-mk@semihalf.com> References: <20210505073348.6394-1-mk@semihalf.com> <20210506142526.28245-1-mk@semihalf.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v3 02/22] net/ena/base: unify arg names for the functions X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Instead of using 'queue' for struct ena_com_admin_queue and 'dev' for struct ena_com_dev variables, use more descriptive 'admin_queue' and 'ena_dev'. This also unifies the names of variables of the type struct ena_com_dev in the driver. Signed-off-by: Michal Krawczyk Reviewed-by: Igor Chauskin Reviewed-by: Guy Tzalik --- v3: * Fix typo in the commit log of the version upgrade patch. drivers/net/ena/base/ena_com.c | 74 +++++++++++++++++----------------- drivers/net/ena/base/ena_com.h | 2 +- 2 files changed, 38 insertions(+), 38 deletions(-) diff --git a/drivers/net/ena/base/ena_com.c b/drivers/net/ena/base/ena_com.c index aae68721fb..f7258254a5 100644 --- a/drivers/net/ena/base/ena_com.c +++ b/drivers/net/ena/base/ena_com.c @@ -80,12 +80,12 @@ static int ena_com_mem_addr_set(struct ena_com_dev *ena_dev, return 0; } -static int ena_com_admin_init_sq(struct ena_com_admin_queue *queue) +static int ena_com_admin_init_sq(struct ena_com_admin_queue *admin_queue) { - struct ena_com_admin_sq *sq = &queue->sq; - u16 size = ADMIN_SQ_SIZE(queue->q_depth); + struct ena_com_admin_sq *sq = &admin_queue->sq; + u16 size = ADMIN_SQ_SIZE(admin_queue->q_depth); - ENA_MEM_ALLOC_COHERENT(queue->q_dmadev, size, sq->entries, sq->dma_addr, + ENA_MEM_ALLOC_COHERENT(admin_queue->q_dmadev, size, sq->entries, sq->dma_addr, sq->mem_handle); if (!sq->entries) { @@ -102,12 +102,12 @@ static int ena_com_admin_init_sq(struct ena_com_admin_queue *queue) return 0; } -static int ena_com_admin_init_cq(struct ena_com_admin_queue *queue) +static int ena_com_admin_init_cq(struct ena_com_admin_queue *admin_queue) { - struct ena_com_admin_cq *cq = &queue->cq; - u16 size = ADMIN_CQ_SIZE(queue->q_depth); + struct ena_com_admin_cq *cq = &admin_queue->cq; + u16 size = ADMIN_CQ_SIZE(admin_queue->q_depth); - ENA_MEM_ALLOC_COHERENT(queue->q_dmadev, size, cq->entries, cq->dma_addr, + ENA_MEM_ALLOC_COHERENT(admin_queue->q_dmadev, size, cq->entries, cq->dma_addr, cq->mem_handle); if (!cq->entries) { @@ -121,16 +121,16 @@ static int ena_com_admin_init_cq(struct ena_com_admin_queue *queue) return 0; } -static int ena_com_admin_init_aenq(struct ena_com_dev *dev, +static int ena_com_admin_init_aenq(struct ena_com_dev *ena_dev, struct ena_aenq_handlers *aenq_handlers) { - struct ena_com_aenq *aenq = &dev->aenq; + struct ena_com_aenq *aenq = &ena_dev->aenq; u32 addr_low, addr_high, aenq_caps; u16 size; - dev->aenq.q_depth = ENA_ASYNC_QUEUE_DEPTH; + ena_dev->aenq.q_depth = ENA_ASYNC_QUEUE_DEPTH; size = ADMIN_AENQ_SIZE(ENA_ASYNC_QUEUE_DEPTH); - ENA_MEM_ALLOC_COHERENT(dev->dmadev, size, + ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev, size, aenq->entries, aenq->dma_addr, aenq->mem_handle); @@ -146,15 +146,15 @@ static int ena_com_admin_init_aenq(struct ena_com_dev *dev, addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(aenq->dma_addr); addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(aenq->dma_addr); - ENA_REG_WRITE32(dev->bus, addr_low, dev->reg_bar + ENA_REGS_AENQ_BASE_LO_OFF); - ENA_REG_WRITE32(dev->bus, addr_high, dev->reg_bar + ENA_REGS_AENQ_BASE_HI_OFF); + ENA_REG_WRITE32(ena_dev->bus, addr_low, ena_dev->reg_bar + ENA_REGS_AENQ_BASE_LO_OFF); + ENA_REG_WRITE32(ena_dev->bus, addr_high, ena_dev->reg_bar + ENA_REGS_AENQ_BASE_HI_OFF); aenq_caps = 0; - aenq_caps |= dev->aenq.q_depth & ENA_REGS_AENQ_CAPS_AENQ_DEPTH_MASK; + aenq_caps |= ena_dev->aenq.q_depth & ENA_REGS_AENQ_CAPS_AENQ_DEPTH_MASK; aenq_caps |= (sizeof(struct ena_admin_aenq_entry) << ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_SHIFT) & ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_MASK; - ENA_REG_WRITE32(dev->bus, aenq_caps, dev->reg_bar + ENA_REGS_AENQ_CAPS_OFF); + ENA_REG_WRITE32(ena_dev->bus, aenq_caps, ena_dev->reg_bar + ENA_REGS_AENQ_CAPS_OFF); if (unlikely(!aenq_handlers)) { ena_trc_err("aenq handlers pointer is NULL\n"); @@ -173,31 +173,31 @@ static void comp_ctxt_release(struct ena_com_admin_queue *queue, ATOMIC32_DEC(&queue->outstanding_cmds); } -static struct ena_comp_ctx *get_comp_ctxt(struct ena_com_admin_queue *queue, +static struct ena_comp_ctx *get_comp_ctxt(struct ena_com_admin_queue *admin_queue, u16 command_id, bool capture) { - if (unlikely(command_id >= queue->q_depth)) { + if (unlikely(command_id >= admin_queue->q_depth)) { ena_trc_err("command id is larger than the queue size. cmd_id: %u queue size %d\n", - command_id, queue->q_depth); + command_id, admin_queue->q_depth); return NULL; } - if (unlikely(!queue->comp_ctx)) { + if (unlikely(!admin_queue->comp_ctx)) { ena_trc_err("Completion context is NULL\n"); return NULL; } - if (unlikely(queue->comp_ctx[command_id].occupied && capture)) { + if (unlikely(admin_queue->comp_ctx[command_id].occupied && capture)) { ena_trc_err("Completion context is occupied\n"); return NULL; } if (capture) { - ATOMIC32_INC(&queue->outstanding_cmds); - queue->comp_ctx[command_id].occupied = true; + ATOMIC32_INC(&admin_queue->outstanding_cmds); + admin_queue->comp_ctx[command_id].occupied = true; } - return &queue->comp_ctx[command_id]; + return &admin_queue->comp_ctx[command_id]; } static struct ena_comp_ctx *__ena_com_submit_admin_cmd(struct ena_com_admin_queue *admin_queue, @@ -260,20 +260,20 @@ static struct ena_comp_ctx *__ena_com_submit_admin_cmd(struct ena_com_admin_queu return comp_ctx; } -static int ena_com_init_comp_ctxt(struct ena_com_admin_queue *queue) +static int ena_com_init_comp_ctxt(struct ena_com_admin_queue *admin_queue) { - size_t size = queue->q_depth * sizeof(struct ena_comp_ctx); + size_t size = admin_queue->q_depth * sizeof(struct ena_comp_ctx); struct ena_comp_ctx *comp_ctx; u16 i; - queue->comp_ctx = ENA_MEM_ALLOC(queue->q_dmadev, size); - if (unlikely(!queue->comp_ctx)) { + admin_queue->comp_ctx = ENA_MEM_ALLOC(admin_queue->q_dmadev, size); + if (unlikely(!admin_queue->comp_ctx)) { ena_trc_err("memory allocation failed\n"); return ENA_COM_NO_MEM; } - for (i = 0; i < queue->q_depth; i++) { - comp_ctx = get_comp_ctxt(queue, i, false); + for (i = 0; i < admin_queue->q_depth; i++) { + comp_ctx = get_comp_ctxt(admin_queue, i, false); if (comp_ctx) ENA_WAIT_EVENT_INIT(comp_ctx->wait_event); } @@ -2049,10 +2049,10 @@ void ena_com_admin_q_comp_intr_handler(struct ena_com_dev *ena_dev) /* ena_handle_specific_aenq_event: * return the handler that is relevant to the specific event group */ -static ena_aenq_handler ena_com_get_specific_aenq_cb(struct ena_com_dev *dev, +static ena_aenq_handler ena_com_get_specific_aenq_cb(struct ena_com_dev *ena_dev, u16 group) { - struct ena_aenq_handlers *aenq_handlers = dev->aenq.aenq_handlers; + struct ena_aenq_handlers *aenq_handlers = ena_dev->aenq.aenq_handlers; if ((group < ENA_MAX_HANDLERS) && aenq_handlers->handlers[group]) return aenq_handlers->handlers[group]; @@ -2064,11 +2064,11 @@ static ena_aenq_handler ena_com_get_specific_aenq_cb(struct ena_com_dev *dev, * handles the aenq incoming events. * pop events from the queue and apply the specific handler */ -void ena_com_aenq_intr_handler(struct ena_com_dev *dev, void *data) +void ena_com_aenq_intr_handler(struct ena_com_dev *ena_dev, void *data) { struct ena_admin_aenq_entry *aenq_e; struct ena_admin_aenq_common_desc *aenq_common; - struct ena_com_aenq *aenq = &dev->aenq; + struct ena_com_aenq *aenq = &ena_dev->aenq; u64 timestamp; ena_aenq_handler handler_cb; u16 masked_head, processed = 0; @@ -2096,7 +2096,7 @@ void ena_com_aenq_intr_handler(struct ena_com_dev *dev, void *data) timestamp); /* Handle specific event*/ - handler_cb = ena_com_get_specific_aenq_cb(dev, + handler_cb = ena_com_get_specific_aenq_cb(ena_dev, aenq_common->group); handler_cb(data, aenq_e); /* call the actual event handler*/ @@ -2121,8 +2121,8 @@ void ena_com_aenq_intr_handler(struct ena_com_dev *dev, void *data) /* write the aenq doorbell after all AENQ descriptors were read */ mb(); - ENA_REG_WRITE32_RELAXED(dev->bus, (u32)aenq->head, - dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF); + ENA_REG_WRITE32_RELAXED(ena_dev->bus, (u32)aenq->head, + ena_dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF); mmiowb(); } diff --git a/drivers/net/ena/base/ena_com.h b/drivers/net/ena/base/ena_com.h index 64d8f247cb..e9601b1a8e 100644 --- a/drivers/net/ena/base/ena_com.h +++ b/drivers/net/ena/base/ena_com.h @@ -522,7 +522,7 @@ void ena_com_admin_q_comp_intr_handler(struct ena_com_dev *ena_dev); * This method goes over the async event notification queue and calls the proper * aenq handler. */ -void ena_com_aenq_intr_handler(struct ena_com_dev *dev, void *data); +void ena_com_aenq_intr_handler(struct ena_com_dev *ena_dev, void *data); /* ena_com_abort_admin_commands - Abort all the outstanding admin commands. * @ena_dev: ENA communication layer struct From patchwork Thu May 6 14:25:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Krawczyk X-Patchwork-Id: 93008 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 62DE9A0524; Thu, 6 May 2021 16:26:06 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 31E234110A; Thu, 6 May 2021 16:25:48 +0200 (CEST) Received: from mail-lf1-f51.google.com (mail-lf1-f51.google.com [209.85.167.51]) by mails.dpdk.org (Postfix) with ESMTP id 7EBE541104 for ; Thu, 6 May 2021 16:25:47 +0200 (CEST) Received: by mail-lf1-f51.google.com with SMTP id c11so8041204lfi.9 for ; Thu, 06 May 2021 07:25:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JM9MHbJz+SWsxy0qdAyCJooIl3F8tsu6pJZ93r2JsQc=; b=02CXfoPQmJr1DTAenSsrX41cThb/PIzbA1GlZNfdu96iL8+EJoAKL/pwYSr3J2uXhM 0VZkkj962iinGIqBHpwzxr0uJdxvUmfBoFa/HW/ttP+zS8z1o3dfUn5iPBLYtGy4Losn 1A5pPQzTk8143qsNKTjr1pwDLEkvgo99bJf5YEdnZuwqorsYxAZS1cR3U+YQFeBNwL7e Z6gA7bR+r7kxvb0PriADip23hWtdK9V4B7qfrdJw2j5k+OB6sp2uv+a+LbUGEZmJmZMg /EK5N+0IxVwTW9MuCPSYAjVFgFdl1Zciwq3j6Itd3dXmmLwHt9qGf09bN5P6FdggXVLS Invg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JM9MHbJz+SWsxy0qdAyCJooIl3F8tsu6pJZ93r2JsQc=; b=JbFokaJDcw/h1NAvF/+KZHoX2tpH75iyzJdGocoHXeLrs7uHYbRaDq7TVkfc0osZSd SUrhdN/jGsR/bIcZOZ1GlieDMNg0SDcPeBTrxamBMwpWiQQxPAXSEVTTjSkFDECdRAXu qFSyMAntZRzvAXmBxD/F0VjVY/yt8zt1aM7z4vNQVPZuA1/BScjdESrTQRw8IgCU1KRi mQZ7lJwCgdep5wyBfh4DH+JIWDQ4/hw1+QZ5wehoQdCkhC1/ZBV8cimF04Ux31xcYxa0 QkvK5WyG5qihzO3JZZ2GmoMnyVuz1ocRlUMmuELU5JN9msEFo2SPDCZIrcCyWdhEiLqO ybag== X-Gm-Message-State: AOAM5308C9jWJldf9XNeGgQUu27Gc0YdZhR9Z/U2x1pprMIWDwj5Bxkt 8gjkY0j/LpyycaHhFT/gdXTu8KaIcIlJt8dY X-Google-Smtp-Source: ABdhPJy5EG8xYfC27bT4oeH23Rlc9F6wIrAlbs6BmKKDATl3W+Hs9+x7nJsHu6DfaXrABC8ceZeT8w== X-Received: by 2002:ac2:5548:: with SMTP id l8mr285514lfk.225.1620311146067; Thu, 06 May 2021 07:25:46 -0700 (PDT) Received: from DESKTOP-U5LNN3J.localdomain (89-79-189-199.dynamic.chello.pl. [89.79.189.199]) by smtp.gmail.com with ESMTPSA id b40sm892908ljr.101.2021.05.06.07.25.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 May 2021 07:25:45 -0700 (PDT) From: Michal Krawczyk To: dev@dpdk.org Cc: ndagan@amazon.com, gtzalik@amazon.com, igorch@amazon.com, upstream@semihalf.com, Michal Krawczyk Date: Thu, 6 May 2021 16:25:07 +0200 Message-Id: <20210506142526.28245-4-mk@semihalf.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210506142526.28245-1-mk@semihalf.com> References: <20210505073348.6394-1-mk@semihalf.com> <20210506142526.28245-1-mk@semihalf.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v3 03/22] net/ena/base: add dev arg to the logging macros X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Some platforms may make use of the device argument to make the logs more verbose and specific for the appropriate device. As it's not used by the ENA DPDK PMD for the logging, the type is just defined, but never used. It may be reconsidered to change this in the future by adding port ID to the message logs, but as for now the logging behavior won't change. Signed-off-by: Michal Krawczyk Reviewed-by: Igor Chauskin Reviewed-by: Guy Tzalik --- drivers/net/ena/base/ena_com.c | 238 ++++++++++++++------------- drivers/net/ena/base/ena_com.h | 21 +++ drivers/net/ena/base/ena_eth_com.c | 78 ++++++--- drivers/net/ena/base/ena_eth_com.h | 17 +- drivers/net/ena/base/ena_plat_dpdk.h | 44 ++--- 5 files changed, 236 insertions(+), 162 deletions(-) diff --git a/drivers/net/ena/base/ena_com.c b/drivers/net/ena/base/ena_com.c index f7258254a5..9931819bbb 100644 --- a/drivers/net/ena/base/ena_com.c +++ b/drivers/net/ena/base/ena_com.c @@ -70,7 +70,7 @@ static int ena_com_mem_addr_set(struct ena_com_dev *ena_dev, dma_addr_t addr) { if ((addr & GENMASK_ULL(ena_dev->dma_addr_bits - 1, 0)) != addr) { - ena_trc_err("dma address has more bits that the device supports\n"); + ena_trc_err(ena_dev, "DMA address has more bits than the device supports\n"); return ENA_COM_INVAL; } @@ -82,6 +82,7 @@ static int ena_com_mem_addr_set(struct ena_com_dev *ena_dev, static int ena_com_admin_init_sq(struct ena_com_admin_queue *admin_queue) { + struct ena_com_dev *ena_dev = admin_queue->ena_dev; struct ena_com_admin_sq *sq = &admin_queue->sq; u16 size = ADMIN_SQ_SIZE(admin_queue->q_depth); @@ -89,7 +90,7 @@ static int ena_com_admin_init_sq(struct ena_com_admin_queue *admin_queue) sq->mem_handle); if (!sq->entries) { - ena_trc_err("memory allocation failed\n"); + ena_trc_err(ena_dev, "Memory allocation failed\n"); return ENA_COM_NO_MEM; } @@ -104,6 +105,7 @@ static int ena_com_admin_init_sq(struct ena_com_admin_queue *admin_queue) static int ena_com_admin_init_cq(struct ena_com_admin_queue *admin_queue) { + struct ena_com_dev *ena_dev = admin_queue->ena_dev; struct ena_com_admin_cq *cq = &admin_queue->cq; u16 size = ADMIN_CQ_SIZE(admin_queue->q_depth); @@ -111,7 +113,7 @@ static int ena_com_admin_init_cq(struct ena_com_admin_queue *admin_queue) cq->mem_handle); if (!cq->entries) { - ena_trc_err("memory allocation failed\n"); + ena_trc_err(ena_dev, "Memory allocation failed\n"); return ENA_COM_NO_MEM; } @@ -136,7 +138,7 @@ static int ena_com_admin_init_aenq(struct ena_com_dev *ena_dev, aenq->mem_handle); if (!aenq->entries) { - ena_trc_err("memory allocation failed\n"); + ena_trc_err(ena_dev, "Memory allocation failed\n"); return ENA_COM_NO_MEM; } @@ -157,7 +159,7 @@ static int ena_com_admin_init_aenq(struct ena_com_dev *ena_dev, ENA_REG_WRITE32(ena_dev->bus, aenq_caps, ena_dev->reg_bar + ENA_REGS_AENQ_CAPS_OFF); if (unlikely(!aenq_handlers)) { - ena_trc_err("aenq handlers pointer is NULL\n"); + ena_trc_err(ena_dev, "AENQ handlers pointer is NULL\n"); return ENA_COM_INVAL; } @@ -177,18 +179,21 @@ static struct ena_comp_ctx *get_comp_ctxt(struct ena_com_admin_queue *admin_queu u16 command_id, bool capture) { if (unlikely(command_id >= admin_queue->q_depth)) { - ena_trc_err("command id is larger than the queue size. cmd_id: %u queue size %d\n", + ena_trc_err(admin_queue->ena_dev, + "Command id is larger than the queue size. cmd_id: %u queue size %d\n", command_id, admin_queue->q_depth); return NULL; } if (unlikely(!admin_queue->comp_ctx)) { - ena_trc_err("Completion context is NULL\n"); + ena_trc_err(admin_queue->ena_dev, + "Completion context is NULL\n"); return NULL; } if (unlikely(admin_queue->comp_ctx[command_id].occupied && capture)) { - ena_trc_err("Completion context is occupied\n"); + ena_trc_err(admin_queue->ena_dev, + "Completion context is occupied\n"); return NULL; } @@ -218,7 +223,7 @@ static struct ena_comp_ctx *__ena_com_submit_admin_cmd(struct ena_com_admin_queu /* In case of queue FULL */ cnt = (u16)ATOMIC32_READ(&admin_queue->outstanding_cmds); if (cnt >= admin_queue->q_depth) { - ena_trc_dbg("admin queue is full.\n"); + ena_trc_dbg(admin_queue->ena_dev, "Admin queue is full.\n"); admin_queue->stats.out_of_space++; return ERR_PTR(ENA_COM_NO_SPACE); } @@ -262,13 +267,14 @@ static struct ena_comp_ctx *__ena_com_submit_admin_cmd(struct ena_com_admin_queu static int ena_com_init_comp_ctxt(struct ena_com_admin_queue *admin_queue) { + struct ena_com_dev *ena_dev = admin_queue->ena_dev; size_t size = admin_queue->q_depth * sizeof(struct ena_comp_ctx); struct ena_comp_ctx *comp_ctx; u16 i; admin_queue->comp_ctx = ENA_MEM_ALLOC(admin_queue->q_dmadev, size); if (unlikely(!admin_queue->comp_ctx)) { - ena_trc_err("memory allocation failed\n"); + ena_trc_err(ena_dev, "Memory allocation failed\n"); return ENA_COM_NO_MEM; } @@ -341,7 +347,7 @@ static int ena_com_init_io_sq(struct ena_com_dev *ena_dev, } if (!io_sq->desc_addr.virt_addr) { - ena_trc_err("memory allocation failed\n"); + ena_trc_err(ena_dev, "Memory allocation failed\n"); return ENA_COM_NO_MEM; } } @@ -366,7 +372,7 @@ static int ena_com_init_io_sq(struct ena_com_dev *ena_dev, io_sq->bounce_buf_ctrl.base_buffer = ENA_MEM_ALLOC(ena_dev->dmadev, size); if (!io_sq->bounce_buf_ctrl.base_buffer) { - ena_trc_err("bounce buffer memory allocation failed\n"); + ena_trc_err(ena_dev, "Bounce buffer memory allocation failed\n"); return ENA_COM_NO_MEM; } @@ -431,7 +437,7 @@ static int ena_com_init_io_cq(struct ena_com_dev *ena_dev, } if (!io_cq->cdesc_addr.virt_addr) { - ena_trc_err("memory allocation failed\n"); + ena_trc_err(ena_dev, "Memory allocation failed\n"); return ENA_COM_NO_MEM; } @@ -452,7 +458,8 @@ static void ena_com_handle_single_admin_completion(struct ena_com_admin_queue *a comp_ctx = get_comp_ctxt(admin_queue, cmd_id, false); if (unlikely(!comp_ctx)) { - ena_trc_err("comp_ctx is NULL. Changing the admin queue running state\n"); + ena_trc_err(admin_queue->ena_dev, + "comp_ctx is NULL. Changing the admin queue running state\n"); admin_queue->running_state = false; return; } @@ -504,10 +511,12 @@ static void ena_com_handle_admin_completion(struct ena_com_admin_queue *admin_qu admin_queue->stats.completed_cmd += comp_num; } -static int ena_com_comp_status_to_errno(u8 comp_status) +static int ena_com_comp_status_to_errno(struct ena_com_admin_queue *admin_queue, + u8 comp_status) { if (unlikely(comp_status != 0)) - ena_trc_err("admin command failed[%u]\n", comp_status); + ena_trc_err(admin_queue->ena_dev, + "Admin command failed[%u]\n", comp_status); switch (comp_status) { case ENA_ADMIN_SUCCESS: @@ -554,7 +563,8 @@ static int ena_com_wait_and_process_admin_cq_polling(struct ena_comp_ctx *comp_c break; if (ENA_TIME_EXPIRE(timeout)) { - ena_trc_err("Wait for completion (polling) timeout\n"); + ena_trc_err(admin_queue->ena_dev, + "Wait for completion (polling) timeout\n"); /* ENA didn't have any completion */ ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags); admin_queue->stats.no_completion++; @@ -570,7 +580,7 @@ static int ena_com_wait_and_process_admin_cq_polling(struct ena_comp_ctx *comp_c } if (unlikely(comp_ctx->status == ENA_CMD_ABORTED)) { - ena_trc_err("Command was aborted\n"); + ena_trc_err(admin_queue->ena_dev, "Command was aborted\n"); ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags); admin_queue->stats.aborted_cmd++; ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags); @@ -579,9 +589,10 @@ static int ena_com_wait_and_process_admin_cq_polling(struct ena_comp_ctx *comp_c } ENA_WARN(comp_ctx->status != ENA_CMD_COMPLETED, - "Invalid comp status %d\n", comp_ctx->status); + admin_queue->ena_dev, "Invalid comp status %d\n", + comp_ctx->status); - ret = ena_com_comp_status_to_errno(comp_ctx->comp_status); + ret = ena_com_comp_status_to_errno(admin_queue, comp_ctx->comp_status); err: comp_ctxt_release(admin_queue, comp_ctx); return ret; @@ -623,7 +634,7 @@ static int ena_com_set_llq(struct ena_com_dev *ena_dev) sizeof(resp)); if (unlikely(ret)) - ena_trc_err("Failed to set LLQ configurations: %d\n", ret); + ena_trc_err(ena_dev, "Failed to set LLQ configurations: %d\n", ret); return ret; } @@ -645,7 +656,7 @@ static int ena_com_config_llq_info(struct ena_com_dev *ena_dev, llq_info->header_location_ctrl = llq_default_cfg->llq_header_location; } else { - ena_trc_err("Invalid header location control, supported: 0x%x\n", + ena_trc_err(ena_dev, "Invalid header location control, supported: 0x%x\n", supported_feat); return -EINVAL; } @@ -660,12 +671,12 @@ static int ena_com_config_llq_info(struct ena_com_dev *ena_dev, } else if (supported_feat & ENA_ADMIN_SINGLE_DESC_PER_ENTRY) { llq_info->desc_stride_ctrl = ENA_ADMIN_SINGLE_DESC_PER_ENTRY; } else { - ena_trc_err("Invalid desc_stride_ctrl, supported: 0x%x\n", + ena_trc_err(ena_dev, "Invalid desc_stride_ctrl, supported: 0x%x\n", supported_feat); return -EINVAL; } - ena_trc_err("Default llq stride ctrl is not supported, performing fallback, default: 0x%x, supported: 0x%x, used: 0x%x\n", + ena_trc_err(ena_dev, "Default llq stride ctrl is not supported, performing fallback, default: 0x%x, supported: 0x%x, used: 0x%x\n", llq_default_cfg->llq_stride_ctrl, supported_feat, llq_info->desc_stride_ctrl); @@ -689,11 +700,12 @@ static int ena_com_config_llq_info(struct ena_com_dev *ena_dev, llq_info->desc_list_entry_size_ctrl = ENA_ADMIN_LIST_ENTRY_SIZE_256B; llq_info->desc_list_entry_size = 256; } else { - ena_trc_err("Invalid entry_size_ctrl, supported: 0x%x\n", supported_feat); + ena_trc_err(ena_dev, "Invalid entry_size_ctrl, supported: 0x%x\n", + supported_feat); return -EINVAL; } - ena_trc_err("Default llq ring entry size is not supported, performing fallback, default: 0x%x, supported: 0x%x, used: 0x%x\n", + ena_trc_err(ena_dev, "Default llq ring entry size is not supported, performing fallback, default: 0x%x, supported: 0x%x, used: 0x%x\n", llq_default_cfg->llq_ring_entry_size, supported_feat, llq_info->desc_list_entry_size); @@ -702,7 +714,7 @@ static int ena_com_config_llq_info(struct ena_com_dev *ena_dev, /* The desc list entry size should be whole multiply of 8 * This requirement comes from __iowrite64_copy() */ - ena_trc_err("illegal entry size %d\n", + ena_trc_err(ena_dev, "Illegal entry size %d\n", llq_info->desc_list_entry_size); return -EINVAL; } @@ -726,12 +738,12 @@ static int ena_com_config_llq_info(struct ena_com_dev *ena_dev, } else if (supported_feat & ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_8) { llq_info->descs_num_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_8; } else { - ena_trc_err("Invalid descs_num_before_header, supported: 0x%x\n", + ena_trc_err(ena_dev, "Invalid descs_num_before_header, supported: 0x%x\n", supported_feat); return -EINVAL; } - ena_trc_err("Default llq num descs before header is not supported, performing fallback, default: 0x%x, supported: 0x%x, used: 0x%x\n", + ena_trc_err(ena_dev, "Default llq num descs before header is not supported, performing fallback, default: 0x%x, supported: 0x%x, used: 0x%x\n", llq_default_cfg->llq_num_decs_before_header, supported_feat, llq_info->descs_num_before_header); @@ -750,7 +762,7 @@ static int ena_com_config_llq_info(struct ena_com_dev *ena_dev, rc = ena_com_set_llq(ena_dev); if (rc) - ena_trc_err("Cannot set LLQ configuration: %d\n", rc); + ena_trc_err(ena_dev, "Cannot set LLQ configuration: %d\n", rc); return rc; } @@ -776,13 +788,15 @@ static int ena_com_wait_and_process_admin_cq_interrupts(struct ena_comp_ctx *com ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags); if (comp_ctx->status == ENA_CMD_COMPLETED) { - ena_trc_err("The ena device sent a completion but the driver didn't receive a MSI-X interrupt (cmd %d), autopolling mode is %s\n", + ena_trc_err(admin_queue->ena_dev, + "The ena device sent a completion but the driver didn't receive a MSI-X interrupt (cmd %d), autopolling mode is %s\n", comp_ctx->cmd_opcode, admin_queue->auto_polling ? "ON" : "OFF"); /* Check if fallback to polling is enabled */ if (admin_queue->auto_polling) admin_queue->polling = true; } else { - ena_trc_err("The ena device didn't send a completion for the admin cmd %d status %d\n", + ena_trc_err(admin_queue->ena_dev, + "The ena device didn't send a completion for the admin cmd %d status %d\n", comp_ctx->cmd_opcode, comp_ctx->status); } /* Check if shifted to polling mode. @@ -796,7 +810,7 @@ static int ena_com_wait_and_process_admin_cq_interrupts(struct ena_comp_ctx *com } } - ret = ena_com_comp_status_to_errno(comp_ctx->comp_status); + ret = ena_com_comp_status_to_errno(admin_queue, comp_ctx->comp_status); err: comp_ctxt_release(admin_queue, comp_ctx); return ret; @@ -844,7 +858,7 @@ static u32 ena_com_reg_bar_read32(struct ena_com_dev *ena_dev, u16 offset) } if (unlikely(i == timeout)) { - ena_trc_err("reading reg failed for timeout. expected: req id[%hu] offset[%hu] actual: req id[%hu] offset[%hu]\n", + ena_trc_err(ena_dev, "Reading reg failed for timeout. expected: req id[%hu] offset[%hu] actual: req id[%hu] offset[%hu]\n", mmio_read->seq_num, offset, read_resp->req_id, @@ -854,7 +868,7 @@ static u32 ena_com_reg_bar_read32(struct ena_com_dev *ena_dev, u16 offset) } if (read_resp->reg_off != offset) { - ena_trc_err("Read failure: wrong offset provided\n"); + ena_trc_err(ena_dev, "Read failure: wrong offset provided\n"); ret = ENA_MMIO_READ_TIMEOUT; } else { ret = read_resp->reg_val; @@ -913,7 +927,7 @@ static int ena_com_destroy_io_sq(struct ena_com_dev *ena_dev, sizeof(destroy_resp)); if (unlikely(ret && (ret != ENA_COM_NO_DEVICE))) - ena_trc_err("failed to destroy io sq error: %d\n", ret); + ena_trc_err(ena_dev, "Failed to destroy io sq error: %d\n", ret); return ret; } @@ -969,7 +983,7 @@ static int wait_for_reset_state(struct ena_com_dev *ena_dev, u32 timeout, val = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF); if (unlikely(val == ENA_MMIO_READ_TIMEOUT)) { - ena_trc_err("Reg read timeout occurred\n"); + ena_trc_err(ena_dev, "Reg read timeout occurred\n"); return ENA_COM_TIMER_EXPIRED; } @@ -1009,7 +1023,7 @@ static int ena_com_get_feature_ex(struct ena_com_dev *ena_dev, int ret; if (!ena_com_check_supported_feature_id(ena_dev, feature_id)) { - ena_trc_dbg("Feature %d isn't supported\n", feature_id); + ena_trc_dbg(ena_dev, "Feature %d isn't supported\n", feature_id); return ENA_COM_UNSUPPORTED; } @@ -1028,7 +1042,7 @@ static int ena_com_get_feature_ex(struct ena_com_dev *ena_dev, &get_cmd.control_buffer.address, control_buf_dma_addr); if (unlikely(ret)) { - ena_trc_err("memory address set failed\n"); + ena_trc_err(ena_dev, "Memory address set failed\n"); return ret; } @@ -1045,7 +1059,7 @@ static int ena_com_get_feature_ex(struct ena_com_dev *ena_dev, sizeof(*get_resp)); if (unlikely(ret)) - ena_trc_err("Failed to submit get_feature command %d error: %d\n", + ena_trc_err(ena_dev, "Failed to submit get_feature command %d error: %d\n", feature_id, ret); return ret; @@ -1157,7 +1171,7 @@ static int ena_com_indirect_table_allocate(struct ena_com_dev *ena_dev, if ((get_resp.u.ind_table.min_size > log_size) || (get_resp.u.ind_table.max_size < log_size)) { - ena_trc_err("indirect table size doesn't fit. requested size: %d while min is:%d and max %d\n", + ena_trc_err(ena_dev, "Indirect table size doesn't fit. requested size: %d while min is:%d and max %d\n", 1 << log_size, 1 << get_resp.u.ind_table.min_size, 1 << get_resp.u.ind_table.max_size); @@ -1261,7 +1275,7 @@ static int ena_com_create_io_sq(struct ena_com_dev *ena_dev, &create_cmd.sq_ba, io_sq->desc_addr.phys_addr); if (unlikely(ret)) { - ena_trc_err("memory address set failed\n"); + ena_trc_err(ena_dev, "Memory address set failed\n"); return ret; } } @@ -1272,7 +1286,7 @@ static int ena_com_create_io_sq(struct ena_com_dev *ena_dev, (struct ena_admin_acq_entry *)&cmd_completion, sizeof(cmd_completion)); if (unlikely(ret)) { - ena_trc_err("Failed to create IO SQ. error: %d\n", ret); + ena_trc_err(ena_dev, "Failed to create IO SQ. error: %d\n", ret); return ret; } @@ -1290,7 +1304,7 @@ static int ena_com_create_io_sq(struct ena_com_dev *ena_dev, cmd_completion.llq_descriptors_offset); } - ena_trc_dbg("created sq[%u], depth[%u]\n", io_sq->idx, io_sq->q_depth); + ena_trc_dbg(ena_dev, "Created sq[%u], depth[%u]\n", io_sq->idx, io_sq->q_depth); return ret; } @@ -1324,7 +1338,7 @@ static void ena_com_update_intr_delay_resolution(struct ena_com_dev *ena_dev, u16 prev_intr_delay_resolution = ena_dev->intr_delay_resolution; if (unlikely(!intr_delay_resolution)) { - ena_trc_err("Illegal intr_delay_resolution provided. Going to use default 1 usec resolution\n"); + ena_trc_err(ena_dev, "Illegal intr_delay_resolution provided. Going to use default 1 usec resolution\n"); intr_delay_resolution = ENA_DEFAULT_INTR_DELAY_RESOLUTION; } @@ -1360,10 +1374,12 @@ int ena_com_execute_admin_command(struct ena_com_admin_queue *admin_queue, comp, comp_size); if (IS_ERR(comp_ctx)) { if (comp_ctx == ERR_PTR(ENA_COM_NO_DEVICE)) - ena_trc_dbg("Failed to submit command [%ld]\n", + ena_trc_dbg(admin_queue->ena_dev, + "Failed to submit command [%ld]\n", PTR_ERR(comp_ctx)); else - ena_trc_err("Failed to submit command [%ld]\n", + ena_trc_err(admin_queue->ena_dev, + "Failed to submit command [%ld]\n", PTR_ERR(comp_ctx)); return PTR_ERR(comp_ctx); @@ -1372,11 +1388,11 @@ int ena_com_execute_admin_command(struct ena_com_admin_queue *admin_queue, ret = ena_com_wait_and_process_admin_cq(comp_ctx, admin_queue); if (unlikely(ret)) { if (admin_queue->running_state) - ena_trc_err("Failed to process command. ret = %d\n", - ret); + ena_trc_err(admin_queue->ena_dev, + "Failed to process command. ret = %d\n", ret); else - ena_trc_dbg("Failed to process command. ret = %d\n", - ret); + ena_trc_dbg(admin_queue->ena_dev, + "Failed to process command. ret = %d\n", ret); } return ret; } @@ -1405,7 +1421,7 @@ int ena_com_create_io_cq(struct ena_com_dev *ena_dev, &create_cmd.cq_ba, io_cq->cdesc_addr.phys_addr); if (unlikely(ret)) { - ena_trc_err("memory address set failed\n"); + ena_trc_err(ena_dev, "Memory address set failed\n"); return ret; } @@ -1415,7 +1431,7 @@ int ena_com_create_io_cq(struct ena_com_dev *ena_dev, (struct ena_admin_acq_entry *)&cmd_completion, sizeof(cmd_completion)); if (unlikely(ret)) { - ena_trc_err("Failed to create IO CQ. error: %d\n", ret); + ena_trc_err(ena_dev, "Failed to create IO CQ. error: %d\n", ret); return ret; } @@ -1434,7 +1450,7 @@ int ena_com_create_io_cq(struct ena_com_dev *ena_dev, (u32 __iomem *)((uintptr_t)ena_dev->reg_bar + cmd_completion.numa_node_register_offset); - ena_trc_dbg("created cq[%u], depth[%u]\n", io_cq->idx, io_cq->q_depth); + ena_trc_dbg(ena_dev, "Created cq[%u], depth[%u]\n", io_cq->idx, io_cq->q_depth); return ret; } @@ -1444,7 +1460,7 @@ int ena_com_get_io_handlers(struct ena_com_dev *ena_dev, u16 qid, struct ena_com_io_cq **io_cq) { if (qid >= ENA_TOTAL_NUM_QUEUES) { - ena_trc_err("Invalid queue number %d but the max is %d\n", + ena_trc_err(ena_dev, "Invalid queue number %d but the max is %d\n", qid, ENA_TOTAL_NUM_QUEUES); return ENA_COM_INVAL; } @@ -1510,7 +1526,7 @@ int ena_com_destroy_io_cq(struct ena_com_dev *ena_dev, sizeof(destroy_resp)); if (unlikely(ret && (ret != ENA_COM_NO_DEVICE))) - ena_trc_err("Failed to destroy IO CQ. error: %d\n", ret); + ena_trc_err(ena_dev, "Failed to destroy IO CQ. error: %d\n", ret); return ret; } @@ -1534,7 +1550,7 @@ void ena_com_admin_aenq_enable(struct ena_com_dev *ena_dev) { u16 depth = ena_dev->aenq.q_depth; - ENA_WARN(ena_dev->aenq.head != depth, "Invalid AENQ state\n"); + ENA_WARN(ena_dev->aenq.head != depth, ena_dev, "Invalid AENQ state\n"); /* Init head_db to mark that all entries in the queue * are initially available @@ -1552,12 +1568,12 @@ int ena_com_set_aenq_config(struct ena_com_dev *ena_dev, u32 groups_flag) ret = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_AENQ_CONFIG, 0); if (ret) { - ena_trc_info("Can't get aenq configuration\n"); + ena_trc_info(ena_dev, "Can't get aenq configuration\n"); return ret; } if ((get_resp.u.aenq.supported_groups & groups_flag) != groups_flag) { - ena_trc_warn("Trying to set unsupported aenq events. supported flag: 0x%x asked flag: 0x%x\n", + ena_trc_warn(ena_dev, "Trying to set unsupported aenq events. supported flag: 0x%x asked flag: 0x%x\n", get_resp.u.aenq.supported_groups, groups_flag); return ENA_COM_UNSUPPORTED; @@ -1578,7 +1594,7 @@ int ena_com_set_aenq_config(struct ena_com_dev *ena_dev, u32 groups_flag) sizeof(resp)); if (unlikely(ret)) - ena_trc_err("Failed to config AENQ ret: %d\n", ret); + ena_trc_err(ena_dev, "Failed to config AENQ ret: %d\n", ret); return ret; } @@ -1589,17 +1605,17 @@ int ena_com_get_dma_width(struct ena_com_dev *ena_dev) int width; if (unlikely(caps == ENA_MMIO_READ_TIMEOUT)) { - ena_trc_err("Reg read timeout occurred\n"); + ena_trc_err(ena_dev, "Reg read timeout occurred\n"); return ENA_COM_TIMER_EXPIRED; } width = (caps & ENA_REGS_CAPS_DMA_ADDR_WIDTH_MASK) >> ENA_REGS_CAPS_DMA_ADDR_WIDTH_SHIFT; - ena_trc_dbg("ENA dma width: %d\n", width); + ena_trc_dbg(ena_dev, "ENA dma width: %d\n", width); if ((width < 32) || width > ENA_MAX_PHYS_ADDR_SIZE_BITS) { - ena_trc_err("DMA width illegal value: %d\n", width); + ena_trc_err(ena_dev, "DMA width illegal value: %d\n", width); return ENA_COM_INVAL; } @@ -1623,16 +1639,16 @@ int ena_com_validate_version(struct ena_com_dev *ena_dev) if (unlikely((ver == ENA_MMIO_READ_TIMEOUT) || (ctrl_ver == ENA_MMIO_READ_TIMEOUT))) { - ena_trc_err("Reg read timeout occurred\n"); + ena_trc_err(ena_dev, "Reg read timeout occurred\n"); return ENA_COM_TIMER_EXPIRED; } - ena_trc_info("ena device version: %d.%d\n", + ena_trc_info(ena_dev, "ENA device version: %d.%d\n", (ver & ENA_REGS_VERSION_MAJOR_VERSION_MASK) >> ENA_REGS_VERSION_MAJOR_VERSION_SHIFT, ver & ENA_REGS_VERSION_MINOR_VERSION_MASK); - ena_trc_info("ena controller version: %d.%d.%d implementation version %d\n", + ena_trc_info(ena_dev, "ENA controller version: %d.%d.%d implementation version %d\n", (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK) >> ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT, (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK) @@ -1648,7 +1664,7 @@ int ena_com_validate_version(struct ena_com_dev *ena_dev) /* Validate the ctrl version without the implementation ID */ if (ctrl_ver_masked < MIN_ENA_CTRL_VER) { - ena_trc_err("ENA ctrl version is lower than the minimal ctrl version the driver supports\n"); + ena_trc_err(ena_dev, "ENA ctrl version is lower than the minimal ctrl version the driver supports\n"); return -1; } @@ -1786,12 +1802,12 @@ int ena_com_admin_init(struct ena_com_dev *ena_dev, dev_sts = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF); if (unlikely(dev_sts == ENA_MMIO_READ_TIMEOUT)) { - ena_trc_err("Reg read timeout occurred\n"); + ena_trc_err(ena_dev, "Reg read timeout occurred\n"); return ENA_COM_TIMER_EXPIRED; } if (!(dev_sts & ENA_REGS_DEV_STS_READY_MASK)) { - ena_trc_err("Device isn't ready, abort com init\n"); + ena_trc_err(ena_dev, "Device isn't ready, abort com init\n"); return ENA_COM_NO_DEVICE; } @@ -1869,7 +1885,7 @@ int ena_com_create_io_queue(struct ena_com_dev *ena_dev, int ret; if (ctx->qid >= ENA_TOTAL_NUM_QUEUES) { - ena_trc_err("Qid (%d) is bigger than max num of queues (%d)\n", + ena_trc_err(ena_dev, "Qid (%d) is bigger than max num of queues (%d)\n", ctx->qid, ENA_TOTAL_NUM_QUEUES); return ENA_COM_INVAL; } @@ -1928,7 +1944,7 @@ void ena_com_destroy_io_queue(struct ena_com_dev *ena_dev, u16 qid) struct ena_com_io_cq *io_cq; if (qid >= ENA_TOTAL_NUM_QUEUES) { - ena_trc_err("Qid (%d) is bigger than max num of queues (%d)\n", + ena_trc_err(ena_dev, "Qid (%d) is bigger than max num of queues (%d)\n", qid, ENA_TOTAL_NUM_QUEUES); return; } @@ -2090,7 +2106,7 @@ void ena_com_aenq_intr_handler(struct ena_com_dev *ena_dev, void *data) timestamp = (u64)aenq_common->timestamp_low | ((u64)aenq_common->timestamp_high << 32); ENA_TOUCH(timestamp); /* In case debug is disabled */ - ena_trc_dbg("AENQ! Group[%x] Syndrom[%x] timestamp: [%" ENA_PRIu64 "s]\n", + ena_trc_dbg(ena_dev, "AENQ! Group[%x] Syndrom[%x] timestamp: [%" ENA_PRIu64 "s]\n", aenq_common->group, aenq_common->syndrom, timestamp); @@ -2137,19 +2153,19 @@ int ena_com_dev_reset(struct ena_com_dev *ena_dev, if (unlikely((stat == ENA_MMIO_READ_TIMEOUT) || (cap == ENA_MMIO_READ_TIMEOUT))) { - ena_trc_err("Reg read32 timeout occurred\n"); + ena_trc_err(ena_dev, "Reg read32 timeout occurred\n"); return ENA_COM_TIMER_EXPIRED; } if ((stat & ENA_REGS_DEV_STS_READY_MASK) == 0) { - ena_trc_err("Device isn't ready, can't reset device\n"); + ena_trc_err(ena_dev, "Device isn't ready, can't reset device\n"); return ENA_COM_INVAL; } timeout = (cap & ENA_REGS_CAPS_RESET_TIMEOUT_MASK) >> ENA_REGS_CAPS_RESET_TIMEOUT_SHIFT; if (timeout == 0) { - ena_trc_err("Invalid timeout value\n"); + ena_trc_err(ena_dev, "Invalid timeout value\n"); return ENA_COM_INVAL; } @@ -2165,7 +2181,7 @@ int ena_com_dev_reset(struct ena_com_dev *ena_dev, rc = wait_for_reset_state(ena_dev, timeout, ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK); if (rc != 0) { - ena_trc_err("Reset indication didn't turn on\n"); + ena_trc_err(ena_dev, "Reset indication didn't turn on\n"); return rc; } @@ -2173,7 +2189,7 @@ int ena_com_dev_reset(struct ena_com_dev *ena_dev, ENA_REG_WRITE32(ena_dev->bus, 0, ena_dev->reg_bar + ENA_REGS_DEV_CTL_OFF); rc = wait_for_reset_state(ena_dev, timeout, 0); if (rc != 0) { - ena_trc_err("Reset indication didn't turn off\n"); + ena_trc_err(ena_dev, "Reset indication didn't turn off\n"); return rc; } @@ -2210,7 +2226,7 @@ static int ena_get_dev_stats(struct ena_com_dev *ena_dev, sizeof(*get_resp)); if (unlikely(ret)) - ena_trc_err("Failed to get stats. error: %d\n", ret); + ena_trc_err(ena_dev, "Failed to get stats. error: %d\n", ret); return ret; } @@ -2253,7 +2269,7 @@ int ena_com_set_dev_mtu(struct ena_com_dev *ena_dev, int mtu) int ret; if (!ena_com_check_supported_feature_id(ena_dev, ENA_ADMIN_MTU)) { - ena_trc_dbg("Feature %d isn't supported\n", ENA_ADMIN_MTU); + ena_trc_dbg(ena_dev, "Feature %d isn't supported\n", ENA_ADMIN_MTU); return ENA_COM_UNSUPPORTED; } @@ -2272,7 +2288,7 @@ int ena_com_set_dev_mtu(struct ena_com_dev *ena_dev, int mtu) sizeof(resp)); if (unlikely(ret)) - ena_trc_err("Failed to set mtu %d. error: %d\n", mtu, ret); + ena_trc_err(ena_dev, "Failed to set mtu %d. error: %d\n", mtu, ret); return ret; } @@ -2286,7 +2302,7 @@ int ena_com_get_offload_settings(struct ena_com_dev *ena_dev, ret = ena_com_get_feature(ena_dev, &resp, ENA_ADMIN_STATELESS_OFFLOAD_CONFIG, 0); if (unlikely(ret)) { - ena_trc_err("Failed to get offload capabilities %d\n", ret); + ena_trc_err(ena_dev, "Failed to get offload capabilities %d\n", ret); return ret; } @@ -2306,7 +2322,7 @@ int ena_com_set_hash_function(struct ena_com_dev *ena_dev) if (!ena_com_check_supported_feature_id(ena_dev, ENA_ADMIN_RSS_HASH_FUNCTION)) { - ena_trc_dbg("Feature %d isn't supported\n", + ena_trc_dbg(ena_dev, "Feature %d isn't supported\n", ENA_ADMIN_RSS_HASH_FUNCTION); return ENA_COM_UNSUPPORTED; } @@ -2318,7 +2334,7 @@ int ena_com_set_hash_function(struct ena_com_dev *ena_dev) return ret; if (!(get_resp.u.flow_hash_func.supported_func & BIT(rss->hash_func))) { - ena_trc_err("Func hash %d isn't supported by device, abort\n", + ena_trc_err(ena_dev, "Func hash %d isn't supported by device, abort\n", rss->hash_func); return ENA_COM_UNSUPPORTED; } @@ -2336,7 +2352,7 @@ int ena_com_set_hash_function(struct ena_com_dev *ena_dev) &cmd.control_buffer.address, rss->hash_key_dma_addr); if (unlikely(ret)) { - ena_trc_err("memory address set failed\n"); + ena_trc_err(ena_dev, "Memory address set failed\n"); return ret; } @@ -2348,7 +2364,7 @@ int ena_com_set_hash_function(struct ena_com_dev *ena_dev) (struct ena_admin_acq_entry *)&resp, sizeof(resp)); if (unlikely(ret)) { - ena_trc_err("Failed to set hash function %d. error: %d\n", + ena_trc_err(ena_dev, "Failed to set hash function %d. error: %d\n", rss->hash_func, ret); return ENA_COM_INVAL; } @@ -2380,7 +2396,7 @@ int ena_com_fill_hash_function(struct ena_com_dev *ena_dev, return rc; if (!(BIT(func) & get_resp.u.flow_hash_func.supported_func)) { - ena_trc_err("Flow hash function %d isn't supported\n", func); + ena_trc_err(ena_dev, "Flow hash function %d isn't supported\n", func); return ENA_COM_UNSUPPORTED; } @@ -2388,7 +2404,7 @@ int ena_com_fill_hash_function(struct ena_com_dev *ena_dev, case ENA_ADMIN_TOEPLITZ: if (key) { if (key_len != sizeof(hash_key->key)) { - ena_trc_err("key len (%hu) doesn't equal the supported size (%zu)\n", + ena_trc_err(ena_dev, "key len (%hu) doesn't equal the supported size (%zu)\n", key_len, sizeof(hash_key->key)); return ENA_COM_INVAL; } @@ -2401,7 +2417,7 @@ int ena_com_fill_hash_function(struct ena_com_dev *ena_dev, rss->hash_init_val = init_val; break; default: - ena_trc_err("Invalid hash function (%d)\n", func); + ena_trc_err(ena_dev, "Invalid hash function (%d)\n", func); return ENA_COM_INVAL; } @@ -2486,7 +2502,7 @@ int ena_com_set_hash_ctrl(struct ena_com_dev *ena_dev) if (!ena_com_check_supported_feature_id(ena_dev, ENA_ADMIN_RSS_HASH_INPUT)) { - ena_trc_dbg("Feature %d isn't supported\n", + ena_trc_dbg(ena_dev, "Feature %d isn't supported\n", ENA_ADMIN_RSS_HASH_INPUT); return ENA_COM_UNSUPPORTED; } @@ -2505,7 +2521,7 @@ int ena_com_set_hash_ctrl(struct ena_com_dev *ena_dev) &cmd.control_buffer.address, rss->hash_ctrl_dma_addr); if (unlikely(ret)) { - ena_trc_err("memory address set failed\n"); + ena_trc_err(ena_dev, "Memory address set failed\n"); return ret; } cmd.control_buffer.length = sizeof(*hash_ctrl); @@ -2516,7 +2532,7 @@ int ena_com_set_hash_ctrl(struct ena_com_dev *ena_dev) (struct ena_admin_acq_entry *)&resp, sizeof(resp)); if (unlikely(ret)) - ena_trc_err("Failed to set hash input. error: %d\n", ret); + ena_trc_err(ena_dev, "Failed to set hash input. error: %d\n", ret); return ret; } @@ -2566,7 +2582,7 @@ int ena_com_set_default_hash_ctrl(struct ena_com_dev *ena_dev) available_fields = hash_ctrl->selected_fields[i].fields & hash_ctrl->supported_fields[i].fields; if (available_fields != hash_ctrl->selected_fields[i].fields) { - ena_trc_err("hash control doesn't support all the desire configuration. proto %x supported %x selected %x\n", + ena_trc_err(ena_dev, "Hash control doesn't support all the desire configuration. proto %x supported %x selected %x\n", i, hash_ctrl->supported_fields[i].fields, hash_ctrl->selected_fields[i].fields); return ENA_COM_UNSUPPORTED; @@ -2592,7 +2608,7 @@ int ena_com_fill_hash_ctrl(struct ena_com_dev *ena_dev, int rc; if (proto >= ENA_ADMIN_RSS_PROTO_NUM) { - ena_trc_err("Invalid proto num (%u)\n", proto); + ena_trc_err(ena_dev, "Invalid proto num (%u)\n", proto); return ENA_COM_INVAL; } @@ -2604,7 +2620,7 @@ int ena_com_fill_hash_ctrl(struct ena_com_dev *ena_dev, /* Make sure all the fields are supported */ supported_fields = hash_ctrl->supported_fields[proto].fields; if ((hash_fields & supported_fields) != hash_fields) { - ena_trc_err("proto %d doesn't support the required fields %x. supports only: %x\n", + ena_trc_err(ena_dev, "Proto %d doesn't support the required fields %x. supports only: %x\n", proto, hash_fields, supported_fields); } @@ -2645,14 +2661,14 @@ int ena_com_indirect_table_set(struct ena_com_dev *ena_dev) if (!ena_com_check_supported_feature_id(ena_dev, ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG)) { - ena_trc_dbg("Feature %d isn't supported\n", + ena_trc_dbg(ena_dev, "Feature %d isn't supported\n", ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG); return ENA_COM_UNSUPPORTED; } ret = ena_com_ind_tbl_convert_to_device(ena_dev); if (ret) { - ena_trc_err("Failed to convert host indirection table to device table\n"); + ena_trc_err(ena_dev, "Failed to convert host indirection table to device table\n"); return ret; } @@ -2669,7 +2685,7 @@ int ena_com_indirect_table_set(struct ena_com_dev *ena_dev) &cmd.control_buffer.address, rss->rss_ind_tbl_dma_addr); if (unlikely(ret)) { - ena_trc_err("memory address set failed\n"); + ena_trc_err(ena_dev, "Memory address set failed\n"); return ret; } @@ -2683,7 +2699,7 @@ int ena_com_indirect_table_set(struct ena_com_dev *ena_dev) sizeof(resp)); if (unlikely(ret)) - ena_trc_err("Failed to set indirect table. error: %d\n", ret); + ena_trc_err(ena_dev, "Failed to set indirect table. error: %d\n", ret); return ret; } @@ -2848,7 +2864,7 @@ int ena_com_set_host_attributes(struct ena_com_dev *ena_dev) &cmd.u.host_attr.debug_ba, host_attr->debug_area_dma_addr); if (unlikely(ret)) { - ena_trc_err("memory address set failed\n"); + ena_trc_err(ena_dev, "Memory address set failed\n"); return ret; } @@ -2856,7 +2872,7 @@ int ena_com_set_host_attributes(struct ena_com_dev *ena_dev) &cmd.u.host_attr.os_info_ba, host_attr->host_info_dma_addr); if (unlikely(ret)) { - ena_trc_err("memory address set failed\n"); + ena_trc_err(ena_dev, "Memory address set failed\n"); return ret; } @@ -2869,7 +2885,7 @@ int ena_com_set_host_attributes(struct ena_com_dev *ena_dev) sizeof(resp)); if (unlikely(ret)) - ena_trc_err("Failed to set host attributes: %d\n", ret); + ena_trc_err(ena_dev, "Failed to set host attributes: %d\n", ret); return ret; } @@ -2881,12 +2897,13 @@ bool ena_com_interrupt_moderation_supported(struct ena_com_dev *ena_dev) ENA_ADMIN_INTERRUPT_MODERATION); } -static int ena_com_update_nonadaptive_moderation_interval(u32 coalesce_usecs, +static int ena_com_update_nonadaptive_moderation_interval(struct ena_com_dev *ena_dev, + u32 coalesce_usecs, u32 intr_delay_resolution, u32 *intr_moder_interval) { if (!intr_delay_resolution) { - ena_trc_err("Illegal interrupt delay granularity value\n"); + ena_trc_err(ena_dev, "Illegal interrupt delay granularity value\n"); return ENA_COM_FAULT; } @@ -2895,11 +2912,11 @@ static int ena_com_update_nonadaptive_moderation_interval(u32 coalesce_usecs, return 0; } - int ena_com_update_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev, u32 tx_coalesce_usecs) { - return ena_com_update_nonadaptive_moderation_interval(tx_coalesce_usecs, + return ena_com_update_nonadaptive_moderation_interval(ena_dev, + tx_coalesce_usecs, ena_dev->intr_delay_resolution, &ena_dev->intr_moder_tx_interval); } @@ -2907,7 +2924,8 @@ int ena_com_update_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_de int ena_com_update_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev, u32 rx_coalesce_usecs) { - return ena_com_update_nonadaptive_moderation_interval(rx_coalesce_usecs, + return ena_com_update_nonadaptive_moderation_interval(ena_dev, + rx_coalesce_usecs, ena_dev->intr_delay_resolution, &ena_dev->intr_moder_rx_interval); } @@ -2923,12 +2941,12 @@ int ena_com_init_interrupt_moderation(struct ena_com_dev *ena_dev) if (rc) { if (rc == ENA_COM_UNSUPPORTED) { - ena_trc_dbg("Feature %d isn't supported\n", + ena_trc_dbg(ena_dev, "Feature %d isn't supported\n", ENA_ADMIN_INTERRUPT_MODERATION); rc = 0; } else { - ena_trc_err("Failed to get interrupt moderation admin cmd. rc: %d\n", - rc); + ena_trc_err(ena_dev, + "Failed to get interrupt moderation admin cmd. rc: %d\n", rc); } /* no moderation supported, disable adaptive support */ @@ -2976,7 +2994,7 @@ int ena_com_config_dev_mode(struct ena_com_dev *ena_dev, (llq_info->descs_num_before_header * sizeof(struct ena_eth_io_tx_desc)); if (unlikely(ena_dev->tx_max_header_size == 0)) { - ena_trc_err("the size of the LLQ entry is smaller than needed\n"); + ena_trc_err(ena_dev, "The size of the LLQ entry is smaller than needed\n"); return -EINVAL; } diff --git a/drivers/net/ena/base/ena_com.h b/drivers/net/ena/base/ena_com.h index e9601b1a8e..cd116e90e6 100644 --- a/drivers/net/ena/base/ena_com.h +++ b/drivers/net/ena/base/ena_com.h @@ -300,6 +300,7 @@ struct ena_com_dev { void __iomem *mem_bar; void *dmadev; void *bus; + ena_netdev *net_device; enum ena_admin_placement_policy_type tx_mem_queue_type; u32 tx_max_header_size; @@ -944,6 +945,26 @@ int ena_com_config_dev_mode(struct ena_com_dev *ena_dev, struct ena_admin_feature_llq_desc *llq_features, struct ena_llq_configurations *llq_default_config); +/* ena_com_io_sq_to_ena_dev - Extract ena_com_dev using contained field io_sq. + * @io_sq: IO submit queue struct + * + * @return - ena_com_dev struct extracted from io_sq + */ +static inline struct ena_com_dev *ena_com_io_sq_to_ena_dev(struct ena_com_io_sq *io_sq) +{ + return container_of(io_sq, struct ena_com_dev, io_sq_queues[io_sq->qid]); +} + +/* ena_com_io_cq_to_ena_dev - Extract ena_com_dev using contained field io_cq. + * @io_sq: IO submit queue struct + * + * @return - ena_com_dev struct extracted from io_sq + */ +static inline struct ena_com_dev *ena_com_io_cq_to_ena_dev(struct ena_com_io_cq *io_cq) +{ + return container_of(io_cq, struct ena_com_dev, io_cq_queues[io_cq->qid]); +} + static inline bool ena_com_get_adaptive_moderation_enabled(struct ena_com_dev *ena_dev) { return ena_dev->adaptive_coalescing; diff --git a/drivers/net/ena/base/ena_eth_com.c b/drivers/net/ena/base/ena_eth_com.c index 5583a310a1..701e6721e3 100644 --- a/drivers/net/ena/base/ena_eth_com.c +++ b/drivers/net/ena/base/ena_eth_com.c @@ -57,12 +57,14 @@ static int ena_com_write_bounce_buffer_to_dev(struct ena_com_io_sq *io_sq, if (is_llq_max_tx_burst_exists(io_sq)) { if (unlikely(!io_sq->entries_in_tx_burst_left)) { - ena_trc_err("Error: trying to send more packets than tx burst allows\n"); + ena_trc_err(ena_com_io_sq_to_ena_dev(io_sq), + "Error: trying to send more packets than tx burst allows\n"); return ENA_COM_NO_SPACE; } io_sq->entries_in_tx_burst_left--; - ena_trc_dbg("decreasing entries_in_tx_burst_left of queue %d to %d\n", + ena_trc_dbg(ena_com_io_sq_to_ena_dev(io_sq), + "Decreasing entries_in_tx_burst_left of queue %d to %d\n", io_sq->qid, io_sq->entries_in_tx_burst_left); } @@ -101,12 +103,14 @@ static int ena_com_write_header_to_bounce(struct ena_com_io_sq *io_sq, llq_info->descs_num_before_header * io_sq->desc_entry_size; if (unlikely((header_offset + header_len) > llq_info->desc_list_entry_size)) { - ena_trc_err("trying to write header larger than llq entry can accommodate\n"); + ena_trc_err(ena_com_io_sq_to_ena_dev(io_sq), + "Trying to write header larger than llq entry can accommodate\n"); return ENA_COM_FAULT; } if (unlikely(!bounce_buffer)) { - ena_trc_err("bounce buffer is NULL\n"); + ena_trc_err(ena_com_io_sq_to_ena_dev(io_sq), + "Bounce buffer is NULL\n"); return ENA_COM_FAULT; } @@ -124,7 +128,8 @@ static void *get_sq_desc_llq(struct ena_com_io_sq *io_sq) bounce_buffer = pkt_ctrl->curr_bounce_buf; if (unlikely(!bounce_buffer)) { - ena_trc_err("bounce buffer is NULL\n"); + ena_trc_err(ena_com_io_sq_to_ena_dev(io_sq), + "Bounce buffer is NULL\n"); return NULL; } @@ -149,7 +154,8 @@ static int ena_com_close_bounce_buffer(struct ena_com_io_sq *io_sq) rc = ena_com_write_bounce_buffer_to_dev(io_sq, pkt_ctrl->curr_bounce_buf); if (unlikely(rc)) { - ena_trc_err("failed to write bounce buffer to device\n"); + ena_trc_err(ena_com_io_sq_to_ena_dev(io_sq), + "Failed to write bounce buffer to device\n"); return rc; } @@ -182,7 +188,8 @@ static int ena_com_sq_update_llq_tail(struct ena_com_io_sq *io_sq) rc = ena_com_write_bounce_buffer_to_dev(io_sq, pkt_ctrl->curr_bounce_buf); if (unlikely(rc)) { - ena_trc_err("failed to write bounce buffer to device\n"); + ena_trc_err(ena_com_io_sq_to_ena_dev(io_sq), + "Failed to write bounce buffer to device\n"); return rc; } @@ -252,7 +259,8 @@ static u16 ena_com_cdesc_rx_pkt_get(struct ena_com_io_cq *io_cq, io_cq->cur_rx_pkt_cdesc_count = 0; io_cq->cur_rx_pkt_cdesc_start_idx = head_masked; - ena_trc_dbg("ena q_id: %d packets were completed. first desc idx %u descs# %d\n", + ena_trc_dbg(ena_com_io_cq_to_ena_dev(io_cq), + "ENA q_id: %d packets were completed. first desc idx %u descs# %d\n", io_cq->qid, *first_cdesc_idx, count); } else { io_cq->cur_rx_pkt_cdesc_count += count; @@ -335,8 +343,9 @@ static int ena_com_create_and_store_tx_meta_desc(struct ena_com_io_sq *io_sq, } } -static void ena_com_rx_set_flags(struct ena_com_rx_ctx *ena_rx_ctx, - struct ena_eth_io_rx_cdesc_base *cdesc) +static void ena_com_rx_set_flags(struct ena_com_io_cq *io_cq, + struct ena_com_rx_ctx *ena_rx_ctx, + struct ena_eth_io_rx_cdesc_base *cdesc) { ena_rx_ctx->l3_proto = cdesc->status & ENA_ETH_IO_RX_CDESC_BASE_L3_PROTO_IDX_MASK; @@ -357,7 +366,8 @@ static void ena_com_rx_set_flags(struct ena_com_rx_ctx *ena_rx_ctx, (cdesc->status & ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_SHIFT; - ena_trc_dbg("ena_rx_ctx->l3_proto %d ena_rx_ctx->l4_proto %d\nena_rx_ctx->l3_csum_err %d ena_rx_ctx->l4_csum_err %d\nhash frag %d frag: %d cdesc_status: %x\n", + ena_trc_dbg(ena_com_io_cq_to_ena_dev(io_cq), + "l3_proto %d l4_proto %d l3_csum_err %d l4_csum_err %d hash %d frag %d cdesc_status %x\n", ena_rx_ctx->l3_proto, ena_rx_ctx->l4_proto, ena_rx_ctx->l3_csum_err, @@ -386,23 +396,26 @@ int ena_com_prepare_tx(struct ena_com_io_sq *io_sq, u64 addr_hi; ENA_WARN(io_sq->direction != ENA_COM_IO_QUEUE_DIRECTION_TX, - "wrong Q type"); + ena_com_io_sq_to_ena_dev(io_sq), "wrong Q type"); /* num_bufs +1 for potential meta desc */ if (unlikely(!ena_com_sq_have_enough_space(io_sq, num_bufs + 1))) { - ena_trc_dbg("Not enough space in the tx queue\n"); + ena_trc_dbg(ena_com_io_sq_to_ena_dev(io_sq), + "Not enough space in the tx queue\n"); return ENA_COM_NO_MEM; } if (unlikely(header_len > io_sq->tx_max_header_size)) { - ena_trc_err("header size is too large %d max header: %d\n", + ena_trc_err(ena_com_io_sq_to_ena_dev(io_sq), + "Header size is too large %d max header: %d\n", header_len, io_sq->tx_max_header_size); return ENA_COM_INVAL; } if (unlikely(io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV && !buffer_to_push)) { - ena_trc_err("push header wasn't provided on LLQ mode\n"); + ena_trc_err(ena_com_io_sq_to_ena_dev(io_sq), + "Push header wasn't provided on LLQ mode\n"); return ENA_COM_INVAL; } @@ -412,7 +425,8 @@ int ena_com_prepare_tx(struct ena_com_io_sq *io_sq, rc = ena_com_create_and_store_tx_meta_desc(io_sq, ena_tx_ctx, &have_meta); if (unlikely(rc)) { - ena_trc_err("failed to create and store tx meta desc\n"); + ena_trc_err(ena_com_io_sq_to_ena_dev(io_sq), + "Failed to create and store tx meta desc\n"); return rc; } @@ -420,7 +434,8 @@ int ena_com_prepare_tx(struct ena_com_io_sq *io_sq, if (unlikely(!num_bufs && !header_len)) { rc = ena_com_close_bounce_buffer(io_sq); if (rc) - ena_trc_err("failed to write buffers to LLQ\n"); + ena_trc_err(ena_com_io_sq_to_ena_dev(io_sq), + "Failed to write buffers to LLQ\n"); *nb_hw_desc = io_sq->tail - start_tail; return rc; } @@ -481,7 +496,8 @@ int ena_com_prepare_tx(struct ena_com_io_sq *io_sq, if (likely(i != 0)) { rc = ena_com_sq_update_tail(io_sq); if (unlikely(rc)) { - ena_trc_err("failed to update sq tail\n"); + ena_trc_err(ena_com_io_sq_to_ena_dev(io_sq), + "Failed to update sq tail\n"); return rc; } @@ -513,13 +529,15 @@ int ena_com_prepare_tx(struct ena_com_io_sq *io_sq, rc = ena_com_sq_update_tail(io_sq); if (unlikely(rc)) { - ena_trc_err("failed to update sq tail of the last descriptor\n"); + ena_trc_err(ena_com_io_sq_to_ena_dev(io_sq), + "Failed to update sq tail of the last descriptor\n"); return rc; } rc = ena_com_close_bounce_buffer(io_sq); if (rc) - ena_trc_err("failed when closing bounce buffer\n"); + ena_trc_err(ena_com_io_sq_to_ena_dev(io_sq), + "Failed when closing bounce buffer\n"); *nb_hw_desc = io_sq->tail - start_tail; return rc; @@ -537,7 +555,7 @@ int ena_com_rx_pkt(struct ena_com_io_cq *io_cq, u16 i = 0; ENA_WARN(io_cq->direction != ENA_COM_IO_QUEUE_DIRECTION_RX, - "wrong Q type"); + ena_com_io_cq_to_ena_dev(io_cq), "wrong Q type"); nb_hw_desc = ena_com_cdesc_rx_pkt_get(io_cq, &cdesc_idx); if (nb_hw_desc == 0) { @@ -545,11 +563,13 @@ int ena_com_rx_pkt(struct ena_com_io_cq *io_cq, return 0; } - ena_trc_dbg("fetch rx packet: queue %d completed desc: %d\n", + ena_trc_dbg(ena_com_io_cq_to_ena_dev(io_cq), + "Fetch rx packet: queue %d completed desc: %d\n", io_cq->qid, nb_hw_desc); if (unlikely(nb_hw_desc > ena_rx_ctx->max_bufs)) { - ena_trc_err("Too many RX cdescs (%d) > MAX(%d)\n", + ena_trc_err(ena_com_io_cq_to_ena_dev(io_cq), + "Too many RX cdescs (%d) > MAX(%d)\n", nb_hw_desc, ena_rx_ctx->max_bufs); return ENA_COM_NO_SPACE; } @@ -573,13 +593,15 @@ int ena_com_rx_pkt(struct ena_com_io_cq *io_cq, /* Update SQ head ptr */ io_sq->next_to_comp += nb_hw_desc; - ena_trc_dbg("[%s][QID#%d] Updating SQ head to: %d\n", __func__, + ena_trc_dbg(ena_com_io_cq_to_ena_dev(io_cq), + "[%s][QID#%d] Updating SQ head to: %d\n", __func__, io_sq->qid, io_sq->next_to_comp); /* Get rx flags from the last pkt */ - ena_com_rx_set_flags(ena_rx_ctx, cdesc); + ena_com_rx_set_flags(io_cq, ena_rx_ctx, cdesc); ena_rx_ctx->descs = nb_hw_desc; + return 0; } @@ -590,7 +612,7 @@ int ena_com_add_single_rx_desc(struct ena_com_io_sq *io_sq, struct ena_eth_io_rx_desc *desc; ENA_WARN(io_sq->direction != ENA_COM_IO_QUEUE_DIRECTION_RX, - "wrong Q type"); + ena_com_io_sq_to_ena_dev(io_sq), "wrong Q type"); if (unlikely(!ena_com_sq_have_enough_space(io_sq, 1))) return ENA_COM_NO_SPACE; @@ -610,6 +632,10 @@ int ena_com_add_single_rx_desc(struct ena_com_io_sq *io_sq, desc->req_id = req_id; + ena_trc_dbg(ena_com_io_sq_to_ena_dev(io_sq), + "[%s] Adding single RX desc, Queue: %u, req_id: %u\n", + __func__, io_sq->qid, req_id); + desc->buff_addr_lo = (u32)ena_buf->paddr; desc->buff_addr_hi = ((ena_buf->paddr & GENMASK_ULL(io_sq->dma_addr_bits - 1, 32)) >> 32); diff --git a/drivers/net/ena/base/ena_eth_com.h b/drivers/net/ena/base/ena_eth_com.h index 7dda16cd9f..0cfd18882e 100644 --- a/drivers/net/ena/base/ena_eth_com.h +++ b/drivers/net/ena/base/ena_eth_com.h @@ -143,7 +143,8 @@ static inline bool ena_com_is_doorbell_needed(struct ena_com_io_sq *io_sq, llq_info->descs_per_entry); } - ena_trc_dbg("queue: %d num_descs: %d num_entries_needed: %d\n", + ena_trc_dbg(ena_com_io_sq_to_ena_dev(io_sq), + "Queue: %d num_descs: %d num_entries_needed: %d\n", io_sq->qid, num_descs, num_entries_needed); return num_entries_needed > io_sq->entries_in_tx_burst_left; @@ -154,14 +155,16 @@ static inline int ena_com_write_sq_doorbell(struct ena_com_io_sq *io_sq) u16 max_entries_in_tx_burst = io_sq->llq_info.max_entries_in_tx_burst; u16 tail = io_sq->tail; - ena_trc_dbg("write submission queue doorbell for queue: %d tail: %d\n", + ena_trc_dbg(ena_com_io_sq_to_ena_dev(io_sq), + "Write submission queue doorbell for queue: %d tail: %d\n", io_sq->qid, tail); ENA_REG_WRITE32(io_sq->bus, tail, io_sq->db_addr); if (is_llq_max_tx_burst_exists(io_sq)) { - ena_trc_dbg("reset available entries in tx burst for queue %d to %d\n", - io_sq->qid, max_entries_in_tx_burst); + ena_trc_dbg(ena_com_io_sq_to_ena_dev(io_sq), + "Reset available entries in tx burst for queue %d to %d\n", + io_sq->qid, max_entries_in_tx_burst); io_sq->entries_in_tx_burst_left = max_entries_in_tx_burst; } @@ -179,7 +182,8 @@ static inline int ena_com_update_dev_comp_head(struct ena_com_io_cq *io_cq) need_update = unreported_comp > (io_cq->q_depth / ENA_COMP_HEAD_THRESH); if (unlikely(need_update)) { - ena_trc_dbg("Write completion queue doorbell for queue %d: head: %d\n", + ena_trc_dbg(ena_com_io_cq_to_ena_dev(io_cq), + "Write completion queue doorbell for queue %d: head: %d\n", io_cq->qid, head); ENA_REG_WRITE32(io_cq->bus, head, io_cq->cq_head_db_reg); io_cq->last_head_update = head; @@ -243,7 +247,8 @@ static inline int ena_com_tx_comp_req_id_get(struct ena_com_io_cq *io_cq, *req_id = READ_ONCE16(cdesc->req_id); if (unlikely(*req_id >= io_cq->q_depth)) { - ena_trc_err("Invalid req id %d\n", cdesc->req_id); + ena_trc_err(ena_com_io_cq_to_ena_dev(io_cq), + "Invalid req id %d\n", cdesc->req_id); return ENA_COM_INVAL; } diff --git a/drivers/net/ena/base/ena_plat_dpdk.h b/drivers/net/ena/base/ena_plat_dpdk.h index ae68f860a5..231d44e0e0 100644 --- a/drivers/net/ena/base/ena_plat_dpdk.h +++ b/drivers/net/ena/base/ena_plat_dpdk.h @@ -32,6 +32,7 @@ typedef uint32_t u32; typedef uint16_t u16; typedef uint8_t u8; +typedef struct rte_eth_dev ena_netdev; typedef uint64_t dma_addr_t; #ifndef ETIME #define ETIME ETIMEDOUT @@ -98,29 +99,32 @@ extern int ena_logtype_com; (~0ULL >> (BITS_PER_LONG_LONG - 1 - (h)))) #ifdef RTE_LIBRTE_ENA_COM_DEBUG -#define ena_trc_log(level, fmt, arg...) \ - rte_log(RTE_LOG_ ## level, ena_logtype_com, \ - "[ENA_COM: %s]" fmt, __func__, ##arg) - -#define ena_trc_dbg(format, arg...) ena_trc_log(DEBUG, format, ##arg) -#define ena_trc_info(format, arg...) ena_trc_log(INFO, format, ##arg) -#define ena_trc_warn(format, arg...) ena_trc_log(WARNING, format, ##arg) -#define ena_trc_err(format, arg...) ena_trc_log(ERR, format, ##arg) +#define ena_trc_log(dev, level, fmt, arg...) \ + ( \ + ENA_TOUCH(dev), \ + rte_log(RTE_LOG_ ## level, ena_logtype_com, \ + "[ENA_COM: %s]" fmt, __func__, ##arg) \ + ) + +#define ena_trc_dbg(dev, format, arg...) ena_trc_log(dev, DEBUG, format, ##arg) +#define ena_trc_info(dev, format, arg...) ena_trc_log(dev, INFO, format, ##arg) +#define ena_trc_warn(dev, format, arg...) ena_trc_log(dev, WARNING, format, ##arg) +#define ena_trc_err(dev, format, arg...) ena_trc_log(dev, ERR, format, ##arg) #else -#define ena_trc_dbg(format, arg...) do { } while (0) -#define ena_trc_info(format, arg...) do { } while (0) -#define ena_trc_warn(format, arg...) do { } while (0) -#define ena_trc_err(format, arg...) do { } while (0) +#define ena_trc_dbg(dev, format, arg...) ENA_TOUCH(dev) +#define ena_trc_info(dev, format, arg...) ENA_TOUCH(dev) +#define ena_trc_warn(dev, format, arg...) ENA_TOUCH(dev) +#define ena_trc_err(dev, format, arg...) ENA_TOUCH(dev) #endif /* RTE_LIBRTE_ENA_COM_DEBUG */ -#define ENA_WARN(cond, format, arg...) \ -do { \ - if (unlikely(cond)) { \ - ena_trc_err( \ - "Warn failed on %s:%s:%d:" format, \ - __FILE__, __func__, __LINE__, ##arg); \ - } \ -} while (0) +#define ENA_WARN(cond, dev, format, arg...) \ + do { \ + if (unlikely(cond)) { \ + ena_trc_err(dev, \ + "Warn failed on %s:%s:%d:" format, \ + __FILE__, __func__, __LINE__, ##arg); \ + } \ + } while (0) /* Spinlock related methods */ #define ena_spinlock_t rte_spinlock_t From patchwork Thu May 6 14:25:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Krawczyk X-Patchwork-Id: 93009 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E981DA0524; Thu, 6 May 2021 16:26:17 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D041F4111D; Thu, 6 May 2021 16:25:49 +0200 (CEST) Received: from mail-lf1-f54.google.com (mail-lf1-f54.google.com [209.85.167.54]) by mails.dpdk.org (Postfix) with ESMTP id 8A9454110F for ; Thu, 6 May 2021 16:25:48 +0200 (CEST) Received: by mail-lf1-f54.google.com with SMTP id j10so8017904lfb.12 for ; Thu, 06 May 2021 07:25:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=qAlEd43IG+W8z9qC7+I6wVwUzQ2CvZGWPb7gGtUidNc=; b=wC0NKeR1rXDhcl1eu24sRDO4AzqjBy6h35gbi2o/nwbietG7NWStVYDIMasRBVjlds 2b+KX6fqTEVt4eNjT35MsRWQ7m6yJ+qYFhWY2H13xoNRhRNpfV+uzuAMR91tyiOc4fC0 a2rgW+sftjnk9wwGPTF58UZ4zpKAy4K1CZAfA2ysAD8WD9Kk4/cBMKKX6rKFjJty0SXf QSt4IJF3497c22/FZSLXM9oI/AApK6vcYVDs+ep0vnkb7xhIWnJx0TFMFELsb+GM8xdC Ehl/YEH280fVoHvxDy/2ofP8wbd9jweUgruj/p+M+q81Z2t4jqJkfRxk1FiVHZsfrGdJ aW3w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qAlEd43IG+W8z9qC7+I6wVwUzQ2CvZGWPb7gGtUidNc=; b=qBx50kfQVA829v/KNe8hkoaVPnLWFQOKMDrZRWrw+ubTfZbPRXNBdp45sIF0vxx0gg O4VTqzzOfffcSunaIGzWHHyaRO2I8BcbhqZO9e9tuZb6rjck8VesaiUGD1v8FTTI0FZk B9FlgrnTbP/UrDHoK/68AP2t1fa8Cjh9lD4RLT+tPa5/i9HdWH6YKrT2CgHs3Hk7L8TO f6agMzGzDFpaY/MxMkx2g9vTFBLGNxWG2UGNjAL6ypgEcHA3CZ+GH3d7T58iqBdq3IqJ udDc70r/hwfX777FzzDAgej/p9/8YQxdi9g0AP44Z3bsF6RZL2P+JzzreuM5jabvVrhI JOxA== X-Gm-Message-State: AOAM531Qg6MqiPh0Gp33BvKp6RBbs3nmlx6nNL06lps+I4rjSuXuaMuY tDQSbUgi/OFcAQKgmeQmW9e46ipqR1Aj9bx8 X-Google-Smtp-Source: ABdhPJynrVxmx9gQYgFR6IgPVeXvK8iR/mhbYW2tF6Vj7LAdy1e91W70KmQ/SCMOiN/pOp9uOHbg7g== X-Received: by 2002:ac2:547c:: with SMTP id e28mr3141343lfn.628.1620311147575; Thu, 06 May 2021 07:25:47 -0700 (PDT) Received: from DESKTOP-U5LNN3J.localdomain (89-79-189-199.dynamic.chello.pl. [89.79.189.199]) by smtp.gmail.com with ESMTPSA id b40sm892908ljr.101.2021.05.06.07.25.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 May 2021 07:25:46 -0700 (PDT) From: Michal Krawczyk To: dev@dpdk.org Cc: ndagan@amazon.com, gtzalik@amazon.com, igorch@amazon.com, upstream@semihalf.com, Michal Krawczyk Date: Thu, 6 May 2021 16:25:08 +0200 Message-Id: <20210506142526.28245-5-mk@semihalf.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210506142526.28245-1-mk@semihalf.com> References: <20210505073348.6394-1-mk@semihalf.com> <20210506142526.28245-1-mk@semihalf.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v3 04/22] net/ena/base: typos, style and comments improvements X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" List of changes: * Comment style was adjusted for the functions * The keys_num at "struct ena_admin_feature_rss_flow_hash_control" was renamed to the key_parts to better describe it's meaning * The RSS indirection table was called "REDIRECTION" -> changed to INDIRECTION * Change AENQ field "syndrom" -> "syndrome" * Calculate number of the RSS key parts or whole key by ussing the common way: sizeof of the first element of the RSS key * Add description of the "enum ena_admin_aq_feature_id" * Rename "map_rx_buf_bidirectional" field as "rx_buf_mirroring" * Other minor style fixes (remove extra spaces, add missing line break, improve indentation) * Remove unused macros ENA_ADMIN_EXTRA_PROPERTIES_* * Restructure the "if {} else if {} else" conditional statement for setting up the meta descriptor Fixes: 99ecfbf845b3 ("ena: import communication layer") Fixes: b68309be44c0 ("net/ena/base: update communication layer for the ENAv2") Fixes: b2b02edeb0d6 ("net/ena/base: upgrade HAL for new HW features") Signed-off-by: Michal Krawczyk Reviewed-by: Igor Chauskin Reviewed-by: Guy Tzalik --- drivers/net/ena/base/ena_com.c | 26 +++--- .../net/ena/base/ena_defs/ena_admin_defs.h | 85 +++++++++---------- drivers/net/ena/base/ena_eth_com.c | 16 ++-- drivers/net/ena/ena_ethdev.c | 4 +- 4 files changed, 66 insertions(+), 65 deletions(-) diff --git a/drivers/net/ena/base/ena_com.c b/drivers/net/ena/base/ena_com.c index 9931819bbb..9dc9f280c4 100644 --- a/drivers/net/ena/base/ena_com.c +++ b/drivers/net/ena/base/ena_com.c @@ -598,7 +598,7 @@ static int ena_com_wait_and_process_admin_cq_polling(struct ena_comp_ctx *comp_c return ret; } -/** +/* * Set the LLQ configurations of the firmware * * The driver provides only the enabled feature values to the device, @@ -1092,7 +1092,7 @@ static void ena_com_hash_key_fill_default_key(struct ena_com_dev *ena_dev) /* The key buffer is stored in the device in an array of * uint32 elements. */ - hash_key->keys_num = ENA_ADMIN_RSS_KEY_PARTS; + hash_key->key_parts = ENA_ADMIN_RSS_KEY_PARTS; } static int ena_com_hash_key_allocate(struct ena_com_dev *ena_dev) @@ -1165,7 +1165,7 @@ static int ena_com_indirect_table_allocate(struct ena_com_dev *ena_dev, int ret; ret = ena_com_get_feature(ena_dev, &get_resp, - ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG, 0); + ENA_ADMIN_RSS_INDIRECTION_TABLE_CONFIG, 0); if (unlikely(ret)) return ret; @@ -1977,6 +1977,7 @@ int ena_com_get_dev_attr_feat(struct ena_com_dev *ena_dev, memcpy(&get_feat_ctx->dev_attr, &get_resp.u.dev_attr, sizeof(get_resp.u.dev_attr)); + ena_dev->supported_features = get_resp.u.dev_attr.supported_features; if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) { @@ -2044,7 +2045,7 @@ int ena_com_get_dev_attr_feat(struct ena_com_dev *ena_dev, return rc; rc = ena_com_get_feature(ena_dev, &get_resp, - ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG, 0); + ENA_ADMIN_RSS_INDIRECTION_TABLE_CONFIG, 0); if (!rc) memcpy(&get_feat_ctx->ind_table, &get_resp.u.ind_table, sizeof(get_resp.u.ind_table)); @@ -2106,9 +2107,9 @@ void ena_com_aenq_intr_handler(struct ena_com_dev *ena_dev, void *data) timestamp = (u64)aenq_common->timestamp_low | ((u64)aenq_common->timestamp_high << 32); ENA_TOUCH(timestamp); /* In case debug is disabled */ - ena_trc_dbg(ena_dev, "AENQ! Group[%x] Syndrom[%x] timestamp: [%" ENA_PRIu64 "s]\n", + ena_trc_dbg(ena_dev, "AENQ! Group[%x] Syndrome[%x] timestamp: [%" ENA_PRIu64 "s]\n", aenq_common->group, - aenq_common->syndrom, + aenq_common->syndrome, timestamp); /* Handle specific event*/ @@ -2410,7 +2411,7 @@ int ena_com_fill_hash_function(struct ena_com_dev *ena_dev, } memcpy(hash_key->key, key, key_len); rss->hash_init_val = init_val; - hash_key->keys_num = key_len / sizeof(u32); + hash_key->key_parts = key_len / sizeof(hash_key->key[0]); } break; case ENA_ADMIN_CRC32: @@ -2465,7 +2466,8 @@ int ena_com_get_hash_key(struct ena_com_dev *ena_dev, u8 *key) ena_dev->rss.hash_key; if (key) - memcpy(key, hash_key->key, (size_t)(hash_key->keys_num) << 2); + memcpy(key, hash_key->key, + (size_t)(hash_key->key_parts) * sizeof(hash_key->key[0])); return 0; } @@ -2660,9 +2662,9 @@ int ena_com_indirect_table_set(struct ena_com_dev *ena_dev) int ret; if (!ena_com_check_supported_feature_id(ena_dev, - ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG)) { + ENA_ADMIN_RSS_INDIRECTION_TABLE_CONFIG)) { ena_trc_dbg(ena_dev, "Feature %d isn't supported\n", - ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG); + ENA_ADMIN_RSS_INDIRECTION_TABLE_CONFIG); return ENA_COM_UNSUPPORTED; } @@ -2677,7 +2679,7 @@ int ena_com_indirect_table_set(struct ena_com_dev *ena_dev) cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE; cmd.aq_common_descriptor.flags = ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK; - cmd.feat_common.feature_id = ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG; + cmd.feat_common.feature_id = ENA_ADMIN_RSS_INDIRECTION_TABLE_CONFIG; cmd.u.ind_table.size = rss->tbl_log_size; cmd.u.ind_table.inline_index = 0xFFFFFFFF; @@ -2715,7 +2717,7 @@ int ena_com_indirect_table_get(struct ena_com_dev *ena_dev, u32 *ind_tbl) sizeof(struct ena_admin_rss_ind_table_entry); rc = ena_com_get_feature_ex(ena_dev, &get_resp, - ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG, + ENA_ADMIN_RSS_INDIRECTION_TABLE_CONFIG, rss->rss_ind_tbl_dma_addr, tbl_size, 0); if (unlikely(rc)) diff --git a/drivers/net/ena/base/ena_defs/ena_admin_defs.h b/drivers/net/ena/base/ena_defs/ena_admin_defs.h index 30e5eead71..40c2db717c 100644 --- a/drivers/net/ena/base/ena_defs/ena_admin_defs.h +++ b/drivers/net/ena/base/ena_defs/ena_admin_defs.h @@ -2,13 +2,9 @@ * Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates. * All rights reserved. */ - #ifndef _ENA_ADMIN_H_ #define _ENA_ADMIN_H_ -#define ENA_ADMIN_EXTRA_PROPERTIES_STRING_LEN 32 -#define ENA_ADMIN_EXTRA_PROPERTIES_COUNT 32 - #define ENA_ADMIN_RSS_KEY_PARTS 10 enum ena_admin_aq_opcode { @@ -33,6 +29,7 @@ enum ena_admin_aq_completion_status { ENA_ADMIN_RESOURCE_BUSY = 7, }; +/* subcommands for the set/get feature admin commands */ enum ena_admin_aq_feature_id { ENA_ADMIN_DEVICE_ATTRIBUTES = 1, ENA_ADMIN_MAX_QUEUES_NUM = 2, @@ -43,7 +40,7 @@ enum ena_admin_aq_feature_id { ENA_ADMIN_MAX_QUEUES_EXT = 7, ENA_ADMIN_RSS_HASH_FUNCTION = 10, ENA_ADMIN_STATELESS_OFFLOAD_CONFIG = 11, - ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG = 12, + ENA_ADMIN_RSS_INDIRECTION_TABLE_CONFIG = 12, ENA_ADMIN_MTU = 14, ENA_ADMIN_RSS_HASH_INPUT = 18, ENA_ADMIN_INTERRUPT_MODERATION = 20, @@ -175,7 +172,7 @@ struct ena_admin_acq_common_desc { uint16_t extended_status; /* indicates to the driver which AQ entry has been consumed by the - * device and could be reused + * device and could be reused */ uint16_t sq_head_indx; }; @@ -220,8 +217,8 @@ struct ena_admin_aq_create_sq_cmd { */ uint8_t sq_caps_3; - /* associated completion queue id. This CQ must be created prior to - * SQ creation + /* associated completion queue id. This CQ must be created prior to SQ + * creation */ uint16_t cq_idx; @@ -360,7 +357,7 @@ struct ena_admin_aq_get_stats_cmd { uint16_t queue_idx; /* device id, value 0xFFFF means mine. only privileged device can get - * stats of other device + * stats of other device */ uint16_t device_id; }; @@ -442,8 +439,8 @@ struct ena_admin_get_set_feature_common_desc { uint8_t feature_id; /* The driver specifies the max feature version it supports and the - * device responds with the currently supported feature version. The - * field is zero based + * device responds with the currently supported feature version. The + * field is zero based */ uint8_t feature_version; @@ -455,7 +452,9 @@ struct ena_admin_device_attr_feature_desc { uint32_t device_version; - /* bitmap of ena_admin_aq_feature_id */ + /* bitmap of ena_admin_aq_feature_id, which represents supported + * subcommands for the set/get feature admin commands. + */ uint32_t supported_features; uint32_t reserved3; @@ -541,32 +540,30 @@ struct ena_admin_feature_llq_desc { uint32_t max_llq_depth; - /* specify the header locations the device supports. bitfield of - * enum ena_admin_llq_header_location. + /* specify the header locations the device supports. bitfield of enum + * ena_admin_llq_header_location. */ uint16_t header_location_ctrl_supported; /* the header location the driver selected to use. */ uint16_t header_location_ctrl_enabled; - /* if inline header is specified - this is the size of descriptor - * list entry. If header in a separate ring is specified - this is - * the size of header ring entry. bitfield of enum - * ena_admin_llq_ring_entry_size. specify the entry sizes the device - * supports + /* if inline header is specified - this is the size of descriptor list + * entry. If header in a separate ring is specified - this is the size + * of header ring entry. bitfield of enum ena_admin_llq_ring_entry_size. + * specify the entry sizes the device supports */ uint16_t entry_size_ctrl_supported; /* the entry size the driver selected to use. */ uint16_t entry_size_ctrl_enabled; - /* valid only if inline header is specified. First entry associated - * with the packet includes descriptors and header. Rest of the - * entries occupied by descriptors. This parameter defines the max - * number of descriptors precedding the header in the first entry. - * The field is bitfield of enum - * ena_admin_llq_num_descs_before_header and specify the values the - * device supports + /* valid only if inline header is specified. First entry associated with + * the packet includes descriptors and header. Rest of the entries + * occupied by descriptors. This parameter defines the max number of + * descriptors precedding the header in the first entry. The field is + * bitfield of enum ena_admin_llq_num_descs_before_header and specify + * the values the device supports */ uint16_t desc_num_before_header_supported; @@ -574,7 +571,7 @@ struct ena_admin_feature_llq_desc { uint16_t desc_num_before_header_enabled; /* valid only if inline was chosen. bitfield of enum - * ena_admin_llq_stride_ctrl + * ena_admin_llq_stride_ctrl */ uint16_t descriptors_stride_ctrl_supported; @@ -584,8 +581,8 @@ struct ena_admin_feature_llq_desc { /* reserved */ uint32_t reserved1; - /* accelerated low latency queues requirement. Driver needs to - * support those requirements in order to use accelerated LLQ + /* accelerated low latency queues requirement. driver needs to + * support those requirements in order to use accelerated llq */ struct ena_admin_accel_mode_req accel_mode; }; @@ -609,8 +606,8 @@ struct ena_admin_queue_ext_feature_fields { uint32_t max_tx_header_size; - /* Maximum Descriptors number, including meta descriptor, allowed for - * a single Tx packet + /* Maximum Descriptors number, including meta descriptor, allowed for a + * single Tx packet */ uint16_t max_per_packet_tx_descs; @@ -633,8 +630,8 @@ struct ena_admin_queue_feature_desc { uint32_t max_header_size; - /* Maximum Descriptors number, including meta descriptor, allowed for - * a single Tx packet + /* Maximum Descriptors number, including meta descriptor, allowed for a + * single Tx packet */ uint16_t max_packet_tx_descs; @@ -730,7 +727,7 @@ enum ena_admin_hash_functions { }; struct ena_admin_feature_rss_flow_hash_control { - uint32_t keys_num; + uint32_t key_parts; uint32_t reserved; @@ -872,7 +869,7 @@ struct ena_admin_host_info { /* 0 : mutable_rss_table_size * 1 : rx_offset * 2 : interrupt_moderation - * 3 : map_rx_buf_bidirectional + * 3 : rx_buf_mirroring * 4 : rss_configurable_function_key * 31:5 : reserved */ @@ -956,7 +953,7 @@ struct ena_admin_queue_ext_feature_desc { struct ena_admin_queue_ext_feature_fields max_queue_ext; uint32_t raw[10]; - } ; + }; }; struct ena_admin_get_feat_resp { @@ -1039,7 +1036,7 @@ struct ena_admin_set_feat_resp { struct ena_admin_aenq_common_desc { uint16_t group; - uint16_t syndrom; + uint16_t syndrome; /* 0 : phase * 7:1 : reserved - MBZ @@ -1063,7 +1060,7 @@ enum ena_admin_aenq_group { ENA_ADMIN_AENQ_GROUPS_NUM = 5, }; -enum ena_admin_aenq_notification_syndrom { +enum ena_admin_aenq_notification_syndrome { ENA_ADMIN_SUSPEND = 0, ENA_ADMIN_RESUME = 1, ENA_ADMIN_UPDATE_HINTS = 2, @@ -1197,8 +1194,8 @@ struct ena_admin_ena_mmio_req_read_less_resp { #define ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK BIT(1) #define ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_SHIFT 2 #define ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_MASK BIT(2) -#define ENA_ADMIN_HOST_INFO_MAP_RX_BUF_BIDIRECTIONAL_SHIFT 3 -#define ENA_ADMIN_HOST_INFO_MAP_RX_BUF_BIDIRECTIONAL_MASK BIT(3) +#define ENA_ADMIN_HOST_INFO_RX_BUF_MIRRORING_SHIFT 3 +#define ENA_ADMIN_HOST_INFO_RX_BUF_MIRRORING_MASK BIT(3) #define ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_SHIFT 4 #define ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_MASK BIT(4) @@ -1652,14 +1649,14 @@ static inline void set_ena_admin_host_info_interrupt_moderation(struct ena_admin p->driver_supported_features |= (val << ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_SHIFT) & ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_MASK; } -static inline uint32_t get_ena_admin_host_info_map_rx_buf_bidirectional(const struct ena_admin_host_info *p) +static inline uint32_t get_ena_admin_host_info_rx_buf_mirroring(const struct ena_admin_host_info *p) { - return (p->driver_supported_features & ENA_ADMIN_HOST_INFO_MAP_RX_BUF_BIDIRECTIONAL_MASK) >> ENA_ADMIN_HOST_INFO_MAP_RX_BUF_BIDIRECTIONAL_SHIFT; + return (p->driver_supported_features & ENA_ADMIN_HOST_INFO_RX_BUF_MIRRORING_MASK) >> ENA_ADMIN_HOST_INFO_RX_BUF_MIRRORING_SHIFT; } -static inline void set_ena_admin_host_info_map_rx_buf_bidirectional(struct ena_admin_host_info *p, uint32_t val) +static inline void set_ena_admin_host_info_rx_buf_mirroring(struct ena_admin_host_info *p, uint32_t val) { - p->driver_supported_features |= (val << ENA_ADMIN_HOST_INFO_MAP_RX_BUF_BIDIRECTIONAL_SHIFT) & ENA_ADMIN_HOST_INFO_MAP_RX_BUF_BIDIRECTIONAL_MASK; + p->driver_supported_features |= (val << ENA_ADMIN_HOST_INFO_RX_BUF_MIRRORING_SHIFT) & ENA_ADMIN_HOST_INFO_RX_BUF_MIRRORING_MASK; } static inline uint32_t get_ena_admin_host_info_rss_configurable_function_key(const struct ena_admin_host_info *p) diff --git a/drivers/net/ena/base/ena_eth_com.c b/drivers/net/ena/base/ena_eth_com.c index 701e6721e3..92a9a10a9e 100644 --- a/drivers/net/ena/base/ena_eth_com.c +++ b/drivers/net/ena/base/ena_eth_com.c @@ -331,16 +331,18 @@ static int ena_com_create_and_store_tx_meta_desc(struct ena_com_io_sq *io_sq, *have_meta = true; return ena_com_create_meta(io_sq, ena_meta); - } else if (ena_com_meta_desc_changed(io_sq, ena_tx_ctx)) { + } + + if (ena_com_meta_desc_changed(io_sq, ena_tx_ctx)) { *have_meta = true; /* Cache the meta desc */ memcpy(&io_sq->cached_tx_meta, ena_meta, sizeof(struct ena_com_tx_meta)); return ena_com_create_meta(io_sq, ena_meta); - } else { - *have_meta = false; - return ENA_COM_OK; } + + *have_meta = false; + return ENA_COM_OK; } static void ena_com_rx_set_flags(struct ena_com_io_cq *io_cq, @@ -626,9 +628,9 @@ int ena_com_add_single_rx_desc(struct ena_com_io_sq *io_sq, desc->length = ena_buf->len; desc->ctrl = ENA_ETH_IO_RX_DESC_FIRST_MASK | - ENA_ETH_IO_RX_DESC_LAST_MASK | - (io_sq->phase & ENA_ETH_IO_RX_DESC_PHASE_MASK) | - ENA_ETH_IO_RX_DESC_COMP_REQ_MASK; + ENA_ETH_IO_RX_DESC_LAST_MASK | + ENA_ETH_IO_RX_DESC_COMP_REQ_MASK | + (io_sq->phase & ENA_ETH_IO_RX_DESC_PHASE_MASK); desc->req_id = req_id; diff --git a/drivers/net/ena/ena_ethdev.c b/drivers/net/ena/ena_ethdev.c index f60e843b7f..f1ff4dad36 100644 --- a/drivers/net/ena/ena_ethdev.c +++ b/drivers/net/ena/ena_ethdev.c @@ -2973,7 +2973,7 @@ static void ena_notification(void *data, aenq_e->aenq_common_desc.group, ENA_ADMIN_NOTIFICATION); - switch (aenq_e->aenq_common_desc.syndrom) { + switch (aenq_e->aenq_common_desc.syndrome) { case ENA_ADMIN_UPDATE_HINTS: hints = (struct ena_admin_ena_hw_hints *) (&aenq_e->inline_data_w4); @@ -2981,7 +2981,7 @@ static void ena_notification(void *data, break; default: PMD_DRV_LOG(ERR, "Invalid aenq notification link state %d\n", - aenq_e->aenq_common_desc.syndrom); + aenq_e->aenq_common_desc.syndrome); } } From patchwork Thu May 6 14:25:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Krawczyk X-Patchwork-Id: 93010 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9B60FA0524; Thu, 6 May 2021 16:26:26 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0C13A41128; Thu, 6 May 2021 16:25:51 +0200 (CEST) Received: from mail-lf1-f51.google.com (mail-lf1-f51.google.com [209.85.167.51]) by mails.dpdk.org (Postfix) with ESMTP id 9C53F4111D for ; Thu, 6 May 2021 16:25:49 +0200 (CEST) Received: by mail-lf1-f51.google.com with SMTP id h4so8125237lfv.0 for ; Thu, 06 May 2021 07:25:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2BdPDoLJORRt243MxZJPI0gvo+5S3HZcl0Ng69/Ukg0=; b=XVf/Qi3FLHyxgxx6kjopiy46eX9ATCBf8bpk0qFsu77eomiF+7ead4zaJjphlB5Y2/ gSe90PXjqNhylacMI3hfKBC9Tz9m+MlrQ8772r9nTqMI+Ykd0B+8822d/2MQZC6dweYA G/t3JONGiExsGn+4UNqUBeWKNa4kCQAifrzkuTsMHnqKIxtAfW7lgoE7z9fuwzkq9PmS vxfVqJt6xfbkJ0t022DAf3rxNZEyZhX4XA+09hUA5lhmYdMSTowSCZAUh9k6RcOtBj1X JNann4H6/rRqi2FPHJyYl7bEt54/VLKHOfh7N4nZlLGxmZXCIK7QD43WKSnEmbIJ21U0 Arvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2BdPDoLJORRt243MxZJPI0gvo+5S3HZcl0Ng69/Ukg0=; b=K4sV4dHjvsZ5N799CpPMOdYh7I4pvMJAVdrf9Td/qR+y0bSewnTLpPGWrdbGSFyfjd CpVeK3vwJdp35DPGgQ9MAKdcf/Oi9bVUku9QzAAb+NrvL4LAJzHS3dsT3t4LCay9bY0Q ohiAJZ0e3rq96cj4PTdBefsC9364Kw88dYqMC5bV7YFtPnUtV+zFxWxJolY4lhInclJb CwbjnXkH+n/KxLAKDzT59PuukZLAcicOqp5mRq1Jf//GOB3sLri4GXkqVT9Hclx/bmWu 9JEeGJHiN4rdcURR1ovHQ4CUv9Pyg4v3i/iNi5npmWJhC1OyJjzHwX27fiHVhf48ICKU NuAA== X-Gm-Message-State: AOAM533SuWQGGEk6RwCWA1Nd7KPzLi+R6/0zORphUpoxoiBkbZ+RxGch dqAY6SICsly58brzwtqTKAqVSfYvT+TJVVOt X-Google-Smtp-Source: ABdhPJw0PZIHjYwDkx63hzBjOP1W80jEq7wPoqgjQJIlWaGMcGE37W+BRBVAAGZsll8Tq0uOyF0FEA== X-Received: by 2002:a19:c712:: with SMTP id x18mr3060424lff.589.1620311148881; Thu, 06 May 2021 07:25:48 -0700 (PDT) Received: from DESKTOP-U5LNN3J.localdomain (89-79-189-199.dynamic.chello.pl. [89.79.189.199]) by smtp.gmail.com with ESMTPSA id b40sm892908ljr.101.2021.05.06.07.25.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 May 2021 07:25:48 -0700 (PDT) From: Michal Krawczyk To: dev@dpdk.org Cc: ndagan@amazon.com, gtzalik@amazon.com, igorch@amazon.com, upstream@semihalf.com, Michal Krawczyk Date: Thu, 6 May 2021 16:25:09 +0200 Message-Id: <20210506142526.28245-6-mk@semihalf.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210506142526.28245-1-mk@semihalf.com> References: <20210505073348.6394-1-mk@semihalf.com> <20210506142526.28245-1-mk@semihalf.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v3 05/22] net/ena/base: fix issues from the static code scan X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" To silence error messages from the static code analysis, make the type conversions explicit where they're intended. Also fix the type for the DMA width value. Fixes: 99ecfbf845b3 ("ena: import communication layer") Signed-off-by: Michal Krawczyk Reviewed-by: Igor Chauskin Reviewed-by: Guy Tzalik --- drivers/net/ena/base/ena_com.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/net/ena/base/ena_com.c b/drivers/net/ena/base/ena_com.c index 9dc9f280c4..0cdeb1a2d9 100644 --- a/drivers/net/ena/base/ena_com.c +++ b/drivers/net/ena/base/ena_com.c @@ -1382,7 +1382,7 @@ int ena_com_execute_admin_command(struct ena_com_admin_queue *admin_queue, "Failed to submit command [%ld]\n", PTR_ERR(comp_ctx)); - return PTR_ERR(comp_ctx); + return (int)PTR_ERR(comp_ctx); } ret = ena_com_wait_and_process_admin_cq(comp_ctx, admin_queue); @@ -1602,7 +1602,7 @@ int ena_com_set_aenq_config(struct ena_com_dev *ena_dev, u32 groups_flag) int ena_com_get_dma_width(struct ena_com_dev *ena_dev) { u32 caps = ena_com_reg_bar_read32(ena_dev, ENA_REGS_CAPS_OFF); - int width; + u32 width; if (unlikely(caps == ENA_MMIO_READ_TIMEOUT)) { ena_trc_err(ena_dev, "Reg read timeout occurred\n"); @@ -2280,7 +2280,7 @@ int ena_com_set_dev_mtu(struct ena_com_dev *ena_dev, int mtu) cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE; cmd.aq_common_descriptor.flags = 0; cmd.feat_common.feature_id = ENA_ADMIN_MTU; - cmd.u.mtu.mtu = mtu; + cmd.u.mtu.mtu = (u32)mtu; ret = ena_com_execute_admin_command(admin_queue, (struct ena_admin_aq_entry *)&cmd, @@ -2691,7 +2691,7 @@ int ena_com_indirect_table_set(struct ena_com_dev *ena_dev) return ret; } - cmd.control_buffer.length = (1ULL << rss->tbl_log_size) * + cmd.control_buffer.length = (u32)(1ULL << rss->tbl_log_size) * sizeof(struct ena_admin_rss_ind_table_entry); ret = ena_com_execute_admin_command(admin_queue, @@ -2713,7 +2713,7 @@ int ena_com_indirect_table_get(struct ena_com_dev *ena_dev, u32 *ind_tbl) u32 tbl_size; int i, rc; - tbl_size = (1ULL << rss->tbl_log_size) * + tbl_size = (u32)(1ULL << rss->tbl_log_size) * sizeof(struct ena_admin_rss_ind_table_entry); rc = ena_com_get_feature_ex(ena_dev, &get_resp, From patchwork Thu May 6 14:25:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Krawczyk X-Patchwork-Id: 93011 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 6646FA0524; Thu, 6 May 2021 16:26:34 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 48B464112C; Thu, 6 May 2021 16:25:53 +0200 (CEST) Received: from mail-lf1-f44.google.com (mail-lf1-f44.google.com [209.85.167.44]) by mails.dpdk.org (Postfix) with ESMTP id 082D941127 for ; Thu, 6 May 2021 16:25:51 +0200 (CEST) Received: by mail-lf1-f44.google.com with SMTP id x20so8077122lfu.6 for ; Thu, 06 May 2021 07:25:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=tULt3E1XAtUcgcortfM3qcqYzItJQ8ZfzTHXKhIBhSk=; b=Kcn3Xil2nzASvskd3OCDIEeHfKyDLvlsL5qUK0MmY68N/XZYONreehWpJOah/bA8nA xdeca35Ks4NuoE3K03lQeh0FMCBLET8IVsm4hxsV5MPKfd0nN8NjDfYKRAwB11Xs4eYY mLM0tEZrdILMFFa3KFgnwmEcDr4mIWJPPeeYYMc8DUl5M7TrReyyzVU9mQb2ATn3X7oc uCvAuoDk5EkYaKfymk5kM7F47+JgX9QVS9t+9qT3TOMVsJ8y5bdKsLMmpX9Nf71vqzVh 2skjOhVGpax+NGuyBhiiCe4ffxyPxdefTB0wcYsd1WKHR1H9lMRSjCfk8d8q4MiL9Pyq EyFA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tULt3E1XAtUcgcortfM3qcqYzItJQ8ZfzTHXKhIBhSk=; b=FF04jzl3OSjZeY9G5nUweR4C4cnq/gPaMLE7u+rjaay8RPPK0t5vb4DWejq/KABgqn d4seITm+3PPQRl5si9WgB3m4jZ9RhYELMmiiO38jIPKiDLJM7Fw8AE5Y6/AooLEiqKe/ toI67ERR9CjtLGB1INEs9g2OYo6tRI/4FeT2BS+0eoUiNhKSz7I4awaQyn98rcycwIhe NvqaMT2weQIrrlAhdvQUsTNq4OImgaMpuz5E3GbIjQUDbxKHa5d3ll7g+W7gvbZlgWvB u8zmGdBIS7RuCLMuclpcBr7X6kvtqo3cydAvmpM371GNw0kvnROSZiwlidunEid0EkY8 lgbQ== X-Gm-Message-State: AOAM531FDHDoz8Ly8R0k50mi1IGe1I/OVU2+CHxitYOmmapdCQp0q1nn K4tTkIsr8WO27ZSMuCEUSg4h2nGv7yMUFoyu X-Google-Smtp-Source: ABdhPJy1N51TAjINsLXGdxpPHtn/PkE4bglGnGQopH9UDFshPFWIHU4Y3hBwSD/PhGhnuHxftUj43A== X-Received: by 2002:a05:6512:3b22:: with SMTP id f34mr3002748lfv.361.1620311150277; Thu, 06 May 2021 07:25:50 -0700 (PDT) Received: from DESKTOP-U5LNN3J.localdomain (89-79-189-199.dynamic.chello.pl. [89.79.189.199]) by smtp.gmail.com with ESMTPSA id b40sm892908ljr.101.2021.05.06.07.25.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 May 2021 07:25:49 -0700 (PDT) From: Michal Krawczyk To: dev@dpdk.org Cc: ndagan@amazon.com, gtzalik@amazon.com, igorch@amazon.com, upstream@semihalf.com, Michal Krawczyk Date: Thu, 6 May 2021 16:25:10 +0200 Message-Id: <20210506142526.28245-7-mk@semihalf.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210506142526.28245-1-mk@semihalf.com> References: <20210505073348.6394-1-mk@semihalf.com> <20210506142526.28245-1-mk@semihalf.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v3 06/22] net/ena/base: destroy multiple "wait events" X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Although the ENA DPDK PMD doesn't have to perform any actions for destroying the wait event, some other platforms have to. The macro "ENA_WAIT_EVENT_DESTROY" was renamed to "ENA_WAIT_EVENTS_DESTROY" and also whole implementation responsible for that was moved to a separate function for better readability. Fixes: 3adcba9a8987 ("net/ena: update HAL to the newer version") Signed-off-by: Michal Krawczyk Reviewed-by: Igor Chauskin Reviewed-by: Guy Tzalik --- drivers/net/ena/base/ena_com.c | 24 +++++++++++++++++------- drivers/net/ena/base/ena_plat_dpdk.h | 4 ++-- 2 files changed, 19 insertions(+), 9 deletions(-) diff --git a/drivers/net/ena/base/ena_com.c b/drivers/net/ena/base/ena_com.c index 0cdeb1a2d9..d025c9cee1 100644 --- a/drivers/net/ena/base/ena_com.c +++ b/drivers/net/ena/base/ena_com.c @@ -1671,6 +1671,22 @@ int ena_com_validate_version(struct ena_com_dev *ena_dev) return 0; } +static void +ena_com_free_ena_admin_queue_comp_ctx(struct ena_com_dev *ena_dev, + struct ena_com_admin_queue *admin_queue) + +{ + if (!admin_queue->comp_ctx) + return; + + ENA_WAIT_EVENTS_DESTROY(admin_queue); + ENA_MEM_FREE(ena_dev->dmadev, + admin_queue->comp_ctx, + (admin_queue->q_depth * sizeof(struct ena_comp_ctx))); + + admin_queue->comp_ctx = NULL; +} + void ena_com_admin_destroy(struct ena_com_dev *ena_dev) { struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; @@ -1679,14 +1695,8 @@ void ena_com_admin_destroy(struct ena_com_dev *ena_dev) struct ena_com_aenq *aenq = &ena_dev->aenq; u16 size; - if (admin_queue->comp_ctx) { - ENA_WAIT_EVENT_DESTROY(admin_queue->comp_ctx->wait_event); - ENA_MEM_FREE(ena_dev->dmadev, - admin_queue->comp_ctx, - (admin_queue->q_depth * sizeof(struct ena_comp_ctx))); - } + ena_com_free_ena_admin_queue_comp_ctx(ena_dev, admin_queue); - admin_queue->comp_ctx = NULL; size = ADMIN_SQ_SIZE(admin_queue->q_depth); if (sq->entries) ENA_MEM_FREE_COHERENT(ena_dev->dmadev, size, sq->entries, diff --git a/drivers/net/ena/base/ena_plat_dpdk.h b/drivers/net/ena/base/ena_plat_dpdk.h index 231d44e0e0..ad7b07b374 100644 --- a/drivers/net/ena/base/ena_plat_dpdk.h +++ b/drivers/net/ena/base/ena_plat_dpdk.h @@ -166,7 +166,7 @@ extern int ena_logtype_com; #define ENA_WAIT_EVENT_SIGNAL(waitevent) pthread_cond_signal(&waitevent.cond) /* pthread condition doesn't need to be rearmed after usage */ #define ENA_WAIT_EVENT_CLEAR(...) -#define ENA_WAIT_EVENT_DESTROY(waitqueue) ((void)(waitqueue)) +#define ENA_WAIT_EVENT_DESTROY(admin_queue) ((void)(admin_queue)) #define ena_wait_event_t ena_wait_queue_t #define ENA_MIGHT_SLEEP() @@ -298,7 +298,7 @@ extern rte_atomic32_t ena_alloc_cnt; #define ENA_TIME_EXPIRE(timeout) (timeout < rte_get_timer_cycles()) #define ENA_GET_SYSTEM_TIMEOUT(timeout_us) \ (timeout_us * rte_get_timer_hz() / 1000000 + rte_get_timer_cycles()) -#define ENA_WAIT_EVENT_DESTROY(waitqueue) ((void)(waitqueue)) +#define ENA_WAIT_EVENTS_DESTROY(waitqueue) ((void)(waitqueue)) #ifndef READ_ONCE #define READ_ONCE(var) (*((volatile typeof(var) *)(&(var)))) From patchwork Thu May 6 14:25:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Krawczyk X-Patchwork-Id: 93012 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8DD45A0524; Thu, 6 May 2021 16:26:41 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 7F31441135; Thu, 6 May 2021 16:25:54 +0200 (CEST) Received: from mail-lf1-f42.google.com (mail-lf1-f42.google.com [209.85.167.42]) by mails.dpdk.org (Postfix) with ESMTP id 4AE884112C for ; Thu, 6 May 2021 16:25:52 +0200 (CEST) Received: by mail-lf1-f42.google.com with SMTP id z9so8032524lfu.8 for ; Thu, 06 May 2021 07:25:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Sw5i2yLiKvMGYwLKt0qDxjPwKtISh+9sE1hkQur5jXg=; b=qxBV62xh81ddvhHAUZds8iwWpzPqgMImwSnm5rk7PBJ81FFeA7xOBcrTwlqJ9dciWp JUXkTI40mtLA9z2PtiHAVFGYqQdkjBcmJUmUJYDubTbv0K94Hy9wtB9FpOUh9+8XXpMr JR66BbW4vzLpsJjIEsh7ORh1D03jknznWFkantuVBU5McCmlCFRFuA9i/Wo1BYF891Gt UNvXasE/RjhrqMXt00CQJvrWIgOa1wjRTZa/RrSomtfg9gJ4L5U7cQjC9qgJdY6f+787 u2pBwTnGvUpMpm6vbKIfkeTU3dbKxJHb5rEywW6VJ2bB+HjZXA1eWCSvTSje+zxNtXnt SQsQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Sw5i2yLiKvMGYwLKt0qDxjPwKtISh+9sE1hkQur5jXg=; b=VTuYKA4j/XbCON6CstY9tfWftAvK6ypk0BwOSpAhxtOlHO+BjU9rZ6UGou7FLCf2Cq skwYVHcTAeATYBHvFWwjd2z6QuP3X6XKsB70xBrKJtE0mzkhT/XNob2Vszt88G8Pf/39 RlNM40Kg4EVDgVbaF83ai5YaKJdIMsrhzpJG3yBCEjo0lLDWiJRboOmtT4kZF6AD9Mt2 aHudBGM1cxhVn6VebfXXJ3zHI/8fuTxMgC44Fy2jUpeeJA2c79gxjyc2zBhqEFj3IiNu PfO2LU1NnGgA3v+J7/d2tYzWW9C7TVLoKEAHeZyXNC6wkpb2pO3bDE9VgrGKD2wblNgz lMBw== X-Gm-Message-State: AOAM531fH/KXSBTYmIgy+wPahiMlaZteXiNAzlFjCxpxy+1CDMFa2fda /AST5bnT8rznEw34sb4ZqdotY9Wr/3hotuHD X-Google-Smtp-Source: ABdhPJxa+ZbQea4klYHItZ2l6DnUkv77866jvseWBlGk/s33qayQn2a8Kp9SAFusNvjlWBCxzP0gPg== X-Received: by 2002:ac2:4a7b:: with SMTP id q27mr3254243lfp.362.1620311151631; Thu, 06 May 2021 07:25:51 -0700 (PDT) Received: from DESKTOP-U5LNN3J.localdomain (89-79-189-199.dynamic.chello.pl. [89.79.189.199]) by smtp.gmail.com with ESMTPSA id b40sm892908ljr.101.2021.05.06.07.25.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 May 2021 07:25:50 -0700 (PDT) From: Michal Krawczyk To: dev@dpdk.org Cc: ndagan@amazon.com, gtzalik@amazon.com, igorch@amazon.com, upstream@semihalf.com, Michal Krawczyk , Amit Bernstein Date: Thu, 6 May 2021 16:25:11 +0200 Message-Id: <20210506142526.28245-8-mk@semihalf.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210506142526.28245-1-mk@semihalf.com> References: <20210505073348.6394-1-mk@semihalf.com> <20210506142526.28245-1-mk@semihalf.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v3 07/22] net/ena/base: remove indir table from ENA feat ctx X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The RSS indirection table shouldn't be included as a part of the device features context. If the driver has to acquire it, it can be done using the separate API whenever the RSS configuration is needed. Signed-off-by: Michal Krawczyk Reviewed-by: Igor Chauskin Reviewed-by: Amit Bernstein --- drivers/net/ena/base/ena_com.c | 11 ----------- drivers/net/ena/base/ena_com.h | 1 - 2 files changed, 12 deletions(-) diff --git a/drivers/net/ena/base/ena_com.c b/drivers/net/ena/base/ena_com.c index d025c9cee1..5ca36ab6d9 100644 --- a/drivers/net/ena/base/ena_com.c +++ b/drivers/net/ena/base/ena_com.c @@ -2054,17 +2054,6 @@ int ena_com_get_dev_attr_feat(struct ena_com_dev *ena_dev, else return rc; - rc = ena_com_get_feature(ena_dev, &get_resp, - ENA_ADMIN_RSS_INDIRECTION_TABLE_CONFIG, 0); - if (!rc) - memcpy(&get_feat_ctx->ind_table, &get_resp.u.ind_table, - sizeof(get_resp.u.ind_table)); - else if (rc == ENA_COM_UNSUPPORTED) - memset(&get_feat_ctx->ind_table, 0x0, - sizeof(get_feat_ctx->ind_table)); - else - return rc; - return 0; } diff --git a/drivers/net/ena/base/ena_com.h b/drivers/net/ena/base/ena_com.h index cd116e90e6..ca84e2e8bc 100644 --- a/drivers/net/ena/base/ena_com.h +++ b/drivers/net/ena/base/ena_com.h @@ -338,7 +338,6 @@ struct ena_com_dev_get_features_ctx { struct ena_admin_feature_offload_desc offload; struct ena_admin_ena_hw_hints hw_hints; struct ena_admin_feature_llq_desc llq; - struct ena_admin_feature_rss_ind_table ind_table; }; struct ena_com_create_io_ctx { From patchwork Thu May 6 14:25:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Krawczyk X-Patchwork-Id: 93013 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 22B73A0524; Thu, 6 May 2021 16:26:50 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 4FE6941142; Thu, 6 May 2021 16:25:56 +0200 (CEST) Received: from mail-lf1-f54.google.com (mail-lf1-f54.google.com [209.85.167.54]) by mails.dpdk.org (Postfix) with ESMTP id B1476410F9 for ; Thu, 6 May 2021 16:25:53 +0200 (CEST) Received: by mail-lf1-f54.google.com with SMTP id c11so8041680lfi.9 for ; Thu, 06 May 2021 07:25:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OftqcSoM7GSchnu3STuHtE/G9PoTgF936ml4WKhFBT4=; b=vpD1MjZ9fnVhGXGonUXHSSxK+Qt5pqpyK1ANwRMhBw3VDqv9+tFbA3MOxuHc5z5XAs JzeBsc+R814BXhiP5s26VEYIpFWvakzcxn2dSBSTzOv73MAcoI0Vli9dx1NLJMFTmTm6 1+4CZLKS2ZPO0TgJQ2gKrBRwdUVGuxZc4Dt/CCBVSDJaRpJKM44lrYyBehD/aMvppDei yMH9eSAg33hRnI8PdpkmrOjU0UG7rtmc2qZ3DgOSfx15Pv/5KXMA5CkeaYwpXJf83HAn fG5DZGVyon9VFG8/2uc2p8WLLD81riWbbo98AeP8Q4/dhjZi+Yl42lnIslwZ9nHnqXNN 7j3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OftqcSoM7GSchnu3STuHtE/G9PoTgF936ml4WKhFBT4=; b=Twl4oNZcq5msuCPFHzaojNyWWHwz7tdD+cQkkacqIL1YCfyrUBc8QgdYwYZI1olyJn oXNWtxysayYFO7BB54i2xZWM4NY41OS6nN8bue2hKtrvjfmr8+Arj6xGhaS4i5Hx8agU Lizisb91QGwHyxOsKmu8t8xd5nK9o4+aLgW4resrTnEfYxXR7QBJ+JMxCZygJnZhlSBT SHFUrRXQW2MixtQbdqjI45iD3MCikqSJqjumY3jAjssPfSDRZrp92CiSU0/URJhFWFkS lAI2CvBP94UPktOWkM01ucdSCbra9IqXMxcLHAbZeYpP9upgQa3L+beF6CgwhWOcONg0 acag== X-Gm-Message-State: AOAM530LaZcXsXS91TIW33B9ybB4xDV28ZFUmI9v0Tb6mwbCOvMCUHls ks5MUNOqdnh/YslGmfWb54YDC7AGAVnxYAwy X-Google-Smtp-Source: ABdhPJx9bbmdOK1BDTU0MCXepcikWQHJmtw6s9/IMmgb0BMnvueBCJvuxxOtl2uyuApTIcM/cgFqEA== X-Received: by 2002:ac2:4198:: with SMTP id z24mr3131906lfh.335.1620311153023; Thu, 06 May 2021 07:25:53 -0700 (PDT) Received: from DESKTOP-U5LNN3J.localdomain (89-79-189-199.dynamic.chello.pl. [89.79.189.199]) by smtp.gmail.com with ESMTPSA id b40sm892908ljr.101.2021.05.06.07.25.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 May 2021 07:25:52 -0700 (PDT) From: Michal Krawczyk To: dev@dpdk.org Cc: ndagan@amazon.com, gtzalik@amazon.com, igorch@amazon.com, upstream@semihalf.com, Michal Krawczyk , Shay Agroskin Date: Thu, 6 May 2021 16:25:12 +0200 Message-Id: <20210506142526.28245-9-mk@semihalf.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210506142526.28245-1-mk@semihalf.com> References: <20210505073348.6394-1-mk@semihalf.com> <20210506142526.28245-1-mk@semihalf.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v3 08/22] net/ena/base: remove mutable RSS from the host info X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This feature wasn't used by any of the drivers. Because of that, it was removed. Signed-off-by: Michal Krawczyk Reviewed-by: Igor Chauskin Reviewed-by: Shay Agroskin --- drivers/net/ena/base/ena_defs/ena_admin_defs.h | 13 +------------ 1 file changed, 1 insertion(+), 12 deletions(-) diff --git a/drivers/net/ena/base/ena_defs/ena_admin_defs.h b/drivers/net/ena/base/ena_defs/ena_admin_defs.h index 40c2db717c..56768e1a1b 100644 --- a/drivers/net/ena/base/ena_defs/ena_admin_defs.h +++ b/drivers/net/ena/base/ena_defs/ena_admin_defs.h @@ -866,7 +866,7 @@ struct ena_admin_host_info { uint16_t reserved; - /* 0 : mutable_rss_table_size + /* 0 : reserved * 1 : rx_offset * 2 : interrupt_moderation * 3 : rx_buf_mirroring @@ -1189,7 +1189,6 @@ struct ena_admin_ena_mmio_req_read_less_resp { #define ENA_ADMIN_HOST_INFO_DEVICE_MASK GENMASK(7, 3) #define ENA_ADMIN_HOST_INFO_BUS_SHIFT 8 #define ENA_ADMIN_HOST_INFO_BUS_MASK GENMASK(15, 8) -#define ENA_ADMIN_HOST_INFO_MUTABLE_RSS_TABLE_SIZE_MASK BIT(0) #define ENA_ADMIN_HOST_INFO_RX_OFFSET_SHIFT 1 #define ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK BIT(1) #define ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_SHIFT 2 @@ -1619,16 +1618,6 @@ static inline void set_ena_admin_host_info_bus(struct ena_admin_host_info *p, ui p->bdf |= (val << ENA_ADMIN_HOST_INFO_BUS_SHIFT) & ENA_ADMIN_HOST_INFO_BUS_MASK; } -static inline uint32_t get_ena_admin_host_info_mutable_rss_table_size(const struct ena_admin_host_info *p) -{ - return p->driver_supported_features & ENA_ADMIN_HOST_INFO_MUTABLE_RSS_TABLE_SIZE_MASK; -} - -static inline void set_ena_admin_host_info_mutable_rss_table_size(struct ena_admin_host_info *p, uint32_t val) -{ - p->driver_supported_features |= val & ENA_ADMIN_HOST_INFO_MUTABLE_RSS_TABLE_SIZE_MASK; -} - static inline uint32_t get_ena_admin_host_info_rx_offset(const struct ena_admin_host_info *p) { return (p->driver_supported_features & ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK) >> ENA_ADMIN_HOST_INFO_RX_OFFSET_SHIFT; From patchwork Thu May 6 14:25:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Krawczyk X-Patchwork-Id: 93014 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 70017A0524; Thu, 6 May 2021 16:26:57 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 92D5F41148; Thu, 6 May 2021 16:25:57 +0200 (CEST) Received: from mail-lj1-f177.google.com (mail-lj1-f177.google.com [209.85.208.177]) by mails.dpdk.org (Postfix) with ESMTP id ED29341139 for ; Thu, 6 May 2021 16:25:54 +0200 (CEST) Received: by mail-lj1-f177.google.com with SMTP id v6so7299433ljj.5 for ; Thu, 06 May 2021 07:25:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1m9OWoWQdkUAjlrBF6vlpG1kMqz+PhogpV2ztlm90oo=; b=s8j4zQlUkiVOfT6DZyJYry1i2dQgW6i6sIJCKy4f6bSYzovq4cFPcCXog3l02Yq0VJ Hn1WsiwopdP+MJQ/+VBC4WTa+HMjxCybADDr5zCkWJGSJh5wg5qhVgGggUsWsZDX96VD J7HX1RxnCU3iehw+UOs7GgRBiTowMkL6wC6mPZPaP59whtdy3nbOSO1fUU6mNfdNZJm6 tA75mfMuz93JoZIGixRj0HIzzV5gPRzyOBZZzh2xTjsLGsOx+61shH3J6Z833O2dwWL0 VtNcXJrQFZT4/IXolt6U+aTPfUHJUH/779W12hJzv88tVReWmYMlw9+2vggIIppokaib qMRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1m9OWoWQdkUAjlrBF6vlpG1kMqz+PhogpV2ztlm90oo=; b=njH5EhIcjez152oD0pZdfnafWjsAdJGR+hGHg0VKeFgQfqbA943sssaSUm83INkqi2 w3d/OMmVXwKWOhpPrbnan5NP8vNsUCb2B1gAzqgzA/GkhI4Rf6QSz48LQz2ooi9zOFdm 0NSh45Iwz3OLK2mY2V0Tu/fH5TBfi6n2jIZhntA1+ampI//nd04Lpkho/jAhGSddv/H3 y1NoC5g0XXY0ph8V7HOBRZZ0eiJAHzOaioRP0pUZu/s6UTFpxFrZorb/75uX8nwHP0R9 pPz2SB1N3sfEUCp3nNrUVUZdoNFY4DawlSxvcCO8O4cvabSybZVn04QqUA2dgBjBuVal AIZA== X-Gm-Message-State: AOAM533l9Cm1G/FaXaGFQBWe4hAqdCO5n5Knw+xCR+GUWqMMa3U6YTXN HxoEEi+oBwPb3h83+Fmqa7zvoL6ou/0EZfcT X-Google-Smtp-Source: ABdhPJwo4eqsV/jv3lIkxJpwYIiwCpufL2OZ3VEEc5ORgmGUxhDpLgQAutGH0htu5Qh1kT/kQNw+7g== X-Received: by 2002:a2e:8596:: with SMTP id b22mr3602326lji.482.1620311154297; Thu, 06 May 2021 07:25:54 -0700 (PDT) Received: from DESKTOP-U5LNN3J.localdomain (89-79-189-199.dynamic.chello.pl. [89.79.189.199]) by smtp.gmail.com with ESMTPSA id b40sm892908ljr.101.2021.05.06.07.25.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 May 2021 07:25:53 -0700 (PDT) From: Michal Krawczyk To: dev@dpdk.org Cc: ndagan@amazon.com, gtzalik@amazon.com, igorch@amazon.com, upstream@semihalf.com, Michal Krawczyk , Amit Bernstein Date: Thu, 6 May 2021 16:25:13 +0200 Message-Id: <20210506142526.28245-10-mk@semihalf.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210506142526.28245-1-mk@semihalf.com> References: <20210505073348.6394-1-mk@semihalf.com> <20210506142526.28245-1-mk@semihalf.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v3 09/22] net/ena/base: update generation date and commit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The current ena_com version was generated on 18.09.2020. Signed-off-by: Michal Krawczyk Reviewed-by: Igor Chauskin Reviewed-by: Amit Bernstein --- drivers/net/ena/base/ena_defs/ena_gen_info.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/ena/base/ena_defs/ena_gen_info.h b/drivers/net/ena/base/ena_defs/ena_gen_info.h index 54bbfda11f..49895108d5 100644 --- a/drivers/net/ena/base/ena_defs/ena_gen_info.h +++ b/drivers/net/ena/base/ena_defs/ena_gen_info.h @@ -2,5 +2,5 @@ * Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates. * All rights reserved. */ -#define ENA_GEN_DATE "Sun Apr 26 13:45:21 DST 2020" -#define ENA_GEN_COMMIT "37aa7c3" +#define ENA_GEN_DATE "Fri Sep 18 17:09:00 IDT 2020" +#define ENA_GEN_COMMIT "0f80d82" From patchwork Thu May 6 14:25:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Krawczyk X-Patchwork-Id: 93015 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0F40BA0524; Thu, 6 May 2021 16:27:04 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id DE9AB4114F; Thu, 6 May 2021 16:25:58 +0200 (CEST) Received: from mail-lf1-f53.google.com (mail-lf1-f53.google.com [209.85.167.53]) by mails.dpdk.org (Postfix) with ESMTP id 501A441143 for ; Thu, 6 May 2021 16:25:56 +0200 (CEST) Received: by mail-lf1-f53.google.com with SMTP id n138so8077925lfa.3 for ; Thu, 06 May 2021 07:25:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6FK++eNy/5mi2hlIqjhjaECSz4j0i7x/XUmiyNUScFs=; b=mo1bfIizS8g6Gnuhu9Bbggy7TL4QAjH/0YZdCKs+4kNEhqiVfgCXJGOKGb7zbj15HY 8u4GHTwX6y+pK/M6rUjb7qAupnRZCJySzbf75ZY4y56tGIzDShpeg5yyhAyQjOOEX9Nk oS7uXnvBk4kCSY+fxlnIcYyq82kbztnyeyAiwHeseMhVkjJyGyKj+j/CPvSaCtROJ4eE 5poctb5Zw7u0QTsd79KxDXKtLueoqE6+d8Ta4uVHHgTNLssQ7hyyJZVzv4xuVd4jPfIt LsGOfz7YoXAxfjhDu9Adp4DwmoJN3r8BZd9kpbxxTl+3s+0d8GZAqiFXEzimyb19yvz+ Dbmg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6FK++eNy/5mi2hlIqjhjaECSz4j0i7x/XUmiyNUScFs=; b=sb3/PmXqPE4dlIVpbWFadPYIXza9xCiozbuRDBwhq0jXOkhagufyOVdmXjqg0FIONG ID5oUZJ2B8IkKgqRI59J450q2p4/J0giAc68/UieZ+VNrrNthdov8p9W0WBrNoLoQFhb keQWdALoVMY6WOpocj/yr4/YGSjI21xJFg2cH3Js6WPJBmnZ4MKDaZsszuL4rtAEq7xz RnX8P91xjCisvWnXQ3IC6LCMbChQ7N4rr9dDHvwWeiQ98jRK+b7/0jjZKX2HCoea5woR EiM+OMkTIs9QRZsD6xcqSbl4wxOFOkIIo0G3xsRkLloAc3WsqlR933dAZtHNZM2lTrbT Tm/Q== X-Gm-Message-State: AOAM5321l0EcVk5lMLr3DQLMHPWAzGmo1LZkPwdLGghyC/wjXxzelChj CEq3V6sQFSlNl/DlR0gvtMErNkbfDq56/2bH X-Google-Smtp-Source: ABdhPJyx98SBR+M/2ujcJ+6IyRu25saWxr5Es8JxbkVTVnYht6ZUdsK+O6sbG/K+bt4U/qrk+Q/JnQ== X-Received: by 2002:a19:9150:: with SMTP id y16mr3095362lfj.396.1620311155593; Thu, 06 May 2021 07:25:55 -0700 (PDT) Received: from DESKTOP-U5LNN3J.localdomain (89-79-189-199.dynamic.chello.pl. [89.79.189.199]) by smtp.gmail.com with ESMTPSA id b40sm892908ljr.101.2021.05.06.07.25.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 May 2021 07:25:54 -0700 (PDT) From: Michal Krawczyk To: dev@dpdk.org Cc: ndagan@amazon.com, gtzalik@amazon.com, igorch@amazon.com, upstream@semihalf.com, Michal Krawczyk , Amit Bernstein Date: Thu, 6 May 2021 16:25:14 +0200 Message-Id: <20210506142526.28245-11-mk@semihalf.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210506142526.28245-1-mk@semihalf.com> References: <20210505073348.6394-1-mk@semihalf.com> <20210506142526.28245-1-mk@semihalf.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v3 10/22] net/ena/base: use rte_prefetch0_write X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" As in the v20.11 rte_prefetch0_write API was added, it should be used in the platform file for the definition of the macro prefetchw, instead of using simply prefetch0. Signed-off-by: Michal Krawczyk Reviewed-by: Igor Chauskin Reviewed-by: Amit Bernstein --- drivers/net/ena/base/ena_plat_dpdk.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ena/base/ena_plat_dpdk.h b/drivers/net/ena/base/ena_plat_dpdk.h index ad7b07b374..c6103e3721 100644 --- a/drivers/net/ena/base/ena_plat_dpdk.h +++ b/drivers/net/ena/base/ena_plat_dpdk.h @@ -290,7 +290,7 @@ extern rte_atomic32_t ena_alloc_cnt; #define might_sleep() #define prefetch(x) rte_prefetch0(x) -#define prefetchw(x) prefetch(x) +#define prefetchw(x) rte_prefetch0_write(x) #define lower_32_bits(x) ((uint32_t)(x)) #define upper_32_bits(x) ((uint32_t)(((x) >> 16) >> 16)) From patchwork Thu May 6 14:25:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Krawczyk X-Patchwork-Id: 93016 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 599FBA0524; Thu, 6 May 2021 16:27:11 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 34E9741155; Thu, 6 May 2021 16:26:00 +0200 (CEST) Received: from mail-lf1-f42.google.com (mail-lf1-f42.google.com [209.85.167.42]) by mails.dpdk.org (Postfix) with ESMTP id C50C74114D for ; Thu, 6 May 2021 16:25:57 +0200 (CEST) Received: by mail-lf1-f42.google.com with SMTP id c11so8042007lfi.9 for ; Thu, 06 May 2021 07:25:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+TfstwEBfR3Juxchy73ZAe3RXg6CAIaKlyFDAXTCKLg=; b=Xdoh0NXQTw8lXHI7uKSJePum0FbA2IZ5R27+v7A4uIKB9vsVTjXQ2jBwyQjpC3v71r 9i4tkG5g8lZBNq3YZ8p5kH84uUYNgKAxXs6fCSjEp4/aN95GM5eSdsBopQ8qvD+B8cfX I+0CEn0avDK9KpwMMEd+mOv3EO29I46wiCnwMjQ6ZsH1DH7eDAEiX6mxe3Jg8UrfVvil vPDGIhjLu4g9N8nMGV4oToFPmb1Wa+haqaNgrQKZK358AkmJmN/DlD88MKjh7JxzTI9r 3ysSN0KyFhcyxycn9U7LNiqW/ZkXvJZAKJHJqdgcy0AKLKSCNCG6eCORrrEj7rLTwvll x+sQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+TfstwEBfR3Juxchy73ZAe3RXg6CAIaKlyFDAXTCKLg=; b=jP8dK8FqXzHOnVAfYQlME1Tmxu9Rphj5uaEcyW0OY+/E5kXYYYAf1C1TQHqdklIlbb t2rND7Il+FSV/koCYegLui+w/l3spG0EhchmScYj5ve4y5Eb1UE+QPsqwMHz9mStFR6/ P0hJZ4RA79LKM9ieDYETNyGZMymbJ+VmshylDfJbsektU/5aCR7QxPYr5Qg/DimmsvGn lEXvr6YU8/V1zmfcslqeTG5qH75jSGIJYW0hGGOHStUwC3cy3w/WuVcBEvynug/hkn3n 0N8VmxhcbW49EToScdeq7Vsi8N2c4km3fd71DFbe9e955cqw9stseutb4hT+cG/jc9OD eVkQ== X-Gm-Message-State: AOAM53249/v3jxKpvDU4EQzyfRnbD+MxjQNG9Agnv14rOye5aVxEANKH kpkk234gv2eDR/JqehkmhKN80fVLMGNDcnW3 X-Google-Smtp-Source: ABdhPJwrOEwi1IoJsr6GqAqeIGiZ9w37nCp7I22vfblqnpMk//306JQ/Podx7o+e1QPI1aygK9Eq4g== X-Received: by 2002:a05:6512:964:: with SMTP id v4mr3214733lft.464.1620311156944; Thu, 06 May 2021 07:25:56 -0700 (PDT) Received: from DESKTOP-U5LNN3J.localdomain (89-79-189-199.dynamic.chello.pl. [89.79.189.199]) by smtp.gmail.com with ESMTPSA id b40sm892908ljr.101.2021.05.06.07.25.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 May 2021 07:25:56 -0700 (PDT) From: Michal Krawczyk To: dev@dpdk.org Cc: ndagan@amazon.com, gtzalik@amazon.com, igorch@amazon.com, upstream@semihalf.com, Amit Bernstein , Shay Agroskin , Michal Krawczyk Date: Thu, 6 May 2021 16:25:15 +0200 Message-Id: <20210506142526.28245-12-mk@semihalf.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210506142526.28245-1-mk@semihalf.com> References: <20210505073348.6394-1-mk@semihalf.com> <20210506142526.28245-1-mk@semihalf.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v3 11/22] net/ena/base: adjust changes to lastest ena-com X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Amit Bernstein 1. As memzone uses unique names, changed alloc coherent macro to use 64 bit size atomic variable to increase the memzone name space 2. "handle" param name change to be consistent with other macros 3. Variable definition displacement 4. Backslash alignment to column 80 Signed-off-by: Amit Bernstein Reviewed-by: Igor Chauskin Reviewed-by: Shay Agroskin Reviewed-by: Michal Krawczyk --- drivers/net/ena/base/ena_plat_dpdk.h | 244 +++++++++++++-------------- drivers/net/ena/ena_ethdev.c | 2 +- 2 files changed, 115 insertions(+), 131 deletions(-) diff --git a/drivers/net/ena/base/ena_plat_dpdk.h b/drivers/net/ena/base/ena_plat_dpdk.h index c6103e3721..4498d53703 100644 --- a/drivers/net/ena/base/ena_plat_dpdk.h +++ b/drivers/net/ena/base/ena_plat_dpdk.h @@ -34,10 +34,12 @@ typedef uint8_t u8; typedef struct rte_eth_dev ena_netdev; typedef uint64_t dma_addr_t; + #ifndef ETIME #define ETIME ETIMEDOUT #endif +#define ENA_PRIu64 PRIu64 #define ena_atomic32_t rte_atomic32_t #define ena_mem_handle_t const struct rte_memzone * @@ -76,7 +78,7 @@ typedef uint64_t dma_addr_t; #define __iomem #define US_PER_S 1000000 -#define ENA_GET_SYSTEM_USECS() \ +#define ENA_GET_SYSTEM_USECS() \ (rte_get_timer_cycles() * US_PER_S / rte_get_timer_hz()) extern int ena_logtype_com; @@ -95,15 +97,15 @@ extern int ena_logtype_com; #define BIT(nr) (1UL << (nr)) #define BITS_PER_LONG (__SIZEOF_LONG__ * 8) #define GENMASK(h, l) (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h)))) -#define GENMASK_ULL(h, l) (((~0ULL) - (1ULL << (l)) + 1) & \ +#define GENMASK_ULL(h, l) (((~0ULL) - (1ULL << (l)) + 1) & \ (~0ULL >> (BITS_PER_LONG_LONG - 1 - (h)))) #ifdef RTE_LIBRTE_ENA_COM_DEBUG -#define ena_trc_log(dev, level, fmt, arg...) \ - ( \ - ENA_TOUCH(dev), \ - rte_log(RTE_LOG_ ## level, ena_logtype_com, \ - "[ENA_COM: %s]" fmt, __func__, ##arg) \ +#define ena_trc_log(dev, level, fmt, arg...) \ + ( \ + ENA_TOUCH(dev), \ + rte_log(RTE_LOG_ ## level, ena_logtype_com, \ + "[ENA_COM: %s]" fmt, __func__, ##arg) \ ) #define ena_trc_dbg(dev, format, arg...) ena_trc_log(dev, DEBUG, format, ##arg) @@ -117,51 +119,51 @@ extern int ena_logtype_com; #define ena_trc_err(dev, format, arg...) ENA_TOUCH(dev) #endif /* RTE_LIBRTE_ENA_COM_DEBUG */ -#define ENA_WARN(cond, dev, format, arg...) \ - do { \ - if (unlikely(cond)) { \ - ena_trc_err(dev, \ - "Warn failed on %s:%s:%d:" format, \ - __FILE__, __func__, __LINE__, ##arg); \ - } \ +#define ENA_WARN(cond, dev, format, arg...) \ + do { \ + if (unlikely(cond)) { \ + ena_trc_err(dev, \ + "Warn failed on %s:%s:%d:" format, \ + __FILE__, __func__, __LINE__, ##arg); \ + } \ } while (0) /* Spinlock related methods */ #define ena_spinlock_t rte_spinlock_t #define ENA_SPINLOCK_INIT(spinlock) rte_spinlock_init(&spinlock) -#define ENA_SPINLOCK_LOCK(spinlock, flags) \ +#define ENA_SPINLOCK_LOCK(spinlock, flags) \ ({(void)flags; rte_spinlock_lock(&spinlock); }) -#define ENA_SPINLOCK_UNLOCK(spinlock, flags) \ +#define ENA_SPINLOCK_UNLOCK(spinlock, flags) \ ({(void)flags; rte_spinlock_unlock(&(spinlock)); }) #define ENA_SPINLOCK_DESTROY(spinlock) ((void)spinlock) -#define q_waitqueue_t \ - struct { \ - pthread_cond_t cond; \ - pthread_mutex_t mutex; \ +#define q_waitqueue_t \ + struct { \ + pthread_cond_t cond; \ + pthread_mutex_t mutex; \ } #define ena_wait_queue_t q_waitqueue_t -#define ENA_WAIT_EVENT_INIT(waitqueue) \ - do { \ - pthread_mutex_init(&(waitqueue).mutex, NULL); \ - pthread_cond_init(&(waitqueue).cond, NULL); \ +#define ENA_WAIT_EVENT_INIT(waitqueue) \ + do { \ + pthread_mutex_init(&(waitqueue).mutex, NULL); \ + pthread_cond_init(&(waitqueue).cond, NULL); \ } while (0) -#define ENA_WAIT_EVENT_WAIT(waitevent, timeout) \ - do { \ - struct timespec wait; \ - struct timeval now; \ - unsigned long timeout_us; \ - gettimeofday(&now, NULL); \ - wait.tv_sec = now.tv_sec + timeout / 1000000UL; \ - timeout_us = timeout % 1000000UL; \ - wait.tv_nsec = (now.tv_usec + timeout_us) * 1000UL; \ - pthread_mutex_lock(&waitevent.mutex); \ - pthread_cond_timedwait(&waitevent.cond, \ - &waitevent.mutex, &wait); \ - pthread_mutex_unlock(&waitevent.mutex); \ +#define ENA_WAIT_EVENT_WAIT(waitevent, timeout) \ + do { \ + struct timespec wait; \ + struct timeval now; \ + unsigned long timeout_us; \ + gettimeofday(&now, NULL); \ + wait.tv_sec = now.tv_sec + timeout / 1000000UL; \ + timeout_us = timeout % 1000000UL; \ + wait.tv_nsec = (now.tv_usec + timeout_us) * 1000UL; \ + pthread_mutex_lock(&waitevent.mutex); \ + pthread_cond_timedwait(&waitevent.cond, \ + &waitevent.mutex, &wait); \ + pthread_mutex_unlock(&waitevent.mutex); \ } while (0) #define ENA_WAIT_EVENT_SIGNAL(waitevent) pthread_cond_signal(&waitevent.cond) /* pthread condition doesn't need to be rearmed after usage */ @@ -173,104 +175,88 @@ extern int ena_logtype_com; #define ena_time_t uint64_t #define ENA_TIME_EXPIRE(timeout) (timeout < rte_get_timer_cycles()) -#define ENA_GET_SYSTEM_TIMEOUT(timeout_us) \ - (timeout_us * rte_get_timer_hz() / 1000000 + rte_get_timer_cycles()) +#define ENA_GET_SYSTEM_TIMEOUT(timeout_us) \ + (timeout_us * rte_get_timer_hz() / 1000000 + rte_get_timer_cycles()) /* * Each rte_memzone should have unique name. * To satisfy it, count number of allocations and add it to name. */ -extern rte_atomic32_t ena_alloc_cnt; - -#define ENA_MEM_ALLOC_COHERENT_ALIGNED( \ - dmadev, size, virt, phys, handle, alignment) \ - do { \ - const struct rte_memzone *mz = NULL; \ - ENA_TOUCH(dmadev); ENA_TOUCH(handle); \ - if (size > 0) { \ - char z_name[RTE_MEMZONE_NAMESIZE]; \ - snprintf(z_name, sizeof(z_name), \ - "ena_alloc_%d", \ - rte_atomic32_add_return(&ena_alloc_cnt, 1)); \ - mz = rte_memzone_reserve_aligned(z_name, size, \ - SOCKET_ID_ANY, \ - RTE_MEMZONE_IOVA_CONTIG, \ - alignment); \ - handle = mz; \ - } \ - if (mz == NULL) { \ - virt = NULL; \ - phys = 0; \ - } else { \ - memset(mz->addr, 0, size); \ - virt = mz->addr; \ - phys = mz->iova; \ - } \ +extern rte_atomic64_t ena_alloc_cnt; + +#define ENA_MEM_ALLOC_COHERENT_ALIGNED( \ + dmadev, size, virt, phys, mem_handle, alignment) \ + do { \ + const struct rte_memzone *mz = NULL; \ + ENA_TOUCH(dmadev); \ + if (size > 0) { \ + char z_name[RTE_MEMZONE_NAMESIZE]; \ + snprintf(z_name, sizeof(z_name), "ena_alloc_%"PRIi64"",\ + rte_atomic64_add_return(&ena_alloc_cnt, 1)); \ + mz = rte_memzone_reserve_aligned(z_name, size, \ + SOCKET_ID_ANY, RTE_MEMZONE_IOVA_CONTIG,\ + alignment); \ + mem_handle = mz; \ + } \ + if (mz == NULL) { \ + virt = NULL; \ + phys = 0; \ + } else { \ + memset(mz->addr, 0, size); \ + virt = mz->addr; \ + phys = mz->iova; \ + } \ } while (0) -#define ENA_MEM_ALLOC_COHERENT(dmadev, size, virt, phys, handle) \ - ENA_MEM_ALLOC_COHERENT_ALIGNED( \ - dmadev, \ - size, \ - virt, \ - phys, \ - handle, \ - RTE_CACHE_LINE_SIZE) -#define ENA_MEM_FREE_COHERENT(dmadev, size, virt, phys, handle) \ - ({ ENA_TOUCH(size); ENA_TOUCH(phys); \ - ENA_TOUCH(dmadev); \ - rte_memzone_free(handle); }) - -#define ENA_MEM_ALLOC_COHERENT_NODE_ALIGNED( \ - dmadev, size, virt, phys, mem_handle, node, dev_node, alignment) \ - do { \ - const struct rte_memzone *mz = NULL; \ - ENA_TOUCH(dmadev); ENA_TOUCH(dev_node); \ - if (size > 0) { \ - char z_name[RTE_MEMZONE_NAMESIZE]; \ - snprintf(z_name, sizeof(z_name), \ - "ena_alloc_%d", \ - rte_atomic32_add_return(&ena_alloc_cnt, 1)); \ - mz = rte_memzone_reserve_aligned(z_name, size, node, \ - RTE_MEMZONE_IOVA_CONTIG, alignment); \ - mem_handle = mz; \ - } \ - if (mz == NULL) { \ - virt = NULL; \ - phys = 0; \ - } else { \ - memset(mz->addr, 0, size); \ - virt = mz->addr; \ - phys = mz->iova; \ - } \ +#define ENA_MEM_ALLOC_COHERENT(dmadev, size, virt, phys, mem_handle) \ + ENA_MEM_ALLOC_COHERENT_ALIGNED(dmadev, size, virt, phys, \ + mem_handle, RTE_CACHE_LINE_SIZE) +#define ENA_MEM_FREE_COHERENT(dmadev, size, virt, phys, mem_handle) \ + ({ ENA_TOUCH(size); ENA_TOUCH(phys); ENA_TOUCH(dmadev); \ + rte_memzone_free(mem_handle); }) + +#define ENA_MEM_ALLOC_COHERENT_NODE_ALIGNED( \ + dmadev, size, virt, phys, mem_handle, node, dev_node, alignment) \ + do { \ + const struct rte_memzone *mz = NULL; \ + ENA_TOUCH(dmadev); ENA_TOUCH(dev_node); \ + if (size > 0) { \ + char z_name[RTE_MEMZONE_NAMESIZE]; \ + snprintf(z_name, sizeof(z_name), "ena_alloc_%"PRIi64"",\ + rte_atomic64_add_return(&ena_alloc_cnt, 1)); \ + mz = rte_memzone_reserve_aligned(z_name, size, \ + node, RTE_MEMZONE_IOVA_CONTIG, alignment); \ + mem_handle = mz; \ + } \ + if (mz == NULL) { \ + virt = NULL; \ + phys = 0; \ + } else { \ + memset(mz->addr, 0, size); \ + virt = mz->addr; \ + phys = mz->iova; \ + } \ } while (0) -#define ENA_MEM_ALLOC_COHERENT_NODE( \ - dmadev, size, virt, phys, mem_handle, node, dev_node) \ - ENA_MEM_ALLOC_COHERENT_NODE_ALIGNED( \ - dmadev, \ - size, \ - virt, \ - phys, \ - mem_handle, \ - node, \ - dev_node, \ - RTE_CACHE_LINE_SIZE) -#define ENA_MEM_ALLOC_NODE(dmadev, size, virt, node, dev_node) \ - do { \ - ENA_TOUCH(dmadev); ENA_TOUCH(dev_node); \ - virt = rte_zmalloc_socket(NULL, size, 0, node); \ +#define ENA_MEM_ALLOC_COHERENT_NODE( \ + dmadev, size, virt, phys, mem_handle, node, dev_node) \ + ENA_MEM_ALLOC_COHERENT_NODE_ALIGNED(dmadev, size, virt, phys, \ + mem_handle, node, dev_node, RTE_CACHE_LINE_SIZE) +#define ENA_MEM_ALLOC_NODE(dmadev, size, virt, node, dev_node) \ + do { \ + ENA_TOUCH(dmadev); ENA_TOUCH(dev_node); \ + virt = rte_zmalloc_socket(NULL, size, 0, node); \ } while (0) #define ENA_MEM_ALLOC(dmadev, size) rte_zmalloc(NULL, size, 1) -#define ENA_MEM_FREE(dmadev, ptr, size) \ +#define ENA_MEM_FREE(dmadev, ptr, size) \ ({ ENA_TOUCH(dmadev); ENA_TOUCH(size); rte_free(ptr); }) #define ENA_DB_SYNC(mem_handle) ((void)mem_handle) -#define ENA_REG_WRITE32(bus, value, reg) \ +#define ENA_REG_WRITE32(bus, value, reg) \ ({ (void)(bus); rte_write32((value), (reg)); }) -#define ENA_REG_WRITE32_RELAXED(bus, value, reg) \ +#define ENA_REG_WRITE32_RELAXED(bus, value, reg) \ ({ (void)(bus); rte_write32_relaxed((value), (reg)); }) -#define ENA_REG_READ32(bus, reg) \ +#define ENA_REG_READ32(bus, reg) \ ({ (void)(bus); rte_read32_relaxed((reg)); }) #define ATOMIC32_INC(i32_ptr) rte_atomic32_inc(i32_ptr) @@ -296,7 +282,7 @@ extern rte_atomic32_t ena_alloc_cnt; #define upper_32_bits(x) ((uint32_t)(((x) >> 16) >> 16)) #define ENA_TIME_EXPIRE(timeout) (timeout < rte_get_timer_cycles()) -#define ENA_GET_SYSTEM_TIMEOUT(timeout_us) \ +#define ENA_GET_SYSTEM_TIMEOUT(timeout_us) \ (timeout_us * rte_get_timer_hz() / 1000000 + rte_get_timer_cycles()) #define ENA_WAIT_EVENTS_DESTROY(waitqueue) ((void)(waitqueue)) @@ -309,14 +295,14 @@ extern rte_atomic32_t ena_alloc_cnt; #define READ_ONCE32(var) READ_ONCE(var) /* The size must be 8 byte align */ -#define ENA_MEMCPY_TO_DEVICE_64(dst, src, size) \ - do { \ - int count, i; \ - uint64_t *to = (uint64_t *)(dst); \ - const uint64_t *from = (const uint64_t *)(src); \ - count = (size) / 8; \ - for (i = 0; i < count; i++, from++, to++) \ - rte_write64_relaxed(*from, to); \ +#define ENA_MEMCPY_TO_DEVICE_64(dst, src, size) \ + do { \ + int count, i; \ + uint64_t *to = (uint64_t *)(dst); \ + const uint64_t *from = (const uint64_t *)(src); \ + count = (size) / 8; \ + for (i = 0; i < count; i++, from++, to++) \ + rte_write64_relaxed(*from, to); \ } while(0) #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) @@ -329,7 +315,5 @@ void ena_rss_key_fill(void *key, size_t size); #define ENA_INTR_INITIAL_TX_INTERVAL_USECS_PLAT 0 -#define ENA_PRIu64 PRIu64 - #include "ena_includes.h" #endif /* DPDK_ENA_COM_ENA_PLAT_DPDK_H_ */ diff --git a/drivers/net/ena/ena_ethdev.c b/drivers/net/ena/ena_ethdev.c index f1ff4dad36..3c9102cd19 100644 --- a/drivers/net/ena/ena_ethdev.c +++ b/drivers/net/ena/ena_ethdev.c @@ -85,7 +85,7 @@ struct ena_stats { * Each rte_memzone should have unique name. * To satisfy it, count number of allocation and add it to name. */ -rte_atomic32_t ena_alloc_cnt; +rte_atomic64_t ena_alloc_cnt; static const struct ena_stats ena_stats_global_strings[] = { ENA_STAT_GLOBAL_ENTRY(wd_expired), From patchwork Thu May 6 14:25:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Krawczyk X-Patchwork-Id: 93017 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id DC63BA0524; Thu, 6 May 2021 16:27:19 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id DFA304115B; Thu, 6 May 2021 16:26:01 +0200 (CEST) Received: from mail-lf1-f48.google.com (mail-lf1-f48.google.com [209.85.167.48]) by mails.dpdk.org (Postfix) with ESMTP id 0B05641152 for ; Thu, 6 May 2021 16:25:59 +0200 (CEST) Received: by mail-lf1-f48.google.com with SMTP id t11so8023355lfl.11 for ; Thu, 06 May 2021 07:25:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=GGtM5qsb7+GqyqX/GA3YsmYDNifrLD8/+HhQUhZLHtY=; b=CiZckHYFp4YZr07sPHSS/VKwHIY2XD0TyfrXQZNEfvOfdGSn62sObV1P28XU19km8h EClGaEisdZDIvSzcYF2CqAxx0pPdwm+8jcIGgoJnmoNqwG0V6+PlNI/BVXGlChVU1uTC pNd6sIDe1VVVcXpMFpRNBrbdD2psqaPrNcpLZysb+QtVVaV6DrbeYboT24d6WLqAKAEC RQBoIpeq+EBMvdQ578909xWrSgD96fi65V+9k4ZG6Vx/thpdS7C3JaWEpzIdJcc0bs63 wNMGmErYhFjjugOGc0CJQyWvou77TxM9aaB1Ehy4AGU9cLwjpHG45fNL8LaDozyEy3j6 eL8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=GGtM5qsb7+GqyqX/GA3YsmYDNifrLD8/+HhQUhZLHtY=; b=c/TIczmbCqFguzNlJvOFEk65MA14rDAbhuzM05nUuGJsdyjwvGgZlpKfqtxUfZzuWu xSukBBc9NtblS/PVhHaoWowATJ+R3W3/2W3M7oSjRmVg+ZuRSEGnd3WyL2hlAXBtvB1I WSt9NZcjAZSdcxU2vgjX6KfjzJm7wiUTvZBS5nmS2gH0UTsd317EsgMakoQycrJcegvK kG2VQx+EevNbs67rHH7xRqguTrtJCMpoKZZSRp5SN+2CeVg696TbHaAf9WyH9TzNouza dsL5FvoJFkOpbTXDvWz70jbBJx4D4p5OM4jzU9I4IXvZRsXUKmO7f5v6pKDIsI+DVAOt HE6A== X-Gm-Message-State: AOAM530w0T4slWkBGx9zchf2IEv1zS9QhrxuXBb0DiEuaX5EugixvIuw fbB27VD6C1SZMfKnEB5GdfoqroYPc9bGHAFx X-Google-Smtp-Source: ABdhPJzWz98LN2XT038WU1A90Qocq8vGLZSPWiuMrUNO8YSw4CJY0ip1ncEcjhVGacHmmvugp8DVCg== X-Received: by 2002:a05:6512:929:: with SMTP id f9mr3101781lft.153.1620311158360; Thu, 06 May 2021 07:25:58 -0700 (PDT) Received: from DESKTOP-U5LNN3J.localdomain (89-79-189-199.dynamic.chello.pl. [89.79.189.199]) by smtp.gmail.com with ESMTPSA id b40sm892908ljr.101.2021.05.06.07.25.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 May 2021 07:25:57 -0700 (PDT) From: Michal Krawczyk To: dev@dpdk.org Cc: ndagan@amazon.com, gtzalik@amazon.com, igorch@amazon.com, upstream@semihalf.com, stable@dpdk.org, Shay Agroskin , Michal Krawczyk Date: Thu, 6 May 2021 16:25:16 +0200 Message-Id: <20210506142526.28245-13-mk@semihalf.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210506142526.28245-1-mk@semihalf.com> References: <20210505073348.6394-1-mk@semihalf.com> <20210506142526.28245-1-mk@semihalf.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v3 12/22] net/ena: fix parsing of large_llq_hdr argument X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Igor Chauskin The code incorrectly checked the return value of comparison when parsing the argument key name. The return value of strcmp should be compared to 0 to identify a match. Fixes: 8a7a73f26cc9 ("net/ena: support large LLQ headers") Cc: stable@dpdk.org Signed-off-by: Igor Chauskin Reviewed-by: Shay Agroskin Reviewed-by: Michal Krawczyk --- drivers/net/ena/ena_ethdev.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ena/ena_ethdev.c b/drivers/net/ena/ena_ethdev.c index 3c9102cd19..cb8ad5c3d0 100644 --- a/drivers/net/ena/ena_ethdev.c +++ b/drivers/net/ena/ena_ethdev.c @@ -2865,7 +2865,7 @@ static int ena_process_bool_devarg(const char *key, } /* Now, assign it to the proper adapter field. */ - if (strcmp(key, ENA_DEVARG_LARGE_LLQ_HDR)) + if (strcmp(key, ENA_DEVARG_LARGE_LLQ_HDR) == 0) adapter->use_large_llq_hdr = bool_value; return 0; From patchwork Thu May 6 14:25:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Krawczyk X-Patchwork-Id: 93018 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 38253A0524; Thu, 6 May 2021 16:27:29 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8CC834116B; Thu, 6 May 2021 16:26:03 +0200 (CEST) Received: from mail-lf1-f54.google.com (mail-lf1-f54.google.com [209.85.167.54]) by mails.dpdk.org (Postfix) with ESMTP id 556EC41156 for ; Thu, 6 May 2021 16:26:00 +0200 (CEST) Received: by mail-lf1-f54.google.com with SMTP id z9so8033177lfu.8 for ; Thu, 06 May 2021 07:26:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ya29Y1oo4CSGqqdor+vF9iZ5PkFZCJ8mO7cQJ+GXFEQ=; b=YcJufDIxem4MeDmnoCMVvoYtbgBMm0F89iE48Rv9OtHSmXArvkdMGjkMnklT13lVK6 3xZM8yfDdsnERlzKNPtnrv+HFIcUV0/FjfL/dkkvwORmroizI0QSUe5jhDR1pWhfe4kR i+J2nnrdZ5I5g0OE1yZpvIVmiS7dO61XWd/gxFo3tJez5QPwA9ysSpFfbau3QQk3tIi0 bI89WMu6TGFzw5Ogl2eCxb3UO401hid7ERsapq+W8Or0P6PwpjEDLLKc61nxiG/+hu2H EgTJOdR60kr0G/AbDL0iee3MUzuBoQ1R0Hyrw7sTYEN9wqAJbRL5Fj4gKwi6K8Xfd6n2 a8tg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ya29Y1oo4CSGqqdor+vF9iZ5PkFZCJ8mO7cQJ+GXFEQ=; b=JGns7fJAhbZ4GaxfaAG42o95rmHbN+VnnKa/yDS4at7L5yyhZcWfOwW8GPYQPqRIqt KJW76VPgq1L/KOPMkA3Xc5x7pi7Zvp00Y7tgqaVzxmMpBeVeITyTuN7TdJlQx+bsxSZb WymmCYf6dKhE/JDRLkppmOADqkn2om+QZOGV5GCOMzMXjokz5fDJjjLbwjChR49P1yHP N9GT7tlzPk0W6joiTOaxDNfCCthigRpUEL7GZ7OW5h0BcFKwu6lVgAGHF56bkTjjp1qv D8urSY/72pNhrd3fgyJyTONTn7svKnQJtAyfFkwxL3uuXGmbb6jXkxb97Hw+waT3Ehbl SsDg== X-Gm-Message-State: AOAM531EfpXgPPQhY3NRvl0EmvoshDAzFybAPRBS8GWZ+zUvyq9YaL31 zD2PJD3UZTvYD0CHvQA3IV893Krs4BQWGEjd X-Google-Smtp-Source: ABdhPJz802lsQkkigQp6mHsBzWfX0wNW684EBTtFt+V7tWDh7VKETG3l5TPmhHx+vVTE99nFJzd8ZA== X-Received: by 2002:a05:6512:12d2:: with SMTP id p18mr3133588lfg.239.1620311159653; Thu, 06 May 2021 07:25:59 -0700 (PDT) Received: from DESKTOP-U5LNN3J.localdomain (89-79-189-199.dynamic.chello.pl. [89.79.189.199]) by smtp.gmail.com with ESMTPSA id b40sm892908ljr.101.2021.05.06.07.25.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 May 2021 07:25:58 -0700 (PDT) From: Michal Krawczyk To: dev@dpdk.org Cc: ndagan@amazon.com, gtzalik@amazon.com, igorch@amazon.com, upstream@semihalf.com, Michal Krawczyk , stable@dpdk.org, Shay Agroskin Date: Thu, 6 May 2021 16:25:17 +0200 Message-Id: <20210506142526.28245-14-mk@semihalf.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210506142526.28245-1-mk@semihalf.com> References: <20210505073348.6394-1-mk@semihalf.com> <20210506142526.28245-1-mk@semihalf.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v3 13/22] net/ena: terminate devargs allowed keys with NULL X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" As the documentation of rte_kvargs_parse() states, the valid_keys argument must be NULL terminated. Lack of this feature may cause segmentation fault if the passed devarg will be different then the supported value. Fixes: 8a7a73f26cc9 ("net/ena: support large LLQ headers") Cc: stable@dpdk.org Signed-off-by: Michal Krawczyk Reviewed-by: Igor Chauskin Reviewed-by: Shay Agroskin Acked-by: Ferruh Yigit make sen --- drivers/net/ena/ena_ethdev.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/net/ena/ena_ethdev.c b/drivers/net/ena/ena_ethdev.c index cb8ad5c3d0..6092288239 100644 --- a/drivers/net/ena/ena_ethdev.c +++ b/drivers/net/ena/ena_ethdev.c @@ -2876,6 +2876,7 @@ static int ena_parse_devargs(struct ena_adapter *adapter, { static const char * const allowed_args[] = { ENA_DEVARG_LARGE_LLQ_HDR, + NULL, }; struct rte_kvargs *kvlist; int rc; From patchwork Thu May 6 14:25:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Krawczyk X-Patchwork-Id: 93019 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id DF8F7A0524; Thu, 6 May 2021 16:27:35 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 077934116F; Thu, 6 May 2021 16:26:05 +0200 (CEST) Received: from mail-lf1-f50.google.com (mail-lf1-f50.google.com [209.85.167.50]) by mails.dpdk.org (Postfix) with ESMTP id 9F1DE4111F for ; Thu, 6 May 2021 16:26:01 +0200 (CEST) Received: by mail-lf1-f50.google.com with SMTP id z13so8100631lft.1 for ; Thu, 06 May 2021 07:26:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CCn/jybjwpSYdpjlPdx2Ac4wk64prMVI0wGVgKgb4uo=; b=TDpEMKs+KeiwJdUYZz//gGdsWKmCrGeVm+dPFy/xm+wkO64YYS01DgcqpeFXPr7Jc3 lQ6TOSPHWY0FWQEh42pByRBuF7NJHlTu2eWO3NPxwcl9NCcGgtF1su/EomViO1stctVv H94UkDm529CX+x0XZgR0W3J0HUlQYT9uaaIzkXsCl0DAOuhxr79ZlE8Fzq/47UnAc/y9 tYHmA4cIZOWIefIz+yzj0XNwp+xDTgd/Jc8OkJ2T5fdSUlN5haGauUKzAxEmuTmYDDnW gObLOCuz2bpwtECLNHrptVOQR/Qn/zEgTPqH8zvCiloKiM3Yd9xx4wuR9QfjUa7XVOaT UXig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CCn/jybjwpSYdpjlPdx2Ac4wk64prMVI0wGVgKgb4uo=; b=UoLCaxi1aKXkIo2odveXHfbcyCJ+sYUV67z4pF59B0pJZ/+/7zKZLnKj9yf4VgylAt 7uyoZlc6QUp+1xOWn/eRhBmY6uPt9w2hEoyEkMZu7PQKBLyPwbv5IUyB1V1FoZr/O8s/ hUof7Tqgod5kuKSvmIoLs3elsLf39Rxwgzg4lcA7946dDL9OkT9e5pvP5ewYiYrIzdc0 wAEKJMmIpA7WHOChtDkREDBT8Nf4neQV+PK2iYaja/yepNxfyMtYj+2TYEkxwKxHCD88 pSHC3UWqG1Lr86Y6TnkubYHZ/QCHiG02N2NNxe1YexBAvVyLE+2Kzqmre0D/KYXjkcyD 4u2Q== X-Gm-Message-State: AOAM531ES/6KOlwiyu644BE24UFCPw9w7h0sUOt2o382xhQVPZ7kmTCp f7H4Rh4VvsHio3ZWiESPwvf44AXvXimUOtYT X-Google-Smtp-Source: ABdhPJw68CxTnDwsPf9m4wqJgBmwR+pLfTZUVdmfIN+TC3zj3rkQppRTJl3A/rfZP7RQBPfT+0oi+g== X-Received: by 2002:ac2:4857:: with SMTP id 23mr3189510lfy.541.1620311160948; Thu, 06 May 2021 07:26:00 -0700 (PDT) Received: from DESKTOP-U5LNN3J.localdomain (89-79-189-199.dynamic.chello.pl. [89.79.189.199]) by smtp.gmail.com with ESMTPSA id b40sm892908ljr.101.2021.05.06.07.25.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 May 2021 07:26:00 -0700 (PDT) From: Michal Krawczyk To: dev@dpdk.org Cc: ndagan@amazon.com, gtzalik@amazon.com, igorch@amazon.com, upstream@semihalf.com, Michal Krawczyk , stable@dpdk.org, Amit Bernstein Date: Thu, 6 May 2021 16:25:18 +0200 Message-Id: <20210506142526.28245-15-mk@semihalf.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210506142526.28245-1-mk@semihalf.com> References: <20210505073348.6394-1-mk@semihalf.com> <20210506142526.28245-1-mk@semihalf.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v3 14/22] net/ena: indicate Rx RSS hash presence X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" To make it possible to the app to determine if the hash was calculated for the packet or not, the PKT_RX_RSS_HASH should be set in the mbuf's ol_flags. As the PMD wasn't setting that, the application couldn't check if there is a hash in a proper way. The hash is valid only if it's UDP or TCP and the IP packet wasn't fragmented. Fixes: e5df9f33db00 ("net/ena: fix passing RSS hash to mbuf") Cc: stable@dpdk.org Signed-off-by: Michal Krawczyk Reviewed-by: Igor Chauskin Reviewed-by: Amit Bernstein --- drivers/net/ena/ena_ethdev.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/net/ena/ena_ethdev.c b/drivers/net/ena/ena_ethdev.c index 6092288239..5d107775f4 100644 --- a/drivers/net/ena/ena_ethdev.c +++ b/drivers/net/ena/ena_ethdev.c @@ -51,6 +51,8 @@ #define ENA_MIN_RING_DESC 128 +#define ENA_PTYPE_HAS_HASH (RTE_PTYPE_L4_TCP | RTE_PTYPE_L4_UDP) + enum ethtool_stringset { ETH_SS_TEST = 0, ETH_SS_STATS, @@ -314,6 +316,11 @@ static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf, else ol_flags |= PKT_RX_L4_CKSUM_GOOD; + if (likely((packet_type & ENA_PTYPE_HAS_HASH) && !ena_rx_ctx->frag)) { + ol_flags |= PKT_RX_RSS_HASH; + mbuf->hash.rss = ena_rx_ctx->hash; + } + mbuf->ol_flags = ol_flags; mbuf->packet_type = packet_type; } @@ -2245,8 +2252,6 @@ static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, ++rx_ring->rx_stats.bad_csum; } - mbuf->hash.rss = ena_rx_ctx.hash; - rx_pkts[completed] = mbuf; rx_ring->rx_stats.bytes += mbuf->pkt_len; } From patchwork Thu May 6 14:25:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Krawczyk X-Patchwork-Id: 93020 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2458EA0524; Thu, 6 May 2021 16:27:42 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B80B141173; Thu, 6 May 2021 16:26:06 +0200 (CEST) Received: from mail-lj1-f180.google.com (mail-lj1-f180.google.com [209.85.208.180]) by mails.dpdk.org (Postfix) with ESMTP id 16A6E41162 for ; Thu, 6 May 2021 16:26:03 +0200 (CEST) Received: by mail-lj1-f180.google.com with SMTP id p12so7314290ljg.1 for ; Thu, 06 May 2021 07:26:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=gAOAdq/3nI0xT6ujf76EsSvcMe11nEit/A1336hWGkU=; b=Sk/OaJ+BaehmocbMdHqD+BY4lwEUVf0aefZoy8Z82twkMgbe0cI4y11WLxWNkYl5j5 cxhzPe0jB8IoCqiX5A55AlcDZmmO1l4HEzJeHBOprxgUqxW6RK/3dJBXudXvn3VYjLM7 3DraKVdSC6ba6KlCtnufH1vIdGuZhDgb/oVVyOSlxk4jpwnh/nPqM49cwBfBKKLT8vui 9mNee0n6vRPvRbAgdxX+hW83ZPyNPW4A3jp7sE1PLHhBg1s2XaCTcDk4AdcIfTa/abTO AdwX+zyVSIKauMKkHK6fMvciDeYMtoaGhWd8Tu55gj7pbqGZweOudcYH+GYjIrwGgNUQ np6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=gAOAdq/3nI0xT6ujf76EsSvcMe11nEit/A1336hWGkU=; b=SSzjW1kwIDy1ffF/O+NT0x+IRqA/2oTrKf3f+GQuPlkXCWhgyYggFcCbSrCX1SoF4u TWa/Le7SgIW0Fd5Sm3qChVUVsS36enfjpBEV5JtM9Y0IT3yxNXqkjmpUmOORXG0sRzWK xMPS63xvOYuIJiNFiW93g7cykbBeAzEtbJWxSxvZVX2BUKqbP2bmd+Sczhw2uYw9Yqq5 iN68vyI83/g3TDW9xjMihaVNj3EPmsi96rYYAh9Nol2a6DjhLP1A00g2jYAHRON9i/Hj AcYlyWvC7MPXhcP/RPM7sleFl0u2qWG+nM8qCW6UKhiBp4CbbwlXh0X4Ug0Upa7HAaaF MSrg== X-Gm-Message-State: AOAM530F0H/IG9+Cf10Ax002pA8V6ZHwEpXamtEhkeg7dCiEgC7a3EWl kwyWIn4mS4hNpuVTpMkpv1kZpcYuFewdiZqM X-Google-Smtp-Source: ABdhPJxqnd13iAydo8mLXgCIIxT9UPJ9BBCu/heOSN0qdBPVVcWamnG9lGb0oYBU+WlFTUcO7alKxw== X-Received: by 2002:a2e:b8ce:: with SMTP id s14mr3683642ljp.475.1620311162287; Thu, 06 May 2021 07:26:02 -0700 (PDT) Received: from DESKTOP-U5LNN3J.localdomain (89-79-189-199.dynamic.chello.pl. [89.79.189.199]) by smtp.gmail.com with ESMTPSA id b40sm892908ljr.101.2021.05.06.07.26.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 May 2021 07:26:01 -0700 (PDT) From: Michal Krawczyk To: dev@dpdk.org Cc: ndagan@amazon.com, gtzalik@amazon.com, igorch@amazon.com, upstream@semihalf.com, Stanislaw Kardach , Michal Krawczyk , Shay Agroskin Date: Thu, 6 May 2021 16:25:19 +0200 Message-Id: <20210506142526.28245-16-mk@semihalf.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210506142526.28245-1-mk@semihalf.com> References: <20210505073348.6394-1-mk@semihalf.com> <20210506142526.28245-1-mk@semihalf.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v3 15/22] net/ena: remove endian swap functions X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Stanislaw Kardach swap*_*_le() functions are not used anywhere and besides there are rte alternatives already present. Fixes: 1173fca25af9 ("ena: add polling-mode driver") Signed-off-by: Stanislaw Kardach Reviewed-by: Michal Krawczyk Reviewed-by: Igor Chauskin Reviewed-by: Shay Agroskin --- drivers/net/ena/ena_platform.h | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/drivers/net/ena/ena_platform.h b/drivers/net/ena/ena_platform.h index d3e40e0e9e..748928b2d9 100644 --- a/drivers/net/ena/ena_platform.h +++ b/drivers/net/ena/ena_platform.h @@ -6,18 +6,6 @@ #ifndef __ENA_PLATFORM_H__ #define __ENA_PLATFORM_H__ -#define swap16_to_le(x) (x) - -#define swap32_to_le(x) (x) - -#define swap64_to_le(x) (x) - -#define swap16_from_le(x) (x) - -#define swap32_from_le(x) (x) - -#define swap64_from_le(x) (x) - #define ena_assert_msg(cond, msg) \ do { \ if (unlikely(!(cond))) { \ From patchwork Thu May 6 14:25:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Krawczyk X-Patchwork-Id: 93021 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E387DA0524; Thu, 6 May 2021 16:27:48 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 10DA241179; Thu, 6 May 2021 16:26:08 +0200 (CEST) Received: from mail-lf1-f41.google.com (mail-lf1-f41.google.com [209.85.167.41]) by mails.dpdk.org (Postfix) with ESMTP id 7EE5441159 for ; Thu, 6 May 2021 16:26:04 +0200 (CEST) Received: by mail-lf1-f41.google.com with SMTP id j10so8019085lfb.12 for ; Thu, 06 May 2021 07:26:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3AKcTU8MDffGzf3VtJfkelWNkIkfg2AS6BXmmnHl1yY=; b=q5I9t5q9UdC6T/lgWouNMrBJeme6OI3jp3EHfXC6hE230UHCjKNWiUe/ccG5f3S2Xo guVbF32o7eEOg9SIvtbh/wjkzBCK4PSQfigHxiTj1lnZ0yBuXG+DR3+/NdvK9wAf1AhM u+edFMJYqQCsxyPEjx6F2YdF2lqK9eZ43dU2cKufpthyCaXrNGXTXowP1EzAFddzx8eA jzEmv5T/JQ5NFoqgzPgwII78znnjTkDieDzVeHx25jV66K1+C/JSaBAZ9S1Tl9LuVW49 +AfiDLf3lNzAfMXeYraoiMCYzyNKExU3zDUxG+/y0IRYEH8tx+YQCzLwjSUom/lXsO/R 27OQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3AKcTU8MDffGzf3VtJfkelWNkIkfg2AS6BXmmnHl1yY=; b=leBCjJbRfe5f/GIh7ejpir2BvT8xgR5f6V9wdsm5SVEi9UXaMO1kvyWpr7rvy/1uV4 9vAbZ5fZMcnO/t42h6/1c7WaunI6x5Kh6+Qvgwas5hzj++7m+GNS5KImSLicc3Dwidfc lbnk7gc3AQNBvFCth1WIACTTu7Oi/ySjpKzhanY0yotLQBf+9Y8Xo+dVaG/NTmdgjufk EGLyKp/HffeHOKChQA6af6XscawLIpp7rdzuZxHWhuaFR5cDs3DuOYkvS/eX46NZFywq 2uToi/QvRfluUdfdk1nKk3QofK4Matehv7i5S6qeEyyZQJRSAp0JqDX1GXWV6aTFT3gf 96Uw== X-Gm-Message-State: AOAM531OGXw7X7cq/jsvRbCYuLKDZTkxpEXmEAqAc1Cmh8djpg4waQ2b D8kh7Z4gh5szcIgOo1BgAyCsYyJPg5eUBCE4 X-Google-Smtp-Source: ABdhPJyteibZkLOo1yPmAcSkloN4IZSn//pPA028lNYZYmXGAMdYJW/OVuSvlxfNma5Ov67PcNPqkQ== X-Received: by 2002:ac2:4887:: with SMTP id x7mr3128630lfc.561.1620311163772; Thu, 06 May 2021 07:26:03 -0700 (PDT) Received: from DESKTOP-U5LNN3J.localdomain (89-79-189-199.dynamic.chello.pl. [89.79.189.199]) by smtp.gmail.com with ESMTPSA id b40sm892908ljr.101.2021.05.06.07.26.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 May 2021 07:26:03 -0700 (PDT) From: Michal Krawczyk To: dev@dpdk.org Cc: ndagan@amazon.com, gtzalik@amazon.com, igorch@amazon.com, upstream@semihalf.com, Stanislaw Kardach , Michal Krawczyk , Shay Agroskin Date: Thu, 6 May 2021 16:25:20 +0200 Message-Id: <20210506142526.28245-17-mk@semihalf.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210506142526.28245-1-mk@semihalf.com> References: <20210505073348.6394-1-mk@semihalf.com> <20210506142526.28245-1-mk@semihalf.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v3 16/22] net/ena: handle spurious wakeups in ENA_WAIT_EVENT X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Stanislaw Kardach pthread_cond_timedwait() may spuriously wakeup according to POSIX. Therefore it is required to check whether predicate is actually true before finishing the waiting loop. Signed-off-by: Stanislaw Kardach Reviewed-by: Michal Krawczyk Reviewed-by: Igor Chauskin Reviewed-by: Shay Agroskin --- drivers/net/ena/base/ena_plat_dpdk.h | 75 +++++++++++++++++----------- 1 file changed, 47 insertions(+), 28 deletions(-) diff --git a/drivers/net/ena/base/ena_plat_dpdk.h b/drivers/net/ena/base/ena_plat_dpdk.h index 4498d53703..1d0454bebe 100644 --- a/drivers/net/ena/base/ena_plat_dpdk.h +++ b/drivers/net/ena/base/ena_plat_dpdk.h @@ -77,6 +77,14 @@ typedef uint64_t dma_addr_t; #define mmiowb rte_io_wmb #define __iomem +#ifndef READ_ONCE +#define READ_ONCE(var) (*((volatile typeof(var) *)(&(var)))) +#endif + +#define READ_ONCE8(var) READ_ONCE(var) +#define READ_ONCE16(var) READ_ONCE(var) +#define READ_ONCE32(var) READ_ONCE(var) + #define US_PER_S 1000000 #define ENA_GET_SYSTEM_USECS() \ (rte_get_timer_cycles() * US_PER_S / rte_get_timer_hz()) @@ -137,40 +145,59 @@ extern int ena_logtype_com; ({(void)flags; rte_spinlock_unlock(&(spinlock)); }) #define ENA_SPINLOCK_DESTROY(spinlock) ((void)spinlock) -#define q_waitqueue_t \ - struct { \ - pthread_cond_t cond; \ - pthread_mutex_t mutex; \ - } +typedef struct { + pthread_cond_t cond; + pthread_mutex_t mutex; + uint8_t flag; +} ena_wait_event_t; -#define ena_wait_queue_t q_waitqueue_t - -#define ENA_WAIT_EVENT_INIT(waitqueue) \ +#define ENA_WAIT_EVENT_INIT(waitevent) \ do { \ - pthread_mutex_init(&(waitqueue).mutex, NULL); \ - pthread_cond_init(&(waitqueue).cond, NULL); \ + ena_wait_event_t *_we = &(waitevent); \ + pthread_mutex_init(&_we->mutex, NULL); \ + pthread_cond_init(&_we->cond, NULL); \ + _we->flag = 0; \ } while (0) #define ENA_WAIT_EVENT_WAIT(waitevent, timeout) \ do { \ + ena_wait_event_t *_we = &(waitevent); \ + typeof(timeout) _tmo = (timeout); \ + int ret = 0; \ struct timespec wait; \ struct timeval now; \ unsigned long timeout_us; \ gettimeofday(&now, NULL); \ - wait.tv_sec = now.tv_sec + timeout / 1000000UL; \ - timeout_us = timeout % 1000000UL; \ + wait.tv_sec = now.tv_sec + _tmo / 1000000UL; \ + timeout_us = _tmo % 1000000UL; \ wait.tv_nsec = (now.tv_usec + timeout_us) * 1000UL; \ - pthread_mutex_lock(&waitevent.mutex); \ - pthread_cond_timedwait(&waitevent.cond, \ - &waitevent.mutex, &wait); \ - pthread_mutex_unlock(&waitevent.mutex); \ + pthread_mutex_lock(&_we->mutex); \ + while (ret == 0 && !_we->flag) { \ + ret = pthread_cond_timedwait(&_we->cond, \ + &_we->mutex, &wait); \ + } \ + /* Asserts only if not working on ena_wait_event_t */ \ + if (unlikely(ret != 0 && ret != ETIMEDOUT)) \ + rte_panic("Invalid wait event. pthread ret: %d\n", \ + ret); \ + else if (unlikely(ret == ETIMEDOUT)) \ + ena_trc_err(NULL, \ + "Timeout waiting for " #waitevent "\n"); \ + _we->flag = 0; \ + pthread_mutex_unlock(&_we->mutex); \ + } while (0) +#define ENA_WAIT_EVENT_SIGNAL(waitevent) \ + do { \ + ena_wait_event_t *_we = &(waitevent); \ + pthread_mutex_lock(&_we->mutex); \ + _we->flag = 1; \ + pthread_cond_signal(&_we->cond); \ + pthread_mutex_unlock(&_we->mutex); \ } while (0) -#define ENA_WAIT_EVENT_SIGNAL(waitevent) pthread_cond_signal(&waitevent.cond) /* pthread condition doesn't need to be rearmed after usage */ #define ENA_WAIT_EVENT_CLEAR(...) -#define ENA_WAIT_EVENT_DESTROY(admin_queue) ((void)(admin_queue)) +#define ENA_WAIT_EVENT_DESTROY(waitevent) ((void)(waitevent)) -#define ena_wait_event_t ena_wait_queue_t #define ENA_MIGHT_SLEEP() #define ena_time_t uint64_t @@ -284,15 +311,7 @@ extern rte_atomic64_t ena_alloc_cnt; #define ENA_TIME_EXPIRE(timeout) (timeout < rte_get_timer_cycles()) #define ENA_GET_SYSTEM_TIMEOUT(timeout_us) \ (timeout_us * rte_get_timer_hz() / 1000000 + rte_get_timer_cycles()) -#define ENA_WAIT_EVENTS_DESTROY(waitqueue) ((void)(waitqueue)) - -#ifndef READ_ONCE -#define READ_ONCE(var) (*((volatile typeof(var) *)(&(var)))) -#endif - -#define READ_ONCE8(var) READ_ONCE(var) -#define READ_ONCE16(var) READ_ONCE(var) -#define READ_ONCE32(var) READ_ONCE(var) +#define ENA_WAIT_EVENTS_DESTROY(admin_queue) ((void)(admin_queue)) /* The size must be 8 byte align */ #define ENA_MEMCPY_TO_DEVICE_64(dst, src, size) \ From patchwork Thu May 6 14:25:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Krawczyk X-Patchwork-Id: 93022 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 37CCAA0524; Thu, 6 May 2021 16:27:55 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6E6D441168; Thu, 6 May 2021 16:26:09 +0200 (CEST) Received: from mail-lf1-f41.google.com (mail-lf1-f41.google.com [209.85.167.41]) by mails.dpdk.org (Postfix) with ESMTP id EB3C84115F for ; Thu, 6 May 2021 16:26:05 +0200 (CEST) Received: by mail-lf1-f41.google.com with SMTP id t11so8023865lfl.11 for ; Thu, 06 May 2021 07:26:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ukRfbvKC/YDCGyLZxijrxJ6E6jo2SKIcvP2YjC+olqo=; b=iTLV1F12r9iT63xo+szlhxtq1grpNEszNOu4JDGgfMrRbaudcwESUSqycxrjaWkp7U 1ivz7fSOq84BA/iCMPp7isehfOjaLBhjOLALY6Zezro2WWz59ZdiHkewsatL+rsGpxZD bN8dOU4YrzBrQiZ7x09QY7zgMy+sxUXzuOrBfeqiJvQbM/jqUIqgJmqL6ItJrI0jbhlK 77BrUvcDlyAdqxY9KapOB2t5ZIIuxvkdn78E7TZKYmM1QGMCJMdr1b0vhKXgCbnl1VOA L0TW3+L+pKr69Gr8kbPTf0h+iyBdvlHUHcqaQvpwMu0Bms5JD9VPc2ggxvgsJcj5JxCn 7a5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ukRfbvKC/YDCGyLZxijrxJ6E6jo2SKIcvP2YjC+olqo=; b=lHVmUZofeAfQoK5doZpTgAhuVIoFssPoTl0wpLY2CyU36i2Z0/kW/YmG3JrKqWK/iI 5pZrFGM9wW3AQ92t/tUyX6HfhbEDWunvfLHAKjMDSWqaK4Gh06+reOvRS6NkG6lI68Hs AXZs076EJsajKlxu3EPntoPN6W9m6GpCPEeeh/UiL60bc/LJ5pjRtgF6/ffjJMTSDQ+b kZjgyuPhAG9H/11qDru/PAiOQEnjqfoeusfNObt9fsqq5KY5gGJGJut8rEWn4JU8URqa n7fZeiXOSYpS09lgYsRUz2GhtydMZJRrsHjghn4B3XZTzO5ZZP57rt6EXusZ1PYHHol4 nVpQ== X-Gm-Message-State: AOAM531qwKLDQjKEx8XyV0j0lqaH4N4GlTtkREW4/2r8Cn8nzAHdrcB/ NzhatW4EBg75j9fW9K1aAgTljd0PyH8fD7jd X-Google-Smtp-Source: ABdhPJyOgWqoPnbYkrK2xWB2+ua4MUIFtha0wY381wh4cG9XVkjFFZWfn0Wxxt0jxXmCgQbBbCeM9Q== X-Received: by 2002:a05:6512:b90:: with SMTP id b16mr3067231lfv.483.1620311165074; Thu, 06 May 2021 07:26:05 -0700 (PDT) Received: from DESKTOP-U5LNN3J.localdomain (89-79-189-199.dynamic.chello.pl. [89.79.189.199]) by smtp.gmail.com with ESMTPSA id b40sm892908ljr.101.2021.05.06.07.26.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 May 2021 07:26:04 -0700 (PDT) From: Michal Krawczyk To: dev@dpdk.org Cc: ndagan@amazon.com, gtzalik@amazon.com, igorch@amazon.com, upstream@semihalf.com, Stanislaw Kardach , Michal Krawczyk , Shay Agroskin Date: Thu, 6 May 2021 16:25:21 +0200 Message-Id: <20210506142526.28245-18-mk@semihalf.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210506142526.28245-1-mk@semihalf.com> References: <20210505073348.6394-1-mk@semihalf.com> <20210506142526.28245-1-mk@semihalf.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v3 17/22] net/ena: support SMP for mz alloc counter X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Stanislaw Kardach Introduce a memory area for ENA driver shared between all the processes of a same prefix (memzone backed). Move the memzone allocation counter for ENA_MEM_ALLOC_COHERENT there so that all processes may utilize it. Signed-off-by: Stanislaw Kardach Reviewed-by: Michal Krawczyk Reviewed-by: Igor Chauskin Reviewed-by: Shay Agroskin --- drivers/net/ena/base/ena_plat_dpdk.h | 6 ++-- drivers/net/ena/ena_ethdev.c | 46 +++++++++++++++++++++++++++- drivers/net/ena/ena_ethdev.h | 8 +++++ 3 files changed, 56 insertions(+), 4 deletions(-) diff --git a/drivers/net/ena/base/ena_plat_dpdk.h b/drivers/net/ena/base/ena_plat_dpdk.h index 1d0454bebe..e17970361a 100644 --- a/drivers/net/ena/base/ena_plat_dpdk.h +++ b/drivers/net/ena/base/ena_plat_dpdk.h @@ -209,7 +209,7 @@ typedef struct { * Each rte_memzone should have unique name. * To satisfy it, count number of allocations and add it to name. */ -extern rte_atomic64_t ena_alloc_cnt; +extern rte_atomic64_t *ena_alloc_cnt; #define ENA_MEM_ALLOC_COHERENT_ALIGNED( \ dmadev, size, virt, phys, mem_handle, alignment) \ @@ -219,7 +219,7 @@ extern rte_atomic64_t ena_alloc_cnt; if (size > 0) { \ char z_name[RTE_MEMZONE_NAMESIZE]; \ snprintf(z_name, sizeof(z_name), "ena_alloc_%"PRIi64"",\ - rte_atomic64_add_return(&ena_alloc_cnt, 1)); \ + rte_atomic64_add_return(ena_alloc_cnt, 1)); \ mz = rte_memzone_reserve_aligned(z_name, size, \ SOCKET_ID_ANY, RTE_MEMZONE_IOVA_CONTIG,\ alignment); \ @@ -249,7 +249,7 @@ extern rte_atomic64_t ena_alloc_cnt; if (size > 0) { \ char z_name[RTE_MEMZONE_NAMESIZE]; \ snprintf(z_name, sizeof(z_name), "ena_alloc_%"PRIi64"",\ - rte_atomic64_add_return(&ena_alloc_cnt, 1)); \ + rte_atomic64_add_return(ena_alloc_cnt, 1)); \ mz = rte_memzone_reserve_aligned(z_name, size, \ node, RTE_MEMZONE_IOVA_CONTIG, alignment); \ mem_handle = mz; \ diff --git a/drivers/net/ena/ena_ethdev.c b/drivers/net/ena/ena_ethdev.c index 5d107775f4..0780e2fee2 100644 --- a/drivers/net/ena/ena_ethdev.c +++ b/drivers/net/ena/ena_ethdev.c @@ -83,11 +83,15 @@ struct ena_stats { /* Device arguments */ #define ENA_DEVARG_LARGE_LLQ_HDR "large_llq_hdr" +#define ENA_MZ_SHARED_DATA "ena_shared_data" + /* * Each rte_memzone should have unique name. * To satisfy it, count number of allocation and add it to name. */ -rte_atomic64_t ena_alloc_cnt; +rte_atomic64_t *ena_alloc_cnt; + +struct ena_shared_data *ena_shared_data; static const struct ena_stats ena_stats_global_strings[] = { ENA_STAT_GLOBAL_ENTRY(wd_expired), @@ -1752,6 +1756,42 @@ static uint32_t ena_calc_max_io_queue_num(struct ena_com_dev *ena_dev, return max_num_io_queues; } +static void ena_prepare_shared_data(struct ena_shared_data *shared_data) +{ + memset(shared_data, 0, sizeof(*shared_data)); +} + +static int ena_shared_data_init(void) +{ + const struct rte_memzone *mz; + + if (ena_shared_data != NULL) + return 0; + + if (rte_eal_process_type() == RTE_PROC_PRIMARY) { + /* Allocate shared memory. */ + mz = rte_memzone_reserve(ENA_MZ_SHARED_DATA, + sizeof(*ena_shared_data), + SOCKET_ID_ANY, 0); + if (mz == NULL) { + PMD_INIT_LOG(CRIT, "Cannot allocate ena shared data"); + return -rte_errno; + } + ena_prepare_shared_data(mz->addr); + } else { + /* Lookup allocated shared memory. */ + mz = rte_memzone_lookup(ENA_MZ_SHARED_DATA); + if (mz == NULL) { + PMD_INIT_LOG(CRIT, "Cannot attach ena shared data"); + return -rte_errno; + } + } + ena_shared_data = mz->addr; + /* Setup ENA_MEM memzone name counter. */ + ena_alloc_cnt = &ena_shared_data->mz_alloc_cnt; + return 0; +} + static int eth_ena_dev_init(struct rte_eth_dev *eth_dev) { struct ena_calc_queue_size_ctx calc_queue_ctx = { 0 }; @@ -1773,6 +1813,10 @@ static int eth_ena_dev_init(struct rte_eth_dev *eth_dev) eth_dev->tx_pkt_burst = ð_ena_xmit_pkts; eth_dev->tx_pkt_prepare = ð_ena_prep_pkts; + rc = ena_shared_data_init(); + if (rc != 0) + return rc; + if (rte_eal_process_type() != RTE_PROC_PRIMARY) return 0; diff --git a/drivers/net/ena/ena_ethdev.h b/drivers/net/ena/ena_ethdev.h index ae235897ee..e8858c6118 100644 --- a/drivers/net/ena/ena_ethdev.h +++ b/drivers/net/ena/ena_ethdev.h @@ -207,6 +207,14 @@ struct ena_offloads { bool rx_csum_supported; }; +/* Holds data shared between all instances of ENA PMD. */ +struct ena_shared_data { + /* Each rte_memzone should have unique name. + * To satisfy it, count number of allocation and add it to name. + */ + rte_atomic64_t mz_alloc_cnt; +}; + /* board specific private data structure */ struct ena_adapter { /* OS defined structs */ From patchwork Thu May 6 14:25:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Krawczyk X-Patchwork-Id: 93023 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B2F87A0524; Thu, 6 May 2021 16:28:01 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A778F41180; Thu, 6 May 2021 16:26:10 +0200 (CEST) Received: from mail-lj1-f177.google.com (mail-lj1-f177.google.com [209.85.208.177]) by mails.dpdk.org (Postfix) with ESMTP id 2FF6441176 for ; Thu, 6 May 2021 16:26:07 +0200 (CEST) Received: by mail-lj1-f177.google.com with SMTP id e12so7298632ljn.2 for ; Thu, 06 May 2021 07:26:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=nOPHTMCCkX8C83tBIu21N5+HJY6fLAgf/yI6j5uKwM8=; b=at/cXFHiZN0IcDyT/yfjd/WEPNohFpuzp057mvtfAFBjG5WXPZzbujMSPxd/r2ORC9 YXx1o1fORW/i/vbQSgdPu2D2qaBd83FWAUvl/rQMXaWxBVOl4GE8RJbdxb3NDWQrvTyU qj2H1rXMmzRjiEsXAGjdh/NYNQg+ZE4Wk3l08vxctF2tXtJc5WvLM13yQRyd8FLloYIS Nzsc9pZju5Gzec2ZnwfdU3wOMCL1mrsLhpT2ydiJkc8LmTO36kTIiW/dNx0FoNzvM+bV 9bNsQPEFVOdSnkzPqqtq+aNQgvtyfRmmih0ijCuNQoqmbxp74SPl8W7UhzpOkxgCrnnt dh7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nOPHTMCCkX8C83tBIu21N5+HJY6fLAgf/yI6j5uKwM8=; b=d2F4tjBTHykh9EV+HP5PH/OiIng9yJ8VSw6orpaXRHUtJnf8iPycbN38LrbpFcx9Ls q7E9mQXkiWt2cUEIwRDAf14E4HZ0Ez/qv2ssYHQd3A4M3NZmJUjIU1a0YpQdGL6Tv1H9 kdbh66kMQA0A2Dg9oQ8KHxikYy2mNtF4Tx8D/h2FGbpsNm6ZAKcpAp7gNnHffc1KOVqy hbwlBX5RcnccelCK4s7EPX33o4L9bnG4exGOyjElBiaYh/YkQ7jdDJJF2XgaBl/0Pg8V dg36FXg7SrCvJZBSIy86NF1l/ovg62KXBEd0LyNVfE2QM3UVW2uLqxJyxd+E5DKLgmZx EhAA== X-Gm-Message-State: AOAM532c1N3oUBqRf+wIsTlt6o4812qiyM039Ohi8y0dEBSHjU9TGBVP uDgkwZ6rdlEzNhl5kT0EGqL+YQnsjwNASfVA X-Google-Smtp-Source: ABdhPJxruCidQnL5EmrFkpO1Auct++5V5Occc1so/K/N9oOXBlwHrRFlS++vQZ+T21bARbdGtO1xRA== X-Received: by 2002:a2e:9c06:: with SMTP id s6mr3632415lji.508.1620311166527; Thu, 06 May 2021 07:26:06 -0700 (PDT) Received: from DESKTOP-U5LNN3J.localdomain (89-79-189-199.dynamic.chello.pl. [89.79.189.199]) by smtp.gmail.com with ESMTPSA id b40sm892908ljr.101.2021.05.06.07.26.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 May 2021 07:26:05 -0700 (PDT) From: Michal Krawczyk To: dev@dpdk.org Cc: ndagan@amazon.com, gtzalik@amazon.com, igorch@amazon.com, upstream@semihalf.com, Stanislaw Kardach , Michal Krawczyk , Shay Agroskin Date: Thu, 6 May 2021 16:25:22 +0200 Message-Id: <20210506142526.28245-19-mk@semihalf.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210506142526.28245-1-mk@semihalf.com> References: <20210505073348.6394-1-mk@semihalf.com> <20210506142526.28245-1-mk@semihalf.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v3 18/22] net/ena: move default RSS key to shared mem X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Stanislaw Kardach Make sure the same random generated RSS key is available to all ENA PMD instances in all processes. Signed-off-by: Stanislaw Kardach Reviewed-by: Michal Krawczyk Reviewed-by: Igor Chauskin Reviewed-by: Shay Agroskin --- drivers/net/ena/ena_ethdev.c | 16 +++++----------- drivers/net/ena/ena_ethdev.h | 1 + 2 files changed, 6 insertions(+), 11 deletions(-) diff --git a/drivers/net/ena/ena_ethdev.c b/drivers/net/ena/ena_ethdev.c index 0780e2fee2..5c365e1ab5 100644 --- a/drivers/net/ena/ena_ethdev.c +++ b/drivers/net/ena/ena_ethdev.c @@ -276,19 +276,9 @@ static const struct eth_dev_ops ena_dev_ops = { void ena_rss_key_fill(void *key, size_t size) { - static bool key_generated; - static uint8_t default_key[ENA_HASH_KEY_SIZE]; - size_t i; - RTE_ASSERT(size <= ENA_HASH_KEY_SIZE); - if (!key_generated) { - for (i = 0; i < ENA_HASH_KEY_SIZE; ++i) - default_key[i] = rte_rand() & 0xff; - key_generated = true; - } - - rte_memcpy(key, default_key, size); + rte_memcpy(key, ena_shared_data->default_key, size); } static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf, @@ -1758,7 +1748,11 @@ static uint32_t ena_calc_max_io_queue_num(struct ena_com_dev *ena_dev, static void ena_prepare_shared_data(struct ena_shared_data *shared_data) { + size_t i; + memset(shared_data, 0, sizeof(*shared_data)); + for (i = 0; i < ENA_HASH_KEY_SIZE; ++i) + shared_data->default_key[i] = rte_rand() & 0xff; } static int ena_shared_data_init(void) diff --git a/drivers/net/ena/ena_ethdev.h b/drivers/net/ena/ena_ethdev.h index e8858c6118..1f7383dce0 100644 --- a/drivers/net/ena/ena_ethdev.h +++ b/drivers/net/ena/ena_ethdev.h @@ -209,6 +209,7 @@ struct ena_offloads { /* Holds data shared between all instances of ENA PMD. */ struct ena_shared_data { + uint8_t default_key[ENA_HASH_KEY_SIZE]; /* Each rte_memzone should have unique name. * To satisfy it, count number of allocation and add it to name. */ From patchwork Thu May 6 14:25:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Krawczyk X-Patchwork-Id: 93024 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2E64AA0524; Thu, 6 May 2021 16:28:09 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D606141188; Thu, 6 May 2021 16:26:12 +0200 (CEST) Received: from mail-lf1-f44.google.com (mail-lf1-f44.google.com [209.85.167.44]) by mails.dpdk.org (Postfix) with ESMTP id A54864111E for ; Thu, 6 May 2021 16:26:08 +0200 (CEST) Received: by mail-lf1-f44.google.com with SMTP id z13so8101178lft.1 for ; Thu, 06 May 2021 07:26:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xQ5KzMcvNm7MJFLzLa3duwUXJFZs4nyU4dVGhI0xeS4=; b=g5O1BmAlaMjhj/6PZBIkE7wytTAGMPKOGy/mbTAguK+XKOUJ/N6x+5yGDOe8/4WUi1 ioGZuF/Y7EfVstbPW1kK+6sCqqzTaeuWY0Cy2E1PvTdwjdGdqmEtL4pRRfVLxX+iRyRF YhrW6yEsF0BsQFlYwrtT36BT4PRT8A8AiU4CaANahJZ1xcRmDv4gLAfw8I/zHHKqKx/q rTLvQwy0wsFJjUimFbyJAeMSMzCVPJBYGnQwaVqfC2ItEsk/0cIF4k7f8Ei3ympaEbxD rHi2TaidYdCt6DXmiiTqXS17tLvRdV6bwwIeFDQg9OTPGVRiXG+KbvTYpq+Z1Ol4wZUV DCMQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xQ5KzMcvNm7MJFLzLa3duwUXJFZs4nyU4dVGhI0xeS4=; b=HGlM69aLWwIkfDqA2+AC7FIX12QCUVdkMfcxXh8qOWeaJ479JwQB2KTDesylihFtb2 dhlGzzDjITtzHIZrWVP2ZRFxlfn3UGKuoThQ5xfgGlJa0d3LEAELTdc42Tf47RWrG1re JReEYWNQTTPbElZT0f3+bjEfYj32zqAYljZpMV5TeHFCh0y1Ghel0sYZZhTj9HzrrDr0 7TvNCR/TrWc8r1f5gU7zaHbBRdqVBia49+1BGlh+C0yqGspcR8ZF7ZLEwVKg4f61bzC4 UPf5Rd6SLovs2SQt7Q1NOnrN4wmt78RdN9u6yVAQ8Dd+NvsYlpJdDTTJRNiGxL47H6u6 2NPQ== X-Gm-Message-State: AOAM532nGj4cZ0qsCnkkGiEmWD9TuGqvmVTICertC6K60QPOqZEoGooU H7OlrWJdDZ6EdNbOHALkEHR0geHUgSlh/tZ5 X-Google-Smtp-Source: ABdhPJw85NCHJRPM06/NbacrAfn9GXKTHOb5ituevL4M0vsgNY3Iae4uBFEbbrwKiZQYeWGwvDASHg== X-Received: by 2002:ac2:43b9:: with SMTP id t25mr3003257lfl.349.1620311167827; Thu, 06 May 2021 07:26:07 -0700 (PDT) Received: from DESKTOP-U5LNN3J.localdomain (89-79-189-199.dynamic.chello.pl. [89.79.189.199]) by smtp.gmail.com with ESMTPSA id b40sm892908ljr.101.2021.05.06.07.26.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 May 2021 07:26:07 -0700 (PDT) From: Michal Krawczyk To: dev@dpdk.org Cc: ndagan@amazon.com, gtzalik@amazon.com, igorch@amazon.com, upstream@semihalf.com, Stanislaw Kardach , Michal Krawczyk , Shay Agroskin Date: Thu, 6 May 2021 16:25:23 +0200 Message-Id: <20210506142526.28245-20-mk@semihalf.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210506142526.28245-1-mk@semihalf.com> References: <20210505073348.6394-1-mk@semihalf.com> <20210506142526.28245-1-mk@semihalf.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v3 19/22] net/ena: make ethdev references smp safe X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Stanislaw Kardach rte_pci_device and rte_eth_dev are process-local structures. Therefore ena_adapter::pdev and ena_adapter::rte_dev cannot be used universally. Switch this to extracting those structures via rte_eth_devices indexing and remove pdev since it's not used outside of init. Signed-off-by: Stanislaw Kardach Reviewed-by: Michal Krawczyk Reviewed-by: Igor Chauskin Reviewed-by: Shay Agroskin --- drivers/net/ena/ena_ethdev.c | 47 ++++++++++++++++++------------------ drivers/net/ena/ena_ethdev.h | 5 ++-- 2 files changed, 25 insertions(+), 27 deletions(-) diff --git a/drivers/net/ena/ena_ethdev.c b/drivers/net/ena/ena_ethdev.c index 5c365e1ab5..90ea40513a 100644 --- a/drivers/net/ena/ena_ethdev.c +++ b/drivers/net/ena/ena_ethdev.c @@ -168,6 +168,7 @@ static const struct rte_pci_id pci_id_ena_map[] = { static struct ena_aenq_handlers aenq_handlers; static int ena_device_init(struct ena_com_dev *ena_dev, + struct rte_pci_device *pdev, struct ena_com_dev_get_features_ctx *get_feat_ctx, bool *wd_state); static int ena_dev_configure(struct rte_eth_dev *dev); @@ -451,11 +452,11 @@ static void ena_config_host_info(struct ena_com_dev *ena_dev) } /* This function calculates the number of xstats based on the current config */ -static unsigned int ena_xstats_calc_num(struct rte_eth_dev *dev) +static unsigned int ena_xstats_calc_num(struct rte_eth_dev_data *data) { return ENA_STATS_ARRAY_GLOBAL + ENA_STATS_ARRAY_ENI + - (dev->data->nb_tx_queues * ENA_STATS_ARRAY_TX) + - (dev->data->nb_rx_queues * ENA_STATS_ARRAY_RX); + (data->nb_tx_queues * ENA_STATS_ARRAY_TX) + + (data->nb_rx_queues * ENA_STATS_ARRAY_RX); } static void ena_config_debug_area(struct ena_adapter *adapter) @@ -463,7 +464,7 @@ static void ena_config_debug_area(struct ena_adapter *adapter) u32 debug_area_size; int rc, ss_count; - ss_count = ena_xstats_calc_num(adapter->rte_dev); + ss_count = ena_xstats_calc_num(adapter->edev_data); /* allocate 32 bytes for each string and 64bit for the value */ debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count; @@ -587,7 +588,7 @@ static int ena_rss_reta_update(struct rte_eth_dev *dev, } PMD_DRV_LOG(DEBUG, "%s(): RSS configured %d entries for port %d\n", - __func__, reta_size, adapter->rte_dev->data->port_id); + __func__, reta_size, dev->data->port_id); return 0; } @@ -631,7 +632,7 @@ static int ena_rss_reta_query(struct rte_eth_dev *dev, static int ena_rss_init_default(struct ena_adapter *adapter) { struct ena_com_dev *ena_dev = &adapter->ena_dev; - uint16_t nb_rx_queues = adapter->rte_dev->data->nb_rx_queues; + uint16_t nb_rx_queues = adapter->edev_data->nb_rx_queues; int rc, i; u32 val; @@ -669,8 +670,7 @@ static int ena_rss_init_default(struct ena_adapter *adapter) PMD_DRV_LOG(ERR, "Cannot flush the indirect table\n"); goto err_fill_indir; } - PMD_DRV_LOG(DEBUG, "RSS configured for port %d\n", - adapter->rte_dev->data->port_id); + PMD_DRV_LOG(DEBUG, "RSS configured for port %d\n", adapter->port_id); return 0; @@ -841,10 +841,10 @@ static uint32_t ena_get_mtu_conf(struct ena_adapter *adapter) { uint32_t max_frame_len = adapter->max_mtu; - if (adapter->rte_eth_dev_data->dev_conf.rxmode.offloads & + if (adapter->edev_data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) max_frame_len = - adapter->rte_eth_dev_data->dev_conf.rxmode.max_rx_pkt_len; + adapter->edev_data->dev_conf.rxmode.max_rx_pkt_len; return max_frame_len; } @@ -1064,8 +1064,8 @@ static int ena_start(struct rte_eth_dev *dev) if (rc) goto err_start_tx; - if (adapter->rte_dev->data->dev_conf.rxmode.mq_mode & - ETH_MQ_RX_RSS_FLAG && adapter->rte_dev->data->nb_rx_queues > 0) { + if (adapter->edev_data->dev_conf.rxmode.mq_mode & + ETH_MQ_RX_RSS_FLAG && adapter->edev_data->nb_rx_queues > 0) { rc = ena_rss_init_default(adapter); if (rc) goto err_rss_init; @@ -1505,6 +1505,7 @@ static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count) } static int ena_device_init(struct ena_com_dev *ena_dev, + struct rte_pci_device *pdev, struct ena_com_dev_get_features_ctx *get_feat_ctx, bool *wd_state) { @@ -1522,9 +1523,7 @@ static int ena_device_init(struct ena_com_dev *ena_dev, /* The PCIe configuration space revision id indicate if mmio reg * read is disabled. */ - readless_supported = - !(((struct rte_pci_device *)ena_dev->dmadev)->id.class_id - & ENA_MMIO_DISABLE_REG_READ); + readless_supported = !(pdev->id.class_id & ENA_MMIO_DISABLE_REG_READ); ena_com_set_mmio_read_mode(ena_dev, readless_supported); /* reset device */ @@ -1634,7 +1633,7 @@ static void ena_timer_wd_callback(__rte_unused struct rte_timer *timer, void *arg) { struct ena_adapter *adapter = arg; - struct rte_eth_dev *dev = adapter->rte_dev; + struct rte_eth_dev *dev = &rte_eth_devices[adapter->port_id]; check_for_missing_keep_alive(adapter); check_for_admin_com_state(adapter); @@ -1819,11 +1818,10 @@ static int eth_ena_dev_init(struct rte_eth_dev *eth_dev) memset(adapter, 0, sizeof(struct ena_adapter)); ena_dev = &adapter->ena_dev; - adapter->rte_eth_dev_data = eth_dev->data; - adapter->rte_dev = eth_dev; + adapter->edev_data = eth_dev->data; + adapter->port_id = eth_dev->data->port_id; pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); - adapter->pdev = pci_dev; PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d", pci_dev->addr.domain, @@ -1843,7 +1841,8 @@ static int eth_ena_dev_init(struct rte_eth_dev *eth_dev) } ena_dev->reg_bar = adapter->regs; - ena_dev->dmadev = adapter->pdev; + /* This is a dummy pointer for ena_com functions. */ + ena_dev->dmadev = adapter; adapter->id_number = adapters_found; @@ -1857,7 +1856,7 @@ static int eth_ena_dev_init(struct rte_eth_dev *eth_dev) } /* device specific initialization routine */ - rc = ena_device_init(ena_dev, &get_feat_ctx, &wd_state); + rc = ena_device_init(ena_dev, pci_dev, &get_feat_ctx, &wd_state); if (rc) { PMD_INIT_LOG(CRIT, "Failed to init ENA device"); goto err; @@ -2716,7 +2715,7 @@ static int ena_xstats_get_names(struct rte_eth_dev *dev, struct rte_eth_xstat_name *xstats_names, unsigned int n) { - unsigned int xstats_count = ena_xstats_calc_num(dev); + unsigned int xstats_count = ena_xstats_calc_num(dev->data); unsigned int stat, i, count = 0; if (n < xstats_count || !xstats_names) @@ -2765,7 +2764,7 @@ static int ena_xstats_get(struct rte_eth_dev *dev, unsigned int n) { struct ena_adapter *adapter = dev->data->dev_private; - unsigned int xstats_count = ena_xstats_calc_num(dev); + unsigned int xstats_count = ena_xstats_calc_num(dev->data); unsigned int stat, i, count = 0; int stat_offset; void *stats_begin; @@ -2997,7 +2996,7 @@ static void ena_update_on_link_change(void *adapter_data, adapter = adapter_data; aenq_link_desc = (struct ena_admin_aenq_link_change_desc *)aenq_e; - eth_dev = adapter->rte_dev; + eth_dev = &rte_eth_devices[adapter->port_id]; status = get_ena_admin_aenq_link_change_desc_link_status(aenq_link_desc); adapter->link_status = status; diff --git a/drivers/net/ena/ena_ethdev.h b/drivers/net/ena/ena_ethdev.h index 1f7383dce0..32e92e1d6b 100644 --- a/drivers/net/ena/ena_ethdev.h +++ b/drivers/net/ena/ena_ethdev.h @@ -219,9 +219,8 @@ struct ena_shared_data { /* board specific private data structure */ struct ena_adapter { /* OS defined structs */ - struct rte_pci_device *pdev; - struct rte_eth_dev_data *rte_eth_dev_data; - struct rte_eth_dev *rte_dev; + struct rte_eth_dev_data *edev_data; + int port_id; struct ena_com_dev ena_dev __rte_cache_aligned; From patchwork Thu May 6 14:25:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Krawczyk X-Patchwork-Id: 93025 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9AC62A0524; Thu, 6 May 2021 16:28:15 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id BC9CC4118D; Thu, 6 May 2021 16:26:14 +0200 (CEST) Received: from mail-lf1-f52.google.com (mail-lf1-f52.google.com [209.85.167.52]) by mails.dpdk.org (Postfix) with ESMTP id 0CF9641134 for ; Thu, 6 May 2021 16:26:10 +0200 (CEST) Received: by mail-lf1-f52.google.com with SMTP id j10so8019560lfb.12 for ; Thu, 06 May 2021 07:26:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=XqLFWwFfQzvhqGVnyC/bfONOpaXwYUdQmB1U7FEKRIU=; b=HJgLkvEvjQE7IBxeC/z0FT6CHQdNb2lJtwHL1hpkEw3MP4Ix0vgZ3vRwNRF7fCovju Yb1A+szLy/01kE0rHNF/muxBDKX8i8Ommiy5vh4vG5J3QSZaeHmrV4ONYKAwwFqIXqgm 9e4R7x1qW3AUDtCYG8IFLigIDSeTrZ6iuJrMLwbmpDk/f7Cnaw2ibmtlxIE4NZPtRpyw fvDtil5XicjBFsdWCqFfF2W7CoR5J9tYoWS8/vgSS0jpwHr+ocyXMGiXWyjkOgiT0E2n pTmF5lsjWKxKPwdq1oK2Kg9BtUtG2wG/0iJj2PFsjGtaGi+sVU401QeZKdzPl4rHXd9i yukw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XqLFWwFfQzvhqGVnyC/bfONOpaXwYUdQmB1U7FEKRIU=; b=ljBYGQIRzwmSrGLb73sE6++886DP9itUk6YSYQwSKcWohpnvOWHp48SrSn8+qGam4C tZI5/b+K+4vJRqabX62oxYdNWgIGxqNv8ZcXfrtuKy/XWzS1+U3vKOEqNgUxMgkOt0hc A0s6/IIQtCZizT81wBTtXHbA1r+ifH852my64Gj7o8AG78e7e2krUmkUZ7eIt02qlJeD LUHgIEADLkUZM5I9gE6SOMDePJ6lnZ8dwQ1SFU0J+DDzM/HrSpTArgyr4D1t4lNmFTW9 XGnj82TBZNn/6TUh9ypDJp2IhZhqt7Q5288nlsNvVJkszih2N8TWq7EFdE717d4UEom5 AgDQ== X-Gm-Message-State: AOAM532UXCfSHf4wBCUi3iOAIkLyH3SZN+4CDPunzHzfI+fW1C3wgUib layxBM+0VNoJT2iwCA278QMTDtgqJm5joyXy X-Google-Smtp-Source: ABdhPJxC40/fyBV7Hab0s8kWF0iZXLWJRNY4VWuCElR5Ea1mv9AymRB/DJzUlv5KPysQsrYBg73UJw== X-Received: by 2002:ac2:5059:: with SMTP id a25mr3045121lfm.484.1620311169247; Thu, 06 May 2021 07:26:09 -0700 (PDT) Received: from DESKTOP-U5LNN3J.localdomain (89-79-189-199.dynamic.chello.pl. [89.79.189.199]) by smtp.gmail.com with ESMTPSA id b40sm892908ljr.101.2021.05.06.07.26.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 May 2021 07:26:08 -0700 (PDT) From: Michal Krawczyk To: dev@dpdk.org Cc: ndagan@amazon.com, gtzalik@amazon.com, igorch@amazon.com, upstream@semihalf.com, Stanislaw Kardach , Michal Krawczyk , Shay Agroskin Date: Thu, 6 May 2021 16:25:24 +0200 Message-Id: <20210506142526.28245-21-mk@semihalf.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210506142526.28245-1-mk@semihalf.com> References: <20210505073348.6394-1-mk@semihalf.com> <20210506142526.28245-1-mk@semihalf.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v3 20/22] net/ena: disable dev_ops not supported in SMP X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Stanislaw Kardach For dev_ops not supported in SMP, either return -EPERM or return without doing anything. In both cases log a warning. Signed-off-by: Stanislaw Kardach Reviewed-by: Michal Krawczyk Reviewed-by: Igor Chauskin Reviewed-by: Shay Agroskin --- drivers/net/ena/ena_ethdev.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/net/ena/ena_ethdev.c b/drivers/net/ena/ena_ethdev.c index 90ea40513a..73e99e956a 100644 --- a/drivers/net/ena/ena_ethdev.c +++ b/drivers/net/ena/ena_ethdev.c @@ -529,6 +529,12 @@ ena_dev_reset(struct rte_eth_dev *dev) { int rc = 0; + /* Cannot release memory in secondary process */ + if (rte_eal_process_type() != RTE_PROC_PRIMARY) { + PMD_DRV_LOG(WARNING, "dev_reset not supported in secondary.\n"); + return -EPERM; + } + ena_destroy_device(dev); rc = eth_ena_dev_init(dev); if (rc) @@ -1052,6 +1058,12 @@ static int ena_start(struct rte_eth_dev *dev) uint64_t ticks; int rc = 0; + /* Cannot allocate memory in secondary process */ + if (rte_eal_process_type() != RTE_PROC_PRIMARY) { + PMD_DRV_LOG(WARNING, "dev_start not supported in secondary.\n"); + return -EPERM; + } + rc = ena_check_valid_conf(adapter); if (rc) return rc; @@ -1098,6 +1110,12 @@ static int ena_stop(struct rte_eth_dev *dev) struct ena_com_dev *ena_dev = &adapter->ena_dev; int rc; + /* Cannot free memory in secondary process */ + if (rte_eal_process_type() != RTE_PROC_PRIMARY) { + PMD_DRV_LOG(WARNING, "dev_stop not supported in secondary.\n"); + return -EPERM; + } + rte_timer_stop_sync(&adapter->timer_wd); ena_queue_stop_all(dev, ENA_RING_TYPE_TX); ena_queue_stop_all(dev, ENA_RING_TYPE_RX); From patchwork Thu May 6 14:25:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Krawczyk X-Patchwork-Id: 93026 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 26EF6A0524; Thu, 6 May 2021 16:28:22 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1CF1B41198; Thu, 6 May 2021 16:26:16 +0200 (CEST) Received: from mail-lf1-f44.google.com (mail-lf1-f44.google.com [209.85.167.44]) by mails.dpdk.org (Postfix) with ESMTP id 65E314003F for ; Thu, 6 May 2021 16:26:11 +0200 (CEST) Received: by mail-lf1-f44.google.com with SMTP id z13so8101384lft.1 for ; Thu, 06 May 2021 07:26:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OVjiNi3rEM6c2TPW5cj3QlpdyHt7FsIV4QxsJDBzno0=; b=TZTIKLyavPOw4IMAhcUX7ZurVRsJzaPmEISAwtTj0vc8ePRrNL8DAEVOyHJK6Ze4DK zwk6q0FKYuG8h/VJmYQdIoM3KIezazmffLgxxClpxAgLBDy5zh5jUEM/7v63OAn2T5sh 23S1tnCSCMsaRS8BhlRUlTBCMKdxQ/pRV2H+XKiBNOjMPXuX9Cq5bD/o8oTit1lHPji0 Ck5SGtW0htknkCHa6yjWKBm8lY5F1c8MPLIgJr5IeNW05Jnv6ADI+NCeEnByqjJzNQCL h0lhfH5LlnXPIhM7jmNUBP4hvvADiHjjIcXAzUl+D9+4iRE4AjnBY1vkYRWJeGpIffhO YP8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OVjiNi3rEM6c2TPW5cj3QlpdyHt7FsIV4QxsJDBzno0=; b=qJ75Owje3ZGkd2+ZMmYCYTRS1A2fRCilB6oToad2roHa6cSi73bvS2xxSjF0/fOv9w sskm4YdrbrXfyIg+TY4GZNIXiAocUUoQi8s2oAgzZGnfgu9INw9O7p8EvRpQl/Pa5HbA vMH0G2xhgkrwaF2/HmdGZ4uVyeRWUN3x9p/qxQGCfIER5hJVspH80lwjbPBzPAwbJtKs c8JgHvuDfM3sa92ipdDY9M3oUMZC/IIBQu6FF3RZUKQcPrrv9cSc72b9RzMhikFqGPys 5nAZNtZ5ZZ4gZbT2GT2tdeENYn1Cz9jEkqZXYlvrt/EsPBmhaeBd+5ukco7SqYZ3o25v vpAg== X-Gm-Message-State: AOAM5300KtqSq8U4my9shUqNJyGDHup68tIelaMxL1a7jaeoSam1E1Lp J/5zkCnpa+ws9oqtnwOua0NvdlpFdjjOpncC X-Google-Smtp-Source: ABdhPJyDZGMunzAuvua64pfnVubDUuK8d6jIHbdChe60zAo2f8j/wBISOYCdYPhBFrawDUnA2OyF6Q== X-Received: by 2002:ac2:5626:: with SMTP id b6mr3185499lff.147.1620311170742; Thu, 06 May 2021 07:26:10 -0700 (PDT) Received: from DESKTOP-U5LNN3J.localdomain (89-79-189-199.dynamic.chello.pl. [89.79.189.199]) by smtp.gmail.com with ESMTPSA id b40sm892908ljr.101.2021.05.06.07.26.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 May 2021 07:26:10 -0700 (PDT) From: Michal Krawczyk To: dev@dpdk.org Cc: ndagan@amazon.com, gtzalik@amazon.com, igorch@amazon.com, upstream@semihalf.com, Stanislaw Kardach , stable@dpdk.org, Michal Krawczyk , Shay Agroskin Date: Thu, 6 May 2021 16:25:25 +0200 Message-Id: <20210506142526.28245-22-mk@semihalf.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210506142526.28245-1-mk@semihalf.com> References: <20210505073348.6394-1-mk@semihalf.com> <20210506142526.28245-1-mk@semihalf.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v3 21/22] net/ena: report default ring size X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Stanislaw Kardach Remove invalid ring size alignment logic and add default rx and tx port ring sizes to the device info spec. The logic in lines 1297 and 1371 is invalid. The RTE_ETH_DEV_FALLBACK_RX_RINGSIZE (and the TX counterpart) is a value that rte_eth_rx_queue_setup() will set if dev_info.default_rxportconf.ring_size is 0 and user provided 0 in nb_rx_desc argument. However the current code treats it as a hint for the PMD to change the ring size to internal defaults. Additionally since the ENA_DEFAULT_RING_SIZE is defined, report it in the device capabilities so that both rte_ethdev code and the user can utilize it for device configuration. Fixes: ea93d37eb49d ("net/ena: add HW queues depth setup") Cc: stable@dpdk.org Signed-off-by: Stanislaw Kardach Reviewed-by: Michal Krawczyk Reviewed-by: Igor Chauskin Reviewed-by: Shay Agroskin --- drivers/net/ena/ena_ethdev.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/drivers/net/ena/ena_ethdev.c b/drivers/net/ena/ena_ethdev.c index 73e99e956a..c5d8e7d43e 100644 --- a/drivers/net/ena/ena_ethdev.c +++ b/drivers/net/ena/ena_ethdev.c @@ -1294,9 +1294,6 @@ static int ena_tx_queue_setup(struct rte_eth_dev *dev, return -EINVAL; } - if (nb_desc == RTE_ETH_DEV_FALLBACK_TX_RINGSIZE) - nb_desc = adapter->max_tx_ring_size; - txq->port_id = dev->data->port_id; txq->next_to_clean = 0; txq->next_to_use = 0; @@ -1368,9 +1365,6 @@ static int ena_rx_queue_setup(struct rte_eth_dev *dev, return ENA_COM_FAULT; } - if (nb_desc == RTE_ETH_DEV_FALLBACK_RX_RINGSIZE) - nb_desc = adapter->max_rx_ring_size; - if (!rte_is_power_of_2(nb_desc)) { PMD_DRV_LOG(ERR, "Unsupported size of RX queue: %d is not a power of 2.\n", @@ -2130,6 +2124,9 @@ static int ena_infos_get(struct rte_eth_dev *dev, dev_info->tx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS, adapter->max_tx_sgl_size); + dev_info->default_rxportconf.ring_size = ENA_DEFAULT_RING_SIZE; + dev_info->default_txportconf.ring_size = ENA_DEFAULT_RING_SIZE; + return 0; } From patchwork Thu May 6 14:25:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Krawczyk X-Patchwork-Id: 93027 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 68D17A0524; Thu, 6 May 2021 16:28:28 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 4CC874119E; Thu, 6 May 2021 16:26:17 +0200 (CEST) Received: from mail-lf1-f44.google.com (mail-lf1-f44.google.com [209.85.167.44]) by mails.dpdk.org (Postfix) with ESMTP id A41C641159 for ; Thu, 6 May 2021 16:26:12 +0200 (CEST) Received: by mail-lf1-f44.google.com with SMTP id t11so8024345lfl.11 for ; Thu, 06 May 2021 07:26:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/Zqi93q/imlecb9g+y3ZvBJrDuFiY+D1ypNp9lgdY8o=; b=QuY2XDhvz0hJJvum5bAD1cU28TONcHa8fl/nGBlYdMQ2nmBvqHSgZSEcYFZNZbq8Ud I2K7Z1hfX38NZBL4AWSLG/DIS9Mztn91NBPdZqMjFrlzPoCXCKuzaETuOWAhqIN1BcAc a8RXvfzbtbgrlC9Ery3+Ng9xQsd76GNiUhTwmiKXs+4tkqCRaZAaql0o3PgefDHzs6NZ uODEqZQQZYdlzqTreAwK6vgIdNH8Tx2JcM3+a0zfnsI0k2M27JresZ/Q4NLiM0aunk5B /Rsr41AwtzoEwnvRCazH42zX5Enjp1h7GcBod8QBEUEEdBwKvN9A38PdzgebNerHHe0T Cl6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/Zqi93q/imlecb9g+y3ZvBJrDuFiY+D1ypNp9lgdY8o=; b=JiYe7oqmCir3Cw+WLf3XW+abE36qp00RB0k+T1xW5VABlNXAouR9aBsEoNahPNUt9A SmuPIpSurSjr/xw3VHjjL88TtxaIOaDdtNevGjoWo0BSgQuwtJEF9salnJGtN/DPF6JS a9rDoODcaKPaTzmYBpwleAs8L7FCqGdRI46oeiVDUwPznqVpcgeetIl3BpCzgF6fpv55 Nxaf7cD496dR+0SE1FiXZDEpRlYFxVm7uFX0WeVDt0kw2RcqkU9ta2nY0OH72CfUGvjr UaC8gayb47BKDPvOLJuHkXz93lKeeHWL8obn1hFJMlFh7f/uTcapgP2uHA+Roaz4Ep6V wLGQ== X-Gm-Message-State: AOAM530EGcQ29BqGyQ3TzqfMbiOLSdIEyzmunnZXURtpDT5X0e1Q11tl r+QdZEYAglI117wzrFdf42bFXuR4F6DZZ6Yv X-Google-Smtp-Source: ABdhPJwJq3w5NzKgUc8howVAkkqTbbvDyOLYsZoQnKMA6MyYReIzITB/kwzJMYf7WSCUuavYv4sAbg== X-Received: by 2002:ac2:5471:: with SMTP id e17mr3044326lfn.630.1620311171983; Thu, 06 May 2021 07:26:11 -0700 (PDT) Received: from DESKTOP-U5LNN3J.localdomain (89-79-189-199.dynamic.chello.pl. [89.79.189.199]) by smtp.gmail.com with ESMTPSA id b40sm892908ljr.101.2021.05.06.07.26.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 May 2021 07:26:11 -0700 (PDT) From: Michal Krawczyk To: dev@dpdk.org Cc: ndagan@amazon.com, gtzalik@amazon.com, igorch@amazon.com, upstream@semihalf.com, Michal Krawczyk Date: Thu, 6 May 2021 16:25:26 +0200 Message-Id: <20210506142526.28245-23-mk@semihalf.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210506142526.28245-1-mk@semihalf.com> References: <20210505073348.6394-1-mk@semihalf.com> <20210506142526.28245-1-mk@semihalf.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v3 22/22] net/ena: update version to v2.3.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This version update contains: * memcpy mapping to the dpdk-optimized version. * ena_com (HAL) update to the latest version. * Bug fixes for the large LLQ headers and devargs parsing. * Mbuf RSS hash presence indication. * Bug fix for the default ring size. * Various fixes for SMP mode (although ENA is not fully MP aware, yet). Signed-off-by: Michal Krawczyk --- v3: * Fix typo in the commit log (double "the") doc/guides/rel_notes/release_21_05.rst | 13 +++++++++++++ drivers/net/ena/ena_ethdev.c | 4 ++-- 2 files changed, 15 insertions(+), 2 deletions(-) diff --git a/doc/guides/rel_notes/release_21_05.rst b/doc/guides/rel_notes/release_21_05.rst index 30dec1c1d1..8cf9afa050 100644 --- a/doc/guides/rel_notes/release_21_05.rst +++ b/doc/guides/rel_notes/release_21_05.rst @@ -287,6 +287,19 @@ New Features * Added support for crypto adapter forward mode in octeontx2 event and crypto device driver. +* **Updated Amazon ENA PMD.** + + The new driver version (v2.3.0) introduces bug fixes and improvements, + including: + + * Changed memcpy mapping to the dpdk-optimized version. + * Updated ena_com (HAL) to the latest version. + * Fixed bugs when requesting large LLQ headers using the devargs. + * Added indication of the RSS hash presence in the mbuf. + * Fixed bug when the default ring size was set. + * Add multiple fixes for the SMP mode (although ENA is not fully MP aware, + yet). + Removed Items ------------- diff --git a/drivers/net/ena/ena_ethdev.c b/drivers/net/ena/ena_ethdev.c index c5d8e7d43e..e1e086f31e 100644 --- a/drivers/net/ena/ena_ethdev.c +++ b/drivers/net/ena/ena_ethdev.c @@ -27,8 +27,8 @@ #include #define DRV_MODULE_VER_MAJOR 2 -#define DRV_MODULE_VER_MINOR 2 -#define DRV_MODULE_VER_SUBMINOR 1 +#define DRV_MODULE_VER_MINOR 3 +#define DRV_MODULE_VER_SUBMINOR 0 #define ENA_IO_TXQ_IDX(q) (2 * (q)) #define ENA_IO_RXQ_IDX(q) (2 * (q) + 1)