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GET /api/patches/85928/?format=api
{ "id": 85928, "url": "http://patches.dpdk.org/api/patches/85928/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20201231072247.5719-16-pnalla@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20201231072247.5719-16-pnalla@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20201231072247.5719-16-pnalla@marvell.com", "date": "2020-12-31T07:22:47", "name": "[15/15] net/octeontx_ep: Input output reset.", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "51e5e89888f065ee5d323845d53dac673ee14806", "submitter": { "id": 2074, "url": "http://patches.dpdk.org/api/people/2074/?format=api", "name": "Pradeep Nalla", "email": "pnalla@marvell.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20201231072247.5719-16-pnalla@marvell.com/mbox/", "series": [ { "id": 14507, "url": "http://patches.dpdk.org/api/series/14507/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=14507", "date": "2020-12-31T07:22:32", "name": "Octeon Tx/Tx2 Endpoint pmd", "version": 1, "mbox": "http://patches.dpdk.org/series/14507/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/85928/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/85928/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (xvm-189-124.dc0.ghst.net [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 4CB04A0A00;\n\tThu, 31 Dec 2020 08:25:47 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 1A78B140D5E;\n\tThu, 31 Dec 2020 08:23:19 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 9F21A140CF9\n for <dev@dpdk.org>; Thu, 31 Dec 2020 08:23:02 +0100 (CET)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 0BV7G0IR022182 for <dev@dpdk.org>; Wed, 30 Dec 2020 23:23:01 -0800", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0a-0016f401.pphosted.com with ESMTP id 35rqgehx5e-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Wed, 30 Dec 2020 23:23:01 -0800", "from SC-EXCH02.marvell.com (10.93.176.82) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Wed, 30 Dec 2020 23:23:00 -0800", "from DC5-EXCH01.marvell.com (10.69.176.38) by SC-EXCH02.marvell.com\n (10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Wed, 30 Dec 2020 23:22:58 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Wed, 30 Dec 2020 23:22:59 -0800", "from localhost.localdomain (unknown [10.111.145.157])\n by maili.marvell.com (Postfix) with ESMTP id 1AECB3F703F;\n Wed, 30 Dec 2020 23:22:59 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=/Hh+tASQ29NcEtRh6iSucHzAcyghwKoCjv0if48wz8U=;\n b=BE5pN2yCvKycTH08x2iiNWd3zpnrto+bqD505CTlsk6G8M6+xb2c7sCvYmYyhUcrgyKg\n K9/clf2M/7oWi4ufTvqtungyE3qnV1ByEZdELK10YYIeFRH41NMbP+tPNuhDLYQpsZhY\n /mbi8WqtsQ1IsKd8SYm5QKJpB7iU/im7Pn5LJu64IFfvY8IK3wKQEte8px/X+6BGcoOC\n twIhpRGR/2/Dbume3vyxrmn6/KUAszMKzBUhZBVSuJu1vQnT8YP7aNH6lMl4I8Jr//JS\n os7GA69uXWcOFM/ZDbGT7vQ1udYaJeKjHB8gUyoZdAwOLdAgs1KS5YURjy9zD0qZc7sQ BA==", "From": "\"Nalla, Pradeep\" <pnalla@marvell.com>", "To": "\"Nalla, Pradeep\" <pnalla@marvell.com>, Radha Mohan Chintakuntla\n <radhac@marvell.com>, Veerasenareddy Burru <vburru@marvell.com>", "CC": "<jerinj@marvell.com>, <sburla@marvell.com>, <dev@dpdk.org>", "Date": "Thu, 31 Dec 2020 07:22:47 +0000", "Message-ID": "<20201231072247.5719-16-pnalla@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20201231072247.5719-1-pnalla@marvell.com>", "References": "<20201231072247.5719-1-pnalla@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.343, 18.0.737\n definitions=2020-12-31_02:2020-12-30,\n 2020-12-31 signatures=0", "Subject": "[dpdk-dev] [PATCH 15/15] net/octeontx_ep: Input output reset.", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: \"Nalla Pradeep\" <pnalla@marvell.com>\n\nFunction to allow resetting input and output queues are added. Supports\nboth otx and otx2 endpoints.\n\nSigned-off-by: Nalla Pradeep <pnalla@marvell.com>\n---\n drivers/net/octeontx_ep/otx2_ep_vf.c | 120 ++++++++++++++++++++++\n drivers/net/octeontx_ep/otx_ep_vf.c | 143 +++++++++++++++++++++++++++\n 2 files changed, 263 insertions(+)", "diff": "diff --git a/drivers/net/octeontx_ep/otx2_ep_vf.c b/drivers/net/octeontx_ep/otx2_ep_vf.c\nindex 0fb8c26a5e..095c43b05a 100644\n--- a/drivers/net/octeontx_ep/otx2_ep_vf.c\n+++ b/drivers/net/octeontx_ep/otx2_ep_vf.c\n@@ -7,6 +7,96 @@\n #include \"otx_ep_common.h\"\n #include \"otx2_ep_vf.h\"\n \n+static int\n+otx2_vf_reset_iq(struct otx_ep_device *otx_ep, int q_no)\n+{\n+\tuint64_t loop = SDP_VF_BUSY_LOOP_COUNT;\n+\tvolatile uint64_t d64 = 0ull;\n+\n+\t/* There is no RST for a ring.\n+\t * Clear all registers one by one after disabling the ring\n+\t */\n+\n+\totx2_write64(d64, otx_ep->hw_addr + SDP_VF_R_IN_ENABLE(q_no));\n+\totx2_write64(d64, otx_ep->hw_addr + SDP_VF_R_IN_INSTR_BADDR(q_no));\n+\totx2_write64(d64, otx_ep->hw_addr + SDP_VF_R_IN_INSTR_RSIZE(q_no));\n+\n+\td64 = 0xFFFFFFFF; /* ~0ull */\n+\totx2_write64(d64, otx_ep->hw_addr + SDP_VF_R_IN_INSTR_DBELL(q_no));\n+\td64 = otx2_read64(otx_ep->hw_addr + SDP_VF_R_IN_INSTR_DBELL(q_no));\n+\n+\twhile ((d64 != 0) && loop--) {\n+\t\totx2_write64(d64, otx_ep->hw_addr +\n+\t\t\t SDP_VF_R_IN_INSTR_DBELL(q_no));\n+\n+\t\trte_delay_ms(1);\n+\n+\t\td64 = otx2_read64(otx_ep->hw_addr +\n+\t\t\t\t SDP_VF_R_IN_INSTR_DBELL(q_no));\n+\t}\n+\n+\tloop = SDP_VF_BUSY_LOOP_COUNT;\n+\td64 = otx2_read64(otx_ep->hw_addr + SDP_VF_R_IN_CNTS(q_no));\n+\twhile ((d64 != 0) && loop--) {\n+\t\totx2_write64(d64, otx_ep->hw_addr + SDP_VF_R_IN_CNTS(q_no));\n+\n+\t\trte_delay_ms(1);\n+\n+\t\td64 = otx2_read64(otx_ep->hw_addr + SDP_VF_R_IN_CNTS(q_no));\n+\t}\n+\n+\td64 = 0ull;\n+\totx2_write64(d64, otx_ep->hw_addr + SDP_VF_R_IN_INT_LEVELS(q_no));\n+\totx2_write64(d64, otx_ep->hw_addr + SDP_VF_R_IN_PKT_CNT(q_no));\n+\totx2_write64(d64, otx_ep->hw_addr + SDP_VF_R_IN_BYTE_CNT(q_no));\n+\n+\treturn 0;\n+}\n+\n+static int\n+otx2_vf_reset_oq(struct otx_ep_device *otx_ep, int q_no)\n+{\n+\tuint64_t loop = SDP_VF_BUSY_LOOP_COUNT;\n+\tvolatile uint64_t d64 = 0ull;\n+\n+\totx2_write64(d64, otx_ep->hw_addr + SDP_VF_R_OUT_ENABLE(q_no));\n+\n+\totx2_write64(d64, otx_ep->hw_addr + SDP_VF_R_OUT_SLIST_BADDR(q_no));\n+\n+\totx2_write64(d64, otx_ep->hw_addr + SDP_VF_R_OUT_SLIST_RSIZE(q_no));\n+\n+\td64 = 0xFFFFFFFF;\n+\totx2_write64(d64, otx_ep->hw_addr + SDP_VF_R_OUT_SLIST_DBELL(q_no));\n+\td64 = otx2_read64(otx_ep->hw_addr + SDP_VF_R_OUT_SLIST_DBELL(q_no));\n+\n+\twhile ((d64 != 0) && loop--) {\n+\t\totx2_write64(d64, otx_ep->hw_addr +\n+\t\t\t SDP_VF_R_OUT_SLIST_DBELL(q_no));\n+\n+\t\trte_delay_ms(1);\n+\n+\t\td64 = otx2_read64(otx_ep->hw_addr +\n+\t\t\t\t SDP_VF_R_OUT_SLIST_DBELL(q_no));\n+\t}\n+\n+\tloop = SDP_VF_BUSY_LOOP_COUNT;\n+\td64 = otx2_read64(otx_ep->hw_addr + SDP_VF_R_OUT_CNTS(q_no));\n+\twhile ((d64 != 0) && (loop--)) {\n+\t\totx2_write64(d64, otx_ep->hw_addr + SDP_VF_R_OUT_CNTS(q_no));\n+\n+\t\trte_delay_ms(1);\n+\n+\t\td64 = otx2_read64(otx_ep->hw_addr + SDP_VF_R_OUT_CNTS(q_no));\n+\t}\n+\n+\td64 = 0ull;\n+\totx2_write64(d64, otx_ep->hw_addr + SDP_VF_R_OUT_INT_LEVELS(q_no));\n+\totx2_write64(d64, otx_ep->hw_addr + SDP_VF_R_OUT_PKT_CNT(q_no));\n+\totx2_write64(d64, otx_ep->hw_addr + SDP_VF_R_OUT_BYTE_CNT(q_no));\n+\n+\treturn 0;\n+}\n+\n static void\n otx2_vf_setup_global_iq_reg(struct otx_ep_device *otx_ep, int q_no)\n {\n@@ -52,11 +142,39 @@ otx2_vf_setup_global_oq_reg(struct otx_ep_device *otx_ep, int q_no)\n \totx2_write64(reg_val, otx_ep->hw_addr + SDP_VF_R_OUT_CONTROL(q_no));\n }\n \n+static int\n+otx2_vf_reset_input_queues(struct otx_ep_device *otx_ep)\n+{\n+\tuint32_t q_no = 0;\n+\n+\totx_ep_dbg(\"%s :\", __func__);\n+\n+\tfor (q_no = 0; q_no < otx_ep->sriov_info.rings_per_vf; q_no++)\n+\t\totx2_vf_reset_iq(otx_ep, q_no);\n+\n+\treturn 0;\n+}\n+\n+static int\n+otx2_vf_reset_output_queues(struct otx_ep_device *otx_ep)\n+{\n+\tuint64_t q_no = 0ull;\n+\n+\totx_ep_dbg(\" %s :\", __func__);\n+\n+\tfor (q_no = 0; q_no < otx_ep->sriov_info.rings_per_vf; q_no++)\n+\t\totx2_vf_reset_oq(otx_ep, q_no);\n+\n+\treturn 0;\n+}\n+\n static void\n otx2_vf_setup_global_input_regs(struct otx_ep_device *otx_ep)\n {\n \tuint64_t q_no = 0ull;\n \n+\totx2_vf_reset_input_queues(otx_ep);\n+\n \tfor (q_no = 0; q_no < (otx_ep->sriov_info.rings_per_vf); q_no++)\n \t\totx2_vf_setup_global_iq_reg(otx_ep, q_no);\n }\n@@ -66,6 +184,8 @@ otx2_vf_setup_global_output_regs(struct otx_ep_device *otx_ep)\n {\n \tuint32_t q_no;\n \n+\totx2_vf_reset_output_queues(otx_ep);\n+\n \tfor (q_no = 0; q_no < (otx_ep->sriov_info.rings_per_vf); q_no++)\n \t\totx2_vf_setup_global_oq_reg(otx_ep, q_no);\n }\ndiff --git a/drivers/net/octeontx_ep/otx_ep_vf.c b/drivers/net/octeontx_ep/otx_ep_vf.c\nindex a7c9d48dbc..0280802aa1 100644\n--- a/drivers/net/octeontx_ep/otx_ep_vf.c\n+++ b/drivers/net/octeontx_ep/otx_ep_vf.c\n@@ -11,6 +11,114 @@\n #include \"otx_ep_common.h\"\n #include \"otx_ep_vf.h\"\n \n+#ifdef OTX_EP_RESET_IOQ\n+static int\n+otx_ep_reset_iq(struct otx_ep_device *otx_ep, int q_no)\n+{\n+\tuint64_t loop = OTX_EP_BUSY_LOOP_COUNT;\n+\tvolatile uint64_t d64 = 0ull;\n+\n+\t/* There is no RST for a ring.\n+\t * Clear all registers one by one after disabling the ring\n+\t */\n+\n+\totx_ep_write64(d64, otx_ep->hw_addr, OTX_EP_R_IN_ENABLE(q_no));\n+\totx_ep_write64(d64, otx_ep->hw_addr, OTX_EP_R_IN_INSTR_BADDR(q_no));\n+\totx_ep_write64(d64, otx_ep->hw_addr, OTX_EP_R_IN_INSTR_RSIZE(q_no));\n+\n+\td64 = 0xFFFFFFFF; /* ~0ull */\n+\totx_ep_write64(d64, otx_ep->hw_addr, OTX_EP_R_IN_INSTR_DBELL(q_no));\n+\td64 = rte_read64(otx_ep->hw_addr + OTX_EP_R_IN_INSTR_DBELL(q_no));\n+\n+\twhile ((d64 != 0) && loop--) {\n+\t\totx_ep_write64(d64, otx_ep->hw_addr,\n+\t\t\t OTX_EP_R_IN_INSTR_DBELL(q_no));\n+\n+\t\trte_delay_ms(1);\n+\n+\t\td64 = rte_read64(otx_ep->hw_addr +\n+\t\t\t\t OTX_EP_R_IN_INSTR_DBELL(q_no));\n+\t}\n+\tif (loop == 0) {\n+\t\totx_ep_err(\"dbell reset failed\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\tloop = OTX_EP_BUSY_LOOP_COUNT;\n+\td64 = rte_read64(otx_ep->hw_addr + OTX_EP_R_IN_CNTS(q_no));\n+\twhile ((d64 != 0) && loop--) {\n+\t\totx_ep_write64(d64, otx_ep->hw_addr, OTX_EP_R_IN_CNTS(q_no));\n+\n+\t\trte_delay_ms(1);\n+\n+\t\td64 = rte_read64(otx_ep->hw_addr + OTX_EP_R_IN_CNTS(q_no));\n+\t}\n+\tif (loop == 0) {\n+\t\totx_ep_err(\"cnt reset failed\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\td64 = 0ull;\n+\totx_ep_write64(d64, otx_ep->hw_addr, OTX_EP_R_IN_INT_LEVELS(q_no));\n+\totx_ep_write64(d64, otx_ep->hw_addr, OTX_EP_R_IN_PKT_CNT(q_no));\n+\totx_ep_write64(d64, otx_ep->hw_addr, OTX_EP_R_IN_BYTE_CNT(q_no));\n+\n+\treturn 0;\n+}\n+\n+static int\n+otx_ep_reset_oq(struct otx_ep_device *otx_ep, int q_no)\n+{\n+\tuint64_t loop = OTX_EP_BUSY_LOOP_COUNT;\n+\tvolatile uint64_t d64 = 0ull;\n+\n+\totx_ep_write64(d64, otx_ep->hw_addr, OTX_EP_R_OUT_ENABLE(q_no));\n+\n+\totx_ep_write64(d64, otx_ep->hw_addr, OTX_EP_R_OUT_SLIST_BADDR(q_no));\n+\n+\totx_ep_write64(d64, otx_ep->hw_addr, OTX_EP_R_OUT_SLIST_RSIZE(q_no));\n+\n+\td64 = 0xFFFFFFFF;\n+\totx_ep_write64(d64, otx_ep->hw_addr, OTX_EP_R_OUT_SLIST_DBELL(q_no));\n+\td64 = rte_read64(otx_ep->hw_addr + OTX_EP_R_OUT_SLIST_DBELL(q_no));\n+\n+\twhile ((d64 != 0) && loop--) {\n+\t\totx_ep_write64(d64, otx_ep->hw_addr,\n+\t\t\t OTX_EP_R_OUT_SLIST_DBELL(q_no));\n+\n+\t\trte_delay_ms(1);\n+\n+\t\td64 = rte_read64(otx_ep->hw_addr +\n+\t\t\t\t OTX_EP_R_OUT_SLIST_DBELL(q_no));\n+\t}\n+\tif (loop == 0) {\n+\t\totx_ep_err(\"dbell reset failed\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\tloop = OTX_EP_BUSY_LOOP_COUNT;\n+\td64 = rte_read64(otx_ep->hw_addr + OTX_EP_R_OUT_CNTS(q_no));\n+\twhile ((d64 != 0) && (loop--)) {\n+\t\totx_ep_write64(d64, otx_ep->hw_addr, OTX_EP_R_OUT_CNTS(q_no));\n+\n+\t\trte_delay_ms(1);\n+\n+\t\td64 = rte_read64(otx_ep->hw_addr + OTX_EP_R_OUT_CNTS(q_no));\n+\t}\n+\tif (loop == 0) {\n+\t\totx_ep_err(\"cnt reset failed\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\n+\td64 = 0ull;\n+\totx_ep_write64(d64, otx_ep->hw_addr, OTX_EP_R_OUT_INT_LEVELS(q_no));\n+\totx_ep_write64(d64, otx_ep->hw_addr, OTX_EP_R_OUT_PKT_CNT(q_no));\n+\totx_ep_write64(d64, otx_ep->hw_addr, OTX_EP_R_OUT_BYTE_CNT(q_no));\n+\n+\treturn 0;\n+}\n+#endif\n \n static void\n otx_ep_setup_global_iq_reg(struct otx_ep_device *otx_ep, int q_no)\n@@ -64,11 +172,42 @@ otx_ep_setup_global_oq_reg(struct otx_ep_device *otx_ep, int q_no)\n \totx_ep_write64(reg_val, otx_ep->hw_addr, OTX_EP_R_OUT_CONTROL(q_no));\n }\n \n+#ifdef OTX_EP_RESET_IOQ\n+static int\n+otx_ep_reset_input_queues(struct otx_ep_device *otx_ep)\n+{\n+\tuint32_t q_no = 0;\n+\n+\totx_ep_dbg(\"%s :\\n\", __func__);\n+\n+\tfor (q_no = 0; q_no < otx_ep->sriov_info.rings_per_vf; q_no++)\n+\t\totx_ep_reset_iq(otx_ep, q_no);\n+\n+\treturn 0;\n+}\n+\n+static int\n+otx_ep_reset_output_queues(struct otx_ep_device *otx_ep)\n+{\n+\tuint64_t q_no = 0ull;\n+\n+\totx_ep_dbg(\" %s :\\n\", __func__);\n+\n+\tfor (q_no = 0; q_no < otx_ep->sriov_info.rings_per_vf; q_no++)\n+\t\totx_ep_reset_oq(otx_ep, q_no);\n+\n+\treturn 0;\n+}\n+#endif\n+\n static void\n otx_ep_setup_global_input_regs(struct otx_ep_device *otx_ep)\n {\n \tuint64_t q_no = 0ull;\n \n+#ifdef OTX_EP_RESET_IOQ\n+\totx_ep_reset_input_queues(otx_ep);\n+#endif\n \tfor (q_no = 0; q_no < (otx_ep->sriov_info.rings_per_vf); q_no++)\n \t\totx_ep_setup_global_iq_reg(otx_ep, q_no);\n }\n@@ -78,8 +217,12 @@ otx_ep_setup_global_output_regs(struct otx_ep_device *otx_ep)\n {\n \tuint32_t q_no;\n \n+#ifdef OTX_EP_RESET_IOQ\n+\totx_ep_reset_output_queues(otx_ep);\n+#endif\n \tfor (q_no = 0; q_no < (otx_ep->sriov_info.rings_per_vf); q_no++)\n \t\totx_ep_setup_global_oq_reg(otx_ep, q_no);\n+\n }\n \n static int\n", "prefixes": [ "15/15" ] }