From patchwork Thu Dec 31 07:22:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pradeep Nalla X-Patchwork-Id: 85928 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (xvm-189-124.dc0.ghst.net [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4CB04A0A00; Thu, 31 Dec 2020 08:25:47 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1A78B140D5E; Thu, 31 Dec 2020 08:23:19 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 9F21A140CF9 for ; Thu, 31 Dec 2020 08:23:02 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 0BV7G0IR022182 for ; Wed, 30 Dec 2020 23:23:01 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=/Hh+tASQ29NcEtRh6iSucHzAcyghwKoCjv0if48wz8U=; b=BE5pN2yCvKycTH08x2iiNWd3zpnrto+bqD505CTlsk6G8M6+xb2c7sCvYmYyhUcrgyKg K9/clf2M/7oWi4ufTvqtungyE3qnV1ByEZdELK10YYIeFRH41NMbP+tPNuhDLYQpsZhY /mbi8WqtsQ1IsKd8SYm5QKJpB7iU/im7Pn5LJu64IFfvY8IK3wKQEte8px/X+6BGcoOC twIhpRGR/2/Dbume3vyxrmn6/KUAszMKzBUhZBVSuJu1vQnT8YP7aNH6lMl4I8Jr//JS os7GA69uXWcOFM/ZDbGT7vQ1udYaJeKjHB8gUyoZdAwOLdAgs1KS5YURjy9zD0qZc7sQ BA== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com with ESMTP id 35rqgehx5e-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Wed, 30 Dec 2020 23:23:01 -0800 Received: from SC-EXCH02.marvell.com (10.93.176.82) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 30 Dec 2020 23:23:00 -0800 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by SC-EXCH02.marvell.com (10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 30 Dec 2020 23:22:58 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 30 Dec 2020 23:22:59 -0800 Received: from localhost.localdomain (unknown [10.111.145.157]) by maili.marvell.com (Postfix) with ESMTP id 1AECB3F703F; Wed, 30 Dec 2020 23:22:59 -0800 (PST) From: "Nalla, Pradeep" To: "Nalla, Pradeep" , Radha Mohan Chintakuntla , Veerasenareddy Burru CC: , , Date: Thu, 31 Dec 2020 07:22:47 +0000 Message-ID: <20201231072247.5719-16-pnalla@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201231072247.5719-1-pnalla@marvell.com> References: <20201231072247.5719-1-pnalla@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.343, 18.0.737 definitions=2020-12-31_02:2020-12-30, 2020-12-31 signatures=0 Subject: [dpdk-dev] [PATCH 15/15] net/octeontx_ep: Input output reset. X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: "Nalla Pradeep" Function to allow resetting input and output queues are added. Supports both otx and otx2 endpoints. Signed-off-by: Nalla Pradeep --- drivers/net/octeontx_ep/otx2_ep_vf.c | 120 ++++++++++++++++++++++ drivers/net/octeontx_ep/otx_ep_vf.c | 143 +++++++++++++++++++++++++++ 2 files changed, 263 insertions(+) diff --git a/drivers/net/octeontx_ep/otx2_ep_vf.c b/drivers/net/octeontx_ep/otx2_ep_vf.c index 0fb8c26a5e..095c43b05a 100644 --- a/drivers/net/octeontx_ep/otx2_ep_vf.c +++ b/drivers/net/octeontx_ep/otx2_ep_vf.c @@ -7,6 +7,96 @@ #include "otx_ep_common.h" #include "otx2_ep_vf.h" +static int +otx2_vf_reset_iq(struct otx_ep_device *otx_ep, int q_no) +{ + uint64_t loop = SDP_VF_BUSY_LOOP_COUNT; + volatile uint64_t d64 = 0ull; + + /* There is no RST for a ring. + * Clear all registers one by one after disabling the ring + */ + + otx2_write64(d64, otx_ep->hw_addr + SDP_VF_R_IN_ENABLE(q_no)); + otx2_write64(d64, otx_ep->hw_addr + SDP_VF_R_IN_INSTR_BADDR(q_no)); + otx2_write64(d64, otx_ep->hw_addr + SDP_VF_R_IN_INSTR_RSIZE(q_no)); + + d64 = 0xFFFFFFFF; /* ~0ull */ + otx2_write64(d64, otx_ep->hw_addr + SDP_VF_R_IN_INSTR_DBELL(q_no)); + d64 = otx2_read64(otx_ep->hw_addr + SDP_VF_R_IN_INSTR_DBELL(q_no)); + + while ((d64 != 0) && loop--) { + otx2_write64(d64, otx_ep->hw_addr + + SDP_VF_R_IN_INSTR_DBELL(q_no)); + + rte_delay_ms(1); + + d64 = otx2_read64(otx_ep->hw_addr + + SDP_VF_R_IN_INSTR_DBELL(q_no)); + } + + loop = SDP_VF_BUSY_LOOP_COUNT; + d64 = otx2_read64(otx_ep->hw_addr + SDP_VF_R_IN_CNTS(q_no)); + while ((d64 != 0) && loop--) { + otx2_write64(d64, otx_ep->hw_addr + SDP_VF_R_IN_CNTS(q_no)); + + rte_delay_ms(1); + + d64 = otx2_read64(otx_ep->hw_addr + SDP_VF_R_IN_CNTS(q_no)); + } + + d64 = 0ull; + otx2_write64(d64, otx_ep->hw_addr + SDP_VF_R_IN_INT_LEVELS(q_no)); + otx2_write64(d64, otx_ep->hw_addr + SDP_VF_R_IN_PKT_CNT(q_no)); + otx2_write64(d64, otx_ep->hw_addr + SDP_VF_R_IN_BYTE_CNT(q_no)); + + return 0; +} + +static int +otx2_vf_reset_oq(struct otx_ep_device *otx_ep, int q_no) +{ + uint64_t loop = SDP_VF_BUSY_LOOP_COUNT; + volatile uint64_t d64 = 0ull; + + otx2_write64(d64, otx_ep->hw_addr + SDP_VF_R_OUT_ENABLE(q_no)); + + otx2_write64(d64, otx_ep->hw_addr + SDP_VF_R_OUT_SLIST_BADDR(q_no)); + + otx2_write64(d64, otx_ep->hw_addr + SDP_VF_R_OUT_SLIST_RSIZE(q_no)); + + d64 = 0xFFFFFFFF; + otx2_write64(d64, otx_ep->hw_addr + SDP_VF_R_OUT_SLIST_DBELL(q_no)); + d64 = otx2_read64(otx_ep->hw_addr + SDP_VF_R_OUT_SLIST_DBELL(q_no)); + + while ((d64 != 0) && loop--) { + otx2_write64(d64, otx_ep->hw_addr + + SDP_VF_R_OUT_SLIST_DBELL(q_no)); + + rte_delay_ms(1); + + d64 = otx2_read64(otx_ep->hw_addr + + SDP_VF_R_OUT_SLIST_DBELL(q_no)); + } + + loop = SDP_VF_BUSY_LOOP_COUNT; + d64 = otx2_read64(otx_ep->hw_addr + SDP_VF_R_OUT_CNTS(q_no)); + while ((d64 != 0) && (loop--)) { + otx2_write64(d64, otx_ep->hw_addr + SDP_VF_R_OUT_CNTS(q_no)); + + rte_delay_ms(1); + + d64 = otx2_read64(otx_ep->hw_addr + SDP_VF_R_OUT_CNTS(q_no)); + } + + d64 = 0ull; + otx2_write64(d64, otx_ep->hw_addr + SDP_VF_R_OUT_INT_LEVELS(q_no)); + otx2_write64(d64, otx_ep->hw_addr + SDP_VF_R_OUT_PKT_CNT(q_no)); + otx2_write64(d64, otx_ep->hw_addr + SDP_VF_R_OUT_BYTE_CNT(q_no)); + + return 0; +} + static void otx2_vf_setup_global_iq_reg(struct otx_ep_device *otx_ep, int q_no) { @@ -52,11 +142,39 @@ otx2_vf_setup_global_oq_reg(struct otx_ep_device *otx_ep, int q_no) otx2_write64(reg_val, otx_ep->hw_addr + SDP_VF_R_OUT_CONTROL(q_no)); } +static int +otx2_vf_reset_input_queues(struct otx_ep_device *otx_ep) +{ + uint32_t q_no = 0; + + otx_ep_dbg("%s :", __func__); + + for (q_no = 0; q_no < otx_ep->sriov_info.rings_per_vf; q_no++) + otx2_vf_reset_iq(otx_ep, q_no); + + return 0; +} + +static int +otx2_vf_reset_output_queues(struct otx_ep_device *otx_ep) +{ + uint64_t q_no = 0ull; + + otx_ep_dbg(" %s :", __func__); + + for (q_no = 0; q_no < otx_ep->sriov_info.rings_per_vf; q_no++) + otx2_vf_reset_oq(otx_ep, q_no); + + return 0; +} + static void otx2_vf_setup_global_input_regs(struct otx_ep_device *otx_ep) { uint64_t q_no = 0ull; + otx2_vf_reset_input_queues(otx_ep); + for (q_no = 0; q_no < (otx_ep->sriov_info.rings_per_vf); q_no++) otx2_vf_setup_global_iq_reg(otx_ep, q_no); } @@ -66,6 +184,8 @@ otx2_vf_setup_global_output_regs(struct otx_ep_device *otx_ep) { uint32_t q_no; + otx2_vf_reset_output_queues(otx_ep); + for (q_no = 0; q_no < (otx_ep->sriov_info.rings_per_vf); q_no++) otx2_vf_setup_global_oq_reg(otx_ep, q_no); } diff --git a/drivers/net/octeontx_ep/otx_ep_vf.c b/drivers/net/octeontx_ep/otx_ep_vf.c index a7c9d48dbc..0280802aa1 100644 --- a/drivers/net/octeontx_ep/otx_ep_vf.c +++ b/drivers/net/octeontx_ep/otx_ep_vf.c @@ -11,6 +11,114 @@ #include "otx_ep_common.h" #include "otx_ep_vf.h" +#ifdef OTX_EP_RESET_IOQ +static int +otx_ep_reset_iq(struct otx_ep_device *otx_ep, int q_no) +{ + uint64_t loop = OTX_EP_BUSY_LOOP_COUNT; + volatile uint64_t d64 = 0ull; + + /* There is no RST for a ring. + * Clear all registers one by one after disabling the ring + */ + + otx_ep_write64(d64, otx_ep->hw_addr, OTX_EP_R_IN_ENABLE(q_no)); + otx_ep_write64(d64, otx_ep->hw_addr, OTX_EP_R_IN_INSTR_BADDR(q_no)); + otx_ep_write64(d64, otx_ep->hw_addr, OTX_EP_R_IN_INSTR_RSIZE(q_no)); + + d64 = 0xFFFFFFFF; /* ~0ull */ + otx_ep_write64(d64, otx_ep->hw_addr, OTX_EP_R_IN_INSTR_DBELL(q_no)); + d64 = rte_read64(otx_ep->hw_addr + OTX_EP_R_IN_INSTR_DBELL(q_no)); + + while ((d64 != 0) && loop--) { + otx_ep_write64(d64, otx_ep->hw_addr, + OTX_EP_R_IN_INSTR_DBELL(q_no)); + + rte_delay_ms(1); + + d64 = rte_read64(otx_ep->hw_addr + + OTX_EP_R_IN_INSTR_DBELL(q_no)); + } + if (loop == 0) { + otx_ep_err("dbell reset failed\n"); + return -1; + } + + loop = OTX_EP_BUSY_LOOP_COUNT; + d64 = rte_read64(otx_ep->hw_addr + OTX_EP_R_IN_CNTS(q_no)); + while ((d64 != 0) && loop--) { + otx_ep_write64(d64, otx_ep->hw_addr, OTX_EP_R_IN_CNTS(q_no)); + + rte_delay_ms(1); + + d64 = rte_read64(otx_ep->hw_addr + OTX_EP_R_IN_CNTS(q_no)); + } + if (loop == 0) { + otx_ep_err("cnt reset failed\n"); + return -1; + } + + d64 = 0ull; + otx_ep_write64(d64, otx_ep->hw_addr, OTX_EP_R_IN_INT_LEVELS(q_no)); + otx_ep_write64(d64, otx_ep->hw_addr, OTX_EP_R_IN_PKT_CNT(q_no)); + otx_ep_write64(d64, otx_ep->hw_addr, OTX_EP_R_IN_BYTE_CNT(q_no)); + + return 0; +} + +static int +otx_ep_reset_oq(struct otx_ep_device *otx_ep, int q_no) +{ + uint64_t loop = OTX_EP_BUSY_LOOP_COUNT; + volatile uint64_t d64 = 0ull; + + otx_ep_write64(d64, otx_ep->hw_addr, OTX_EP_R_OUT_ENABLE(q_no)); + + otx_ep_write64(d64, otx_ep->hw_addr, OTX_EP_R_OUT_SLIST_BADDR(q_no)); + + otx_ep_write64(d64, otx_ep->hw_addr, OTX_EP_R_OUT_SLIST_RSIZE(q_no)); + + d64 = 0xFFFFFFFF; + otx_ep_write64(d64, otx_ep->hw_addr, OTX_EP_R_OUT_SLIST_DBELL(q_no)); + d64 = rte_read64(otx_ep->hw_addr + OTX_EP_R_OUT_SLIST_DBELL(q_no)); + + while ((d64 != 0) && loop--) { + otx_ep_write64(d64, otx_ep->hw_addr, + OTX_EP_R_OUT_SLIST_DBELL(q_no)); + + rte_delay_ms(1); + + d64 = rte_read64(otx_ep->hw_addr + + OTX_EP_R_OUT_SLIST_DBELL(q_no)); + } + if (loop == 0) { + otx_ep_err("dbell reset failed\n"); + return -1; + } + + loop = OTX_EP_BUSY_LOOP_COUNT; + d64 = rte_read64(otx_ep->hw_addr + OTX_EP_R_OUT_CNTS(q_no)); + while ((d64 != 0) && (loop--)) { + otx_ep_write64(d64, otx_ep->hw_addr, OTX_EP_R_OUT_CNTS(q_no)); + + rte_delay_ms(1); + + d64 = rte_read64(otx_ep->hw_addr + OTX_EP_R_OUT_CNTS(q_no)); + } + if (loop == 0) { + otx_ep_err("cnt reset failed\n"); + return -1; + } + + + d64 = 0ull; + otx_ep_write64(d64, otx_ep->hw_addr, OTX_EP_R_OUT_INT_LEVELS(q_no)); + otx_ep_write64(d64, otx_ep->hw_addr, OTX_EP_R_OUT_PKT_CNT(q_no)); + otx_ep_write64(d64, otx_ep->hw_addr, OTX_EP_R_OUT_BYTE_CNT(q_no)); + + return 0; +} +#endif static void otx_ep_setup_global_iq_reg(struct otx_ep_device *otx_ep, int q_no) @@ -64,11 +172,42 @@ otx_ep_setup_global_oq_reg(struct otx_ep_device *otx_ep, int q_no) otx_ep_write64(reg_val, otx_ep->hw_addr, OTX_EP_R_OUT_CONTROL(q_no)); } +#ifdef OTX_EP_RESET_IOQ +static int +otx_ep_reset_input_queues(struct otx_ep_device *otx_ep) +{ + uint32_t q_no = 0; + + otx_ep_dbg("%s :\n", __func__); + + for (q_no = 0; q_no < otx_ep->sriov_info.rings_per_vf; q_no++) + otx_ep_reset_iq(otx_ep, q_no); + + return 0; +} + +static int +otx_ep_reset_output_queues(struct otx_ep_device *otx_ep) +{ + uint64_t q_no = 0ull; + + otx_ep_dbg(" %s :\n", __func__); + + for (q_no = 0; q_no < otx_ep->sriov_info.rings_per_vf; q_no++) + otx_ep_reset_oq(otx_ep, q_no); + + return 0; +} +#endif + static void otx_ep_setup_global_input_regs(struct otx_ep_device *otx_ep) { uint64_t q_no = 0ull; +#ifdef OTX_EP_RESET_IOQ + otx_ep_reset_input_queues(otx_ep); +#endif for (q_no = 0; q_no < (otx_ep->sriov_info.rings_per_vf); q_no++) otx_ep_setup_global_iq_reg(otx_ep, q_no); } @@ -78,8 +217,12 @@ otx_ep_setup_global_output_regs(struct otx_ep_device *otx_ep) { uint32_t q_no; +#ifdef OTX_EP_RESET_IOQ + otx_ep_reset_output_queues(otx_ep); +#endif for (q_no = 0; q_no < (otx_ep->sriov_info.rings_per_vf); q_no++) otx_ep_setup_global_oq_reg(otx_ep, q_no); + } static int