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GET /api/patches/85352/?format=api
{ "id": 85352, "url": "http://patches.dpdk.org/api/patches/85352/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20201217173037.11396-19-talshn@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20201217173037.11396-19-talshn@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20201217173037.11396-19-talshn@nvidia.com", "date": "2020-12-17T17:30:20", "name": "[18/35] net/mlx5/windows: initial probing implementation", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "2f4110b24058ed36553f0d9c3d55129bb9afc1a6", "submitter": { "id": 1893, "url": "http://patches.dpdk.org/api/people/1893/?format=api", "name": "Tal Shnaiderman", "email": "talshn@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20201217173037.11396-19-talshn@nvidia.com/mbox/", "series": [ { "id": 14351, "url": "http://patches.dpdk.org/api/series/14351/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=14351", "date": "2020-12-17T17:30:04", "name": "mlx5 Windows support - part #6", "version": 1, "mbox": "http://patches.dpdk.org/series/14351/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/85352/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/85352/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 927DEA09F6;\n\tThu, 17 Dec 2020 18:38:31 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id C6EEFCAE2;\n\tThu, 17 Dec 2020 18:33:35 +0100 (CET)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by dpdk.org (Postfix) with ESMTP id A3DFCCA4D\n for <dev@dpdk.org>; Thu, 17 Dec 2020 18:33:10 +0100 (CET)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n talshn@nvidia.com) with SMTP; 17 Dec 2020 19:33:06 +0200", "from nvidia.com (l-wincomp04-vm.mtl.labs.mlnx [10.237.1.5])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 0BHHX45d021771;\n Thu, 17 Dec 2020 19:33:06 +0200" ], "From": "Tal Shnaiderman <talshn@nvidia.com>", "To": "dev@dpdk.org", "Cc": "thomas@monjalon.net, matan@nvidia.com, rasland@nvidia.com,\n ophirmu@nvidia.com", "Date": "Thu, 17 Dec 2020 19:30:20 +0200", "Message-Id": "<20201217173037.11396-19-talshn@nvidia.com>", "X-Mailer": "git-send-email 2.16.1.windows.4", "In-Reply-To": "<20201217173037.11396-1-talshn@nvidia.com>", "References": "<20201217173037.11396-1-talshn@nvidia.com>", "Subject": "[dpdk-dev] [PATCH 18/35] net/mlx5/windows: initial probing\n\timplementation", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This commit implements mlx5_os_pci_probe API under Windows. It does all\nrequired initializations then it gets the PCI device list using glue API\nget_device_list(). Next, all non MLX5 matched devices are filtered out.\nThe supported NIC types are: CONNECTX4VF, CONNECTX4LXVF, CONNECTX5VF,\nCONNECTX5EXVF, CONNECTX5BFVF, CONNECTX6VF, MELLANOX_CONNECTX6DXVF. Each\ndevice in the list is assigned with default configuration parameters,\nmost of them are 0. The default dv_flow_en parameter value is 1 (which\nmeans Windows match and action flows are based on DV code). Next for\neach PCI device call mlx5_dev_spawn() to create an eth device (struct\nrte_ethdev). The implementation of device spawn is in the follow up\ncommit. Finally, the device list is free.\n\nSigned-off-by: Tal Shnaiderman <talshn@nvidia.com>\nSigned-off-by: Ophir Munk <ophirmu@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/net/mlx5/windows/mlx5_os.c | 268 +++++++++++++++++++++++++++++++++++++\n 1 file changed, 268 insertions(+)", "diff": "diff --git a/drivers/net/mlx5/windows/mlx5_os.c b/drivers/net/mlx5/windows/mlx5_os.c\nindex 14bd5bf39a..7f7e2f8f7c 100644\n--- a/drivers/net/mlx5/windows/mlx5_os.c\n+++ b/drivers/net/mlx5/windows/mlx5_os.c\n@@ -9,6 +9,7 @@\n #include <stdlib.h>\n \n #include <rte_windows.h>\n+#include <rte_ethdev_pci.h>\n \n #include <mlx5_glue.h>\n #include <mlx5_devx_cmds.h>\n@@ -26,6 +27,65 @@\n #include \"mlx5_mr.h\"\n #include \"mlx5_flow.h\"\n \n+static const char *MZ_MLX5_PMD_SHARED_DATA = \"mlx5_pmd_shared_data\";\n+\n+/* Spinlock for mlx5_shared_data allocation. */\n+static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER;\n+\n+/**\n+ * Initialize shared data between primary and secondary process.\n+ *\n+ * A memzone is reserved by primary process and secondary processes attach to\n+ * the memzone.\n+ *\n+ * @return\n+ * 0 on success, a negative errno value otherwise and rte_errno is set.\n+ */\n+static int\n+mlx5_init_shared_data(void)\n+{\n+\tconst struct rte_memzone *mz;\n+\tint ret = 0;\n+\n+\trte_spinlock_lock(&mlx5_shared_data_lock);\n+\tif (mlx5_shared_data == NULL) {\n+\t\t/* Allocate shared memory. */\n+\t\tmz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA,\n+\t\t\t\t\t sizeof(*mlx5_shared_data),\n+\t\t\t\t\t SOCKET_ID_ANY, 0);\n+\t\tif (mz == NULL) {\n+\t\t\tDRV_LOG(ERR,\n+\t\t\t\t\"Cannot allocate mlx5 shared data\");\n+\t\t\tret = -rte_errno;\n+\t\t\tgoto error;\n+\t\t}\n+\t\tmlx5_shared_data = mz->addr;\n+\t\tmemset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data));\n+\t\trte_spinlock_init(&mlx5_shared_data->lock);\n+\t}\n+error:\n+\trte_spinlock_unlock(&mlx5_shared_data_lock);\n+\treturn ret;\n+}\n+\n+/**\n+ * PMD global initialization.\n+ *\n+ * Independent from individual device, this function initializes global\n+ * per-PMD data structures distinguishing primary and secondary processes.\n+ * Hence, each initialization is called once per a process.\n+ *\n+ * @return\n+ * 0 on success, a negative errno value otherwise and rte_errno is set.\n+ */\n+static int\n+mlx5_init_once(void)\n+{\n+\tif (mlx5_init_shared_data())\n+\t\treturn -rte_errno;\n+\treturn 0;\n+}\n+\n /**\n * Get mlx5 device attributes.\n *\n@@ -147,6 +207,31 @@ mlx5_os_open_device(const struct mlx5_dev_spawn_data *spawn,\n \treturn err;\n }\n \n+/**\n+ * Spawn an Ethernet device from Verbs information.\n+ *\n+ * @param dpdk_dev\n+ * Backing DPDK device.\n+ * @param spawn\n+ * Verbs device parameters (name, port, switch_info) to spawn.\n+ * @param config\n+ * Device configuration parameters.\n+ *\n+ * @return\n+ * NULL pointer. Operation is not supported and rte_errno is set to ENOTSUP.\n+ */\n+static struct rte_eth_dev *\n+mlx5_dev_spawn(struct rte_device *dpdk_dev,\n+\t struct mlx5_dev_spawn_data *spawn,\n+\t struct mlx5_dev_config *config)\n+{\n+\t(void)dpdk_dev;\n+\t(void)spawn;\n+\t(void)config;\n+\trte_errno = -ENOTSUP;\n+\treturn NULL;\n+}\n+\n /**\n * This function should share events between multiple ports of single IB\n * device. Currently it has no support under Windows.\n@@ -339,6 +424,189 @@ mlx5_os_set_allmulti(struct rte_eth_dev *dev, int enable)\n \treturn -ENOTSUP;\n }\n \n+/**\n+ * DPDK callback to register a PCI device.\n+ *\n+ * This function spawns Ethernet devices out of a given PCI device.\n+ *\n+ * @param[in] pci_drv\n+ * PCI driver structure (mlx5_driver).\n+ * @param[in] pci_dev\n+ * PCI device information.\n+ *\n+ * @return\n+ * 0 on success, a negative errno value otherwise and rte_errno is set.\n+ */\n+int\n+mlx5_os_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,\n+\t\t struct rte_pci_device *pci_dev)\n+{\n+\tstruct devx_device_bdf *devx_bdf_devs, *orig_devx_bdf_devs;\n+\t/*\n+\t * Number of found IB Devices matching with requested PCI BDF.\n+\t * nd != 1 means there are multiple IB devices over the same\n+\t * PCI device and we have representors and master.\n+\t */\n+\tunsigned int nd = 0;\n+\t/*\n+\t * Number of found IB device Ports. nd = 1 and np = 1..n means\n+\t * we have the single multiport IB device, and there may be\n+\t * representors attached to some of found ports.\n+\t * Currently not supported.\n+\t * unsigned int np = 0;\n+\t */\n+\n+\t/*\n+\t * Number of DPDK ethernet devices to Spawn - either over\n+\t * multiple IB devices or multiple ports of single IB device.\n+\t * Actually this is the number of iterations to spawn.\n+\t */\n+\tunsigned int ns = 0;\n+\t/*\n+\t * Bonding device\n+\t * < 0 - no bonding device (single one)\n+\t * >= 0 - bonding device (value is slave PF index)\n+\t */\n+\tint bd = -1;\n+\tstruct mlx5_dev_spawn_data *list = NULL;\n+\tstruct mlx5_dev_config dev_config;\n+\tunsigned int dev_config_vf;\n+\tint ret;\n+\tuint32_t restore;\n+\n+\tif (rte_eal_process_type() == RTE_PROC_SECONDARY) {\n+\t\tDRV_LOG(ERR, \"Secondary process is not supported on Windows.\");\n+\t\treturn -ENOTSUP;\n+\n+\t}\n+\tret = mlx5_init_once();\n+\tif (ret) {\n+\t\tDRV_LOG(ERR, \"unable to init PMD global data: %s\",\n+\t\t\tstrerror(rte_errno));\n+\t\treturn -rte_errno;\n+\t}\n+\terrno = 0;\n+\tdevx_bdf_devs = mlx5_glue->get_device_list(&ret);\n+\torig_devx_bdf_devs = devx_bdf_devs;\n+\tif (!devx_bdf_devs) {\n+\t\trte_errno = errno ? errno : ENOSYS;\n+\t\tDRV_LOG(ERR, \"cannot list devices, is ib_uverbs loaded?\");\n+\t\treturn -rte_errno;\n+\t}\n+\t/*\n+\t * First scan the list of all Infiniband devices to find\n+\t * matching ones, gathering into the list.\n+\t */\n+\tstruct devx_device_bdf *devx_bdf_match[ret + 1];\n+\n+\twhile (ret-- > 0) {\n+\t\tif (pci_dev->addr.bus != devx_bdf_devs->bus_id ||\n+\t\t pci_dev->addr.devid != devx_bdf_devs->dev_id ||\n+\t\t pci_dev->addr.function != devx_bdf_devs->fnc_id) {\n+\t\t\tdevx_bdf_devs++;\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\tdevx_bdf_match[nd++] = devx_bdf_devs;\n+\t}\n+\tdevx_bdf_match[nd] = NULL;\n+\tif (!nd) {\n+\t\t/* No device matches, just complain and bail out. */\n+\t\tDRV_LOG(WARNING,\n+\t\t\t\"no DevX device matches PCI device \" PCI_PRI_FMT \",\"\n+\t\t\t\" is DevX Configured?\",\n+\t\t\tpci_dev->addr.domain, pci_dev->addr.bus,\n+\t\t\tpci_dev->addr.devid, pci_dev->addr.function);\n+\t\trte_errno = ENOENT;\n+\t\tret = -rte_errno;\n+\t\tgoto exit;\n+\t}\n+\t/*\n+\t * Now we can determine the maximal\n+\t * amount of devices to be spawned.\n+\t */\n+\tlist = mlx5_malloc(MLX5_MEM_ZERO,\n+\t\t\t sizeof(struct mlx5_dev_spawn_data),\n+\t\t\t RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);\n+\tif (!list) {\n+\t\tDRV_LOG(ERR, \"spawn data array allocation failure\");\n+\t\trte_errno = ENOMEM;\n+\t\tret = -rte_errno;\n+\t\tgoto exit;\n+\t}\n+\tmemset(&list[ns].info, 0, sizeof(list[ns].info));\n+\tlist[ns].max_port = 1;\n+\tlist[ns].phys_port = 1;\n+\tlist[ns].phys_dev = devx_bdf_match[ns];\n+\tlist[ns].eth_dev = NULL;\n+\tlist[ns].pci_dev = pci_dev;\n+\tlist[ns].pf_bond = bd;\n+\tlist[ns].ifindex = -1; /* Spawn will assign */\n+\tlist[ns].info =\n+\t\t(struct mlx5_switch_info){\n+\t\t\t.master = 0,\n+\t\t\t.representor = 0,\n+\t\t\t.name_type = MLX5_PHYS_PORT_NAME_TYPE_UPLINK,\n+\t\t\t.port_name = 0,\n+\t\t\t.switch_id = 0,\n+\t\t};\n+\t/* Device specific configuration. */\n+\tswitch (pci_dev->id.device_id) {\n+\tcase PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:\n+\tcase PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:\n+\tcase PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:\n+\tcase PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:\n+\tcase PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF:\n+\tcase PCI_DEVICE_ID_MELLANOX_CONNECTX6VF:\n+\tcase PCI_DEVICE_ID_MELLANOX_CONNECTXVF:\n+\t\tdev_config_vf = 1;\n+\t\tbreak;\n+\tdefault:\n+\t\tdev_config_vf = 0;\n+\t\tbreak;\n+\t}\n+\t/* Default configuration. */\n+\tmemset(&dev_config, 0, sizeof(struct mlx5_dev_config));\n+\tdev_config.vf = dev_config_vf;\n+\tdev_config.mps = 0;\n+\tdev_config.dbnc = MLX5_ARG_UNSET;\n+\tdev_config.rx_vec_en = 1;\n+\tdev_config.txq_inline_max = MLX5_ARG_UNSET;\n+\tdev_config.txq_inline_min = MLX5_ARG_UNSET;\n+\tdev_config.txq_inline_mpw = MLX5_ARG_UNSET;\n+\tdev_config.txqs_inline = MLX5_ARG_UNSET;\n+\tdev_config.vf_nl_en = 0;\n+\tdev_config.mr_ext_memseg_en = 1;\n+\tdev_config.mprq.max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN;\n+\tdev_config.mprq.min_rxqs_num = MLX5_MPRQ_MIN_RXQS;\n+\tdev_config.dv_esw_en = 0;\n+\tdev_config.dv_flow_en = 1;\n+\tdev_config.decap_en = 0;\n+\tdev_config.log_hp_size = MLX5_ARG_UNSET;\n+\tlist[ns].eth_dev = mlx5_dev_spawn(&pci_dev->device,\n+\t\t\t\t\t &list[ns],\n+\t\t\t\t\t &dev_config);\n+\tif (!list[ns].eth_dev)\n+\t\tgoto exit;\n+\trestore = list[ns].eth_dev->data->dev_flags;\n+\trte_eth_copy_pci_info(list[ns].eth_dev, pci_dev);\n+\t/* Restore non-PCI flags cleared by the above call. */\n+\tlist[ns].eth_dev->data->dev_flags |= restore;\n+\trte_eth_dev_probing_finish(list[ns].eth_dev);\n+\tret = 0;\n+exit:\n+\t/*\n+\t * Do the routine cleanup:\n+\t * - free allocated spawn data array\n+\t * - free the device list\n+\t */\n+\tif (list)\n+\t\tmlx5_free(list);\n+\tMLX5_ASSERT(orig_devx_bdf_devs);\n+\tmlx5_glue->free_device_list(orig_devx_bdf_devs);\n+\treturn ret;\n+}\n+\n /**\n * Set the reg_mr and dereg_mr call backs\n *\n", "prefixes": [ "18/35" ] }