From patchwork Thu Dec 17 17:30:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tal Shnaiderman X-Patchwork-Id: 85342 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5C0E7A09F6; Thu, 17 Dec 2020 18:34:40 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 4E6C2CA5A; Thu, 17 Dec 2020 18:33:20 +0100 (CET) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by dpdk.org (Postfix) with ESMTP id 154C5CA3A for ; Thu, 17 Dec 2020 18:33:09 +0100 (CET) Received: from Internal Mail-Server by MTLPINE1 (envelope-from talshn@nvidia.com) with SMTP; 17 Dec 2020 19:33:04 +0200 Received: from nvidia.com (l-wincomp04-vm.mtl.labs.mlnx [10.237.1.5]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 0BHHX45M021771; Thu, 17 Dec 2020 19:33:04 +0200 From: Tal Shnaiderman To: dev@dpdk.org Cc: thomas@monjalon.net, matan@nvidia.com, rasland@nvidia.com, ophirmu@nvidia.com Date: Thu, 17 Dec 2020 19:30:03 +0200 Message-Id: <20201217173037.11396-2-talshn@nvidia.com> X-Mailer: git-send-email 2.16.1.windows.4 In-Reply-To: <20201217173037.11396-1-talshn@nvidia.com> References: <20201217173037.11396-1-talshn@nvidia.com> Subject: [dpdk-dev] [PATCH 01/35] common/mlx5/windows: add missing DV and IBV definitions X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Ophir Munk Add missing DV and IBV definition to file mlx5_win_defs.h. The definitions originated from rdma-core library which is not part of Windows. They are referenced in shared files that must compile under Windows such as mlx5_flow_dv.c and mlx5_rxtx.c. Signed-off-by: Ophir Munk Acked-by: Matan Azrad --- drivers/common/mlx5/windows/mlx5_win_defs.h | 141 ++++++++++++++++++++++++++++ 1 file changed, 141 insertions(+) diff --git a/drivers/common/mlx5/windows/mlx5_win_defs.h b/drivers/common/mlx5/windows/mlx5_win_defs.h index 72a3131f5e..e9569e4431 100644 --- a/drivers/common/mlx5/windows/mlx5_win_defs.h +++ b/drivers/common/mlx5/windows/mlx5_win_defs.h @@ -22,4 +22,145 @@ enum { MLX5_CQE_RESP_ERR = 14, MLX5_CQE_INVALID = 15, }; + +enum { + MLX5_OPCODE_NOP = 0x00, + MLX5_OPCODE_SEND_INVAL = 0x01, + MLX5_OPCODE_RDMA_WRITE = 0x08, + MLX5_OPCODE_RDMA_WRITE_IMM = 0x09, + MLX5_OPCODE_SEND = 0x0a, + MLX5_OPCODE_SEND_IMM = 0x0b, + MLX5_OPCODE_TSO = 0x0e, + MLX5_OPCODE_RDMA_READ = 0x10, + MLX5_OPCODE_ATOMIC_CS = 0x11, + MLX5_OPCODE_ATOMIC_FA = 0x12, + MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14, + MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15, + MLX5_OPCODE_FMR = 0x19, + MLX5_OPCODE_LOCAL_INVAL = 0x1b, + MLX5_OPCODE_CONFIG_CMD = 0x1f, + MLX5_OPCODE_UMR = 0x25, + MLX5_OPCODE_TAG_MATCHING = 0x28 +}; + +enum mlx5dv_cq_init_attr_mask { + MLX5DV_CQ_INIT_ATTR_MASK_COMPRESSED_CQE = 1 << 0, + MLX5DV_CQ_INIT_ATTR_MASK_FLAGS = 1 << 1, + MLX5DV_CQ_INIT_ATTR_MASK_CQE_SIZE = 1 << 2, +}; + +enum mlx5dv_cqe_comp_res_format { + MLX5DV_CQE_RES_FORMAT_HASH = 1 << 0, + MLX5DV_CQE_RES_FORMAT_CSUM = 1 << 1, + MLX5DV_CQE_RES_FORMAT_CSUM_STRIDX = 1 << 2, +}; + +enum ibv_access_flags { + IBV_ACCESS_LOCAL_WRITE = 1, + IBV_ACCESS_REMOTE_WRITE = 1 << 1, + IBV_ACCESS_REMOTE_READ = 1 << 2, + IBV_ACCESS_REMOTE_ATOMIC = 1 << 3, + IBV_ACCESS_MW_BIND = 1 << 4, + IBV_ACCESS_ZERO_BASED = 1 << 5, + IBV_ACCESS_ON_DEMAND = 1 << 6, +}; + +enum mlx5_ib_uapi_devx_create_event_channel_flags { + MLX5_IB_UAPI_DEVX_CR_EV_CH_FLAGS_OMIT_DATA = 1 << 0, +}; + +#define MLX5DV_DEVX_CREATE_EVENT_CHANNEL_FLAGS_OMIT_EV_DATA \ + MLX5_IB_UAPI_DEVX_CR_EV_CH_FLAGS_OMIT_DATA + +enum { + MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR = 0x01, + MLX5_CQE_SYNDROME_LOCAL_QP_OP_ERR = 0x02, + MLX5_CQE_SYNDROME_LOCAL_PROT_ERR = 0x04, + MLX5_CQE_SYNDROME_WR_FLUSH_ERR = 0x05, + MLX5_CQE_SYNDROME_MW_BIND_ERR = 0x06, + MLX5_CQE_SYNDROME_BAD_RESP_ERR = 0x10, + MLX5_CQE_SYNDROME_LOCAL_ACCESS_ERR = 0x11, + MLX5_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR = 0x12, + MLX5_CQE_SYNDROME_REMOTE_ACCESS_ERR = 0x13, + MLX5_CQE_SYNDROME_REMOTE_OP_ERR = 0x14, + MLX5_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR = 0x15, + MLX5_CQE_SYNDROME_RNR_RETRY_EXC_ERR = 0x16, + MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR = 0x22, +}; + +enum { + MLX5_ETH_WQE_L3_CSUM = (1 << 6), + MLX5_ETH_WQE_L4_CSUM = (1 << 7), +}; + +/* + * RX Hash fields enable to set which incoming packet's field should + * participates in RX Hash. Each flag represent certain packet's field, + * when the flag is set the field that is represented by the flag will + * participate in RX Hash calculation. + * Note: IPV4 and IPV6 flags can't be enabled together on the same QP, + * TCP and UDP flags can't be enabled together on the same QP. + */ +enum ibv_rx_hash_fields { + IBV_RX_HASH_SRC_IPV4 = 1 << 0, + IBV_RX_HASH_DST_IPV4 = 1 << 1, + IBV_RX_HASH_SRC_IPV6 = 1 << 2, + IBV_RX_HASH_DST_IPV6 = 1 << 3, + IBV_RX_HASH_SRC_PORT_TCP = 1 << 4, + IBV_RX_HASH_DST_PORT_TCP = 1 << 5, + IBV_RX_HASH_SRC_PORT_UDP = 1 << 6, + IBV_RX_HASH_DST_PORT_UDP = 1 << 7, + IBV_RX_HASH_IPSEC_SPI = 1 << 8, + IBV_RX_HASH_INNER = (1 << 31), +}; + +enum { + MLX5_RCV_DBR = 0, + MLX5_SND_DBR = 1, +}; + +#ifndef MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2 +#define MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2 0x0 +#endif +#ifndef MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL +#define MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL 0x1 +#endif +#ifndef MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 +#define MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 0x2 +#endif +#ifndef MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL +#define MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL 0x3 +#endif + +struct mlx5_err_cqe { + uint8_t rsvd0[32]; + uint32_t srqn; + uint8_t rsvd1[18]; + uint8_t vendor_err_synd; + uint8_t syndrome; + uint32_t s_wqe_opcode_qpn; + uint16_t wqe_counter; + uint8_t signature; + uint8_t op_own; +}; + +struct mlx5_wqe_srq_next_seg { + uint8_t rsvd0[2]; + rte_be16_t next_wqe_index; + uint8_t signature; + uint8_t rsvd1[11]; +}; + +enum ibv_wq_state { + IBV_WQS_RESET, + IBV_WQS_RDY, + IBV_WQS_ERR, + IBV_WQS_UNKNOWN +}; + +struct mlx5_wqe_data_seg { + rte_be32_t byte_count; + rte_be32_t lkey; + rte_be64_t addr; +}; #endif /* __MLX5_WIN_DEFS_H__ */ From patchwork Thu Dec 17 17:30:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tal Shnaiderman X-Patchwork-Id: 85338 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 6395FA09F6; Thu, 17 Dec 2020 18:33:15 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 64B30CA35; Thu, 17 Dec 2020 18:33:12 +0100 (CET) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by dpdk.org (Postfix) with ESMTP id F17E2CA35 for ; Thu, 17 Dec 2020 18:33:09 +0100 (CET) Received: from Internal Mail-Server by MTLPINE1 (envelope-from talshn@nvidia.com) with SMTP; 17 Dec 2020 19:33:04 +0200 Received: from nvidia.com (l-wincomp04-vm.mtl.labs.mlnx [10.237.1.5]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 0BHHX45N021771; Thu, 17 Dec 2020 19:33:04 +0200 From: Tal Shnaiderman To: dev@dpdk.org Cc: thomas@monjalon.net, matan@nvidia.com, rasland@nvidia.com, ophirmu@nvidia.com Date: Thu, 17 Dec 2020 19:30:04 +0200 Message-Id: <20201217173037.11396-3-talshn@nvidia.com> X-Mailer: git-send-email 2.16.1.windows.4 In-Reply-To: <20201217173037.11396-1-talshn@nvidia.com> References: <20201217173037.11396-1-talshn@nvidia.com> Subject: [dpdk-dev] [PATCH 02/35] mlx5/windows: add mlx5 macros for fs name and path X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Ophir Munk ibdev_name and ibdev_path sizes are defined in Windows DevX differently from the sizes used in Linux with IBV_SYSFS_NAME_MAX and IBV_SYSFS_PATH_MAX. Added MLX5_FS_NAME_MAX and MLX5_FS_NAME_PATH in mlx5_os.h for both OSs. Signed-off-by: Tal Shnaiderman Acked-by: Matan Azrad --- drivers/net/mlx5/linux/mlx5_os.h | 4 ++-- drivers/net/mlx5/mlx5.h | 4 ++-- drivers/net/mlx5/windows/mlx5_os.h | 17 +++++++++++++++++ 3 files changed, 21 insertions(+), 4 deletions(-) create mode 100644 drivers/net/mlx5/windows/mlx5_os.h diff --git a/drivers/net/mlx5/linux/mlx5_os.h b/drivers/net/mlx5/linux/mlx5_os.h index 759def2f4b..f38c2f3015 100644 --- a/drivers/net/mlx5/linux/mlx5_os.h +++ b/drivers/net/mlx5/linux/mlx5_os.h @@ -10,8 +10,8 @@ /* verb enumerations translations to local enums. */ enum { - DEV_SYSFS_NAME_MAX = IBV_SYSFS_NAME_MAX + 1, - DEV_SYSFS_PATH_MAX = IBV_SYSFS_PATH_MAX + 1 + MLX5_FS_NAME_MAX = IBV_SYSFS_NAME_MAX + 1, + MLX5_FS_PATH_MAX = IBV_SYSFS_PATH_MAX + 1 }; #define PCI_DRV_FLAGS (RTE_PCI_DRV_INTR_LSC | \ diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index a9db597f2b..e5794744bd 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -701,8 +701,8 @@ struct mlx5_dev_ctx_shared { void *pd; /* Protection Domain. */ uint32_t pdn; /* Protection Domain number. */ uint32_t tdn; /* Transport Domain number. */ - char ibdev_name[DEV_SYSFS_NAME_MAX]; /* SYSFS dev name. */ - char ibdev_path[DEV_SYSFS_PATH_MAX]; /* SYSFS dev path for secondary */ + char ibdev_name[MLX5_FS_NAME_MAX]; /* SYSFS dev name. */ + char ibdev_path[MLX5_FS_PATH_MAX]; /* SYSFS dev path for secondary */ struct mlx5_dev_attr device_attr; /* Device properties. */ int numa_node; /* Numa node of backing physical device. */ LIST_ENTRY(mlx5_dev_ctx_shared) mem_event_cb; diff --git a/drivers/net/mlx5/windows/mlx5_os.h b/drivers/net/mlx5/windows/mlx5_os.h new file mode 100644 index 0000000000..b94f588461 --- /dev/null +++ b/drivers/net/mlx5/windows/mlx5_os.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright 2020 Mellanox Technologies, Ltd + */ + +#ifndef RTE_PMD_MLX5_OS_H_ +#define RTE_PMD_MLX5_OS_H_ + +#include "mlx5_win_ext.h" + +enum { + MLX5_FS_NAME_MAX = MLX5_DEVX_DEVICE_NAME_SIZE + 1, + MLX5_FS_PATH_MAX = MLX5_DEVX_DEVICE_PNP_SIZE + 1 +}; + +#define PCI_DRV_FLAGS 0 + +#endif /* RTE_PMD_MLX5_OS_H_ */ From patchwork Thu Dec 17 17:30:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tal Shnaiderman X-Patchwork-Id: 85340 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8D6F1A09F6; Thu, 17 Dec 2020 18:33:53 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 05635CA49; Thu, 17 Dec 2020 18:33:17 +0100 (CET) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by dpdk.org (Postfix) with ESMTP id ECF23CA2C for ; Thu, 17 Dec 2020 18:33:09 +0100 (CET) Received: from Internal Mail-Server by MTLPINE1 (envelope-from talshn@nvidia.com) with SMTP; 17 Dec 2020 19:33:04 +0200 Received: from nvidia.com (l-wincomp04-vm.mtl.labs.mlnx [10.237.1.5]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 0BHHX45O021771; Thu, 17 Dec 2020 19:33:04 +0200 From: Tal Shnaiderman To: dev@dpdk.org Cc: thomas@monjalon.net, matan@nvidia.com, rasland@nvidia.com, ophirmu@nvidia.com Date: Thu, 17 Dec 2020 19:30:05 +0200 Message-Id: <20201217173037.11396-4-talshn@nvidia.com> X-Mailer: git-send-email 2.16.1.windows.4 In-Reply-To: <20201217173037.11396-1-talshn@nvidia.com> References: <20201217173037.11396-1-talshn@nvidia.com> Subject: [dpdk-dev] [PATCH 03/35] common/mlx5: add rte compatibility header file X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Ophir Munk Add #include to file mlx5_devx_cmds.h. It is required for Windows to identify the __rte_internal definition. Signed-off-by: Ophir Munk Acked-by: Matan Azrad --- drivers/common/mlx5/mlx5_devx_cmds.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h index 8277fdbc39..b335b7c82c 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.h +++ b/drivers/common/mlx5/mlx5_devx_cmds.h @@ -7,6 +7,7 @@ #include "mlx5_glue.h" #include "mlx5_prm.h" +#include /* * Defines the amount of retries to allocate the first UAR in the page. From patchwork Thu Dec 17 17:30:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tal Shnaiderman X-Patchwork-Id: 85372 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8F70CA09F6; Thu, 17 Dec 2020 18:44:52 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 882C0CCEC; Thu, 17 Dec 2020 18:34:02 +0100 (CET) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by dpdk.org (Postfix) with ESMTP id 513CECA41 for ; Thu, 17 Dec 2020 18:33:09 +0100 (CET) Received: from Internal Mail-Server by MTLPINE1 (envelope-from talshn@nvidia.com) with SMTP; 17 Dec 2020 19:33:04 +0200 Received: from nvidia.com (l-wincomp04-vm.mtl.labs.mlnx [10.237.1.5]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 0BHHX45P021771; Thu, 17 Dec 2020 19:33:04 +0200 From: Tal Shnaiderman To: dev@dpdk.org Cc: thomas@monjalon.net, matan@nvidia.com, rasland@nvidia.com, ophirmu@nvidia.com Date: Thu, 17 Dec 2020 19:30:06 +0200 Message-Id: <20201217173037.11396-5-talshn@nvidia.com> X-Mailer: git-send-email 2.16.1.windows.4 In-Reply-To: <20201217173037.11396-1-talshn@nvidia.com> References: <20201217173037.11396-1-talshn@nvidia.com> Subject: [dpdk-dev] [PATCH 04/35] common/mlx5/windows: add DevX UAR getters X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Ophir Munk The following getters are added: mlx5_os_get_devx_uar_mmap_offset, mlx5_os_get_devx_uar_base_addr, mlx5_os_get_devx_uar_reg_addr, mlx5_os_get_devx_uar_page_id. This commit is the Windows equivalent of the Linux implementation in [1]. [1] commit 8638e19a10aa ("net/mlx5: remove more DV dependencies") Signed-off-by: Ophir Munk Acked-by: Matan Azrad --- drivers/common/mlx5/windows/mlx5_common_os.h | 75 ++++++++++++++++++++++++++++ 1 file changed, 75 insertions(+) diff --git a/drivers/common/mlx5/windows/mlx5_common_os.h b/drivers/common/mlx5/windows/mlx5_common_os.h index ba166412cc..ac5b848bc2 100644 --- a/drivers/common/mlx5/windows/mlx5_common_os.h +++ b/drivers/common/mlx5/windows/mlx5_common_os.h @@ -6,6 +6,7 @@ #define RTE_PMD_MLX5_COMMON_OS_H_ #include +#include #include @@ -15,6 +16,8 @@ #include "mlx5_common_mr.h" #include "mlx5_win_ext.h" +#define MLX5_BF_OFFSET 0x800 + /** * This API allocates aligned or non-aligned memory. The free can be on either * aligned or nonaligned memory. To be protected - even though there may be no @@ -144,6 +147,78 @@ mlx5_os_get_umem_id(void *umem) return ((struct mlx5_devx_umem *)umem)->umem_id; } +/** + * Get mmap offset. Given a pointer to an DevX UAR object of type + * 'struct mlx5dv_devx_uar *' - return its mmap offset. + * In Windows, mmap_offset is unused. + * + * @param[in] uar + * Pointer to UAR object. + * + * @return + * 0 as mmap_offset is unused + */ +static inline off_t +mlx5_os_get_devx_uar_mmap_offset(void *uar) +{ + RTE_SET_USED(uar); + return 0; +} + +/** + * Get base addr pointer. Given a pointer to an UAR object of type + * 'struct mlx5dv_devx_uar *' - return its base address. + * + * @param[in] uar + * Pointer to an UAR object. + * + * @return + * The base address if UAR is valid, NULL otherwise. + */ +static inline void * +mlx5_os_get_devx_uar_base_addr(void *uar) +{ + if (!uar) + return NULL; + return ((devx_uar_handle *)uar)->uar_page; +} + +/** + * Get reg addr pointer. Given a pointer to an UAR object of type + * 'struct mlx5dv_devx_uar *' - return its reg address. + * + * @param[in] uar + * Pointer to an UAR object. + * + * @return + * The reg address if UAR is valid, NULL otherwise. + */ +static inline void * +mlx5_os_get_devx_uar_reg_addr(void *uar) +{ + if (!uar) + return NULL; + return ((char *)((devx_uar_handle *)uar)->uar_page) + MLX5_BF_OFFSET; +} + +/** + * Get page id. Given a pointer to an UAR object of type + * 'struct mlx5dv_devx_uar *' - return its page id. + * + * @param[in] uar + * Pointer to an UAR object. + * + * @return + * The page id if UAR is valid, 0 otherwise. + */ +static inline uint32_t +mlx5_os_get_devx_uar_page_id(void *uar) +{ + if (!uar) + return 0; + return ((devx_uar_handle *)uar)->uar_index; +} + void *mlx5_os_alloc_pd(void *ctx); int mlx5_os_dealloc_pd(void *pd); void *mlx5_os_umem_reg(void *ctx, void *addr, size_t size, uint32_t access); From patchwork Thu Dec 17 17:30:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tal Shnaiderman X-Patchwork-Id: 85343 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 371FDA09F6; Thu, 17 Dec 2020 18:34:58 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 88093CA64; Thu, 17 Dec 2020 18:33:21 +0100 (CET) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by dpdk.org (Postfix) with ESMTP id 0C438CA38 for ; Thu, 17 Dec 2020 18:33:09 +0100 (CET) Received: from Internal Mail-Server by MTLPINE1 (envelope-from talshn@nvidia.com) with SMTP; 17 Dec 2020 19:33:04 +0200 Received: from nvidia.com (l-wincomp04-vm.mtl.labs.mlnx [10.237.1.5]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 0BHHX45Q021771; Thu, 17 Dec 2020 19:33:04 +0200 From: Tal Shnaiderman To: dev@dpdk.org Cc: thomas@monjalon.net, matan@nvidia.com, rasland@nvidia.com, ophirmu@nvidia.com Date: Thu, 17 Dec 2020 19:30:07 +0200 Message-Id: <20201217173037.11396-6-talshn@nvidia.com> X-Mailer: git-send-email 2.16.1.windows.4 In-Reply-To: <20201217173037.11396-1-talshn@nvidia.com> References: <20201217173037.11396-1-talshn@nvidia.com> Subject: [dpdk-dev] [PATCH 05/35] common/mlx5/windows: wrap event channel APIs with OS calls X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This commit is the Windows equivalent of the Linux implementation. Windows returns an error ENOTSUP for the APIs to create/destroy event channel or to subscribe an event. Signed-off-by: Tal Shnaiderman Signed-off-by: Ophir Munk Acked-by: Matan Azrad --- drivers/common/mlx5/windows/mlx5_common_os.h | 29 ++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/drivers/common/mlx5/windows/mlx5_common_os.h b/drivers/common/mlx5/windows/mlx5_common_os.h index ac5b848bc2..e92533c4d3 100644 --- a/drivers/common/mlx5/windows/mlx5_common_os.h +++ b/drivers/common/mlx5/windows/mlx5_common_os.h @@ -219,6 +219,35 @@ mlx5_os_get_devx_uar_page_id(void *uar) return ((devx_uar_handle *)uar)->uar_index; } +static inline void * +mlx5_os_devx_create_event_channel(void *ctx, int flags) +{ + (void)ctx; + (void)flags; + errno = ENOTSUP; + return NULL; +} + +static inline void +mlx5_os_devx_destroy_event_channel(void *eventc) +{ + (void)eventc; +} + +static inline int +mlx5_os_devx_subscribe_devx_event(void *eventc, + void *obj, + uint16_t events_sz, uint16_t events_num[], + uint64_t cookie) +{ + (void)eventc; + (void)obj; + (void)events_sz; + (void)events_num; + (void)cookie; + return -ENOTSUP; +} + void *mlx5_os_alloc_pd(void *ctx); int mlx5_os_dealloc_pd(void *pd); void *mlx5_os_umem_reg(void *ctx, void *addr, size_t size, uint32_t access); From patchwork Thu Dec 17 17:30:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tal Shnaiderman X-Patchwork-Id: 85348 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9F4CEA09F6; Thu, 17 Dec 2020 18:36:54 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id ABF3FCAC3; Thu, 17 Dec 2020 18:33:29 +0100 (CET) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by dpdk.org (Postfix) with ESMTP id 644C1CA44 for ; Thu, 17 Dec 2020 18:33:10 +0100 (CET) Received: from Internal Mail-Server by MTLPINE1 (envelope-from talshn@nvidia.com) with SMTP; 17 Dec 2020 19:33:04 +0200 Received: from nvidia.com (l-wincomp04-vm.mtl.labs.mlnx [10.237.1.5]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 0BHHX45R021771; Thu, 17 Dec 2020 19:33:04 +0200 From: Tal Shnaiderman To: dev@dpdk.org Cc: thomas@monjalon.net, matan@nvidia.com, rasland@nvidia.com, ophirmu@nvidia.com Date: Thu, 17 Dec 2020 19:30:08 +0200 Message-Id: <20201217173037.11396-7-talshn@nvidia.com> X-Mailer: git-send-email 2.16.1.windows.4 In-Reply-To: <20201217173037.11396-1-talshn@nvidia.com> References: <20201217173037.11396-1-talshn@nvidia.com> Subject: [dpdk-dev] [PATCH 06/35] net/mlx5/windows: add memory region callbacks X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Ophir Munk This commit is the Windows part implementation of [1]. [1] commit d5ed8aa9449d ("net/mlx5: add memory region callbacks in per-device cache")' Signed-off-by: Ophir Munk Acked-by: Matan Azrad --- drivers/net/mlx5/windows/mlx5_os.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/net/mlx5/windows/mlx5_os.c b/drivers/net/mlx5/windows/mlx5_os.c index 43665bff7f..de23f0ac88 100644 --- a/drivers/net/mlx5/windows/mlx5_os.c +++ b/drivers/net/mlx5/windows/mlx5_os.c @@ -295,6 +295,23 @@ mlx5_os_set_allmulti(struct rte_eth_dev *dev, int enable) return -ENOTSUP; } +/** + * Set the reg_mr and dereg_mr call backs + * + * @param reg_mr_cb[out] + * Pointer to reg_mr func + * @param dereg_mr_cb[out] + * Pointer to dereg_mr func + * + */ +void +mlx5_os_set_reg_mr_cb(mlx5_reg_mr_t *reg_mr_cb, + mlx5_dereg_mr_t *dereg_mr_cb) +{ + *reg_mr_cb = mlx5_os_reg_mr; + *dereg_mr_cb = mlx5_os_dereg_mr; +} + const struct mlx5_flow_driver_ops mlx5_flow_verbs_drv_ops = {0}; const struct eth_dev_ops mlx5_os_dev_ops = { From patchwork Thu Dec 17 17:30:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tal Shnaiderman X-Patchwork-Id: 85341 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1CA60A09F6; Thu, 17 Dec 2020 18:34:19 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id BA992CA52; Thu, 17 Dec 2020 18:33:18 +0100 (CET) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by dpdk.org (Postfix) with ESMTP id 110F6CA39 for ; Thu, 17 Dec 2020 18:33:09 +0100 (CET) Received: from Internal Mail-Server by MTLPINE1 (envelope-from talshn@nvidia.com) with SMTP; 17 Dec 2020 19:33:04 +0200 Received: from nvidia.com (l-wincomp04-vm.mtl.labs.mlnx [10.237.1.5]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 0BHHX45S021771; Thu, 17 Dec 2020 19:33:04 +0200 From: Tal Shnaiderman To: dev@dpdk.org Cc: thomas@monjalon.net, matan@nvidia.com, rasland@nvidia.com, ophirmu@nvidia.com Date: Thu, 17 Dec 2020 19:30:09 +0200 Message-Id: <20201217173037.11396-8-talshn@nvidia.com> X-Mailer: git-send-email 2.16.1.windows.4 In-Reply-To: <20201217173037.11396-1-talshn@nvidia.com> References: <20201217173037.11396-1-talshn@nvidia.com> Subject: [dpdk-dev] [PATCH 07/35] net/mlx5/windows: add stubs for MP requests X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Ophir Munk Windows supports the primary process with no secondary process control. This commit adds stubs for requests to start/stop the data-path to the secondary process and for requests to start/stop a queue of the primary process. Signed-off-by: Ophir Munk Acked-by: Matan Azrad --- drivers/net/mlx5/windows/meson.build | 1 + drivers/net/mlx5/windows/mlx5_mp_os.c | 71 +++++++++++++++++++++++++++++++++++ 2 files changed, 72 insertions(+) create mode 100644 drivers/net/mlx5/windows/mlx5_mp_os.c diff --git a/drivers/net/mlx5/windows/meson.build b/drivers/net/mlx5/windows/meson.build index 2ea0792a40..f87dcb1b4c 100644 --- a/drivers/net/mlx5/windows/meson.build +++ b/drivers/net/mlx5/windows/meson.build @@ -4,5 +4,6 @@ includes += include_directories('.') sources += files( 'mlx5_os.c', + 'mlx5_mp_os.c', ) diff --git a/drivers/net/mlx5/windows/mlx5_mp_os.c b/drivers/net/mlx5/windows/mlx5_mp_os.c new file mode 100644 index 0000000000..db793b1f7d --- /dev/null +++ b/drivers/net/mlx5/windows/mlx5_mp_os.c @@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright 2020 Mellanox Technologies, Ltd + */ + +#include +#include + +#include +#include +#include + +#include +#include +#include + +#include "mlx5.h" +#include "mlx5_rxtx.h" +#include "mlx5_utils.h" + +/** + * Broadcast request of starting data-path to secondary processes. The request + * is synchronous. + * + * @param[in] dev + * Pointer to Ethernet structure. + */ +void +mlx5_mp_os_req_start_rxtx(struct rte_eth_dev *dev) +{ + RTE_SET_USED(dev); +} + +/** + * Broadcast request of stopping data-path to secondary processes. The request + * is synchronous. + * + * @param[in] dev + * Pointer to Ethernet structure. + */ +void +mlx5_mp_os_req_stop_rxtx(struct rte_eth_dev *dev) +{ + RTE_SET_USED(dev); +} + +/** + * Request Verbs Rx/Tx queue stop or start to the primary process. + * + * @param[in] dev + * Pointer to Ethernet structure. + * @param queue_id + * Queue ID to control. + * @param req_type + * request type + * MLX5_MP_REQ_QUEUE_RX_START - start Rx queue + * MLX5_MP_REQ_QUEUE_TX_START - stop Tx queue + * MLX5_MP_REQ_QUEUE_RX_STOP - stop Rx queue + * MLX5_MP_REQ_QUEUE_TX_STOP - stop Tx queue + * @return + * 0 on success, a negative errno value otherwise and + * rte_errno is set. + */ +int +mlx5_mp_os_req_queue_control(struct rte_eth_dev *dev, uint16_t queue_id, + enum mlx5_mp_req_type req_type) +{ + RTE_SET_USED(dev); + RTE_SET_USED(queue_id); + RTE_SET_USED(req_type); + return -ENOTSUP; +} From patchwork Thu Dec 17 17:30:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tal Shnaiderman X-Patchwork-Id: 85351 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 60267A09F6; Thu, 17 Dec 2020 18:38:04 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 6C0AFCAD9; Thu, 17 Dec 2020 18:33:34 +0100 (CET) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by dpdk.org (Postfix) with ESMTP id 96D23CA4A for ; Thu, 17 Dec 2020 18:33:10 +0100 (CET) Received: from Internal Mail-Server by MTLPINE1 (envelope-from talshn@nvidia.com) with SMTP; 17 Dec 2020 19:33:04 +0200 Received: from nvidia.com (l-wincomp04-vm.mtl.labs.mlnx [10.237.1.5]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 0BHHX45T021771; Thu, 17 Dec 2020 19:33:04 +0200 From: Tal Shnaiderman To: dev@dpdk.org Cc: thomas@monjalon.net, matan@nvidia.com, rasland@nvidia.com, ophirmu@nvidia.com Date: Thu, 17 Dec 2020 19:30:10 +0200 Message-Id: <20201217173037.11396-9-talshn@nvidia.com> X-Mailer: git-send-email 2.16.1.windows.4 In-Reply-To: <20201217173037.11396-1-talshn@nvidia.com> References: <20201217173037.11396-1-talshn@nvidia.com> Subject: [dpdk-dev] [PATCH 08/35] net/mlx5/windows: support get mac X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This commits implements API mlx5_get_mac(). It returns the MAC address saved in the device context since its creation. Signed-off-by: Tal Shnaiderman Acked-by: Matan Azrad --- drivers/net/mlx5/windows/meson.build | 1 + drivers/net/mlx5/windows/mlx5_ethdev_os.c | 43 +++++++++++++++++++++++++++++++ 2 files changed, 44 insertions(+) create mode 100644 drivers/net/mlx5/windows/mlx5_ethdev_os.c diff --git a/drivers/net/mlx5/windows/meson.build b/drivers/net/mlx5/windows/meson.build index f87dcb1b4c..b5d9f0ee04 100644 --- a/drivers/net/mlx5/windows/meson.build +++ b/drivers/net/mlx5/windows/meson.build @@ -5,5 +5,6 @@ includes += include_directories('.') sources += files( 'mlx5_os.c', 'mlx5_mp_os.c', + 'mlx5_ethdev_os.c', ) diff --git a/drivers/net/mlx5/windows/mlx5_ethdev_os.c b/drivers/net/mlx5/windows/mlx5_ethdev_os.c new file mode 100644 index 0000000000..0662c095d1 --- /dev/null +++ b/drivers/net/mlx5/windows/mlx5_ethdev_os.c @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright 2020 Mellanox Technologies, Ltd + */ +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +/** + * Get MAC address by querying netdevice. + * + * @param[in] dev + * Pointer to Ethernet device. + * @param[out] mac + * MAC address output buffer. + * + * @return + * 0 on success, a negative errno value otherwise and rte_errno is set. + */ +int +mlx5_get_mac(struct rte_eth_dev *dev, uint8_t (*mac)[RTE_ETHER_ADDR_LEN]) +{ + struct mlx5_priv *priv; + mlx5_context_st *context_obj; + + if (!dev) { + rte_errno = EINVAL; + return -rte_errno; + } + priv = dev->data->dev_private; + context_obj = (mlx5_context_st *)priv->sh->ctx; + memcpy(mac, context_obj->mlx5_dev.eth_mac, RTE_ETHER_ADDR_LEN); + return 0; +} From patchwork Thu Dec 17 17:30:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tal Shnaiderman X-Patchwork-Id: 85347 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 16D92A09F6; Thu, 17 Dec 2020 18:36:34 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 31886CABD; Thu, 17 Dec 2020 18:33:28 +0100 (CET) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by dpdk.org (Postfix) with ESMTP id 6D4E2CA46 for ; Thu, 17 Dec 2020 18:33:10 +0100 (CET) Received: from Internal Mail-Server by MTLPINE1 (envelope-from talshn@nvidia.com) with SMTP; 17 Dec 2020 19:33:04 +0200 Received: from nvidia.com (l-wincomp04-vm.mtl.labs.mlnx [10.237.1.5]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 0BHHX45U021771; Thu, 17 Dec 2020 19:33:04 +0200 From: Tal Shnaiderman To: dev@dpdk.org Cc: thomas@monjalon.net, matan@nvidia.com, rasland@nvidia.com, ophirmu@nvidia.com Date: Thu, 17 Dec 2020 19:30:11 +0200 Message-Id: <20201217173037.11396-10-talshn@nvidia.com> X-Mailer: git-send-email 2.16.1.windows.4 In-Reply-To: <20201217173037.11396-1-talshn@nvidia.com> References: <20201217173037.11396-1-talshn@nvidia.com> Subject: [dpdk-dev] [PATCH 09/35] net/mlx5/windows: add ethdev stub operations X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Ophir Munk This commits adds ethdev stubs. These APIs are called from shared code that must compile under Linux and Windows. The following stubs are added: mlx5_set_mtu mlx5_os_read_dev_counters mlx5_intr_callback_unregister mlx5_os_get_stats_n mlx5_os_stats_init mlx5_set_link_down mlx5_set_link_up mlx5_dev_get_flow_ctrl mlx5_dev_set_flow_ctrl mlx5_get_module_info mlx5_get_module_eeprom Signed-off-by: Ophir Munk Acked-by: Matan Azrad --- drivers/net/mlx5/windows/mlx5_ethdev_os.c | 199 ++++++++++++++++++++++++++++++ 1 file changed, 199 insertions(+) diff --git a/drivers/net/mlx5/windows/mlx5_ethdev_os.c b/drivers/net/mlx5/windows/mlx5_ethdev_os.c index 0662c095d1..4925fd893f 100644 --- a/drivers/net/mlx5/windows/mlx5_ethdev_os.c +++ b/drivers/net/mlx5/windows/mlx5_ethdev_os.c @@ -41,3 +41,202 @@ mlx5_get_mac(struct rte_eth_dev *dev, uint8_t (*mac)[RTE_ETHER_ADDR_LEN]) memcpy(mac, context_obj->mlx5_dev.eth_mac, RTE_ETHER_ADDR_LEN); return 0; } + +/** + * Set device MTU. + * + * @param dev + * Pointer to Ethernet device. + * @param mtu + * MTU value to set. + * + * @return + * 0 on success, a negative errno value otherwise and rte_errno is set. + */ +int +mlx5_set_mtu(struct rte_eth_dev *dev, uint16_t mtu) +{ + RTE_SET_USED(dev); + RTE_SET_USED(mtu); + return -ENOTSUP; +} + +/* + * Unregister callback handler safely. The handler may be active + * while we are trying to unregister it, in this case code -EAGAIN + * is returned by rte_intr_callback_unregister(). This routine checks + * the return code and tries to unregister handler again. + * + * @param handle + * interrupt handle + * @param cb_fn + * pointer to callback routine + * @cb_arg + * opaque callback parameter + */ +void +mlx5_intr_callback_unregister(const struct rte_intr_handle *handle, + rte_intr_callback_fn cb_fn, void *cb_arg) +{ + RTE_SET_USED(handle); + RTE_SET_USED(cb_fn); + RTE_SET_USED(cb_arg); +} + +/** + * DPDK callback to get flow control status. + * + * @param dev + * Pointer to Ethernet device structure. + * @param[out] fc_conf + * Flow control output buffer. + * + * @return + * 0 on success, a negative errno value otherwise and rte_errno is set. + */ +int +mlx5_dev_get_flow_ctrl(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) +{ + RTE_SET_USED(dev); + RTE_SET_USED(fc_conf); + return -ENOTSUP; +} + +/** + * DPDK callback to modify flow control parameters. + * + * @param dev + * Pointer to Ethernet device structure. + * @param[in] fc_conf + * Flow control parameters. + * + * @return + * 0 on success, a negative errno value otherwise and rte_errno is set. + */ +int +mlx5_dev_set_flow_ctrl(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) +{ + RTE_SET_USED(dev); + RTE_SET_USED(fc_conf); + return -ENOTSUP; +} + +/** + * Query the number of statistics provided by ETHTOOL. + * + * @param dev + * Pointer to Ethernet device. + * + * @return + * Number of statistics on success, negative errno value otherwise and + * rte_errno is set. + */ +int +mlx5_os_get_stats_n(struct rte_eth_dev *dev) +{ + RTE_SET_USED(dev); + return -ENOTSUP; +} + +/** + * Init the structures to read device counters. + * + * @param dev + * Pointer to Ethernet device. + */ +void +mlx5_os_stats_init(struct rte_eth_dev *dev) +{ + RTE_SET_USED(dev); +} + +/** + * Read device counters table. + * + * @param dev + * Pointer to Ethernet device. + * @param[out] stats + * Counters table output buffer. + * + * @return + * 0 on success and stats is filled, negative errno value otherwise and + * rte_errno is set. + */ +int +mlx5_os_read_dev_counters(struct rte_eth_dev *dev, uint64_t *stats) +{ + RTE_SET_USED(dev); + RTE_SET_USED(stats); + return -ENOTSUP; +} + +/** + * DPDK callback to bring the link DOWN. + * + * @param dev + * Pointer to Ethernet device structure. + * + * @return + * 0 on success, a negative errno value otherwise + */ +int +mlx5_set_link_down(struct rte_eth_dev *dev) +{ + RTE_SET_USED(dev); + return -ENOTSUP; +} + +/** + * DPDK callback to bring the link UP. + * + * @param dev + * Pointer to Ethernet device structure. + * + * @return + * 0 on success, a negative errno value otherwise + */ +int +mlx5_set_link_up(struct rte_eth_dev *dev) +{ + RTE_SET_USED(dev); + return -ENOTSUP; +} + +/** + * DPDK callback to retrieve plug-in module EEPROM information (type and size). + * + * @param dev + * Pointer to Ethernet device structure. + * @param[out] modinfo + * Storage for plug-in module EEPROM information. + * + * @return + * 0 on success, a negative errno value otherwise and rte_errno is set. + */ +int +mlx5_get_module_info(struct rte_eth_dev *dev, + struct rte_eth_dev_module_info *modinfo) +{ + RTE_SET_USED(dev); + RTE_SET_USED(modinfo); + return -ENOTSUP; +} + +/** + * DPDK callback to retrieve plug-in module EEPROM data. + * + * @param dev + * Pointer to Ethernet device structure. + * @param[out] info + * Storage for plug-in module EEPROM data. + * + * @return + * 0 on success, a negative errno value otherwise and rte_errno is set. + */ +int mlx5_get_module_eeprom(struct rte_eth_dev *dev, + struct rte_dev_eeprom_info *info) +{ + RTE_SET_USED(dev); + RTE_SET_USED(info); + return -ENOTSUP; +} From patchwork Thu Dec 17 17:30:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tal Shnaiderman X-Patchwork-Id: 85345 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 17693A09F6; Thu, 17 Dec 2020 18:35:41 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 90907CA97; Thu, 17 Dec 2020 18:33:24 +0100 (CET) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by dpdk.org (Postfix) with ESMTP id 62C80CA41 for ; Thu, 17 Dec 2020 18:33:10 +0100 (CET) Received: from Internal Mail-Server by MTLPINE1 (envelope-from talshn@nvidia.com) with SMTP; 17 Dec 2020 19:33:05 +0200 Received: from nvidia.com (l-wincomp04-vm.mtl.labs.mlnx [10.237.1.5]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 0BHHX45V021771; Thu, 17 Dec 2020 19:33:05 +0200 From: Tal Shnaiderman To: dev@dpdk.org Cc: thomas@monjalon.net, matan@nvidia.com, rasland@nvidia.com, ophirmu@nvidia.com Date: Thu, 17 Dec 2020 19:30:12 +0200 Message-Id: <20201217173037.11396-11-talshn@nvidia.com> X-Mailer: git-send-email 2.16.1.windows.4 In-Reply-To: <20201217173037.11396-1-talshn@nvidia.com> References: <20201217173037.11396-1-talshn@nvidia.com> Subject: [dpdk-dev] [PATCH 10/35] net/mlx5/windows: support link update X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add support for mlx5_link_update() to get link speed and link state. Other parameters are currently hard-coded. Signed-off-by: Tal Shnaiderman Acked-by: Matan Azrad --- drivers/net/mlx5/windows/mlx5_ethdev_os.c | 44 +++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/drivers/net/mlx5/windows/mlx5_ethdev_os.c b/drivers/net/mlx5/windows/mlx5_ethdev_os.c index 4925fd893f..c99eac9868 100644 --- a/drivers/net/mlx5/windows/mlx5_ethdev_os.c +++ b/drivers/net/mlx5/windows/mlx5_ethdev_os.c @@ -170,6 +170,50 @@ mlx5_os_read_dev_counters(struct rte_eth_dev *dev, uint64_t *stats) return -ENOTSUP; } +/** + * DPDK callback to retrieve physical link information. + * + * @param dev + * Pointer to Ethernet device structure. + * @param wait_to_complete + * Wait for request completion. + * + * @return + * 0 if link status was not updated, positive if it was, a negative errno + * value otherwise and rte_errno is set. + */ +int +mlx5_link_update(struct rte_eth_dev *dev, int wait_to_complete) +{ + RTE_SET_USED(wait_to_complete); + struct mlx5_priv *priv; + mlx5_context_st *context_obj; + struct rte_eth_link dev_link; + int ret; + + ret = 0; + if (!dev) { + rte_errno = EINVAL; + return -rte_errno; + } + priv = dev->data->dev_private; + context_obj = (mlx5_context_st *)priv->sh->ctx; + dev_link.link_speed = context_obj->mlx5_dev.link_speed / (1024 * 1024); + dev_link.link_status = + (context_obj->mlx5_dev.link_state == 1 && !mlx5_is_removed(dev)) + ? 1 : 0; + dev_link.link_duplex = 1; + if (dev->data->dev_link.link_speed != dev_link.link_speed || + dev->data->dev_link.link_duplex != dev_link.link_duplex || + dev->data->dev_link.link_autoneg != dev_link.link_autoneg || + dev->data->dev_link.link_status != dev_link.link_status) + ret = 1; + else + ret = 0; + dev->data->dev_link = dev_link; + return ret; +} + /** * DPDK callback to bring the link DOWN. * From patchwork Thu Dec 17 17:30:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tal Shnaiderman X-Patchwork-Id: 85344 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5F27CA09F6; Thu, 17 Dec 2020 18:35:24 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id EA329CA86; Thu, 17 Dec 2020 18:33:22 +0100 (CET) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by dpdk.org (Postfix) with ESMTP id 41751CA40 for ; Thu, 17 Dec 2020 18:33:10 +0100 (CET) Received: from Internal Mail-Server by MTLPINE1 (envelope-from talshn@nvidia.com) with SMTP; 17 Dec 2020 19:33:05 +0200 Received: from nvidia.com (l-wincomp04-vm.mtl.labs.mlnx [10.237.1.5]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 0BHHX45W021771; Thu, 17 Dec 2020 19:33:05 +0200 From: Tal Shnaiderman To: dev@dpdk.org Cc: thomas@monjalon.net, matan@nvidia.com, rasland@nvidia.com, ophirmu@nvidia.com Date: Thu, 17 Dec 2020 19:30:13 +0200 Message-Id: <20201217173037.11396-12-talshn@nvidia.com> X-Mailer: git-send-email 2.16.1.windows.4 In-Reply-To: <20201217173037.11396-1-talshn@nvidia.com> References: <20201217173037.11396-1-talshn@nvidia.com> Subject: [dpdk-dev] [PATCH 11/35] net/mlx5/windows: support read clock X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This commit adds a new glue function query_rt_values to support the new API mlx5_read_clock(). Signed-off-by: Tal Shnaiderman Acked-by: Matan Azrad --- drivers/common/mlx5/mlx5_prm.h | 1 + drivers/common/mlx5/windows/mlx5_glue.c | 26 ++++++++++++++++++++++++++ drivers/common/mlx5/windows/mlx5_glue.h | 1 + drivers/common/mlx5/windows/mlx5_win_ext.h | 6 ++++++ drivers/net/mlx5/windows/mlx5_ethdev_os.c | 30 ++++++++++++++++++++++++++++++ 5 files changed, 64 insertions(+) diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index d62d2558eb..ac42238d30 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -594,6 +594,7 @@ struct mlx5_modification_cmd { }; }; +typedef uint64_t u64; typedef uint32_t u32; typedef uint16_t u16; typedef uint8_t u8; diff --git a/drivers/common/mlx5/windows/mlx5_glue.c b/drivers/common/mlx5/windows/mlx5_glue.c index 3896cf0932..167531823b 100644 --- a/drivers/common/mlx5/windows/mlx5_glue.c +++ b/drivers/common/mlx5/windows/mlx5_glue.c @@ -283,6 +283,31 @@ mlx5_glue_devx_fs_rule_del(void *flow) return devx_fs_rule_del(flow); } +static int +mlx5_glue_query_rt_values(void *ctx, void *devx_clock) +{ + struct mlx5_context *mlx5_ctx; + struct mlx5_devx_clock *clock; + int err; + + if (!ctx) { + errno = EINVAL; + return errno; + } + mlx5_ctx = (struct mlx5_context *)ctx; + clock = (struct mlx5_devx_clock *)devx_clock; + err = devx_hca_clock_query( + mlx5_ctx->devx_ctx, + &clock->p_iseg_internal_timer, + &clock->clock_frequency_hz, + &clock->is_stable_clock_frequency); + if (err) { + errno = err; + return errno; + } + return 0; +} + alignas(RTE_CACHE_LINE_SIZE) const struct mlx5_glue *mlx5_glue = &(const struct mlx5_glue){ .version = MLX5_GLUE_VERSION, @@ -304,4 +329,5 @@ const struct mlx5_glue *mlx5_glue = &(const struct mlx5_glue){ .devx_fs_rule_add = mlx5_glue_devx_fs_rule_add, .devx_fs_rule_del = mlx5_glue_devx_fs_rule_del, .devx_query_eqn = mlx5_glue_devx_query_eqn, + .query_rt_values = mlx5_glue_query_rt_values, }; diff --git a/drivers/common/mlx5/windows/mlx5_glue.h b/drivers/common/mlx5/windows/mlx5_glue.h index f2261ec7ac..bfaaa2a493 100644 --- a/drivers/common/mlx5/windows/mlx5_glue.h +++ b/drivers/common/mlx5/windows/mlx5_glue.h @@ -51,6 +51,7 @@ struct mlx5_glue { void *(*devx_fs_rule_add)(void *ctx, void *in, uint32_t inlen); int (*devx_fs_rule_del)(void *flow); int (*devx_query_eqn)(void *context, uint32_t cpus, uint32_t *eqn); + int (*query_rt_values)(void *ctx, void *devx_clock); }; extern const struct mlx5_glue *mlx5_glue; diff --git a/drivers/common/mlx5/windows/mlx5_win_ext.h b/drivers/common/mlx5/windows/mlx5_win_ext.h index 8e697b30c1..a14a6ccc3d 100644 --- a/drivers/common/mlx5/windows/mlx5_win_ext.h +++ b/drivers/common/mlx5/windows/mlx5_win_ext.h @@ -34,6 +34,12 @@ struct mlx5_pd { devx_device_ctx *devx_ctx; }; +struct mlx5_devx_clock { + void *p_iseg_internal_timer; + u64 clock_frequency_hz; + int is_stable_clock_frequency; +}; + #define GET_DEVX_CTX(ctx) (((mlx5_context_st *)ctx)->devx_ctx) #define GET_OBJ_CTX(obj) (((mlx5_devx_obj_st *)obj)->devx_ctx) diff --git a/drivers/net/mlx5/windows/mlx5_ethdev_os.c b/drivers/net/mlx5/windows/mlx5_ethdev_os.c index c99eac9868..1b68a7b6e8 100644 --- a/drivers/net/mlx5/windows/mlx5_ethdev_os.c +++ b/drivers/net/mlx5/windows/mlx5_ethdev_os.c @@ -14,6 +14,7 @@ #include #include #include +#include /** * Get MAC address by querying netdevice. @@ -284,3 +285,32 @@ int mlx5_get_module_eeprom(struct rte_eth_dev *dev, RTE_SET_USED(info); return -ENOTSUP; } + +/** + * Get device current raw clock counter + * + * @param dev + * Pointer to Ethernet device structure. + * @param[out] time + * Current raw clock counter of the device. + * + * @return + * 0 if the clock has correctly been read + * The value of errno in case of error + */ +int +mlx5_read_clock(struct rte_eth_dev *dev, uint64_t *clock) +{ + int err; + struct mlx5_devx_clock mlx5_clock; + struct mlx5_priv *priv = dev->data->dev_private; + mlx5_context_st *context_obj = (mlx5_context_st *)priv->sh->ctx; + + err = mlx5_glue->query_rt_values(context_obj, &mlx5_clock); + if (err != 0) { + DRV_LOG(WARNING, "Could not query the clock"); + return err; + } + *clock = *(uint64_t volatile *)mlx5_clock.p_iseg_internal_timer; + return 0; +} From patchwork Thu Dec 17 17:30:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tal Shnaiderman X-Patchwork-Id: 85353 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id E4A02A09F6; Thu, 17 Dec 2020 18:38:52 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id F1C18CB00; Thu, 17 Dec 2020 18:33:36 +0100 (CET) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by dpdk.org (Postfix) with ESMTP id 771FFCA49 for ; Thu, 17 Dec 2020 18:33:10 +0100 (CET) Received: from Internal Mail-Server by MTLPINE1 (envelope-from talshn@nvidia.com) with SMTP; 17 Dec 2020 19:33:05 +0200 Received: from nvidia.com (l-wincomp04-vm.mtl.labs.mlnx [10.237.1.5]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 0BHHX45X021771; Thu, 17 Dec 2020 19:33:05 +0200 From: Tal Shnaiderman To: dev@dpdk.org Cc: thomas@monjalon.net, matan@nvidia.com, rasland@nvidia.com, ophirmu@nvidia.com Date: Thu, 17 Dec 2020 19:30:14 +0200 Message-Id: <20201217173037.11396-13-talshn@nvidia.com> X-Mailer: git-send-email 2.16.1.windows.4 In-Reply-To: <20201217173037.11396-1-talshn@nvidia.com> References: <20201217173037.11396-1-talshn@nvidia.com> Subject: [dpdk-dev] [PATCH 12/35] net/mlx5/windows: support get mtu X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This commit implements API mlx5_get_mtu(). It returns the MTU size as saved in the device context since its creation. Signed-off-by: Tal Shnaiderman Acked-by: Matan Azrad --- drivers/net/mlx5/windows/mlx5_ethdev_os.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/net/mlx5/windows/mlx5_ethdev_os.c b/drivers/net/mlx5/windows/mlx5_ethdev_os.c index 1b68a7b6e8..614322b9f9 100644 --- a/drivers/net/mlx5/windows/mlx5_ethdev_os.c +++ b/drivers/net/mlx5/windows/mlx5_ethdev_os.c @@ -43,6 +43,33 @@ mlx5_get_mac(struct rte_eth_dev *dev, uint8_t (*mac)[RTE_ETHER_ADDR_LEN]) return 0; } +/** + * Get device MTU. + * + * @param dev + * Pointer to Ethernet device. + * @param[out] mtu + * MTU value output buffer. + * + * @return + * 0 on success, a negative errno value otherwise and rte_errno is set. + */ +int +mlx5_get_mtu(struct rte_eth_dev *dev, uint16_t *mtu) +{ + struct mlx5_priv *priv; + mlx5_context_st *context_obj; + + if (!dev) { + rte_errno = EINVAL; + return -rte_errno; + } + priv = dev->data->dev_private; + context_obj = (mlx5_context_st *)priv->sh->ctx; + *mtu = context_obj->mlx5_dev.mtu_bytes; + return 0; +} + /** * Set device MTU. * From patchwork Thu Dec 17 17:30:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tal Shnaiderman X-Patchwork-Id: 85349 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 34671A09F6; Thu, 17 Dec 2020 18:37:24 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 219D3CAC9; Thu, 17 Dec 2020 18:33:31 +0100 (CET) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by dpdk.org (Postfix) with ESMTP id 643CDCA42 for ; Thu, 17 Dec 2020 18:33:10 +0100 (CET) Received: from Internal Mail-Server by MTLPINE1 (envelope-from talshn@nvidia.com) with SMTP; 17 Dec 2020 19:33:05 +0200 Received: from nvidia.com (l-wincomp04-vm.mtl.labs.mlnx [10.237.1.5]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 0BHHX45Y021771; Thu, 17 Dec 2020 19:33:05 +0200 From: Tal Shnaiderman To: dev@dpdk.org Cc: thomas@monjalon.net, matan@nvidia.com, rasland@nvidia.com, ophirmu@nvidia.com Date: Thu, 17 Dec 2020 19:30:15 +0200 Message-Id: <20201217173037.11396-14-talshn@nvidia.com> X-Mailer: git-send-email 2.16.1.windows.4 In-Reply-To: <20201217173037.11396-1-talshn@nvidia.com> References: <20201217173037.11396-1-talshn@nvidia.com> Subject: [dpdk-dev] [PATCH 13/35] net/mlx5/windows: support get interface name X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This commit copies the interface name as saved in the device context since its creation. Signed-off-by: Tal Shnaiderman Acked-by: Matan Azrad --- drivers/net/mlx5/windows/mlx5_ethdev_os.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/drivers/net/mlx5/windows/mlx5_ethdev_os.c b/drivers/net/mlx5/windows/mlx5_ethdev_os.c index 614322b9f9..f0355ac671 100644 --- a/drivers/net/mlx5/windows/mlx5_ethdev_os.c +++ b/drivers/net/mlx5/windows/mlx5_ethdev_os.c @@ -43,6 +43,34 @@ mlx5_get_mac(struct rte_eth_dev *dev, uint8_t (*mac)[RTE_ETHER_ADDR_LEN]) return 0; } +/** + * Get interface name from private structure. + * + * + * @param[in] dev + * Pointer to Ethernet device. + * @param[out] ifname + * Interface name output buffer. + * + * @return + * 0 on success, a negative errno value otherwise and rte_errno is set. + */ +int +mlx5_get_ifname(const struct rte_eth_dev *dev, char (*ifname)[IF_NAMESIZE]) +{ + struct mlx5_priv *priv; + mlx5_context_st *context_obj; + + if (!dev) { + rte_errno = EINVAL; + return -rte_errno; + } + priv = dev->data->dev_private; + context_obj = (mlx5_context_st *)priv->sh->ctx; + strncpy(*ifname, context_obj->mlx5_dev.name, IF_NAMESIZE); + return 0; +} + /** * Get device MTU. * From patchwork Thu Dec 17 17:30:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tal Shnaiderman X-Patchwork-Id: 85346 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id E6F16A09F6; Thu, 17 Dec 2020 18:36:07 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 1B133CAA3; Thu, 17 Dec 2020 18:33:26 +0100 (CET) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by dpdk.org (Postfix) with ESMTP id 415BCCA3E for ; Thu, 17 Dec 2020 18:33:10 +0100 (CET) Received: from Internal Mail-Server by MTLPINE1 (envelope-from talshn@nvidia.com) with SMTP; 17 Dec 2020 19:33:05 +0200 Received: from nvidia.com (l-wincomp04-vm.mtl.labs.mlnx [10.237.1.5]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 0BHHX45Z021771; Thu, 17 Dec 2020 19:33:05 +0200 From: Tal Shnaiderman To: dev@dpdk.org Cc: thomas@monjalon.net, matan@nvidia.com, rasland@nvidia.com, ophirmu@nvidia.com Date: Thu, 17 Dec 2020 19:30:16 +0200 Message-Id: <20201217173037.11396-15-talshn@nvidia.com> X-Mailer: git-send-email 2.16.1.windows.4 In-Reply-To: <20201217173037.11396-1-talshn@nvidia.com> References: <20201217173037.11396-1-talshn@nvidia.com> Subject: [dpdk-dev] [PATCH 14/35] net/mlx5/windows: support device removed query X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This commit implements mlx5_is_removed() API. A new glue call 'init_shutdown_event' is added to support the new API. Signed-off-by: Tal Shnaiderman Acked-by: Matan Azrad --- drivers/common/mlx5/windows/mlx5_glue.c | 21 +++++++++++++++++++++ drivers/common/mlx5/windows/mlx5_glue.h | 1 + drivers/common/mlx5/windows/mlx5_win_ext.h | 2 +- drivers/net/mlx5/windows/mlx5_ethdev_os.c | 20 ++++++++++++++++++++ 4 files changed, 43 insertions(+), 1 deletion(-) diff --git a/drivers/common/mlx5/windows/mlx5_glue.c b/drivers/common/mlx5/windows/mlx5_glue.c index 167531823b..aef6d3b5f4 100644 --- a/drivers/common/mlx5/windows/mlx5_glue.c +++ b/drivers/common/mlx5/windows/mlx5_glue.c @@ -308,6 +308,26 @@ mlx5_glue_query_rt_values(void *ctx, void *devx_clock) return 0; } +static int +mlx5_glue_devx_init_showdown_event(void *ctx) +{ + struct mlx5_context *mlx5_ctx; + int err; + + if (!ctx) { + errno = EINVAL; + return errno; + } + mlx5_ctx = (struct mlx5_context *)ctx; + err = devx_query_shutdown_event(mlx5_ctx->devx_ctx, + &mlx5_ctx->shutdown_event_obj); + if (err) { + errno = err; + return errno; + } + return 0; +} + alignas(RTE_CACHE_LINE_SIZE) const struct mlx5_glue *mlx5_glue = &(const struct mlx5_glue){ .version = MLX5_GLUE_VERSION, @@ -330,4 +350,5 @@ const struct mlx5_glue *mlx5_glue = &(const struct mlx5_glue){ .devx_fs_rule_del = mlx5_glue_devx_fs_rule_del, .devx_query_eqn = mlx5_glue_devx_query_eqn, .query_rt_values = mlx5_glue_query_rt_values, + .devx_init_showdown_event = mlx5_glue_devx_init_showdown_event, }; diff --git a/drivers/common/mlx5/windows/mlx5_glue.h b/drivers/common/mlx5/windows/mlx5_glue.h index bfaaa2a493..420bfb27ef 100644 --- a/drivers/common/mlx5/windows/mlx5_glue.h +++ b/drivers/common/mlx5/windows/mlx5_glue.h @@ -52,6 +52,7 @@ struct mlx5_glue { int (*devx_fs_rule_del)(void *flow); int (*devx_query_eqn)(void *context, uint32_t cpus, uint32_t *eqn); int (*query_rt_values)(void *ctx, void *devx_clock); + int (*devx_init_showdown_event)(void *ctx); }; extern const struct mlx5_glue *mlx5_glue; diff --git a/drivers/common/mlx5/windows/mlx5_win_ext.h b/drivers/common/mlx5/windows/mlx5_win_ext.h index a14a6ccc3d..111af2e8da 100644 --- a/drivers/common/mlx5/windows/mlx5_win_ext.h +++ b/drivers/common/mlx5/windows/mlx5_win_ext.h @@ -14,7 +14,7 @@ extern "C" { typedef struct mlx5_context { devx_device_ctx *devx_ctx; struct devx_device mlx5_dev; - + struct devx_shutdown_event shutdown_event_obj; } mlx5_context_st; typedef struct { diff --git a/drivers/net/mlx5/windows/mlx5_ethdev_os.c b/drivers/net/mlx5/windows/mlx5_ethdev_os.c index f0355ac671..f4ec855302 100644 --- a/drivers/net/mlx5/windows/mlx5_ethdev_os.c +++ b/drivers/net/mlx5/windows/mlx5_ethdev_os.c @@ -369,3 +369,23 @@ mlx5_read_clock(struct rte_eth_dev *dev, uint64_t *clock) *clock = *(uint64_t volatile *)mlx5_clock.p_iseg_internal_timer; return 0; } + +/** + * Check if mlx5 device was removed. + * + * @param dev + * Pointer to Ethernet device structure. + * + * @return + * 1 when device is removed, otherwise 0. + */ +int +mlx5_is_removed(struct rte_eth_dev *dev) +{ + struct mlx5_priv *priv = dev->data->dev_private; + mlx5_context_st *context_obj = (mlx5_context_st *)priv->sh->ctx; + + if (*context_obj->shutdown_event_obj.p_flag) + return 1; + return 0; +} From patchwork Thu Dec 17 17:30:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tal Shnaiderman X-Patchwork-Id: 85357 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 33054A09F7; Thu, 17 Dec 2020 18:40:15 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 103FECB41; Thu, 17 Dec 2020 18:33:42 +0100 (CET) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by dpdk.org (Postfix) with ESMTP id BE79BCA37 for ; Thu, 17 Dec 2020 18:33:10 +0100 (CET) Received: from Internal Mail-Server by MTLPINE1 (envelope-from talshn@nvidia.com) with SMTP; 17 Dec 2020 19:33:05 +0200 Received: from nvidia.com (l-wincomp04-vm.mtl.labs.mlnx [10.237.1.5]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 0BHHX45a021771; Thu, 17 Dec 2020 19:33:05 +0200 From: Tal Shnaiderman To: dev@dpdk.org Cc: thomas@monjalon.net, matan@nvidia.com, rasland@nvidia.com, ophirmu@nvidia.com Date: Thu, 17 Dec 2020 19:30:17 +0200 Message-Id: <20201217173037.11396-16-talshn@nvidia.com> X-Mailer: git-send-email 2.16.1.windows.4 In-Reply-To: <20201217173037.11396-1-talshn@nvidia.com> References: <20201217173037.11396-1-talshn@nvidia.com> Subject: [dpdk-dev] [PATCH 15/35] net/mlx5/windws: add VLAN stubs X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Ophir Munk This commit adds stubs to VLAN VM operations. It is the Windows equivalent implementation of [1]. The Linux implementation was based on Netlink APIs which are not supported in Windows. [1] commit 7af10d29a4a0 ("net/mlx5/linux: refactor VLAN") Signed-off-by: Ophir Munk Acked-by: Matan Azrad --- drivers/net/mlx5/windows/meson.build | 1 + drivers/net/mlx5/windows/mlx5_vlan_os.c | 83 +++++++++++++++++++++++++++++++++ 2 files changed, 84 insertions(+) create mode 100644 drivers/net/mlx5/windows/mlx5_vlan_os.c diff --git a/drivers/net/mlx5/windows/meson.build b/drivers/net/mlx5/windows/meson.build index b5d9f0ee04..87e34d3cda 100644 --- a/drivers/net/mlx5/windows/meson.build +++ b/drivers/net/mlx5/windows/meson.build @@ -6,5 +6,6 @@ sources += files( 'mlx5_os.c', 'mlx5_mp_os.c', 'mlx5_ethdev_os.c', + 'mlx5_vlan_os.c', ) diff --git a/drivers/net/mlx5/windows/mlx5_vlan_os.c b/drivers/net/mlx5/windows/mlx5_vlan_os.c new file mode 100644 index 0000000000..d3b11e0001 --- /dev/null +++ b/drivers/net/mlx5/windows/mlx5_vlan_os.c @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright 2020 Mellanox Technologies, Ltd + */ + +#include +#include +#include +#include + +/* + * Not needed by this file; included to work around the lack of off_t + * definition for mlx5dv.h with unpatched rdma-core versions. + */ +#include + +#include +#include + +#include +#include + +/* + * Release VLAN network device, created for VM workaround. + * + * @param[in] dev + * Ethernet device object, Netlink context provider. + * @param[in] vlan + * Object representing the network device to release. + */ +void +mlx5_vlan_vmwa_release(struct rte_eth_dev *dev, + struct mlx5_vf_vlan *vlan) +{ + RTE_SET_USED(dev); + RTE_SET_USED(vlan); +} + +/** + * Acquire VLAN interface with specified tag for VM workaround. + * + * @param[in] dev + * Ethernet device object, Netlink context provider. + * @param[in] vlan + * Object representing the network device to acquire. + */ +void +mlx5_vlan_vmwa_acquire(struct rte_eth_dev *dev, + struct mlx5_vf_vlan *vlan) +{ + RTE_SET_USED(dev); + RTE_SET_USED(vlan); +} + +/* + * Create per ethernet device VLAN VM workaround context + * + * @param dev + * Pointer to Ethernet device structure. + * @param ifindex + * Interface index. + * + * @Return + * Pointer to mlx5_nl_vlan_vmwa_context + */ +void * +mlx5_vlan_vmwa_init(struct rte_eth_dev *dev, uint32_t ifindex) +{ + RTE_SET_USED(dev); + RTE_SET_USED(ifindex); + return NULL; +} + +/* + * Destroy per ethernet device VLAN VM workaround context + * + * @param dev + * Pointer to VM context + */ +void +mlx5_vlan_vmwa_exit(void *vmctx) +{ + RTE_SET_USED(vmctx); +} From patchwork Thu Dec 17 17:30:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tal Shnaiderman X-Patchwork-Id: 85356 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id A6DB7A09F6; Thu, 17 Dec 2020 18:39:54 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 90CACCB2F; Thu, 17 Dec 2020 18:33:40 +0100 (CET) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by dpdk.org (Postfix) with ESMTP id B7197CA2C for ; Thu, 17 Dec 2020 18:33:10 +0100 (CET) Received: from Internal Mail-Server by MTLPINE1 (envelope-from talshn@nvidia.com) with SMTP; 17 Dec 2020 19:33:05 +0200 Received: from nvidia.com (l-wincomp04-vm.mtl.labs.mlnx [10.237.1.5]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 0BHHX45b021771; Thu, 17 Dec 2020 19:33:05 +0200 From: Tal Shnaiderman To: dev@dpdk.org Cc: thomas@monjalon.net, matan@nvidia.com, rasland@nvidia.com, ophirmu@nvidia.com Date: Thu, 17 Dec 2020 19:30:18 +0200 Message-Id: <20201217173037.11396-17-talshn@nvidia.com> X-Mailer: git-send-email 2.16.1.windows.4 In-Reply-To: <20201217173037.11396-1-talshn@nvidia.com> References: <20201217173037.11396-1-talshn@nvidia.com> Subject: [dpdk-dev] [PATCH 16/35] net/mlx5/windows: support get pdn X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Implement OS function call to get pdn. Signed-off-by: Tal Shnaiderman Acked-by: Matan Azrad --- drivers/net/mlx5/windows/mlx5_os.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/net/mlx5/windows/mlx5_os.c b/drivers/net/mlx5/windows/mlx5_os.c index de23f0ac88..01d66cc855 100644 --- a/drivers/net/mlx5/windows/mlx5_os.c +++ b/drivers/net/mlx5/windows/mlx5_os.c @@ -312,6 +312,27 @@ mlx5_os_set_reg_mr_cb(mlx5_reg_mr_t *reg_mr_cb, *dereg_mr_cb = mlx5_os_dereg_mr; } +/** + * Extract pdn of PD object using DevX + * + * @param[in] pd + * Pointer to the DevX PD object. + * @param[out] pdn + * Pointer to the PD object number variable. + * + * @return + * 0 on success, error value otherwise. + */ +int +mlx5_os_get_pdn(void *pd, uint32_t *pdn) +{ + if (!pd) + return -EINVAL; + + *pdn = ((struct mlx5_pd *)pd)->pdn; + return 0; +} + const struct mlx5_flow_driver_ops mlx5_flow_verbs_drv_ops = {0}; const struct eth_dev_ops mlx5_os_dev_ops = { From patchwork Thu Dec 17 17:30:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tal Shnaiderman X-Patchwork-Id: 85358 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id F3222A09F6; Thu, 17 Dec 2020 18:40:34 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 88435CB47; Thu, 17 Dec 2020 18:33:43 +0100 (CET) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by dpdk.org (Postfix) with ESMTP id C7F20CA39 for ; Thu, 17 Dec 2020 18:33:10 +0100 (CET) Received: from Internal Mail-Server by MTLPINE1 (envelope-from talshn@nvidia.com) with SMTP; 17 Dec 2020 19:33:05 +0200 Received: from nvidia.com (l-wincomp04-vm.mtl.labs.mlnx [10.237.1.5]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 0BHHX45c021771; Thu, 17 Dec 2020 19:33:05 +0200 From: Tal Shnaiderman To: dev@dpdk.org Cc: thomas@monjalon.net, matan@nvidia.com, rasland@nvidia.com, ophirmu@nvidia.com Date: Thu, 17 Dec 2020 19:30:19 +0200 Message-Id: <20201217173037.11396-18-talshn@nvidia.com> X-Mailer: git-send-email 2.16.1.windows.4 In-Reply-To: <20201217173037.11396-1-talshn@nvidia.com> References: <20201217173037.11396-1-talshn@nvidia.com> Subject: [dpdk-dev] [PATCH 17/35] net/mlx5/windows: support open device X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Ophir Munk This commit implements mlx5_os_open_device() API. It calls glue API open_device() then glue API query_device() to fill in 'struct mlx5_context' with data for later usage. Signed-off-by: Ophir Munk Signed-off-by: Tal Shnaiderman Acked-by: Matan Azrad --- drivers/net/mlx5/windows/mlx5_os.c | 44 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/drivers/net/mlx5/windows/mlx5_os.c b/drivers/net/mlx5/windows/mlx5_os.c index 01d66cc855..14bd5bf39a 100644 --- a/drivers/net/mlx5/windows/mlx5_os.c +++ b/drivers/net/mlx5/windows/mlx5_os.c @@ -103,6 +103,50 @@ mlx5_os_set_nonblock_channel_fd(int fd) return -ENOTSUP; } +/** + * Function API open device under Windows + * + * This function calls the Windows glue APIs to open a device. + * + * @param[in] spawn + * Pointer to the device attributes (name, port, etc). + * @param[out] config + * Pointer to device configuration structure. + * @param[out] sh + * Pointer to shared context structure. + * + * @return + * 0 on success, a positive error value otherwise. + */ +int +mlx5_os_open_device(const struct mlx5_dev_spawn_data *spawn, + const struct mlx5_dev_config *config, + struct mlx5_dev_ctx_shared *sh) +{ + RTE_SET_USED(config); + int err = 0; + struct mlx5_context *mlx5_ctx; + + pthread_mutex_init(&sh->txpp.mutex, NULL); + /* Set numa node from pci probe */ + sh->numa_node = spawn->pci_dev->device.numa_node; + + /* Try to open device with DevX */ + rte_errno = 0; + sh->ctx = mlx5_glue->open_device(spawn->phys_dev); + if (!sh->ctx) { + DRV_LOG(ERR, "open_device failed"); + err = errno; + return err; + } + sh->devx = 1; + mlx5_ctx = (struct mlx5_context *)sh->ctx; + err = mlx5_glue->query_device(spawn->phys_dev, &mlx5_ctx->mlx5_dev); + if (err) + DRV_LOG(ERR, "Failed to query device context fields."); + return err; +} + /** * This function should share events between multiple ports of single IB * device. Currently it has no support under Windows. From patchwork Thu Dec 17 17:30:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tal Shnaiderman X-Patchwork-Id: 85352 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 927DEA09F6; Thu, 17 Dec 2020 18:38:31 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id C6EEFCAE2; Thu, 17 Dec 2020 18:33:35 +0100 (CET) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by dpdk.org (Postfix) with ESMTP id A3DFCCA4D for ; Thu, 17 Dec 2020 18:33:10 +0100 (CET) Received: from Internal Mail-Server by MTLPINE1 (envelope-from talshn@nvidia.com) with SMTP; 17 Dec 2020 19:33:06 +0200 Received: from nvidia.com (l-wincomp04-vm.mtl.labs.mlnx [10.237.1.5]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 0BHHX45d021771; Thu, 17 Dec 2020 19:33:06 +0200 From: Tal Shnaiderman To: dev@dpdk.org Cc: thomas@monjalon.net, matan@nvidia.com, rasland@nvidia.com, ophirmu@nvidia.com Date: Thu, 17 Dec 2020 19:30:20 +0200 Message-Id: <20201217173037.11396-19-talshn@nvidia.com> X-Mailer: git-send-email 2.16.1.windows.4 In-Reply-To: <20201217173037.11396-1-talshn@nvidia.com> References: <20201217173037.11396-1-talshn@nvidia.com> Subject: [dpdk-dev] [PATCH 18/35] net/mlx5/windows: initial probing implementation X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This commit implements mlx5_os_pci_probe API under Windows. It does all required initializations then it gets the PCI device list using glue API get_device_list(). Next, all non MLX5 matched devices are filtered out. The supported NIC types are: CONNECTX4VF, CONNECTX4LXVF, CONNECTX5VF, CONNECTX5EXVF, CONNECTX5BFVF, CONNECTX6VF, MELLANOX_CONNECTX6DXVF. Each device in the list is assigned with default configuration parameters, most of them are 0. The default dv_flow_en parameter value is 1 (which means Windows match and action flows are based on DV code). Next for each PCI device call mlx5_dev_spawn() to create an eth device (struct rte_ethdev). The implementation of device spawn is in the follow up commit. Finally, the device list is free. Signed-off-by: Tal Shnaiderman Signed-off-by: Ophir Munk Acked-by: Matan Azrad --- drivers/net/mlx5/windows/mlx5_os.c | 268 +++++++++++++++++++++++++++++++++++++ 1 file changed, 268 insertions(+) diff --git a/drivers/net/mlx5/windows/mlx5_os.c b/drivers/net/mlx5/windows/mlx5_os.c index 14bd5bf39a..7f7e2f8f7c 100644 --- a/drivers/net/mlx5/windows/mlx5_os.c +++ b/drivers/net/mlx5/windows/mlx5_os.c @@ -9,6 +9,7 @@ #include #include +#include #include #include @@ -26,6 +27,65 @@ #include "mlx5_mr.h" #include "mlx5_flow.h" +static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data"; + +/* Spinlock for mlx5_shared_data allocation. */ +static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER; + +/** + * Initialize shared data between primary and secondary process. + * + * A memzone is reserved by primary process and secondary processes attach to + * the memzone. + * + * @return + * 0 on success, a negative errno value otherwise and rte_errno is set. + */ +static int +mlx5_init_shared_data(void) +{ + const struct rte_memzone *mz; + int ret = 0; + + rte_spinlock_lock(&mlx5_shared_data_lock); + if (mlx5_shared_data == NULL) { + /* Allocate shared memory. */ + mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA, + sizeof(*mlx5_shared_data), + SOCKET_ID_ANY, 0); + if (mz == NULL) { + DRV_LOG(ERR, + "Cannot allocate mlx5 shared data"); + ret = -rte_errno; + goto error; + } + mlx5_shared_data = mz->addr; + memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data)); + rte_spinlock_init(&mlx5_shared_data->lock); + } +error: + rte_spinlock_unlock(&mlx5_shared_data_lock); + return ret; +} + +/** + * PMD global initialization. + * + * Independent from individual device, this function initializes global + * per-PMD data structures distinguishing primary and secondary processes. + * Hence, each initialization is called once per a process. + * + * @return + * 0 on success, a negative errno value otherwise and rte_errno is set. + */ +static int +mlx5_init_once(void) +{ + if (mlx5_init_shared_data()) + return -rte_errno; + return 0; +} + /** * Get mlx5 device attributes. * @@ -147,6 +207,31 @@ mlx5_os_open_device(const struct mlx5_dev_spawn_data *spawn, return err; } +/** + * Spawn an Ethernet device from Verbs information. + * + * @param dpdk_dev + * Backing DPDK device. + * @param spawn + * Verbs device parameters (name, port, switch_info) to spawn. + * @param config + * Device configuration parameters. + * + * @return + * NULL pointer. Operation is not supported and rte_errno is set to ENOTSUP. + */ +static struct rte_eth_dev * +mlx5_dev_spawn(struct rte_device *dpdk_dev, + struct mlx5_dev_spawn_data *spawn, + struct mlx5_dev_config *config) +{ + (void)dpdk_dev; + (void)spawn; + (void)config; + rte_errno = -ENOTSUP; + return NULL; +} + /** * This function should share events between multiple ports of single IB * device. Currently it has no support under Windows. @@ -339,6 +424,189 @@ mlx5_os_set_allmulti(struct rte_eth_dev *dev, int enable) return -ENOTSUP; } +/** + * DPDK callback to register a PCI device. + * + * This function spawns Ethernet devices out of a given PCI device. + * + * @param[in] pci_drv + * PCI driver structure (mlx5_driver). + * @param[in] pci_dev + * PCI device information. + * + * @return + * 0 on success, a negative errno value otherwise and rte_errno is set. + */ +int +mlx5_os_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, + struct rte_pci_device *pci_dev) +{ + struct devx_device_bdf *devx_bdf_devs, *orig_devx_bdf_devs; + /* + * Number of found IB Devices matching with requested PCI BDF. + * nd != 1 means there are multiple IB devices over the same + * PCI device and we have representors and master. + */ + unsigned int nd = 0; + /* + * Number of found IB device Ports. nd = 1 and np = 1..n means + * we have the single multiport IB device, and there may be + * representors attached to some of found ports. + * Currently not supported. + * unsigned int np = 0; + */ + + /* + * Number of DPDK ethernet devices to Spawn - either over + * multiple IB devices or multiple ports of single IB device. + * Actually this is the number of iterations to spawn. + */ + unsigned int ns = 0; + /* + * Bonding device + * < 0 - no bonding device (single one) + * >= 0 - bonding device (value is slave PF index) + */ + int bd = -1; + struct mlx5_dev_spawn_data *list = NULL; + struct mlx5_dev_config dev_config; + unsigned int dev_config_vf; + int ret; + uint32_t restore; + + if (rte_eal_process_type() == RTE_PROC_SECONDARY) { + DRV_LOG(ERR, "Secondary process is not supported on Windows."); + return -ENOTSUP; + + } + ret = mlx5_init_once(); + if (ret) { + DRV_LOG(ERR, "unable to init PMD global data: %s", + strerror(rte_errno)); + return -rte_errno; + } + errno = 0; + devx_bdf_devs = mlx5_glue->get_device_list(&ret); + orig_devx_bdf_devs = devx_bdf_devs; + if (!devx_bdf_devs) { + rte_errno = errno ? errno : ENOSYS; + DRV_LOG(ERR, "cannot list devices, is ib_uverbs loaded?"); + return -rte_errno; + } + /* + * First scan the list of all Infiniband devices to find + * matching ones, gathering into the list. + */ + struct devx_device_bdf *devx_bdf_match[ret + 1]; + + while (ret-- > 0) { + if (pci_dev->addr.bus != devx_bdf_devs->bus_id || + pci_dev->addr.devid != devx_bdf_devs->dev_id || + pci_dev->addr.function != devx_bdf_devs->fnc_id) { + devx_bdf_devs++; + continue; + } + + devx_bdf_match[nd++] = devx_bdf_devs; + } + devx_bdf_match[nd] = NULL; + if (!nd) { + /* No device matches, just complain and bail out. */ + DRV_LOG(WARNING, + "no DevX device matches PCI device " PCI_PRI_FMT "," + " is DevX Configured?", + pci_dev->addr.domain, pci_dev->addr.bus, + pci_dev->addr.devid, pci_dev->addr.function); + rte_errno = ENOENT; + ret = -rte_errno; + goto exit; + } + /* + * Now we can determine the maximal + * amount of devices to be spawned. + */ + list = mlx5_malloc(MLX5_MEM_ZERO, + sizeof(struct mlx5_dev_spawn_data), + RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); + if (!list) { + DRV_LOG(ERR, "spawn data array allocation failure"); + rte_errno = ENOMEM; + ret = -rte_errno; + goto exit; + } + memset(&list[ns].info, 0, sizeof(list[ns].info)); + list[ns].max_port = 1; + list[ns].phys_port = 1; + list[ns].phys_dev = devx_bdf_match[ns]; + list[ns].eth_dev = NULL; + list[ns].pci_dev = pci_dev; + list[ns].pf_bond = bd; + list[ns].ifindex = -1; /* Spawn will assign */ + list[ns].info = + (struct mlx5_switch_info){ + .master = 0, + .representor = 0, + .name_type = MLX5_PHYS_PORT_NAME_TYPE_UPLINK, + .port_name = 0, + .switch_id = 0, + }; + /* Device specific configuration. */ + switch (pci_dev->id.device_id) { + case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF: + case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF: + case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF: + case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF: + case PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF: + case PCI_DEVICE_ID_MELLANOX_CONNECTX6VF: + case PCI_DEVICE_ID_MELLANOX_CONNECTXVF: + dev_config_vf = 1; + break; + default: + dev_config_vf = 0; + break; + } + /* Default configuration. */ + memset(&dev_config, 0, sizeof(struct mlx5_dev_config)); + dev_config.vf = dev_config_vf; + dev_config.mps = 0; + dev_config.dbnc = MLX5_ARG_UNSET; + dev_config.rx_vec_en = 1; + dev_config.txq_inline_max = MLX5_ARG_UNSET; + dev_config.txq_inline_min = MLX5_ARG_UNSET; + dev_config.txq_inline_mpw = MLX5_ARG_UNSET; + dev_config.txqs_inline = MLX5_ARG_UNSET; + dev_config.vf_nl_en = 0; + dev_config.mr_ext_memseg_en = 1; + dev_config.mprq.max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN; + dev_config.mprq.min_rxqs_num = MLX5_MPRQ_MIN_RXQS; + dev_config.dv_esw_en = 0; + dev_config.dv_flow_en = 1; + dev_config.decap_en = 0; + dev_config.log_hp_size = MLX5_ARG_UNSET; + list[ns].eth_dev = mlx5_dev_spawn(&pci_dev->device, + &list[ns], + &dev_config); + if (!list[ns].eth_dev) + goto exit; + restore = list[ns].eth_dev->data->dev_flags; + rte_eth_copy_pci_info(list[ns].eth_dev, pci_dev); + /* Restore non-PCI flags cleared by the above call. */ + list[ns].eth_dev->data->dev_flags |= restore; + rte_eth_dev_probing_finish(list[ns].eth_dev); + ret = 0; +exit: + /* + * Do the routine cleanup: + * - free allocated spawn data array + * - free the device list + */ + if (list) + mlx5_free(list); + MLX5_ASSERT(orig_devx_bdf_devs); + mlx5_glue->free_device_list(orig_devx_bdf_devs); + return ret; +} + /** * Set the reg_mr and dereg_mr call backs * From patchwork Thu Dec 17 17:30:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tal Shnaiderman X-Patchwork-Id: 85350 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 57CC9A09F6; Thu, 17 Dec 2020 18:37:48 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id B4176CAD0; Thu, 17 Dec 2020 18:33:32 +0100 (CET) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by dpdk.org (Postfix) with ESMTP id 75B62CA48 for ; Thu, 17 Dec 2020 18:33:10 +0100 (CET) Received: from Internal Mail-Server by MTLPINE1 (envelope-from talshn@nvidia.com) with SMTP; 17 Dec 2020 19:33:06 +0200 Received: from nvidia.com (l-wincomp04-vm.mtl.labs.mlnx [10.237.1.5]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 0BHHX45e021771; Thu, 17 Dec 2020 19:33:06 +0200 From: Tal Shnaiderman To: dev@dpdk.org Cc: thomas@monjalon.net, matan@nvidia.com, rasland@nvidia.com, ophirmu@nvidia.com Date: Thu, 17 Dec 2020 19:30:21 +0200 Message-Id: <20201217173037.11396-20-talshn@nvidia.com> X-Mailer: git-send-email 2.16.1.windows.4 In-Reply-To: <20201217173037.11396-1-talshn@nvidia.com> References: <20201217173037.11396-1-talshn@nvidia.com> Subject: [dpdk-dev] [PATCH 19/35] net/mlx5/windws: spawn eth devices X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Ophir Munk This commit implements mlx5_dev_spawn() API which allocates an eth device (struct rte_eth_dev) for each PCI device. When working with representors virtual functions (as in Linux), one PCI device may spawn several eth devices: the master device for the main physical function (PF) and several representors for the virtual functions (VFs). However, currently Windows does not work in switch dev mode, therefore, no VFs are created and no representors are spawned. In this case one eth device is created per one PCI main port. In addition to device creation - the device configuration must be correctly set. The device arguments (devargs - set by the user) are parsed but they may be overridden by Windows limitations or hardware configurations. Some associated network parameters are stored in eth device (e.g. ifindex, MAC address, MTU) and some callback (e.g. burst functions) are set. Signed-off-by: Ophir Munk Signed-off-by: Tal Shnaiderman Acked-by: Matan Azrad --- drivers/common/mlx5/windows/mlx5_win_defs.h | 6 + drivers/net/mlx5/windows/mlx5_os.c | 456 +++++++++++++++++++++++++++- 2 files changed, 457 insertions(+), 5 deletions(-) diff --git a/drivers/common/mlx5/windows/mlx5_win_defs.h b/drivers/common/mlx5/windows/mlx5_win_defs.h index e9569e4431..d8f20993e0 100644 --- a/drivers/common/mlx5/windows/mlx5_win_defs.h +++ b/drivers/common/mlx5/windows/mlx5_win_defs.h @@ -163,4 +163,10 @@ struct mlx5_wqe_data_seg { rte_be32_t lkey; rte_be64_t addr; }; + +#define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4) +#define IBV_DEVICE_RAW_IP_CSUM (1 << 26) +#define IBV_RAW_PACKET_CAP_CVLAN_STRIPPING (1 << 0) +#define IBV_RAW_PACKET_CAP_SCATTER_FCS (1 << 1) +#define IBV_QPT_RAW_PACKET 8 #endif /* __MLX5_WIN_DEFS_H__ */ diff --git a/drivers/net/mlx5/windows/mlx5_os.c b/drivers/net/mlx5/windows/mlx5_os.c index 7f7e2f8f7c..985729f2a6 100644 --- a/drivers/net/mlx5/windows/mlx5_os.c +++ b/drivers/net/mlx5/windows/mlx5_os.c @@ -26,6 +26,9 @@ #include "mlx5_autoconf.h" #include "mlx5_mr.h" #include "mlx5_flow.h" +#include "mlx5_devx.h" + +#define MLX5_TAGS_HLIST_ARRAY_SIZE 8192 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data"; @@ -142,6 +145,42 @@ mlx5_os_get_dev_attr(void *ctx, struct mlx5_dev_attr *device_attr) return err; } +/** + * Initialize DR related data within private structure. + * Routine checks the reference counter and does actual + * resources creation/initialization only if counter is zero. + * + * @param[in] priv + * Pointer to the private device data structure. + * + * @return + * Zero on success, positive error code otherwise. + */ +static int +mlx5_alloc_shared_dr(struct mlx5_priv *priv) +{ + struct mlx5_dev_ctx_shared *sh = priv->sh; + int err = 0; + + if (!sh->flow_tbls) + err = mlx5_alloc_table_hash_list(priv); + else + DRV_LOG(DEBUG, "sh->flow_tbls[%p] already created, reuse\n", + (void *)sh->flow_tbls); + return err; +} +/** + * Destroy DR related data within private structure. + * + * @param[in] priv + * Pointer to the private device data structure. + */ +void +mlx5_os_free_shared_dr(struct mlx5_priv *priv) +{ + mlx5_free_table_hash_list(priv); +} + /** * Set the completion channel file descriptor interrupt as non-blocking. * Currently it has no support under Windows. @@ -207,6 +246,45 @@ mlx5_os_open_device(const struct mlx5_dev_spawn_data *spawn, return err; } +/** + * DV flow counter mode detect and config. + * + * @param dev + * Pointer to rte_eth_dev structure. + * + */ +static void +mlx5_flow_counter_mode_config(struct rte_eth_dev *dev __rte_unused) +{ +#ifdef HAVE_IBV_FLOW_DV_SUPPORT + struct mlx5_priv *priv = dev->data->dev_private; + struct mlx5_dev_ctx_shared *sh = priv->sh; + bool fallback; + +#ifndef HAVE_IBV_DEVX_ASYNC + fallback = true; +#else + fallback = false; + if (!priv->config.devx || !priv->config.dv_flow_en || + !priv->config.hca_attr.flow_counters_dump || + !(priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4) || + (mlx5_flow_dv_discover_counter_offset_support(dev) == -ENOTSUP)) + fallback = true; +#endif + if (fallback) + DRV_LOG(INFO, "Use fall-back DV counter management. Flow " + "counter dump:%d, bulk_alloc_bitmap:0x%hhx.", + priv->config.hca_attr.flow_counters_dump, + priv->config.hca_attr.flow_counter_bulk_alloc_bitmap); + /* Initialize fallback mode only on the port initializes sh. */ + if (sh->refcnt == 1) + sh->cmng.counter_fallback = fallback; + else if (fallback != sh->cmng.counter_fallback) + DRV_LOG(WARNING, "Port %d in sh has different fallback mode " + "with others:%d.", PORT_ID(priv), fallback); +#endif +} + /** * Spawn an Ethernet device from Verbs information. * @@ -218,17 +296,385 @@ mlx5_os_open_device(const struct mlx5_dev_spawn_data *spawn, * Device configuration parameters. * * @return - * NULL pointer. Operation is not supported and rte_errno is set to ENOTSUP. + * A valid Ethernet device object on success, NULL otherwise and rte_errno + * is set. The following errors are defined: + * + * EEXIST: device is already spawned */ static struct rte_eth_dev * mlx5_dev_spawn(struct rte_device *dpdk_dev, struct mlx5_dev_spawn_data *spawn, struct mlx5_dev_config *config) { - (void)dpdk_dev; - (void)spawn; - (void)config; - rte_errno = -ENOTSUP; + const struct mlx5_switch_info *switch_info = &spawn->info; + struct mlx5_dev_ctx_shared *sh = NULL; + struct mlx5_dev_attr device_attr; + struct rte_eth_dev *eth_dev = NULL; + struct mlx5_priv *priv = NULL; + int err = 0; + unsigned int cqe_comp; + unsigned int cqe_pad = 0; + struct rte_ether_addr mac; + char name[RTE_ETH_NAME_MAX_LEN]; + int own_domain_id = 0; + uint16_t port_id; + + /* Build device name. */ + strlcpy(name, dpdk_dev->name, sizeof(name)); + /* check if the device is already spawned */ + if (rte_eth_dev_get_port_by_name(name, &port_id) == 0) { + rte_errno = EEXIST; + return NULL; + } + DRV_LOG(DEBUG, "naming Ethernet device \"%s\"", name); + /* + * Some parameters are needed in advance to create device context. We + * process the devargs here to get ones, and later process devargs + * again to override some hardware settings. + */ + err = mlx5_args(config, dpdk_dev->devargs); + if (err) { + err = rte_errno; + DRV_LOG(ERR, "failed to process device arguments: %s", + strerror(rte_errno)); + goto error; + } + mlx5_malloc_mem_select(config->sys_mem_en); + sh = mlx5_alloc_shared_dev_ctx(spawn, config); + if (!sh) + return NULL; + config->devx = sh->devx; + /* Initialize the shutdown event in mlx5_dev_spawn to + * support mlx5_is_removed for Windows. + */ + err = mlx5_glue->devx_init_showdown_event(sh->ctx); + if (err) { + DRV_LOG(ERR, "failed to init showdown event: %s", + strerror(errno)); + goto error; + } + DRV_LOG(DEBUG, "MPW isn't supported"); + mlx5_os_get_dev_attr(sh->ctx, &device_attr); + config->swp = 0; + config->ind_table_max_size = + sh->device_attr.max_rwq_indirection_table_size; + if (RTE_CACHE_LINE_SIZE == 128 && + !(device_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP)) + cqe_comp = 0; + else + cqe_comp = 1; + config->cqe_comp = cqe_comp; + DRV_LOG(DEBUG, "tunnel offloading is not supported"); + config->tunnel_en = 0; + DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is no supported"); + config->mpls_en = 0; + /* Allocate private eth device data. */ + priv = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE, + sizeof(*priv), + RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); + if (priv == NULL) { + DRV_LOG(ERR, "priv allocation failure"); + err = ENOMEM; + goto error; + } + priv->sh = sh; + priv->dev_port = spawn->phys_port; + priv->pci_dev = spawn->pci_dev; + priv->mtu = RTE_ETHER_MTU; + priv->mp_id.port_id = port_id; + strlcpy(priv->mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN); + priv->representor = !!switch_info->representor; + priv->master = !!switch_info->master; + priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID; + priv->vport_meta_tag = 0; + priv->vport_meta_mask = 0; + priv->pf_bond = spawn->pf_bond; + priv->vport_id = -1; + /* representor_id field keeps the unmodified VF index. */ + priv->representor_id = -1; + /* + * Look for sibling devices in order to reuse their switch domain + * if any, otherwise allocate one. + */ + MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) { + const struct mlx5_priv *opriv = + rte_eth_devices[port_id].data->dev_private; + + if (!opriv || + opriv->sh != priv->sh || + opriv->domain_id == + RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) + continue; + priv->domain_id = opriv->domain_id; + break; + } + if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) { + err = rte_eth_switch_domain_alloc(&priv->domain_id); + if (err) { + err = rte_errno; + DRV_LOG(ERR, "unable to allocate switch domain: %s", + strerror(rte_errno)); + goto error; + } + own_domain_id = 1; + } + /* Override some values set by hardware configuration. */ + mlx5_args(config, dpdk_dev->devargs); + err = mlx5_dev_check_sibling_config(priv, config); + if (err) + goto error; + config->hw_csum = !!(sh->device_attr.device_cap_flags_ex & + IBV_DEVICE_RAW_IP_CSUM); + DRV_LOG(DEBUG, "checksum offloading is %ssupported", + (config->hw_csum ? "" : "not ")); + DRV_LOG(DEBUG, "counters are not supported"); + config->ind_table_max_size = + sh->device_attr.max_rwq_indirection_table_size; + /* + * Remove this check once DPDK supports larger/variable + * indirection tables. + */ + if (config->ind_table_max_size > (unsigned int)ETH_RSS_RETA_SIZE_512) + config->ind_table_max_size = ETH_RSS_RETA_SIZE_512; + DRV_LOG(DEBUG, "maximum Rx indirection table size is %u", + config->ind_table_max_size); + config->hw_vlan_strip = !!(sh->device_attr.raw_packet_caps & + IBV_RAW_PACKET_CAP_CVLAN_STRIPPING); + DRV_LOG(DEBUG, "VLAN stripping is %ssupported", + (config->hw_vlan_strip ? "" : "not ")); + config->hw_fcs_strip = !!(sh->device_attr.raw_packet_caps & + IBV_RAW_PACKET_CAP_SCATTER_FCS); + if (config->hw_padding) { + DRV_LOG(DEBUG, "Rx end alignment padding isn't supported"); + config->hw_padding = 0; + } + config->tso = (sh->device_attr.max_tso > 0 && + (sh->device_attr.tso_supported_qpts & + (1 << IBV_QPT_RAW_PACKET))); + if (config->tso) + config->tso_max_payload_sz = sh->device_attr.max_tso; + DRV_LOG(DEBUG, "%sMPS is %s.", + config->mps == MLX5_MPW_ENHANCED ? "enhanced " : + config->mps == MLX5_MPW ? "legacy " : "", + config->mps != MLX5_MPW_DISABLED ? "enabled" : "disabled"); + if (config->cqe_comp && !cqe_comp) { + DRV_LOG(WARNING, "Rx CQE compression isn't supported."); + config->cqe_comp = 0; + } + if (config->cqe_pad && !cqe_pad) { + DRV_LOG(WARNING, "Rx CQE padding isn't supported."); + config->cqe_pad = 0; + } else if (config->cqe_pad) { + DRV_LOG(INFO, "Rx CQE padding is enabled."); + } + if (config->devx) { + err = mlx5_devx_cmd_query_hca_attr(sh->ctx, &config->hca_attr); + if (err) { + err = -err; + goto error; + } + /* Check relax ordering support. */ + sh->cmng.relaxed_ordering_read = 0; + sh->cmng.relaxed_ordering_write = 0; + if (!haswell_broadwell_cpu) { + sh->cmng.relaxed_ordering_write = + config->hca_attr.relaxed_ordering_write; + sh->cmng.relaxed_ordering_read = + config->hca_attr.relaxed_ordering_read; + } + } + if (config->devx) { + uint32_t reg[MLX5_ST_SZ_DW(register_mtutc)]; + + err = config->hca_attr.access_register_user ? + mlx5_devx_cmd_register_read + (sh->ctx, MLX5_REGISTER_ID_MTUTC, 0, + reg, MLX5_ST_SZ_DW(register_mtutc)) : ENOTSUP; + if (!err) { + uint32_t ts_mode; + + /* MTUTC register is read successfully. */ + ts_mode = MLX5_GET(register_mtutc, reg, + time_stamp_mode); + if (ts_mode == MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME) + config->rt_timestamp = 1; + } else { + /* Kernel does not support register reading. */ + if (config->hca_attr.dev_freq_khz == + (NS_PER_S / MS_PER_S)) + config->rt_timestamp = 1; + } + } + if (config->mprq.enabled) { + DRV_LOG(WARNING, "Multi-Packet RQ isn't supported"); + config->mprq.enabled = 0; + } + if (config->max_dump_files_num == 0) + config->max_dump_files_num = 128; + eth_dev = rte_eth_dev_allocate(name); + if (eth_dev == NULL) { + DRV_LOG(ERR, "can not allocate rte ethdev"); + err = ENOMEM; + goto error; + } + if (priv->representor) { + eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR; + eth_dev->data->representor_id = priv->representor_id; + } + /* + * Store associated network device interface index. This index + * is permanent throughout the lifetime of device. So, we may store + * the ifindex here and use the cached value further. + */ + MLX5_ASSERT(spawn->ifindex); + priv->if_index = spawn->ifindex; + eth_dev->data->dev_private = priv; + priv->dev_data = eth_dev->data; + eth_dev->data->mac_addrs = priv->mac; + eth_dev->device = dpdk_dev; + eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; + /* Configure the first MAC address by default. */ + if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) { + DRV_LOG(ERR, + "port %u cannot get MAC address, is mlx5_en" + " loaded? (errno: %s).", + eth_dev->data->port_id, strerror(rte_errno)); + err = ENODEV; + goto error; + } + DRV_LOG(INFO, + "port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x", + eth_dev->data->port_id, + mac.addr_bytes[0], mac.addr_bytes[1], + mac.addr_bytes[2], mac.addr_bytes[3], + mac.addr_bytes[4], mac.addr_bytes[5]); +#ifdef RTE_LIBRTE_MLX5_DEBUG + { + char ifname[IF_NAMESIZE]; + + if (mlx5_get_ifname(eth_dev, &ifname) == 0) + DRV_LOG(DEBUG, "port %u ifname is \"%s\"", + eth_dev->data->port_id, ifname); + else + DRV_LOG(DEBUG, "port %u ifname is unknown.", + eth_dev->data->port_id); + } +#endif + /* Get actual MTU if possible. */ + err = mlx5_get_mtu(eth_dev, &priv->mtu); + if (err) { + err = rte_errno; + goto error; + } + DRV_LOG(DEBUG, "port %u MTU is %u.", eth_dev->data->port_id, + priv->mtu); + /* Initialize burst functions to prevent crashes before link-up. */ + eth_dev->rx_pkt_burst = removed_rx_burst; + eth_dev->tx_pkt_burst = removed_tx_burst; + eth_dev->dev_ops = &mlx5_os_dev_ops; + eth_dev->rx_descriptor_status = mlx5_rx_descriptor_status; + eth_dev->tx_descriptor_status = mlx5_tx_descriptor_status; + eth_dev->rx_queue_count = mlx5_rx_queue_count; + /* Register MAC address. */ + claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0)); + priv->flows = 0; + priv->ctrl_flows = 0; + TAILQ_INIT(&priv->flow_meters); + TAILQ_INIT(&priv->flow_meter_profiles); + /* Bring Ethernet device up. */ + DRV_LOG(DEBUG, "port %u forcing Ethernet interface up.", + eth_dev->data->port_id); + /* nl calls are unsupported - set to -1 not to fail on release */ + priv->nl_socket_rdma = -1; + priv->nl_socket_route = -1; + mlx5_set_link_up(eth_dev); + /* + * Even though the interrupt handler is not installed yet, + * interrupts will still trigger on the async_fd from + * Verbs context returned by ibv_open_device(). + */ + mlx5_link_update(eth_dev, 0); + config->dv_esw_en = 0; + /* Detect minimal data bytes to inline. */ + mlx5_set_min_inline(spawn, config); + /* Store device configuration on private structure. */ + priv->config = *config; + /* Create context for virtual machine VLAN workaround. */ + priv->vmwa_context = NULL; + if (config->dv_flow_en) { + err = mlx5_alloc_shared_dr(priv); + if (err) + goto error; + } + /* No supported flow priority number detection. */ + priv->config.flow_prio = -1; + if (!priv->config.dv_esw_en && + priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) { + DRV_LOG(WARNING, "metadata mode %u is not supported " + "(no E-Switch)", priv->config.dv_xmeta_en); + priv->config.dv_xmeta_en = MLX5_XMETA_MODE_LEGACY; + } + mlx5_set_metadata_mask(eth_dev); + if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY && + !priv->sh->dv_regc0_mask) { + DRV_LOG(ERR, "metadata mode %u is not supported " + "(no metadata reg_c[0] is available).", + priv->config.dv_xmeta_en); + err = ENOTSUP; + goto error; + } + mlx5_cache_list_init(&priv->hrxqs, "hrxq", 0, eth_dev, + mlx5_hrxq_create_cb, + mlx5_hrxq_match_cb, + mlx5_hrxq_remove_cb); + /* Query availability of metadata reg_c's. */ + err = mlx5_flow_discover_mreg_c(eth_dev); + if (err < 0) { + err = -err; + goto error; + } + if (!mlx5_flow_ext_mreg_supported(eth_dev)) { + DRV_LOG(DEBUG, + "port %u extensive metadata register is not supported.", + eth_dev->data->port_id); + if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) { + DRV_LOG(ERR, "metadata mode %u is not supported " + "(no metadata registers available).", + priv->config.dv_xmeta_en); + err = ENOTSUP; + goto error; + } + } + if (config->devx && config->dv_flow_en) { + priv->obj_ops = devx_obj_ops; + } else { + DRV_LOG(ERR, "Flow mode %u is not supported " + "(Windows flow must be DevX with DV flow enabled).", + priv->config.dv_flow_en); + err = ENOTSUP; + goto error; + } + mlx5_flow_counter_mode_config(eth_dev); + return eth_dev; +error: + if (priv) { + if (own_domain_id) + claim_zero(rte_eth_switch_domain_free(priv->domain_id)); + mlx5_free(priv); + if (eth_dev != NULL) + eth_dev->data->dev_private = NULL; + } + if (eth_dev != NULL) { + /* mac_addrs must not be freed alone because part of + * dev_private + **/ + eth_dev->data->mac_addrs = NULL; + rte_eth_dev_release_port(eth_dev); + } + if (sh) + mlx5_free_shared_dev_ctx(sh); + MLX5_ASSERT(err > 0); + rte_errno = err; return NULL; } From patchwork Thu Dec 17 17:30:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tal Shnaiderman X-Patchwork-Id: 85354 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 18A36A09F6; Thu, 17 Dec 2020 18:39:14 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 1676FCB05; Thu, 17 Dec 2020 18:33:38 +0100 (CET) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by dpdk.org (Postfix) with ESMTP id A3CDDCA4C for ; Thu, 17 Dec 2020 18:33:10 +0100 (CET) Received: from Internal Mail-Server by MTLPINE1 (envelope-from talshn@nvidia.com) with SMTP; 17 Dec 2020 19:33:06 +0200 Received: from nvidia.com (l-wincomp04-vm.mtl.labs.mlnx [10.237.1.5]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 0BHHX45f021771; Thu, 17 Dec 2020 19:33:06 +0200 From: Tal Shnaiderman To: dev@dpdk.org Cc: thomas@monjalon.net, matan@nvidia.com, rasland@nvidia.com, ophirmu@nvidia.com Date: Thu, 17 Dec 2020 19:30:22 +0200 Message-Id: <20201217173037.11396-21-talshn@nvidia.com> X-Mailer: git-send-email 2.16.1.windows.4 In-Reply-To: <20201217173037.11396-1-talshn@nvidia.com> References: <20201217173037.11396-1-talshn@nvidia.com> Subject: [dpdk-dev] [PATCH 20/35] net/mlx5/windows: support VF PCI address X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Support VF BDF scanning by checking both the BDF and raw BDF provided by DevX. In Linux a PCI address is formatted as: domain, bus, device, function (DBDF). This is right for both a PF and a VF. In Windows a PF also has a DBDF format, but the domain is always 0, while a VF has a special "domain" called "Virtual PCI Bus, Serial" (for example: "Virtual PCI Bus Slot 2 Serial 2") or segment. The full VF format under Windows is called raw DBF. Windows special domain must be considered and DevX must be called to support it. Signed-off-by: Tal Shnaiderman Acked-by: Matan Azrad --- drivers/net/mlx5/windows/mlx5_os.c | 75 +++++++++++++++++++++++++++++++++++--- 1 file changed, 70 insertions(+), 5 deletions(-) diff --git a/drivers/net/mlx5/windows/mlx5_os.c b/drivers/net/mlx5/windows/mlx5_os.c index 985729f2a6..274975ecc6 100644 --- a/drivers/net/mlx5/windows/mlx5_os.c +++ b/drivers/net/mlx5/windows/mlx5_os.c @@ -870,6 +870,68 @@ mlx5_os_set_allmulti(struct rte_eth_dev *dev, int enable) return -ENOTSUP; } +/** + * Detect if a devx_device_bdf object has identical DBDF values to the + * rte_pci_addr found in bus/pci probing + * + * @param[in] devx_bdf + * Pointer to the devx_device_bdf structure. + * @param[in] addr + * Pointer to the rte_pci_addr structure. + * + * @return + * 1 on Device match, 0 on mismatch. + */ +static int +mlx5_match_devx_bdf_to_addr(struct devx_device_bdf *devx_bdf, + struct rte_pci_addr *addr) +{ + if (addr->domain != (devx_bdf->bus_id >> 8) || + addr->bus != (devx_bdf->bus_id & 0xff) || + addr->devid != devx_bdf->dev_id || + addr->function != devx_bdf->fnc_id) { + return 0; + } + return 1; +} + +/** + * Detect if a devx_device_bdf object matches the rte_pci_addr + * found in bus/pci probing + * Compare both the Native/PF BDF and the raw_bdf representing a VF BDF. + * + * @param[in] devx_bdf + * Pointer to the devx_device_bdf structure. + * @param[in] addr + * Pointer to the rte_pci_addr structure. + * + * @return + * 1 on Device match, 0 on mismatch, rte_errno code on failure. + */ +static int +mlx5_match_devx_devices_to_addr(struct devx_device_bdf *devx_bdf, + struct rte_pci_addr *addr) +{ + int err; + struct devx_device mlx5_dev; + + if (mlx5_match_devx_bdf_to_addr(devx_bdf, addr)) + return 1; + /** + * Didn't match on Native/PF BDF, could still + * Match a VF BDF, check it next + */ + err = mlx5_glue->query_device(devx_bdf, &mlx5_dev); + if (err) { + DRV_LOG(ERR, "query_device failed"); + rte_errno = err; + return rte_errno; + } + if (mlx5_match_devx_bdf_to_addr(&mlx5_dev.raw_bdf, addr)) + return 1; + return 0; +} + /** * DPDK callback to register a PCI device. * @@ -917,7 +979,7 @@ mlx5_os_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, struct mlx5_dev_spawn_data *list = NULL; struct mlx5_dev_config dev_config; unsigned int dev_config_vf; - int ret; + int ret, err; uint32_t restore; if (rte_eal_process_type() == RTE_PROC_SECONDARY) { @@ -946,13 +1008,16 @@ mlx5_os_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, struct devx_device_bdf *devx_bdf_match[ret + 1]; while (ret-- > 0) { - if (pci_dev->addr.bus != devx_bdf_devs->bus_id || - pci_dev->addr.devid != devx_bdf_devs->dev_id || - pci_dev->addr.function != devx_bdf_devs->fnc_id) { + err = mlx5_match_devx_devices_to_addr(devx_bdf_devs, + &pci_dev->addr); + if (!err) { devx_bdf_devs++; continue; } - + if (err != 1) { + ret = -err; + goto exit; + } devx_bdf_match[nd++] = devx_bdf_devs; } devx_bdf_match[nd] = NULL; From patchwork Thu Dec 17 17:30:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tal Shnaiderman X-Patchwork-Id: 85355 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9970BA09F6; Thu, 17 Dec 2020 18:39:34 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 5E307CB19; Thu, 17 Dec 2020 18:33:39 +0100 (CET) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by dpdk.org (Postfix) with ESMTP id A3500CA35 for ; Thu, 17 Dec 2020 18:33:10 +0100 (CET) Received: from Internal Mail-Server by MTLPINE1 (envelope-from talshn@nvidia.com) with SMTP; 17 Dec 2020 19:33:06 +0200 Received: from nvidia.com (l-wincomp04-vm.mtl.labs.mlnx [10.237.1.5]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 0BHHX45g021771; Thu, 17 Dec 2020 19:33:06 +0200 From: Tal Shnaiderman To: dev@dpdk.org Cc: thomas@monjalon.net, matan@nvidia.com, rasland@nvidia.com, ophirmu@nvidia.com Date: Thu, 17 Dec 2020 19:30:23 +0200 Message-Id: <20201217173037.11396-22-talshn@nvidia.com> X-Mailer: git-send-email 2.16.1.windows.4 In-Reply-To: <20201217173037.11396-1-talshn@nvidia.com> References: <20201217173037.11396-1-talshn@nvidia.com> Subject: [dpdk-dev] [PATCH 21/35] net/mlx5/linux: wrap adjust flow priority with OS calls X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Ophir Munk mlx5_flow_adjust_priority() is used to adjust priorities according to priorities levels. It is Verbs based and it is called from shared code (mlx5_flow_dv.c). Therefore, wrap it in an OS API. Signed-off-by: Ophir Munk Acked-by: Matan Azrad --- drivers/net/mlx5/linux/mlx5_flow_os.h | 20 ++++++++++++++++++++ drivers/net/mlx5/mlx5_flow_dv.c | 5 +++-- 2 files changed, 23 insertions(+), 2 deletions(-) diff --git a/drivers/net/mlx5/linux/mlx5_flow_os.h b/drivers/net/mlx5/linux/mlx5_flow_os.h index a6bd2c01e1..c7003a194e 100644 --- a/drivers/net/mlx5/linux/mlx5_flow_os.h +++ b/drivers/net/mlx5/linux/mlx5_flow_os.h @@ -365,4 +365,24 @@ mlx5_flow_os_destroy_flow_action(void *action) return mlx5_glue->destroy_flow_action(action); } +/** + * OS wrapper over Verbs API. + * Adjust flow priority based on the highest layer and the request priority. + * + * @param[in] dev + * Pointer to the Ethernet device structure. + * @param[in] priority + * The rule base priority. + * @param[in] subpriority + * The priority based on the items. + * + * @return + * The new priority. + */ +static inline uint32_t +mlx5_os_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority, + uint32_t subpriority) +{ + return mlx5_flow_adjust_priority(dev, priority, subpriority); +} #endif /* RTE_PMD_MLX5_FLOW_OS_H_ */ diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index 911042b677..40c8e54a09 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -10600,8 +10600,9 @@ flow_dv_translate(struct rte_eth_dev *dev, /* Register matcher. */ matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf, matcher.mask.size); - matcher.priority = mlx5_flow_adjust_priority(dev, priority, - matcher.priority); + matcher.priority = mlx5_os_flow_adjust_priority(dev, + priority, + matcher.priority); /* reserved field no needs to be set to 0 here. */ tbl_key.domain = attr->transfer; tbl_key.direction = attr->egress; From patchwork Thu Dec 17 17:30:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tal Shnaiderman X-Patchwork-Id: 85360 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 517A2A09F6; Thu, 17 Dec 2020 18:41:09 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 6E952CB85; Thu, 17 Dec 2020 18:33:46 +0100 (CET) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by dpdk.org (Postfix) with ESMTP id D75DECA3A for ; Thu, 17 Dec 2020 18:33:10 +0100 (CET) Received: from Internal Mail-Server by MTLPINE1 (envelope-from talshn@nvidia.com) with SMTP; 17 Dec 2020 19:33:06 +0200 Received: from nvidia.com (l-wincomp04-vm.mtl.labs.mlnx [10.237.1.5]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 0BHHX45h021771; Thu, 17 Dec 2020 19:33:06 +0200 From: Tal Shnaiderman To: dev@dpdk.org Cc: thomas@monjalon.net, matan@nvidia.com, rasland@nvidia.com, ophirmu@nvidia.com Date: Thu, 17 Dec 2020 19:30:24 +0200 Message-Id: <20201217173037.11396-23-talshn@nvidia.com> X-Mailer: git-send-email 2.16.1.windows.4 In-Reply-To: <20201217173037.11396-1-talshn@nvidia.com> References: <20201217173037.11396-1-talshn@nvidia.com> Subject: [dpdk-dev] [PATCH 22/35] net/mlx5/linux: add OS default miss flow action X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Ophir Munk Wrap glue call dr_create_flow_action_default_miss() with an OS API. This commit is a follow up on [1]. [1] commit d4d85aa6f13a ("common/mlx5: add default miss action") commit b293fbf9672b ("net/mlx5: add OS specific flow actions operations") Signed-off-by: Ophir Munk Acked-by: Matan Azrad --- drivers/net/mlx5/linux/mlx5_flow_os.h | 16 ++++++++++++++++ drivers/net/mlx5/mlx5_flow_dv.c | 8 +++++--- 2 files changed, 21 insertions(+), 3 deletions(-) diff --git a/drivers/net/mlx5/linux/mlx5_flow_os.h b/drivers/net/mlx5/linux/mlx5_flow_os.h index c7003a194e..7706b3be48 100644 --- a/drivers/net/mlx5/linux/mlx5_flow_os.h +++ b/drivers/net/mlx5/linux/mlx5_flow_os.h @@ -350,6 +350,22 @@ mlx5_flow_os_create_flow_action_drop(void **action) return (*action) ? 0 : -1; } +/** + * Create flow action: default miss. + * + * @param[out] action + * Pointer to a valid action on success, NULL otherwise. + * + * @return + * 0 on success, or -1 on failure and errno is set. + */ +static inline int +mlx5_flow_os_create_flow_action_default_miss(void **action) +{ + *action = mlx5_glue->dr_create_flow_action_default_miss(); + return (*action) ? 0 : -1; +} + /** * Destroy flow action. * diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index 40c8e54a09..6d377b6dab 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -8763,11 +8763,13 @@ flow_dv_sample_create_cb(struct mlx5_cache_list *list __rte_unused, "for sample"); goto error; } + int ret; + cache_resource->normal_path_tbl = tbl; if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) { - cache_resource->default_miss = - mlx5_glue->dr_create_flow_action_default_miss(); - if (!cache_resource->default_miss) { + ret = mlx5_flow_os_create_flow_action_default_miss + (&cache_resource->default_miss); + if (!ret) { rte_flow_error_set(error, ENOMEM, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, From patchwork Thu Dec 17 17:30:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tal Shnaiderman X-Patchwork-Id: 85359 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id C31EAA09F6; Thu, 17 Dec 2020 18:40:52 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 07BB1CB79; Thu, 17 Dec 2020 18:33:45 +0100 (CET) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by dpdk.org (Postfix) with ESMTP id D80C4CA51 for ; Thu, 17 Dec 2020 18:33:10 +0100 (CET) Received: from Internal Mail-Server by MTLPINE1 (envelope-from talshn@nvidia.com) with SMTP; 17 Dec 2020 19:33:06 +0200 Received: from nvidia.com (l-wincomp04-vm.mtl.labs.mlnx [10.237.1.5]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 0BHHX45i021771; Thu, 17 Dec 2020 19:33:06 +0200 From: Tal Shnaiderman To: dev@dpdk.org Cc: thomas@monjalon.net, matan@nvidia.com, rasland@nvidia.com, ophirmu@nvidia.com, stable@dpdk.org Date: Thu, 17 Dec 2020 19:30:25 +0200 Message-Id: <20201217173037.11396-24-talshn@nvidia.com> X-Mailer: git-send-email 2.16.1.windows.4 In-Reply-To: <20201217173037.11396-1-talshn@nvidia.com> References: <20201217173037.11396-1-talshn@nvidia.com> Subject: [dpdk-dev] [PATCH 23/35] net/mlx5/linux: fix add OS dest_devx_tir action X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Ophir Munk Wrap glue call dv_create_flow_action_dest_devx_tir() with an OS API. Fixes: b293fbf9672b ("net/mlx5: add OS specific flow actions operations") Cc: stable@dpdk.org Signed-off-by: Ophir Munk Acked-by: Matan Azrad --- drivers/net/mlx5/linux/mlx5_flow_os.h | 26 ++++++++++++++++++++++++++ drivers/net/mlx5/mlx5_devx.c | 7 +++---- 2 files changed, 29 insertions(+), 4 deletions(-) diff --git a/drivers/net/mlx5/linux/mlx5_flow_os.h b/drivers/net/mlx5/linux/mlx5_flow_os.h index 7706b3be48..6f3b7324ff 100644 --- a/drivers/net/mlx5/linux/mlx5_flow_os.h +++ b/drivers/net/mlx5/linux/mlx5_flow_os.h @@ -366,6 +366,32 @@ mlx5_flow_os_create_flow_action_default_miss(void **action) return (*action) ? 0 : -1; } +/** + * Create flow action: dest_devx_tir + * + * @param[in] tir + * Pointer to DevX tir object + * @param[out] action + * Pointer to a valid action on success, NULL otherwise. + * + * @return + * 0 on success, or -1 on failure and errno is set. + */ +static inline int +mlx5_flow_os_create_flow_action_dest_devx_tir(struct mlx5_devx_obj *tir, + void **action) +{ +#ifdef HAVE_IBV_FLOW_DV_SUPPORT + *action = mlx5_glue->dv_create_flow_action_dest_devx_tir(tir->obj); + return (*action) ? 0 : -1; +#else + /* If no DV support - skip the operation and return success */ + RTE_SET_USED(tir); + *action = 0; + return 0; +#endif +} + /** * Destroy flow action. * diff --git a/drivers/net/mlx5/mlx5_devx.c b/drivers/net/mlx5/mlx5_devx.c index 84a5c55ee0..aa8ca7f401 100644 --- a/drivers/net/mlx5/mlx5_devx.c +++ b/drivers/net/mlx5/mlx5_devx.c @@ -23,7 +23,7 @@ #include "mlx5_utils.h" #include "mlx5_devx.h" #include "mlx5_flow.h" - +#include "mlx5_flow_os.h" /** * Modify RQ vlan stripping offload @@ -942,9 +942,8 @@ mlx5_devx_hrxq_new(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq, goto error; } #ifdef HAVE_IBV_FLOW_DV_SUPPORT - hrxq->action = mlx5_glue->dv_create_flow_action_dest_devx_tir - (hrxq->tir->obj); - if (!hrxq->action) { + if (mlx5_flow_os_create_flow_action_dest_devx_tir(hrxq->tir, + &hrxq->action)) { rte_errno = errno; goto error; } From patchwork Thu Dec 17 17:30:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tal Shnaiderman X-Patchwork-Id: 85364 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id ABE42A09F6; Thu, 17 Dec 2020 18:42:21 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id A8C28CBF4; Thu, 17 Dec 2020 18:33:51 +0100 (CET) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by dpdk.org (Postfix) with ESMTP id D83F9CA52 for ; Thu, 17 Dec 2020 18:33:10 +0100 (CET) Received: from Internal Mail-Server by MTLPINE1 (envelope-from talshn@nvidia.com) with SMTP; 17 Dec 2020 19:33:06 +0200 Received: from nvidia.com (l-wincomp04-vm.mtl.labs.mlnx [10.237.1.5]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 0BHHX45j021771; Thu, 17 Dec 2020 19:33:06 +0200 From: Tal Shnaiderman To: dev@dpdk.org Cc: thomas@monjalon.net, matan@nvidia.com, rasland@nvidia.com, ophirmu@nvidia.com, Dekel Peled Date: Thu, 17 Dec 2020 19:30:26 +0200 Message-Id: <20201217173037.11396-25-talshn@nvidia.com> X-Mailer: git-send-email 2.16.1.windows.4 In-Reply-To: <20201217173037.11396-1-talshn@nvidia.com> References: <20201217173037.11396-1-talshn@nvidia.com> Subject: [dpdk-dev] [PATCH 24/35] net/mlx5/windows: introduce flow support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Ophir Munk This patch adds the initial flow framework under Windows OS. It supports a subset of filters (ETH, IPV4, UDP) and a QUEUE action. It is based on DevX mechanism to send commands to the NIC through the kernel. It does not support steering rules (i.e. writing directly to the NIC memory). The Windows framework uses the existing DV framework where file mlx5_flow_dv.c remains intact. Steps involved in flow creation: 1. Create a domain (RX, TX, FDB). Since domains are created by steering rules and not with DevX, Windows does not require a domain object (this means switch dev mode which requires an FDB domain is not supported). 2. Create a table object. Windows only supports table 0. The call to mlx5_flow_os_create_flow_tbl() silently returns successfully. 3. Create a matcher object. A matcher struct is created by calling mlx5_flow_os_create_flow_matcher(). The matcher validation and translation are part of the DV implementation. The matcher bits that were created by DV in standard PRM format are copied into the matcher struct. 4. Create an action object. The call to mlx5_flow_os_create_flow_action_dest_devx_tir() creates an action struct with the TIR type and id. This struct will be a parameter later in a call to flow creation. All other action calls (e.g. packet reformat, header modification, jump to flow table, etc) return with a non supported error. 5. Create the flow. The call to mlx5_flow_os_create_flow() receives the matcher struct, action struct, and copy them into Windows specific fs_rule struct, then it calls glue API devx_fs_rule_add(). Details on additional APIs: * mlx5_flow_os_get_type() is called during flow type selection. In Windows it constantly returns MLX5_FLOW_TYPE_DV. * mlx5_flow_os_item_supported() is called before starting DV items validation or translation. It filters out the OS non supported items in advance. * mlx5_flow_os_action_supported() is called before starting DV actions validation or translation. It filters out the OS non supported actions in advance. * mlx5_flow_adjust_priority() is an OS stub for flow priority adjustment. Windows only supports flow priority 0. * Alarm API: mlx5_os_alarm_cancel() and mlx5_os_alarm_set() are implemented in Windows to match their Linux counterpart, see [1]. Currently they return -ENOTSUP. [1] ("net/mlx5/linux: wrap rte alarm API with mlx5") Signed-off-by: Ophir Munk Signed-off-by: Dekel Peled Acked-by: Matan Azrad --- drivers/common/mlx5/windows/mlx5_win_defs.h | 7 + drivers/net/mlx5/windows/meson.build | 1 + drivers/net/mlx5/windows/mlx5_flow_os.c | 188 ++++++++++++++ drivers/net/mlx5/windows/mlx5_flow_os.h | 363 ++++++++++++++++++++++++++++ 4 files changed, 559 insertions(+) create mode 100644 drivers/net/mlx5/windows/mlx5_flow_os.c create mode 100644 drivers/net/mlx5/windows/mlx5_flow_os.h diff --git a/drivers/common/mlx5/windows/mlx5_win_defs.h b/drivers/common/mlx5/windows/mlx5_win_defs.h index d8f20993e0..27dcf40819 100644 --- a/drivers/common/mlx5/windows/mlx5_win_defs.h +++ b/drivers/common/mlx5/windows/mlx5_win_defs.h @@ -169,4 +169,11 @@ struct mlx5_wqe_data_seg { #define IBV_RAW_PACKET_CAP_CVLAN_STRIPPING (1 << 0) #define IBV_RAW_PACKET_CAP_SCATTER_FCS (1 << 1) #define IBV_QPT_RAW_PACKET 8 + +enum { + MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT = 0x0, + MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE = 0x1, + MLX5_FLOW_CONTEXT_DEST_TYPE_TIR = 0x2, + MLX5_FLOW_CONTEXT_DEST_TYPE_QP = 0x3, +}; #endif /* __MLX5_WIN_DEFS_H__ */ diff --git a/drivers/net/mlx5/windows/meson.build b/drivers/net/mlx5/windows/meson.build index 87e34d3cda..8404dc1247 100644 --- a/drivers/net/mlx5/windows/meson.build +++ b/drivers/net/mlx5/windows/meson.build @@ -7,5 +7,6 @@ sources += files( 'mlx5_mp_os.c', 'mlx5_ethdev_os.c', 'mlx5_vlan_os.c', + 'mlx5_flow_os.c', ) diff --git a/drivers/net/mlx5/windows/mlx5_flow_os.c b/drivers/net/mlx5/windows/mlx5_flow_os.c new file mode 100644 index 0000000000..8c504fc69c --- /dev/null +++ b/drivers/net/mlx5/windows/mlx5_flow_os.c @@ -0,0 +1,188 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright 2020 Mellanox Technologies, Ltd + */ + +#include "mlx5_flow_os.h" +#include "mlx5_win_ext.h" + +/** + * Verify the @p attributes will be correctly understood by the NIC and store + * them in the @p flow if everything is correct. + * + * @param[in] dev + * Pointer to dev struct. + * @param[in] attributes + * Pointer to flow attributes + * @param[in] external + * This flow rule is created by request external to PMD. + * @param[out] error + * Pointer to error structure. + * + * @return + * - 0 on success and non root table (not a valid option for Windows yet). + * - 1 on success and root table. + * - a negative errno value otherwise and rte_errno is set. + */ +int +mlx5_flow_os_validate_flow_attributes(struct rte_eth_dev *dev, + const struct rte_flow_attr *attributes, + bool external, + struct rte_flow_error *error) +{ + int ret = 1; + + RTE_SET_USED(dev); + RTE_SET_USED(external); + if (attributes->group) + return rte_flow_error_set(error, ENOTSUP, + RTE_FLOW_ERROR_TYPE_ATTR_GROUP, + NULL, + "groups are not supported"); + if (attributes->priority) + return rte_flow_error_set(error, ENOTSUP, + RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY, + NULL, + "priorities are not supported"); + if (attributes->transfer) + return rte_flow_error_set(error, ENOTSUP, + RTE_FLOW_ERROR_TYPE_ATTR_TRANSFER, + NULL, + "transfer not supported"); + if (!(attributes->ingress)) + return rte_flow_error_set(error, ENOTSUP, + RTE_FLOW_ERROR_TYPE_ATTR_INGRESS, + NULL, "must specify ingress only"); + return ret; +} + +/** + * Create flow matcher in a flow table. + * + * @param[in] ctx + * Pointer to relevant device context. + * @param[in] attr + * Pointer to relevant attributes. + * @param[in] table + * Pointer to table object. + * @param[out] matcher + * Pointer to a valid flow matcher object on success, NULL otherwise. + * + * @return + * 0 on success, or errno on failure. + */ +int +mlx5_flow_os_create_flow_matcher(void *ctx, + void *attr, + void *table, + void **matcher) +{ + RTE_SET_USED(ctx); + RTE_SET_USED(attr); + RTE_SET_USED(table); + *matcher = NULL; + rte_errno = ENOTSUP; + return -rte_errno; +} + +/** + * Destroy flow matcher. + * + * @param[in] matcher + * Pointer to matcher object to destroy. + * + * @return + * 0 on success, or the value of errno on failure. + */ +int +mlx5_flow_os_destroy_flow_matcher(void *matcher) +{ + RTE_SET_USED(matcher); + rte_errno = ENOTSUP; + return -rte_errno; +} + +/** + * Create flow action: dest_devx_tir + * + * @param[in] tir + * Pointer to DevX tir object + * @param[out] action + * Pointer to a valid action on success, NULL otherwise. + * + * @return + * 0 on success, or errno on failure. + */ +int +mlx5_flow_os_create_flow_action_dest_devx_tir(struct mlx5_devx_obj *tir, + void **action) +{ + RTE_SET_USED(tir); + *action = NULL; + rte_errno = ENOTSUP; + return -rte_errno; +} + +/** + * Destroy flow action. + * + * @param[in] action + * Pointer to action object to destroy. + * + * @return + * 0 on success, or the value of errno on failure. + */ +int +mlx5_flow_os_destroy_flow_action(void *action) +{ + RTE_SET_USED(action); + rte_errno = ENOTSUP; + return -rte_errno; +} + +/** + * Create flow rule. + * + * @param[in] matcher + * Pointer to match mask structure. + * @param[in] match_value + * Pointer to match value structure. + * @param[in] num_actions + * Number of actions in flow rule. + * @param[in] actions + * Pointer to array of flow rule actions. + * @param[out] flow + * Pointer to a valid flow rule object on success, NULL otherwise. + * + * @return + * 0 on success, or errno on failure. + */ +int +mlx5_flow_os_create_flow(void *matcher, void *match_value, + size_t num_actions, + void *actions[], void **flow) +{ + RTE_SET_USED(matcher); + RTE_SET_USED(match_value); + RTE_SET_USED(num_actions); + RTE_SET_USED(actions); + *flow = NULL; + rte_errno = ENOTSUP; + return -rte_errno; +} + +/** + * Destroy flow rule. + * + * @param[in] drv_flow_ptr + * Pointer to flow rule object. + * + * @return + * 0 on success, errno on failure. + */ +int +mlx5_flow_os_destroy_flow(void *drv_flow_ptr) +{ + RTE_SET_USED(dev_flow_ptr); + rte_errno = ENOTSUP; + return -rte_errno; +} diff --git a/drivers/net/mlx5/windows/mlx5_flow_os.h b/drivers/net/mlx5/windows/mlx5_flow_os.h new file mode 100644 index 0000000000..1e762c17dc --- /dev/null +++ b/drivers/net/mlx5/windows/mlx5_flow_os.h @@ -0,0 +1,363 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright 2020 Mellanox Technologies, Ltd + */ + +#ifndef RTE_PMD_MLX5_FLOW_OS_H_ +#define RTE_PMD_MLX5_FLOW_OS_H_ + +#include "mlx5_flow.h" + +#if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) +extern const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops; +#endif + +/** + * Get OS enforced flow type. MLX5_FLOW_TYPE_MAX means "non enforced type". + * + * @return + * Flow type (MLX5_FLOW_TYPE_MAX) + */ +static inline enum mlx5_flow_drv_type +mlx5_flow_os_get_type(void) +{ + return MLX5_FLOW_TYPE_DV; +} + +/** + * Check if item type is supported. + * + * @param item + * Item type to check. + * + * @return + * True is this item type is supported, false if not supported. + */ +static inline bool +mlx5_flow_os_item_supported(int item) +{ + switch (item) { + case RTE_FLOW_ITEM_TYPE_END: + case RTE_FLOW_ITEM_TYPE_VOID: + case RTE_FLOW_ITEM_TYPE_ETH: + case RTE_FLOW_ITEM_TYPE_IPV4: + case RTE_FLOW_ITEM_TYPE_UDP: + return true; + default: + return false; + } +} + +/** + * Check if action type is supported. + * + * @param action + * Action type to check. + * + * @return + * True is this action type is supported, false if not supported. + */ +static inline bool +mlx5_flow_os_action_supported(int action) +{ + switch (action) { + case RTE_FLOW_ACTION_TYPE_END: + case RTE_FLOW_ACTION_TYPE_VOID: + case RTE_FLOW_ACTION_TYPE_QUEUE: + case RTE_FLOW_ACTION_TYPE_RSS: + return true; + default: + return false; + } +} + +/** + * Create flow table. + * + * @param[in] domain + * Pointer to relevant domain. + * @param[in] table_id + * Table ID. + * @param[out] table + * NULL (no table object required) + * + * @return + * 0 if table_id is 0, negative value otherwise and errno is set. + */ +static inline int +mlx5_flow_os_create_flow_tbl(void *domain, uint32_t table_id, void **table) +{ + RTE_SET_USED(domain); + *table = NULL; + if (table_id) { + rte_errno = ENOTSUP; + return -rte_errno; + } + return 0; +} + +/** + * Destroy flow table. + * + * @param table + * Pointer to table to destroy. + * + * @return + * 0 on success (silently ignored). + */ +static inline int +mlx5_flow_os_destroy_flow_tbl(void *table) +{ + RTE_SET_USED(table); + /* Silently ignore */ + return 0; +} + +/** + * Create flow action: packet reformat. + * + * @param[in] ctx + * Pointer to relevant device context. + * @param[in] domain + * Pointer to domain handler. + * @param[in] resource + * Pointer to action data resource. + * @param[out] action + * Pointer to a valid action on success, NULL otherwise. + * + * + * @return + * 0 on success, or negative value on failure and errno is set. + */ +static inline int +mlx5_flow_os_create_flow_action_packet_reformat(void *ctx, void *domain, + void *resource, void **action) +{ + RTE_SET_USED(ctx); + RTE_SET_USED(domain); + RTE_SET_USED(resource); + RTE_SET_USED(action); + rte_errno = ENOTSUP; + return -rte_errno; +} + +/** + * Create flow action: modify header. + * + * @param[in] ctx + * Pointer to relevant device context. + * @param[in] domain + * Pointer to domain handler. + * @param[in] resource + * Pointer to action data resource. + * @param[in] actions_len + * Total length of actions data in resource. + * @param[out] action + * Pointer to a valid action on success, NULL otherwise. + * + * + * @return + * 0 on success, or -1 on failure and errno is set. + */ +static inline int +mlx5_flow_os_create_flow_action_modify_header(void *ctx, + void *domain, + void *resource, + uint32_t actions_len, + void **action) +{ + RTE_SET_USED(ctx); + RTE_SET_USED(domain); + RTE_SET_USED(resource); + RTE_SET_USED(actions_len); + RTE_SET_USED(action); + rte_errno = ENOTSUP; + return -rte_errno; +} + +/** + * Create flow action: destination flow table. + * + * @param[in] tbl_obj + * Pointer to destination table object. + * @param[out] action + * Pointer to a valid action on success, NULL otherwise. + * + * @return + * 0 on success, or negative value on failure and errno is set. + */ +static inline int +mlx5_flow_os_create_flow_action_dest_flow_tbl(void *tbl_obj, void **action) +{ + RTE_SET_USED(tbl_obj); + RTE_SET_USED(action); + rte_errno = ENOTSUP; + return -rte_errno; +} + +/** + * Create flow action: destination port. + * + * @param[in] domain + * Pointer to domain handler. + * @param[in] port_id + * Destination port ID. + * @param[out] action + * Pointer to a valid action on success, NULL otherwise. + * + * @return + * 0 on success, or negative value on failure and errno is set. + */ +static inline int +mlx5_flow_os_create_flow_action_dest_port(void *domain, uint32_t port_id, + void **action) +{ + RTE_SET_USED(domain); + RTE_SET_USED(port_id); + *action = NULL; + rte_errno = ENOTSUP; + return -rte_errno; +} + +/** + * Create flow action: push vlan. + * + * @param[in] domain + * Pointer to domain handler. + * @param[in] vlan_tag + * VLAN tag value. + * @param[out] action + * Pointer to a valid action on success, NULL otherwise. + * + * @return + * 0 on success, or negative value on failure and errno is set. + */ +static inline int +mlx5_flow_os_create_flow_action_push_vlan(void *domain, rte_be32_t vlan_tag, + void **action) +{ + RTE_SET_USED(domain); + RTE_SET_USED(vlan_tag); + *action = NULL; + rte_errno = ENOTSUP; + return -rte_errno; +} + +/** + * Create flow action: count. + * + * @param[in] cnt_obj + * Pointer to DevX counter object. + * @param[in] offset + * Offset of counter in array. + * @param[out] action + * Pointer to a valid action on success, NULL otherwise. + * + * @return + * 0 on success, or negative value on failure and errno is set. + */ +static inline int +mlx5_flow_os_create_flow_action_count(void *cnt_obj, uint16_t offset, + void **action) +{ + RTE_SET_USED(cnt_obj); + RTE_SET_USED(offset); + *action = NULL; + rte_errno = ENOTSUP; + return -rte_errno; +} + +/** + * Create flow action: tag. + * + * @param[in] tag + * Tag value. + * @param[out] action + * Pointer to a valid action on success, NULL otherwise. + * + * @return + * 0 on success, or negative value on failure and errno is set. + */ +static inline int +mlx5_flow_os_create_flow_action_tag(uint32_t tag, void **action) +{ + RTE_SET_USED(tag); + *action = NULL; + rte_errno = ENOTSUP; + return -rte_errno; +} + +/** + * Create flow action: drop. + * + * @param[out] action + * Pointer to a valid action on success, NULL otherwise. + * + * @return + * 0 on success, or negative value on failure and errno is set. + */ +static inline int +mlx5_flow_os_create_flow_action_drop(void **action) +{ + *action = NULL; + rte_errno = ENOTSUP; + return -rte_errno; +} + +/** + * Create flow action: default miss. + * + * @param[out] action + * NULL action pointer. + * + * @return + * 0 as success. + */ +static inline int +mlx5_flow_os_create_flow_action_default_miss(void **action) +{ + *action = 0; + /* Silently ignore */ + return 0; +} + +/** + * OS stub for mlx5_flow_adjust_priority() API. + * Windows only supports flow priority 0 that cannot be adjusted. + * + * @param[in] dev + * Pointer to the Ethernet device structure. + * @param[in] priority + * The rule base priority. + * @param[in] subpriority + * The priority based on the items. + * + * @return + * 0 + */ +static inline uint32_t +mlx5_os_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority, + uint32_t subpriority) +{ + RTE_SET_USED(dev); + RTE_SET_USED(priority); + RTE_SET_USED(subpriority); + return 0; +} + +int mlx5_flow_os_validate_flow_attributes(struct rte_eth_dev *dev, + const struct rte_flow_attr *attributes, + bool external, + struct rte_flow_error *error); +int mlx5_flow_os_create_flow_matcher(void *ctx, + void *attr, + void *table, + void **matcher); +int mlx5_flow_os_destroy_flow_matcher(void *matcher); +int mlx5_flow_os_create_flow_action_dest_devx_tir(struct mlx5_devx_obj *tir, + void **action); +int mlx5_flow_os_destroy_flow_action(void *action); +int mlx5_flow_os_create_flow(void *matcher, void *match_value, + size_t num_actions, + void *actions[], void **flow); +int mlx5_flow_os_destroy_flow(void *drv_flow_ptr); +#endif /* RTE_PMD_MLX5_FLOW_OS_H_ */ From patchwork Thu Dec 17 17:30:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tal Shnaiderman X-Patchwork-Id: 85362 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 26B10A09F6; Thu, 17 Dec 2020 18:41:43 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 00A01CBAC; Thu, 17 Dec 2020 18:33:48 +0100 (CET) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by dpdk.org (Postfix) with ESMTP id F1E2FCA54 for ; Thu, 17 Dec 2020 18:33:10 +0100 (CET) Received: from Internal Mail-Server by MTLPINE1 (envelope-from talshn@nvidia.com) with SMTP; 17 Dec 2020 19:33:07 +0200 Received: from nvidia.com (l-wincomp04-vm.mtl.labs.mlnx [10.237.1.5]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 0BHHX45k021771; Thu, 17 Dec 2020 19:33:07 +0200 From: Tal Shnaiderman To: dev@dpdk.org Cc: thomas@monjalon.net, matan@nvidia.com, rasland@nvidia.com, ophirmu@nvidia.com Date: Thu, 17 Dec 2020 19:30:27 +0200 Message-Id: <20201217173037.11396-26-talshn@nvidia.com> X-Mailer: git-send-email 2.16.1.windows.4 In-Reply-To: <20201217173037.11396-1-talshn@nvidia.com> References: <20201217173037.11396-1-talshn@nvidia.com> Subject: [dpdk-dev] [PATCH 25/35] net/mlx5/windows: create flow matcher object X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Ophir Munk This commit implements the mlx5_flow_os_create_flow_matcher() API. It is the Linux rdma-core equivalent implementation. Missing rdma-core parameters (e.g. struct mlx5dv_flow_match_parameters) are added to file mlx5_win_defs.h. The API allocates space to hold the PRM bits in PRM fte_match_param format and copy the DV translated PRM bits into the matcher struct. This matcher struct will be used later by the flow creation API. Signed-off-by: Ophir Munk Acked-by: Matan Azrad --- drivers/common/mlx5/windows/mlx5_win_defs.h | 57 +++++++++++++++++++++++++++++ drivers/net/mlx5/windows/mlx5_flow_os.c | 32 ++++++++++++---- drivers/net/mlx5/windows/mlx5_flow_os.h | 1 + 3 files changed, 83 insertions(+), 7 deletions(-) diff --git a/drivers/common/mlx5/windows/mlx5_win_defs.h b/drivers/common/mlx5/windows/mlx5_win_defs.h index 27dcf40819..231c3220a3 100644 --- a/drivers/common/mlx5/windows/mlx5_win_defs.h +++ b/drivers/common/mlx5/windows/mlx5_win_defs.h @@ -132,6 +132,63 @@ enum { #define MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL 0x3 #endif +enum ibv_flow_flags { + IBV_FLOW_ATTR_FLAGS_ALLOW_LOOP_BACK = 1 << 0, + IBV_FLOW_ATTR_FLAGS_DONT_TRAP = 1 << 1, + IBV_FLOW_ATTR_FLAGS_EGRESS = 1 << 2, +}; + +enum ibv_flow_attr_type { + /* Steering according to rule specifications. */ + IBV_FLOW_ATTR_NORMAL = 0x0, + /* + * Default unicast and multicast rule - + * receive all Eth traffic which isn't steered to any QP. + */ + IBV_FLOW_ATTR_ALL_DEFAULT = 0x1, + /* + * Default multicast rule - + * receive all Eth multicast traffic which isn't steered to any QP. + */ + IBV_FLOW_ATTR_MC_DEFAULT = 0x2, + /* Sniffer rule - receive all port traffic. */ + IBV_FLOW_ATTR_SNIFFER = 0x3, +}; + +enum mlx5dv_flow_table_type { + MLX5_IB_UAPI_FLOW_TABLE_TYPE_NIC_RX = 0x0, + MLX5_IB_UAPI_FLOW_TABLE_TYPE_NIC_TX = 0x1, + MLX5_IB_UAPI_FLOW_TABLE_TYPE_FDB = 0x2, + MLX5_IB_UAPI_FLOW_TABLE_TYPE_RDMA_RX = 0x3, +}; + +#define MLX5DV_FLOW_TABLE_TYPE_NIC_RX MLX5_IB_UAPI_FLOW_TABLE_TYPE_NIC_RX +#define MLX5DV_FLOW_TABLE_TYPE_NIC_TX MLX5_IB_UAPI_FLOW_TABLE_TYPE_NIC_TX +#define MLX5DV_FLOW_TABLE_TYPE_FDB MLX5_IB_UAPI_FLOW_TABLE_TYPE_FDB +#define MLX5DV_FLOW_TABLE_TYPE_RDMA_RX MLX5_IB_UAPI_FLOW_TABLE_TYPE_RDMA_RX + +struct mlx5dv_flow_match_parameters { + size_t match_sz; + uint64_t match_buf[]; /* Device spec format */ +}; + +struct mlx5dv_flow_matcher_attr { + enum ibv_flow_attr_type type; + uint32_t flags; /* From enum ibv_flow_flags. */ + uint16_t priority; + uint8_t match_criteria_enable; /* Device spec format. */ + struct mlx5dv_flow_match_parameters *match_mask; + uint64_t comp_mask; /* Use mlx5dv_flow_matcher_attr_mask. */ + enum mlx5dv_flow_table_type ft_type; +}; + +/* Windows specific mlx5_matcher. */ +struct mlx5_matcher { + void *ctx; + struct mlx5dv_flow_matcher_attr attr; + uint64_t match_buf[]; +}; + struct mlx5_err_cqe { uint8_t rsvd0[32]; uint32_t srqn; diff --git a/drivers/net/mlx5/windows/mlx5_flow_os.c b/drivers/net/mlx5/windows/mlx5_flow_os.c index 8c504fc69c..0ade518910 100644 --- a/drivers/net/mlx5/windows/mlx5_flow_os.c +++ b/drivers/net/mlx5/windows/mlx5_flow_os.c @@ -76,12 +76,31 @@ mlx5_flow_os_create_flow_matcher(void *ctx, void *table, void **matcher) { - RTE_SET_USED(ctx); - RTE_SET_USED(attr); + struct mlx5dv_flow_matcher_attr *mattr; + RTE_SET_USED(table); *matcher = NULL; - rte_errno = ENOTSUP; - return -rte_errno; + mattr = attr; + if (mattr->type != IBV_FLOW_ATTR_NORMAL) { + rte_errno = ENOTSUP; + return -rte_errno; + } + struct mlx5_matcher *mlx5_matcher = + mlx5_malloc(MLX5_MEM_ZERO, + sizeof(struct mlx5_matcher) + + MLX5_ST_SZ_BYTES(fte_match_param), + 0, SOCKET_ID_ANY); + if (!mlx5_matcher) { + rte_errno = ENOMEM; + return -rte_errno; + } + mlx5_matcher->ctx = ctx; + memcpy(&mlx5_matcher->attr, attr, sizeof(mlx5_matcher->attr)); + memcpy(&mlx5_matcher->match_buf, + mattr->match_mask->match_buf, + MLX5_ST_SZ_BYTES(fte_match_param)); + *matcher = mlx5_matcher; + return 0; } /** @@ -96,9 +115,8 @@ mlx5_flow_os_create_flow_matcher(void *ctx, int mlx5_flow_os_destroy_flow_matcher(void *matcher) { - RTE_SET_USED(matcher); - rte_errno = ENOTSUP; - return -rte_errno; + mlx5_free(matcher); + return 0; } /** diff --git a/drivers/net/mlx5/windows/mlx5_flow_os.h b/drivers/net/mlx5/windows/mlx5_flow_os.h index 1e762c17dc..50185669cf 100644 --- a/drivers/net/mlx5/windows/mlx5_flow_os.h +++ b/drivers/net/mlx5/windows/mlx5_flow_os.h @@ -6,6 +6,7 @@ #define RTE_PMD_MLX5_FLOW_OS_H_ #include "mlx5_flow.h" +#include "mlx5_malloc.h" #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) extern const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops; From patchwork Thu Dec 17 17:30:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tal Shnaiderman X-Patchwork-Id: 85361 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 54E45A09F6; Thu, 17 Dec 2020 18:41:26 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id C2E9BCB9F; Thu, 17 Dec 2020 18:33:47 +0100 (CET) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by dpdk.org (Postfix) with ESMTP id F3324CA56 for ; Thu, 17 Dec 2020 18:33:10 +0100 (CET) Received: from Internal Mail-Server by MTLPINE1 (envelope-from talshn@nvidia.com) with SMTP; 17 Dec 2020 19:33:07 +0200 Received: from nvidia.com (l-wincomp04-vm.mtl.labs.mlnx [10.237.1.5]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 0BHHX45l021771; Thu, 17 Dec 2020 19:33:07 +0200 From: Tal Shnaiderman To: dev@dpdk.org Cc: thomas@monjalon.net, matan@nvidia.com, rasland@nvidia.com, ophirmu@nvidia.com Date: Thu, 17 Dec 2020 19:30:28 +0200 Message-Id: <20201217173037.11396-27-talshn@nvidia.com> X-Mailer: git-send-email 2.16.1.windows.4 In-Reply-To: <20201217173037.11396-1-talshn@nvidia.com> References: <20201217173037.11396-1-talshn@nvidia.com> Subject: [dpdk-dev] [PATCH 26/35] net/mlx5/windows: create flow action dest TIR object X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Ophir Munk This commit implements mlx5_flow_os_create_flow_action_dest_devx_tir() API as the Linux rdma-core equivalent. Missing rdma-core parameters are added to file mlx5_win_defs.h. The action TIR id and type (MLX5_FLOW_CONTEXT_DEST_TYPE_TIR) are saved in the action struct. The action struct will be added to array of actions and will be used later by the flow creation API. Signed-off-by: Ophir Munk Acked-by: Matan Azrad --- drivers/common/mlx5/windows/mlx5_win_defs.h | 17 +++++++++++++++++ drivers/net/mlx5/windows/mlx5_flow_os.c | 22 +++++++++++++++------- 2 files changed, 32 insertions(+), 7 deletions(-) diff --git a/drivers/common/mlx5/windows/mlx5_win_defs.h b/drivers/common/mlx5/windows/mlx5_win_defs.h index 231c3220a3..8a1c2c5af9 100644 --- a/drivers/common/mlx5/windows/mlx5_win_defs.h +++ b/drivers/common/mlx5/windows/mlx5_win_defs.h @@ -189,6 +189,17 @@ struct mlx5_matcher { uint64_t match_buf[]; }; +/* + * Windows mlx5_action. This struct is the + * equivalent of rdma-core struct mlx5dv_dr_action. + */ +struct mlx5_action { + int type; + struct { + uint32_t id; + } dest_tir; +}; + struct mlx5_err_cqe { uint8_t rsvd0[32]; uint32_t srqn; @@ -233,4 +244,10 @@ enum { MLX5_FLOW_CONTEXT_DEST_TYPE_TIR = 0x2, MLX5_FLOW_CONTEXT_DEST_TYPE_QP = 0x3, }; + +enum { + MLX5_MATCH_OUTER_HEADERS = 1 << 0, + MLX5_MATCH_MISC_PARAMETERS = 1 << 1, + MLX5_MATCH_INNER_HEADERS = 1 << 2, +}; #endif /* __MLX5_WIN_DEFS_H__ */ diff --git a/drivers/net/mlx5/windows/mlx5_flow_os.c b/drivers/net/mlx5/windows/mlx5_flow_os.c index 0ade518910..0c0fba3720 100644 --- a/drivers/net/mlx5/windows/mlx5_flow_os.c +++ b/drivers/net/mlx5/windows/mlx5_flow_os.c @@ -134,10 +134,19 @@ int mlx5_flow_os_create_flow_action_dest_devx_tir(struct mlx5_devx_obj *tir, void **action) { - RTE_SET_USED(tir); - *action = NULL; - rte_errno = ENOTSUP; - return -rte_errno; + struct mlx5_action *mlx5_action = + mlx5_malloc(MLX5_MEM_ZERO, + sizeof(struct mlx5_action), + 0, SOCKET_ID_ANY); + + if (!mlx5_action) { + rte_errno = ENOMEM; + return -rte_errno; + } + mlx5_action->type = MLX5_FLOW_CONTEXT_DEST_TYPE_TIR; + mlx5_action->dest_tir.id = tir->id; + *action = mlx5_action; + return 0; } /** @@ -152,9 +161,8 @@ mlx5_flow_os_create_flow_action_dest_devx_tir(struct mlx5_devx_obj *tir, int mlx5_flow_os_destroy_flow_action(void *action) { - RTE_SET_USED(action); - rte_errno = ENOTSUP; - return -rte_errno; + mlx5_free(action); + return 0; } /** From patchwork Thu Dec 17 17:30:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tal Shnaiderman X-Patchwork-Id: 85366 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0D340A09F6; Thu, 17 Dec 2020 18:42:59 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 42B7ECC4B; Thu, 17 Dec 2020 18:33:54 +0100 (CET) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by dpdk.org (Postfix) with ESMTP id 0EB6BCA58 for ; Thu, 17 Dec 2020 18:33:10 +0100 (CET) Received: from Internal Mail-Server by MTLPINE1 (envelope-from talshn@nvidia.com) with SMTP; 17 Dec 2020 19:33:07 +0200 Received: from nvidia.com (l-wincomp04-vm.mtl.labs.mlnx [10.237.1.5]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 0BHHX45m021771; Thu, 17 Dec 2020 19:33:07 +0200 From: Tal Shnaiderman To: dev@dpdk.org Cc: thomas@monjalon.net, matan@nvidia.com, rasland@nvidia.com, ophirmu@nvidia.com Date: Thu, 17 Dec 2020 19:30:29 +0200 Message-Id: <20201217173037.11396-28-talshn@nvidia.com> X-Mailer: git-send-email 2.16.1.windows.4 In-Reply-To: <20201217173037.11396-1-talshn@nvidia.com> References: <20201217173037.11396-1-talshn@nvidia.com> Subject: [dpdk-dev] [PATCH 27/35] net/mlx5/windows: create flow rule X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Ophir Munk This commit implements mlx5_flow_os_create_flow() API. It is equivalent to Linux rdma-core implementation. The API receives the matcher mask, matcher value and an array of actions. They are copied into a PRM-like struct devx_fs_rule_add_in. Then glue API devx_fs_rule_add() is called. Signed-off-by: Ophir Munk Acked-by: Matan Azrad --- drivers/common/mlx5/mlx5_prm.h | 6 +++++ drivers/net/mlx5/windows/mlx5_flow_os.c | 46 ++++++++++++++++++++++++++------- 2 files changed, 42 insertions(+), 10 deletions(-) diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index ac42238d30..8c9b53ce10 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -825,6 +825,12 @@ struct mlx5_ifc_fte_match_param_bits { #endif }; +struct mlx5_ifc_dest_format_struct_bits { + u8 destination_type[0x8]; + u8 destination_id[0x18]; + u8 reserved_0[0x20]; +}; + enum { MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT, MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT, diff --git a/drivers/net/mlx5/windows/mlx5_flow_os.c b/drivers/net/mlx5/windows/mlx5_flow_os.c index 0c0fba3720..daf4e15ddb 100644 --- a/drivers/net/mlx5/windows/mlx5_flow_os.c +++ b/drivers/net/mlx5/windows/mlx5_flow_os.c @@ -187,13 +187,41 @@ mlx5_flow_os_create_flow(void *matcher, void *match_value, size_t num_actions, void *actions[], void **flow) { - RTE_SET_USED(matcher); - RTE_SET_USED(match_value); - RTE_SET_USED(num_actions); - RTE_SET_USED(actions); - *flow = NULL; - rte_errno = ENOTSUP; - return -rte_errno; + struct mlx5_action *action; + int i; + struct mlx5_matcher *mlx5_matcher = matcher; + struct mlx5_flow_dv_match_params *mlx5_match_value = match_value; + uint32_t in[MLX5_ST_SZ_DW(devx_fs_rule_add_in)] = {0}; + void *matcher_c = MLX5_ADDR_OF(devx_fs_rule_add_in, in, + match_criteria); + void *matcher_v = MLX5_ADDR_OF(devx_fs_rule_add_in, in, + match_value); + + MLX5_ASSERT(mlx5_matcher->ctx); + memcpy(matcher_c, mlx5_matcher->match_buf, + mlx5_match_value->size); + /* Use mlx5_match_value->size for match criteria */ + memcpy(matcher_v, mlx5_match_value->buf, + mlx5_match_value->size); + for (i = 0; i < num_actions; i++) { + action = actions[i]; + switch (action->type) { + case MLX5_FLOW_CONTEXT_DEST_TYPE_TIR: + MLX5_SET(devx_fs_rule_add_in, in, + dest.destination_type, + MLX5_FLOW_CONTEXT_DEST_TYPE_TIR); + MLX5_SET(devx_fs_rule_add_in, in, + dest.destination_id, + action->dest_tir.id); + break; + default: + break; + } + MLX5_SET(devx_fs_rule_add_in, in, match_criteria_enable, + MLX5_MATCH_OUTER_HEADERS); + } + *flow = mlx5_glue->devx_fs_rule_add(mlx5_matcher->ctx, in, sizeof(in)); + return (*flow) ? 0 : -1; } /** @@ -208,7 +236,5 @@ mlx5_flow_os_create_flow(void *matcher, void *match_value, int mlx5_flow_os_destroy_flow(void *drv_flow_ptr) { - RTE_SET_USED(dev_flow_ptr); - rte_errno = ENOTSUP; - return -rte_errno; + return mlx5_glue->devx_fs_rule_del(drv_flow_ptr); } From patchwork Thu Dec 17 17:30:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tal Shnaiderman X-Patchwork-Id: 85363 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8D79BA09F6; Thu, 17 Dec 2020 18:42:02 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 70258CBD7; Thu, 17 Dec 2020 18:33:50 +0100 (CET) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by dpdk.org (Postfix) with ESMTP id 01C1FCA57 for ; Thu, 17 Dec 2020 18:33:10 +0100 (CET) Received: from Internal Mail-Server by MTLPINE1 (envelope-from talshn@nvidia.com) with SMTP; 17 Dec 2020 19:33:07 +0200 Received: from nvidia.com (l-wincomp04-vm.mtl.labs.mlnx [10.237.1.5]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 0BHHX45n021771; Thu, 17 Dec 2020 19:33:07 +0200 From: Tal Shnaiderman To: dev@dpdk.org Cc: thomas@monjalon.net, matan@nvidia.com, rasland@nvidia.com, ophirmu@nvidia.com Date: Thu, 17 Dec 2020 19:30:30 +0200 Message-Id: <20201217173037.11396-29-talshn@nvidia.com> X-Mailer: git-send-email 2.16.1.windows.4 In-Reply-To: <20201217173037.11396-1-talshn@nvidia.com> References: <20201217173037.11396-1-talshn@nvidia.com> Subject: [dpdk-dev] [PATCH 28/35] net/mlx5: use HAVE_INFINIBAND_VERBS_H in shared code X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Ophir Munk Use macro HAVE_INFINIBAND_VERBS_H to successfully compile files both under Linux and Windows (or any non Linux in general). Under Windows this macro: 1. Hides Verbs references. 2. Exposes required DV structs that are under ifdefs related to rdma core. Linux code under definitions such as #ifdef HAVE_IBV_FLOW_DV_SUPPORT is required unconditionally under Windows however those definitions are never effective without rdma-core presence. Therefore update the #ifdef condition to consider HAVE_INFINIBAND_VERBS_H as well (undefined macro when running without an rdma-core library). For example: -#ifdef HAVE_IBV_FLOW_DV_SUPPORT +#if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) Signed-off-by: Ophir Munk Acked-by: Matan Azrad --- drivers/net/mlx5/mlx5.c | 4 ++-- drivers/net/mlx5/mlx5.h | 4 ++-- drivers/net/mlx5/mlx5_devx.c | 8 ++++---- drivers/net/mlx5/mlx5_flow.c | 2 +- drivers/net/mlx5/mlx5_flow.h | 16 +++++++--------- drivers/net/mlx5/mlx5_flow_dv.c | 2 +- drivers/net/mlx5/mlx5_flow_verbs.c | 6 ++++++ 7 files changed, 23 insertions(+), 19 deletions(-) diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c index ea5cf80ac1..a5fc10af6f 100644 --- a/drivers/net/mlx5/mlx5.c +++ b/drivers/net/mlx5/mlx5.c @@ -187,7 +187,7 @@ static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_dev_ctx_list = static pthread_mutex_t mlx5_dev_ctx_list_mutex = PTHREAD_MUTEX_INITIALIZER; static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = { -#ifdef HAVE_IBV_FLOW_DV_SUPPORT +#if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) [MLX5_IPOOL_DECAP_ENCAP] = { .size = sizeof(struct mlx5_flow_dv_encap_decap_resource), .trunk_size = 64, @@ -1148,7 +1148,7 @@ mlx5_alloc_table_hash_list(struct mlx5_priv *priv __rte_unused) { int err = 0; /* Tables are only used in DV and DR modes. */ -#ifdef HAVE_IBV_FLOW_DV_SUPPORT +#if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) struct mlx5_dev_ctx_shared *sh = priv->sh; char s[MLX5_HLIST_NAMESIZE]; diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index e5794744bd..2fbeb9112d 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -36,7 +36,7 @@ #define MLX5_SH(dev) (((struct mlx5_priv *)(dev)->data->dev_private)->sh) enum mlx5_ipool_index { -#ifdef HAVE_IBV_FLOW_DV_SUPPORT +#if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) MLX5_IPOOL_DECAP_ENCAP = 0, /* Pool for encap/decap resource. */ MLX5_IPOOL_PUSH_VLAN, /* Pool for push vlan resource. */ MLX5_IPOOL_TAG, /* Pool for tag resource. */ @@ -833,7 +833,7 @@ struct mlx5_hrxq { void *qp; /* Verbs queue pair. */ struct mlx5_devx_obj *tir; /* DevX TIR object. */ }; -#ifdef HAVE_IBV_FLOW_DV_SUPPORT +#if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) void *action; /* DV QP action pointer. */ #endif uint64_t hash_fields; /* Verbs Hash fields. */ diff --git a/drivers/net/mlx5/mlx5_devx.c b/drivers/net/mlx5/mlx5_devx.c index aa8ca7f401..da3bb784be 100644 --- a/drivers/net/mlx5/mlx5_devx.c +++ b/drivers/net/mlx5/mlx5_devx.c @@ -941,7 +941,7 @@ mlx5_devx_hrxq_new(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq, rte_errno = errno; goto error; } -#ifdef HAVE_IBV_FLOW_DV_SUPPORT +#if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) if (mlx5_flow_os_create_flow_action_dest_devx_tir(hrxq->tir, &hrxq->action)) { rte_errno = errno; @@ -1111,7 +1111,7 @@ mlx5_txq_obj_hairpin_new(struct rte_eth_dev *dev, uint16_t idx) return 0; } -#ifdef HAVE_MLX5DV_DEVX_UAR_OFFSET +#if defined(HAVE_MLX5DV_DEVX_UAR_OFFSET) || !defined(HAVE_INFINIBAND_VERBS_H) /** * Release DevX SQ resources. * @@ -1421,7 +1421,7 @@ mlx5_txq_devx_obj_new(struct rte_eth_dev *dev, uint16_t idx) if (txq_ctrl->type == MLX5_TXQ_TYPE_HAIRPIN) return mlx5_txq_obj_hairpin_new(dev, idx); -#ifndef HAVE_MLX5DV_DEVX_UAR_OFFSET +#if !defined(HAVE_MLX5DV_DEVX_UAR_OFFSET) && defined(HAVE_INFINIBAND_VERBS_H) DRV_LOG(ERR, "Port %u Tx queue %u cannot create with DevX, no UAR.", dev->data->port_id, idx); rte_errno = ENOMEM; @@ -1522,7 +1522,7 @@ mlx5_txq_devx_obj_release(struct mlx5_txq_obj *txq_obj) if (txq_obj->txq_ctrl->type == MLX5_TXQ_TYPE_HAIRPIN) { if (txq_obj->tis) claim_zero(mlx5_devx_cmd_destroy(txq_obj->tis)); -#ifdef HAVE_MLX5DV_DEVX_UAR_OFFSET +#if defined(HAVE_MLX5DV_DEVX_UAR_OFFSET) || !defined(HAVE_INFINIBAND_VERBS_H) } else { mlx5_txq_release_devx_resources(txq_obj); #endif diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c index 66491bbf78..4035090cbb 100644 --- a/drivers/net/mlx5/mlx5_flow.c +++ b/drivers/net/mlx5/mlx5_flow.c @@ -73,7 +73,7 @@ const struct mlx5_flow_driver_ops mlx5_flow_null_drv_ops; const struct mlx5_flow_driver_ops *flow_drv_ops[] = { [MLX5_FLOW_TYPE_MIN] = &mlx5_flow_null_drv_ops, -#ifdef HAVE_IBV_FLOW_DV_SUPPORT +#if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) [MLX5_FLOW_TYPE_DV] = &mlx5_flow_dv_drv_ops, #endif [MLX5_FLOW_TYPE_VERBS] = &mlx5_flow_verbs_drv_ops, diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h index d85dd19929..ee85c9d8a5 100644 --- a/drivers/net/mlx5/mlx5_flow.h +++ b/drivers/net/mlx5/mlx5_flow.h @@ -600,12 +600,6 @@ struct mlx5_flow_dv_dest_array_resource { /**< Action resources. */ }; -/* Verbs specification header. */ -struct ibv_spec_header { - enum ibv_flow_spec_type type; - uint16_t size; -}; - /* PMD flow priority for tunnel */ #define MLX5_TUNNEL_PRIO_GET(rss_desc) \ ((rss_desc)->level >= 2 ? MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4) @@ -652,7 +646,7 @@ struct mlx5_flow_handle { uint32_t rix_srss; /**< Indicates shared RSS fate action. */ }; -#ifdef HAVE_IBV_FLOW_DV_SUPPORT +#if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) struct mlx5_flow_handle_dv dvh; #endif } __rte_packed; @@ -662,7 +656,7 @@ struct mlx5_flow_handle { * structure in Verbs. No DV flows attributes will be accessed. * Macro offsetof() could also be used here. */ -#ifdef HAVE_IBV_FLOW_DV_SUPPORT +#if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) #define MLX5_FLOW_HANDLE_VERBS_SIZE \ (sizeof(struct mlx5_flow_handle) - sizeof(struct mlx5_flow_handle_dv)) #else @@ -700,6 +694,7 @@ struct mlx5_flow_dv_workspace { /**< Pointer to the destination array resource. */ }; +#ifdef HAVE_INFINIBAND_VERBS_H /* * Maximal Verbs flow specifications & actions size. * Some elements are mutually exclusive, but enough space should be allocated. @@ -756,6 +751,7 @@ struct mlx5_flow_verbs_workspace { uint8_t specs[MLX5_VERBS_MAX_SPEC_ACT_SIZE]; /**< Specifications & actions buffer of verbs flow. */ }; +#endif /* HAVE_INFINIBAND_VERBS_H */ /** Maximal number of device sub-flows supported. */ #define MLX5_NUM_MAX_DEV_FLOWS 32 @@ -773,10 +769,12 @@ struct mlx5_flow { uint8_t skip_scale:1; /**< 1 if skip the scale the table with factor. */ union { -#ifdef HAVE_IBV_FLOW_DV_SUPPORT +#if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) struct mlx5_flow_dv_workspace dv; #endif +#ifdef HAVE_INFINIBAND_VERBS_H struct mlx5_flow_verbs_workspace verbs; +#endif }; struct mlx5_flow_handle *handle; uint32_t handle_idx; /* Index of the mlx5 flow handle memory. */ diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index 6d377b6dab..b73ee8401c 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -35,7 +35,7 @@ #include "mlx5_rxtx.h" #include "rte_pmd_mlx5.h" -#ifdef HAVE_IBV_FLOW_DV_SUPPORT +#if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0 diff --git a/drivers/net/mlx5/mlx5_flow_verbs.c b/drivers/net/mlx5/mlx5_flow_verbs.c index 59291fbd09..2d4381946d 100644 --- a/drivers/net/mlx5/mlx5_flow_verbs.c +++ b/drivers/net/mlx5/mlx5_flow_verbs.c @@ -39,6 +39,12 @@ static const uint32_t priority_map_5[][MLX5_PRIORITY_MAP_MAX] = { { 9, 10, 11 }, { 12, 13, 14 }, }; +/* Verbs specification header. */ +struct ibv_spec_header { + enum ibv_flow_spec_type type; + uint16_t size; +}; + /** * Discover the maximum number of priority available. * From patchwork Thu Dec 17 17:30:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tal Shnaiderman X-Patchwork-Id: 85367 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4B32EA09F6; Thu, 17 Dec 2020 18:43:18 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id E63F2CC65; Thu, 17 Dec 2020 18:33:55 +0100 (CET) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by dpdk.org (Postfix) with ESMTP id 19830CA59 for ; Thu, 17 Dec 2020 18:33:10 +0100 (CET) Received: from Internal Mail-Server by MTLPINE1 (envelope-from talshn@nvidia.com) with SMTP; 17 Dec 2020 19:33:07 +0200 Received: from nvidia.com (l-wincomp04-vm.mtl.labs.mlnx [10.237.1.5]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 0BHHX45o021771; Thu, 17 Dec 2020 19:33:07 +0200 From: Tal Shnaiderman To: dev@dpdk.org Cc: thomas@monjalon.net, matan@nvidia.com, rasland@nvidia.com, ophirmu@nvidia.com Date: Thu, 17 Dec 2020 19:30:31 +0200 Message-Id: <20201217173037.11396-30-talshn@nvidia.com> X-Mailer: git-send-email 2.16.1.windows.4 In-Reply-To: <20201217173037.11396-1-talshn@nvidia.com> References: <20201217173037.11396-1-talshn@nvidia.com> Subject: [dpdk-dev] [PATCH 29/35] net/mlx5: fix separating eth_dev_ops per OS X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Ophir Munk There are three types of eth_dev_ops: primary, secondary and isolate represented in three callback tables per OS. In this commit the OS specific eth dev tables are unified into shared tables in file mlx5.c. Starting from this commit all operating systems must implement the same eth dev APIs. In case an OS does not support an API - it can return in its implementation an error ENOTSUP. Fixes: 042f5c94fd3a ("net/mlx5: refactor device operations for Linux") Fixes: b541ecb63618 ("net/mlx5: refactor eth dev ops for Windows") Signed-off-by: Ophir Munk Acked-by: Matan Azrad --- drivers/net/mlx5/linux/mlx5_os.c | 154 +------------------------------------ drivers/net/mlx5/mlx5.c | 150 ++++++++++++++++++++++++++++++++++++ drivers/net/mlx5/mlx5.h | 6 +- drivers/net/mlx5/mlx5_flow.c | 4 +- drivers/net/mlx5/windows/mlx5_os.c | 110 +------------------------- 5 files changed, 158 insertions(+), 266 deletions(-) diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c index 4f68c74267..8353ac22e0 100644 --- a/drivers/net/mlx5/linux/mlx5_os.c +++ b/drivers/net/mlx5/linux/mlx5_os.c @@ -757,7 +757,7 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, rte_eth_devices[priv->sh->bond_dev].device; else eth_dev->device = dpdk_dev; - eth_dev->dev_ops = &mlx5_os_dev_sec_ops; + eth_dev->dev_ops = &mlx5_dev_sec_ops; eth_dev->rx_descriptor_status = mlx5_rx_descriptor_status; eth_dev->tx_descriptor_status = mlx5_tx_descriptor_status; err = mlx5_proc_priv_init(eth_dev); @@ -1432,7 +1432,7 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, /* Initialize burst functions to prevent crashes before link-up. */ eth_dev->rx_pkt_burst = removed_rx_burst; eth_dev->tx_pkt_burst = removed_tx_burst; - eth_dev->dev_ops = &mlx5_os_dev_ops; + eth_dev->dev_ops = &mlx5_dev_ops; eth_dev->rx_descriptor_status = mlx5_rx_descriptor_status; eth_dev->tx_descriptor_status = mlx5_tx_descriptor_status; eth_dev->rx_queue_count = mlx5_rx_queue_count; @@ -2611,153 +2611,3 @@ mlx5_os_mac_addr_flush(struct rte_eth_dev *dev) dev->data->mac_addrs, MLX5_MAX_MAC_ADDRESSES, priv->mac_own); } - -const struct eth_dev_ops mlx5_os_dev_ops = { - .dev_configure = mlx5_dev_configure, - .dev_start = mlx5_dev_start, - .dev_stop = mlx5_dev_stop, - .dev_set_link_down = mlx5_set_link_down, - .dev_set_link_up = mlx5_set_link_up, - .dev_close = mlx5_dev_close, - .promiscuous_enable = mlx5_promiscuous_enable, - .promiscuous_disable = mlx5_promiscuous_disable, - .allmulticast_enable = mlx5_allmulticast_enable, - .allmulticast_disable = mlx5_allmulticast_disable, - .link_update = mlx5_link_update, - .stats_get = mlx5_stats_get, - .stats_reset = mlx5_stats_reset, - .xstats_get = mlx5_xstats_get, - .xstats_reset = mlx5_xstats_reset, - .xstats_get_names = mlx5_xstats_get_names, - .fw_version_get = mlx5_fw_version_get, - .dev_infos_get = mlx5_dev_infos_get, - .read_clock = mlx5_txpp_read_clock, - .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get, - .vlan_filter_set = mlx5_vlan_filter_set, - .rx_queue_setup = mlx5_rx_queue_setup, - .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup, - .tx_queue_setup = mlx5_tx_queue_setup, - .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup, - .rx_queue_release = mlx5_rx_queue_release, - .tx_queue_release = mlx5_tx_queue_release, - .rx_queue_start = mlx5_rx_queue_start, - .rx_queue_stop = mlx5_rx_queue_stop, - .tx_queue_start = mlx5_tx_queue_start, - .tx_queue_stop = mlx5_tx_queue_stop, - .flow_ctrl_get = mlx5_dev_get_flow_ctrl, - .flow_ctrl_set = mlx5_dev_set_flow_ctrl, - .mac_addr_remove = mlx5_mac_addr_remove, - .mac_addr_add = mlx5_mac_addr_add, - .mac_addr_set = mlx5_mac_addr_set, - .set_mc_addr_list = mlx5_set_mc_addr_list, - .mtu_set = mlx5_dev_set_mtu, - .vlan_strip_queue_set = mlx5_vlan_strip_queue_set, - .vlan_offload_set = mlx5_vlan_offload_set, - .reta_update = mlx5_dev_rss_reta_update, - .reta_query = mlx5_dev_rss_reta_query, - .rss_hash_update = mlx5_rss_hash_update, - .rss_hash_conf_get = mlx5_rss_hash_conf_get, - .filter_ctrl = mlx5_dev_filter_ctrl, - .rxq_info_get = mlx5_rxq_info_get, - .txq_info_get = mlx5_txq_info_get, - .rx_burst_mode_get = mlx5_rx_burst_mode_get, - .tx_burst_mode_get = mlx5_tx_burst_mode_get, - .rx_queue_intr_enable = mlx5_rx_intr_enable, - .rx_queue_intr_disable = mlx5_rx_intr_disable, - .is_removed = mlx5_is_removed, - .udp_tunnel_port_add = mlx5_udp_tunnel_port_add, - .get_module_info = mlx5_get_module_info, - .get_module_eeprom = mlx5_get_module_eeprom, - .hairpin_cap_get = mlx5_hairpin_cap_get, - .mtr_ops_get = mlx5_flow_meter_ops_get, - .hairpin_bind = mlx5_hairpin_bind, - .hairpin_unbind = mlx5_hairpin_unbind, - .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports, - .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update, - .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind, - .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind, -}; - -/* Available operations from secondary process. */ -const struct eth_dev_ops mlx5_os_dev_sec_ops = { - .stats_get = mlx5_stats_get, - .stats_reset = mlx5_stats_reset, - .xstats_get = mlx5_xstats_get, - .xstats_reset = mlx5_xstats_reset, - .xstats_get_names = mlx5_xstats_get_names, - .fw_version_get = mlx5_fw_version_get, - .dev_infos_get = mlx5_dev_infos_get, - .read_clock = mlx5_txpp_read_clock, - .rx_queue_start = mlx5_rx_queue_start, - .rx_queue_stop = mlx5_rx_queue_stop, - .tx_queue_start = mlx5_tx_queue_start, - .tx_queue_stop = mlx5_tx_queue_stop, - .rxq_info_get = mlx5_rxq_info_get, - .txq_info_get = mlx5_txq_info_get, - .rx_burst_mode_get = mlx5_rx_burst_mode_get, - .tx_burst_mode_get = mlx5_tx_burst_mode_get, - .get_module_info = mlx5_get_module_info, - .get_module_eeprom = mlx5_get_module_eeprom, -}; - -/* Available operations in flow isolated mode. */ -const struct eth_dev_ops mlx5_os_dev_ops_isolate = { - .dev_configure = mlx5_dev_configure, - .dev_start = mlx5_dev_start, - .dev_stop = mlx5_dev_stop, - .dev_set_link_down = mlx5_set_link_down, - .dev_set_link_up = mlx5_set_link_up, - .dev_close = mlx5_dev_close, - .promiscuous_enable = mlx5_promiscuous_enable, - .promiscuous_disable = mlx5_promiscuous_disable, - .allmulticast_enable = mlx5_allmulticast_enable, - .allmulticast_disable = mlx5_allmulticast_disable, - .link_update = mlx5_link_update, - .stats_get = mlx5_stats_get, - .stats_reset = mlx5_stats_reset, - .xstats_get = mlx5_xstats_get, - .xstats_reset = mlx5_xstats_reset, - .xstats_get_names = mlx5_xstats_get_names, - .fw_version_get = mlx5_fw_version_get, - .dev_infos_get = mlx5_dev_infos_get, - .read_clock = mlx5_txpp_read_clock, - .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get, - .vlan_filter_set = mlx5_vlan_filter_set, - .rx_queue_setup = mlx5_rx_queue_setup, - .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup, - .tx_queue_setup = mlx5_tx_queue_setup, - .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup, - .rx_queue_release = mlx5_rx_queue_release, - .tx_queue_release = mlx5_tx_queue_release, - .rx_queue_start = mlx5_rx_queue_start, - .rx_queue_stop = mlx5_rx_queue_stop, - .tx_queue_start = mlx5_tx_queue_start, - .tx_queue_stop = mlx5_tx_queue_stop, - .flow_ctrl_get = mlx5_dev_get_flow_ctrl, - .flow_ctrl_set = mlx5_dev_set_flow_ctrl, - .mac_addr_remove = mlx5_mac_addr_remove, - .mac_addr_add = mlx5_mac_addr_add, - .mac_addr_set = mlx5_mac_addr_set, - .set_mc_addr_list = mlx5_set_mc_addr_list, - .mtu_set = mlx5_dev_set_mtu, - .vlan_strip_queue_set = mlx5_vlan_strip_queue_set, - .vlan_offload_set = mlx5_vlan_offload_set, - .filter_ctrl = mlx5_dev_filter_ctrl, - .rxq_info_get = mlx5_rxq_info_get, - .txq_info_get = mlx5_txq_info_get, - .rx_burst_mode_get = mlx5_rx_burst_mode_get, - .tx_burst_mode_get = mlx5_tx_burst_mode_get, - .rx_queue_intr_enable = mlx5_rx_intr_enable, - .rx_queue_intr_disable = mlx5_rx_intr_disable, - .is_removed = mlx5_is_removed, - .get_module_info = mlx5_get_module_info, - .get_module_eeprom = mlx5_get_module_eeprom, - .hairpin_cap_get = mlx5_hairpin_cap_get, - .mtr_ops_get = mlx5_flow_meter_ops_get, - .hairpin_bind = mlx5_hairpin_bind, - .hairpin_unbind = mlx5_hairpin_unbind, - .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports, - .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update, - .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind, - .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind, -}; diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c index a5fc10af6f..7a8cc84aaa 100644 --- a/drivers/net/mlx5/mlx5.c +++ b/drivers/net/mlx5/mlx5.c @@ -1430,6 +1430,156 @@ mlx5_dev_close(struct rte_eth_dev *dev) return 0; } +const struct eth_dev_ops mlx5_dev_ops = { + .dev_configure = mlx5_dev_configure, + .dev_start = mlx5_dev_start, + .dev_stop = mlx5_dev_stop, + .dev_set_link_down = mlx5_set_link_down, + .dev_set_link_up = mlx5_set_link_up, + .dev_close = mlx5_dev_close, + .promiscuous_enable = mlx5_promiscuous_enable, + .promiscuous_disable = mlx5_promiscuous_disable, + .allmulticast_enable = mlx5_allmulticast_enable, + .allmulticast_disable = mlx5_allmulticast_disable, + .link_update = mlx5_link_update, + .stats_get = mlx5_stats_get, + .stats_reset = mlx5_stats_reset, + .xstats_get = mlx5_xstats_get, + .xstats_reset = mlx5_xstats_reset, + .xstats_get_names = mlx5_xstats_get_names, + .fw_version_get = mlx5_fw_version_get, + .dev_infos_get = mlx5_dev_infos_get, + .read_clock = mlx5_txpp_read_clock, + .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get, + .vlan_filter_set = mlx5_vlan_filter_set, + .rx_queue_setup = mlx5_rx_queue_setup, + .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup, + .tx_queue_setup = mlx5_tx_queue_setup, + .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup, + .rx_queue_release = mlx5_rx_queue_release, + .tx_queue_release = mlx5_tx_queue_release, + .rx_queue_start = mlx5_rx_queue_start, + .rx_queue_stop = mlx5_rx_queue_stop, + .tx_queue_start = mlx5_tx_queue_start, + .tx_queue_stop = mlx5_tx_queue_stop, + .flow_ctrl_get = mlx5_dev_get_flow_ctrl, + .flow_ctrl_set = mlx5_dev_set_flow_ctrl, + .mac_addr_remove = mlx5_mac_addr_remove, + .mac_addr_add = mlx5_mac_addr_add, + .mac_addr_set = mlx5_mac_addr_set, + .set_mc_addr_list = mlx5_set_mc_addr_list, + .mtu_set = mlx5_dev_set_mtu, + .vlan_strip_queue_set = mlx5_vlan_strip_queue_set, + .vlan_offload_set = mlx5_vlan_offload_set, + .reta_update = mlx5_dev_rss_reta_update, + .reta_query = mlx5_dev_rss_reta_query, + .rss_hash_update = mlx5_rss_hash_update, + .rss_hash_conf_get = mlx5_rss_hash_conf_get, + .filter_ctrl = mlx5_dev_filter_ctrl, + .rxq_info_get = mlx5_rxq_info_get, + .txq_info_get = mlx5_txq_info_get, + .rx_burst_mode_get = mlx5_rx_burst_mode_get, + .tx_burst_mode_get = mlx5_tx_burst_mode_get, + .rx_queue_intr_enable = mlx5_rx_intr_enable, + .rx_queue_intr_disable = mlx5_rx_intr_disable, + .is_removed = mlx5_is_removed, + .udp_tunnel_port_add = mlx5_udp_tunnel_port_add, + .get_module_info = mlx5_get_module_info, + .get_module_eeprom = mlx5_get_module_eeprom, + .hairpin_cap_get = mlx5_hairpin_cap_get, + .mtr_ops_get = mlx5_flow_meter_ops_get, + .hairpin_bind = mlx5_hairpin_bind, + .hairpin_unbind = mlx5_hairpin_unbind, + .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports, + .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update, + .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind, + .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind, +}; + +/* Available operations from secondary process. */ +const struct eth_dev_ops mlx5_dev_sec_ops = { + .stats_get = mlx5_stats_get, + .stats_reset = mlx5_stats_reset, + .xstats_get = mlx5_xstats_get, + .xstats_reset = mlx5_xstats_reset, + .xstats_get_names = mlx5_xstats_get_names, + .fw_version_get = mlx5_fw_version_get, + .dev_infos_get = mlx5_dev_infos_get, + .read_clock = mlx5_txpp_read_clock, + .rx_queue_start = mlx5_rx_queue_start, + .rx_queue_stop = mlx5_rx_queue_stop, + .tx_queue_start = mlx5_tx_queue_start, + .tx_queue_stop = mlx5_tx_queue_stop, + .rxq_info_get = mlx5_rxq_info_get, + .txq_info_get = mlx5_txq_info_get, + .rx_burst_mode_get = mlx5_rx_burst_mode_get, + .tx_burst_mode_get = mlx5_tx_burst_mode_get, + .get_module_info = mlx5_get_module_info, + .get_module_eeprom = mlx5_get_module_eeprom, +}; + +/* Available operations in flow isolated mode. */ +const struct eth_dev_ops mlx5_dev_ops_isolate = { + .dev_configure = mlx5_dev_configure, + .dev_start = mlx5_dev_start, + .dev_stop = mlx5_dev_stop, + .dev_set_link_down = mlx5_set_link_down, + .dev_set_link_up = mlx5_set_link_up, + .dev_close = mlx5_dev_close, + .promiscuous_enable = mlx5_promiscuous_enable, + .promiscuous_disable = mlx5_promiscuous_disable, + .allmulticast_enable = mlx5_allmulticast_enable, + .allmulticast_disable = mlx5_allmulticast_disable, + .link_update = mlx5_link_update, + .stats_get = mlx5_stats_get, + .stats_reset = mlx5_stats_reset, + .xstats_get = mlx5_xstats_get, + .xstats_reset = mlx5_xstats_reset, + .xstats_get_names = mlx5_xstats_get_names, + .fw_version_get = mlx5_fw_version_get, + .dev_infos_get = mlx5_dev_infos_get, + .read_clock = mlx5_txpp_read_clock, + .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get, + .vlan_filter_set = mlx5_vlan_filter_set, + .rx_queue_setup = mlx5_rx_queue_setup, + .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup, + .tx_queue_setup = mlx5_tx_queue_setup, + .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup, + .rx_queue_release = mlx5_rx_queue_release, + .tx_queue_release = mlx5_tx_queue_release, + .rx_queue_start = mlx5_rx_queue_start, + .rx_queue_stop = mlx5_rx_queue_stop, + .tx_queue_start = mlx5_tx_queue_start, + .tx_queue_stop = mlx5_tx_queue_stop, + .flow_ctrl_get = mlx5_dev_get_flow_ctrl, + .flow_ctrl_set = mlx5_dev_set_flow_ctrl, + .mac_addr_remove = mlx5_mac_addr_remove, + .mac_addr_add = mlx5_mac_addr_add, + .mac_addr_set = mlx5_mac_addr_set, + .set_mc_addr_list = mlx5_set_mc_addr_list, + .mtu_set = mlx5_dev_set_mtu, + .vlan_strip_queue_set = mlx5_vlan_strip_queue_set, + .vlan_offload_set = mlx5_vlan_offload_set, + .filter_ctrl = mlx5_dev_filter_ctrl, + .rxq_info_get = mlx5_rxq_info_get, + .txq_info_get = mlx5_txq_info_get, + .rx_burst_mode_get = mlx5_rx_burst_mode_get, + .tx_burst_mode_get = mlx5_tx_burst_mode_get, + .rx_queue_intr_enable = mlx5_rx_intr_enable, + .rx_queue_intr_disable = mlx5_rx_intr_disable, + .is_removed = mlx5_is_removed, + .get_module_info = mlx5_get_module_info, + .get_module_eeprom = mlx5_get_module_eeprom, + .hairpin_cap_get = mlx5_hairpin_cap_get, + .mtr_ops_get = mlx5_flow_meter_ops_get, + .hairpin_bind = mlx5_hairpin_bind, + .hairpin_unbind = mlx5_hairpin_unbind, + .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports, + .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update, + .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind, + .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind, +}; + /** * Verify and store value for device argument. * diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index 2fbeb9112d..0cb907c599 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -140,9 +140,9 @@ struct mlx5_local_data { extern struct mlx5_shared_data *mlx5_shared_data; /* Dev ops structs */ -extern const struct eth_dev_ops mlx5_os_dev_ops; -extern const struct eth_dev_ops mlx5_os_dev_sec_ops; -extern const struct eth_dev_ops mlx5_os_dev_ops_isolate; +extern const struct eth_dev_ops mlx5_dev_ops; +extern const struct eth_dev_ops mlx5_dev_sec_ops; +extern const struct eth_dev_ops mlx5_dev_ops_isolate; struct mlx5_counter_ctrl { /* Name of the counter. */ diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c index 4035090cbb..b1c061a3f0 100644 --- a/drivers/net/mlx5/mlx5_flow.c +++ b/drivers/net/mlx5/mlx5_flow.c @@ -6135,9 +6135,9 @@ mlx5_flow_isolate(struct rte_eth_dev *dev, } priv->isolated = !!enable; if (enable) - dev->dev_ops = &mlx5_os_dev_ops_isolate; + dev->dev_ops = &mlx5_dev_ops_isolate; else - dev->dev_ops = &mlx5_os_dev_ops; + dev->dev_ops = &mlx5_dev_ops; dev->rx_descriptor_status = mlx5_rx_descriptor_status; dev->tx_descriptor_status = mlx5_tx_descriptor_status; diff --git a/drivers/net/mlx5/windows/mlx5_os.c b/drivers/net/mlx5/windows/mlx5_os.c index 274975ecc6..66b897968f 100644 --- a/drivers/net/mlx5/windows/mlx5_os.c +++ b/drivers/net/mlx5/windows/mlx5_os.c @@ -571,7 +571,7 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, /* Initialize burst functions to prevent crashes before link-up. */ eth_dev->rx_pkt_burst = removed_rx_burst; eth_dev->tx_pkt_burst = removed_tx_burst; - eth_dev->dev_ops = &mlx5_os_dev_ops; + eth_dev->dev_ops = &mlx5_dev_ops; eth_dev->rx_descriptor_status = mlx5_rx_descriptor_status; eth_dev->tx_descriptor_status = mlx5_tx_descriptor_status; eth_dev->rx_queue_count = mlx5_rx_queue_count; @@ -1157,111 +1157,3 @@ mlx5_os_get_pdn(void *pd, uint32_t *pdn) } const struct mlx5_flow_driver_ops mlx5_flow_verbs_drv_ops = {0}; - -const struct eth_dev_ops mlx5_os_dev_ops = { - .dev_configure = mlx5_dev_configure, - .dev_start = mlx5_dev_start, - .dev_stop = mlx5_dev_stop, - .dev_close = mlx5_dev_close, - .mtu_set = mlx5_dev_set_mtu, - .link_update = mlx5_link_update, - .stats_get = mlx5_stats_get, - .stats_reset = mlx5_stats_reset, - .dev_infos_get = mlx5_dev_infos_get, - .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get, - .promiscuous_enable = mlx5_promiscuous_enable, - .promiscuous_disable = mlx5_promiscuous_disable, - .allmulticast_enable = mlx5_allmulticast_enable, - .allmulticast_disable = mlx5_allmulticast_disable, - .xstats_get = mlx5_xstats_get, - .xstats_reset = mlx5_xstats_reset, - .xstats_get_names = mlx5_xstats_get_names, - .fw_version_get = mlx5_fw_version_get, - .read_clock = mlx5_read_clock, - .vlan_filter_set = mlx5_vlan_filter_set, - .rx_queue_setup = mlx5_rx_queue_setup, - .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup, - .tx_queue_setup = mlx5_tx_queue_setup, - .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup, - .rx_queue_release = mlx5_rx_queue_release, - .tx_queue_release = mlx5_tx_queue_release, - .flow_ctrl_get = mlx5_dev_get_flow_ctrl, - .flow_ctrl_set = mlx5_dev_set_flow_ctrl, - .mac_addr_remove = mlx5_mac_addr_remove, - .mac_addr_add = mlx5_mac_addr_add, - .mac_addr_set = mlx5_mac_addr_set, - .set_mc_addr_list = mlx5_set_mc_addr_list, - .vlan_strip_queue_set = mlx5_vlan_strip_queue_set, - .vlan_offload_set = mlx5_vlan_offload_set, - .reta_update = mlx5_dev_rss_reta_update, - .reta_query = mlx5_dev_rss_reta_query, - .rss_hash_update = mlx5_rss_hash_update, - .rss_hash_conf_get = mlx5_rss_hash_conf_get, - .filter_ctrl = mlx5_dev_filter_ctrl, - .rxq_info_get = mlx5_rxq_info_get, - .txq_info_get = mlx5_txq_info_get, - .rx_burst_mode_get = mlx5_rx_burst_mode_get, - .tx_burst_mode_get = mlx5_tx_burst_mode_get, - .rx_queue_intr_enable = mlx5_rx_intr_enable, - .rx_queue_intr_disable = mlx5_rx_intr_disable, - .is_removed = mlx5_is_removed, - .udp_tunnel_port_add = mlx5_udp_tunnel_port_add, - .get_module_info = mlx5_get_module_info, - .get_module_eeprom = mlx5_get_module_eeprom, - .hairpin_cap_get = mlx5_hairpin_cap_get, - .mtr_ops_get = mlx5_flow_meter_ops_get, -}; - -/* Available operations from secondary process. */ -const struct eth_dev_ops mlx5_os_dev_sec_ops = {0}; - -/* Available operations in flow isolated mode. */ -const struct eth_dev_ops mlx5_os_dev_ops_isolate = { - .dev_configure = mlx5_dev_configure, - .dev_start = mlx5_dev_start, - .dev_stop = mlx5_dev_stop, - .dev_close = mlx5_dev_close, - .mtu_set = mlx5_dev_set_mtu, - .link_update = mlx5_link_update, - .stats_get = mlx5_stats_get, - .stats_reset = mlx5_stats_reset, - .dev_infos_get = mlx5_dev_infos_get, - .dev_set_link_down = mlx5_set_link_down, - .dev_set_link_up = mlx5_set_link_up, - .promiscuous_enable = mlx5_promiscuous_enable, - .promiscuous_disable = mlx5_promiscuous_disable, - .allmulticast_enable = mlx5_allmulticast_enable, - .allmulticast_disable = mlx5_allmulticast_disable, - .xstats_get = mlx5_xstats_get, - .xstats_reset = mlx5_xstats_reset, - .xstats_get_names = mlx5_xstats_get_names, - .fw_version_get = mlx5_fw_version_get, - .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get, - .vlan_filter_set = mlx5_vlan_filter_set, - .rx_queue_setup = mlx5_rx_queue_setup, - .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup, - .tx_queue_setup = mlx5_tx_queue_setup, - .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup, - .rx_queue_release = mlx5_rx_queue_release, - .tx_queue_release = mlx5_tx_queue_release, - .flow_ctrl_get = mlx5_dev_get_flow_ctrl, - .flow_ctrl_set = mlx5_dev_set_flow_ctrl, - .mac_addr_remove = mlx5_mac_addr_remove, - .mac_addr_add = mlx5_mac_addr_add, - .mac_addr_set = mlx5_mac_addr_set, - .set_mc_addr_list = mlx5_set_mc_addr_list, - .vlan_strip_queue_set = mlx5_vlan_strip_queue_set, - .vlan_offload_set = mlx5_vlan_offload_set, - .filter_ctrl = mlx5_dev_filter_ctrl, - .rxq_info_get = mlx5_rxq_info_get, - .txq_info_get = mlx5_txq_info_get, - .rx_burst_mode_get = mlx5_rx_burst_mode_get, - .tx_burst_mode_get = mlx5_tx_burst_mode_get, - .rx_queue_intr_enable = mlx5_rx_intr_enable, - .rx_queue_intr_disable = mlx5_rx_intr_disable, - .is_removed = mlx5_is_removed, - .get_module_info = mlx5_get_module_info, - .get_module_eeprom = mlx5_get_module_eeprom, - .hairpin_cap_get = mlx5_hairpin_cap_get, - .mtr_ops_get = mlx5_flow_meter_ops_get, -}; From patchwork Thu Dec 17 17:30:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tal Shnaiderman X-Patchwork-Id: 85365 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id ADEA6A09F6; Thu, 17 Dec 2020 18:42:40 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 07E57CC2B; Thu, 17 Dec 2020 18:33:53 +0100 (CET) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by dpdk.org (Postfix) with ESMTP id 19AE4CA5A for ; Thu, 17 Dec 2020 18:33:10 +0100 (CET) Received: from Internal Mail-Server by MTLPINE1 (envelope-from talshn@nvidia.com) with SMTP; 17 Dec 2020 19:33:07 +0200 Received: from nvidia.com (l-wincomp04-vm.mtl.labs.mlnx [10.237.1.5]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 0BHHX45p021771; Thu, 17 Dec 2020 19:33:07 +0200 From: Tal Shnaiderman To: dev@dpdk.org Cc: thomas@monjalon.net, matan@nvidia.com, rasland@nvidia.com, ophirmu@nvidia.com, stable@dpdk.org Date: Thu, 17 Dec 2020 19:30:32 +0200 Message-Id: <20201217173037.11396-31-talshn@nvidia.com> X-Mailer: git-send-email 2.16.1.windows.4 In-Reply-To: <20201217173037.11396-1-talshn@nvidia.com> References: <20201217173037.11396-1-talshn@nvidia.com> Subject: [dpdk-dev] [PATCH 30/35] net/mlx5: define MLX5_NAMESIZE for device interface size X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Windows Devx interface name is the same as device name with different size then IF_NAMESIZE. to support it MLX5_NAMESIZE is defined with IF_NAMESIZE value for Linux and MLX5_FS_NAME_MAX value for Windows. Fixes: e9c0b96e3526 ("net/mlx5: move Linux ifname function") Cc: stable@dpdk.org Signed-off-by: Tal Shnaiderman Acked-by: Matan Azrad --- drivers/net/mlx5/linux/mlx5_ethdev_os.c | 4 ++-- drivers/net/mlx5/linux/mlx5_os.c | 2 +- drivers/net/mlx5/linux/mlx5_os.h | 6 ++---- drivers/net/mlx5/mlx5.h | 3 ++- drivers/net/mlx5/windows/mlx5_ethdev_os.c | 4 ++-- drivers/net/mlx5/windows/mlx5_os.c | 2 +- drivers/net/mlx5/windows/mlx5_os.h | 2 ++ 7 files changed, 12 insertions(+), 11 deletions(-) diff --git a/drivers/net/mlx5/linux/mlx5_ethdev_os.c b/drivers/net/mlx5/linux/mlx5_ethdev_os.c index 128845cb52..e36a78091c 100644 --- a/drivers/net/mlx5/linux/mlx5_ethdev_os.c +++ b/drivers/net/mlx5/linux/mlx5_ethdev_os.c @@ -143,7 +143,7 @@ struct ethtool_link_settings { * 0 on success, a negative errno value otherwise and rte_errno is set. */ int -mlx5_get_ifname(const struct rte_eth_dev *dev, char (*ifname)[IF_NAMESIZE]) +mlx5_get_ifname(const struct rte_eth_dev *dev, char (*ifname)[MLX5_NAMESIZE]) { struct mlx5_priv *priv = dev->data->dev_private; unsigned int ifindex; @@ -151,7 +151,7 @@ mlx5_get_ifname(const struct rte_eth_dev *dev, char (*ifname)[IF_NAMESIZE]) MLX5_ASSERT(priv); MLX5_ASSERT(priv->sh); if (priv->bond_ifindex > 0) { - memcpy(ifname, priv->bond_name, IF_NAMESIZE); + memcpy(ifname, priv->bond_name, MLX5_NAMESIZE); return 0; } ifindex = mlx5_ifindex(dev); diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c index 8353ac22e0..6812a1f215 100644 --- a/drivers/net/mlx5/linux/mlx5_os.c +++ b/drivers/net/mlx5/linux/mlx5_os.c @@ -1411,7 +1411,7 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, mac.addr_bytes[4], mac.addr_bytes[5]); #ifdef RTE_LIBRTE_MLX5_DEBUG { - char ifname[IF_NAMESIZE]; + char ifname[MLX5_NAMESIZE]; if (mlx5_get_ifname(eth_dev, &ifname) == 0) DRV_LOG(DEBUG, "port %u ifname is \"%s\"", diff --git a/drivers/net/mlx5/linux/mlx5_os.h b/drivers/net/mlx5/linux/mlx5_os.h index f38c2f3015..6100a130e0 100644 --- a/drivers/net/mlx5/linux/mlx5_os.h +++ b/drivers/net/mlx5/linux/mlx5_os.h @@ -14,11 +14,9 @@ enum { MLX5_FS_PATH_MAX = IBV_SYSFS_PATH_MAX + 1 }; +#define MLX5_NAMESIZE IF_NAMESIZE + #define PCI_DRV_FLAGS (RTE_PCI_DRV_INTR_LSC | \ RTE_PCI_DRV_INTR_RMV | \ RTE_PCI_DRV_PROBE_AGAIN) - -/* mlx5_ethdev_os.c */ - -int mlx5_get_ifname(const struct rte_eth_dev *dev, char (*ifname)[IF_NAMESIZE]); #endif /* RTE_PMD_MLX5_OS_H_ */ diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index 0cb907c599..8fc39a124c 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -950,7 +950,7 @@ struct mlx5_priv { int32_t pf_bond; /* >=0 means PF index in bonding configuration. */ unsigned int if_index; /* Associated kernel network device index. */ uint32_t bond_ifindex; /**< Bond interface index. */ - char bond_name[IF_NAMESIZE]; /**< Bond interface name. */ + char bond_name[MLX5_NAMESIZE]; /**< Bond interface name. */ /* RX/TX queues. */ unsigned int rxqs_n; /* RX queues array size. */ unsigned int txqs_n; /* TX queues array size. */ @@ -1067,6 +1067,7 @@ int mlx5_dev_configure_rss_reta(struct rte_eth_dev *dev); /* mlx5_ethdev_os.c */ +int mlx5_get_ifname(const struct rte_eth_dev *dev, char (*ifname)[MLX5_NAMESIZE]); unsigned int mlx5_ifindex(const struct rte_eth_dev *dev); int mlx5_get_mac(struct rte_eth_dev *dev, uint8_t (*mac)[RTE_ETHER_ADDR_LEN]); int mlx5_get_mtu(struct rte_eth_dev *dev, uint16_t *mtu); diff --git a/drivers/net/mlx5/windows/mlx5_ethdev_os.c b/drivers/net/mlx5/windows/mlx5_ethdev_os.c index f4ec855302..076c688699 100644 --- a/drivers/net/mlx5/windows/mlx5_ethdev_os.c +++ b/drivers/net/mlx5/windows/mlx5_ethdev_os.c @@ -56,7 +56,7 @@ mlx5_get_mac(struct rte_eth_dev *dev, uint8_t (*mac)[RTE_ETHER_ADDR_LEN]) * 0 on success, a negative errno value otherwise and rte_errno is set. */ int -mlx5_get_ifname(const struct rte_eth_dev *dev, char (*ifname)[IF_NAMESIZE]) +mlx5_get_ifname(const struct rte_eth_dev *dev, char (*ifname)[MLX5_NAMESIZE]) { struct mlx5_priv *priv; mlx5_context_st *context_obj; @@ -67,7 +67,7 @@ mlx5_get_ifname(const struct rte_eth_dev *dev, char (*ifname)[IF_NAMESIZE]) } priv = dev->data->dev_private; context_obj = (mlx5_context_st *)priv->sh->ctx; - strncpy(*ifname, context_obj->mlx5_dev.name, IF_NAMESIZE); + strncpy(*ifname, context_obj->mlx5_dev.name, MLX5_NAMESIZE); return 0; } diff --git a/drivers/net/mlx5/windows/mlx5_os.c b/drivers/net/mlx5/windows/mlx5_os.c index 66b897968f..396edf80ad 100644 --- a/drivers/net/mlx5/windows/mlx5_os.c +++ b/drivers/net/mlx5/windows/mlx5_os.c @@ -550,7 +550,7 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, mac.addr_bytes[4], mac.addr_bytes[5]); #ifdef RTE_LIBRTE_MLX5_DEBUG { - char ifname[IF_NAMESIZE]; + char ifname[MLX5_NAMESIZE]; if (mlx5_get_ifname(eth_dev, &ifname) == 0) DRV_LOG(DEBUG, "port %u ifname is \"%s\"", diff --git a/drivers/net/mlx5/windows/mlx5_os.h b/drivers/net/mlx5/windows/mlx5_os.h index b94f588461..7fe41d4e90 100644 --- a/drivers/net/mlx5/windows/mlx5_os.h +++ b/drivers/net/mlx5/windows/mlx5_os.h @@ -14,4 +14,6 @@ enum { #define PCI_DRV_FLAGS 0 +#define MLX5_NAMESIZE MLX5_FS_NAME_MAX + #endif /* RTE_PMD_MLX5_OS_H_ */ From patchwork Thu Dec 17 17:30:33 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tal Shnaiderman X-Patchwork-Id: 85369 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 6CD0BA09F6; Thu, 17 Dec 2020 18:43:55 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 66746CCA4; Thu, 17 Dec 2020 18:33:58 +0100 (CET) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by dpdk.org (Postfix) with ESMTP id 32AEDCA5C for ; Thu, 17 Dec 2020 18:33:10 +0100 (CET) Received: from Internal Mail-Server by MTLPINE1 (envelope-from talshn@nvidia.com) with SMTP; 17 Dec 2020 19:33:07 +0200 Received: from nvidia.com (l-wincomp04-vm.mtl.labs.mlnx [10.237.1.5]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 0BHHX45q021771; Thu, 17 Dec 2020 19:33:07 +0200 From: Tal Shnaiderman To: dev@dpdk.org Cc: thomas@monjalon.net, matan@nvidia.com, rasland@nvidia.com, ophirmu@nvidia.com Date: Thu, 17 Dec 2020 19:30:33 +0200 Message-Id: <20201217173037.11396-32-talshn@nvidia.com> X-Mailer: git-send-email 2.16.1.windows.4 In-Reply-To: <20201217173037.11396-1-talshn@nvidia.com> References: <20201217173037.11396-1-talshn@nvidia.com> Subject: [dpdk-dev] [PATCH 31/35] net/mlx5: use OS independent code in ASO feature X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Modify the ASO feature to use OS independent code not to break Windows build. Signed-off-by: Tal Shnaiderman Acked-by: Matan Azrad --- drivers/net/mlx5/mlx5_flow_age.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/drivers/net/mlx5/mlx5_flow_age.c b/drivers/net/mlx5/mlx5_flow_age.c index cea2cf769d..1f15f19800 100644 --- a/drivers/net/mlx5/mlx5_flow_age.c +++ b/drivers/net/mlx5/mlx5_flow_age.c @@ -4,6 +4,7 @@ #include #include #include +#include #include #include @@ -53,7 +54,7 @@ mlx5_aso_cq_create(void *ctx, struct mlx5_aso_cq *cq, uint16_t log_desc_n, int socket, int uar_page_id, uint32_t eqn) { struct mlx5_devx_cq_attr attr = { 0 }; - size_t pgsize = sysconf(_SC_PAGESIZE); + size_t pgsize = rte_mem_page_size(); uint32_t umem_size; uint16_t cq_size = 1 << log_desc_n; @@ -66,7 +67,7 @@ mlx5_aso_cq_create(void *ctx, struct mlx5_aso_cq *cq, uint16_t log_desc_n, rte_errno = ENOMEM; return -ENOMEM; } - cq->umem_obj = mlx5_glue->devx_umem_reg(ctx, + cq->umem_obj = mlx5_os_umem_reg(ctx, (void *)(uintptr_t)cq->umem_buf, umem_size, IBV_ACCESS_LOCAL_WRITE); @@ -143,7 +144,7 @@ mlx5_aso_devx_reg_mr(void *ctx, size_t length, struct mlx5_aso_devx_mr *mr, DRV_LOG(ERR, "Failed to create ASO bits mem for MR by Devx."); return -1; } - mr->umem = mlx5_glue->devx_umem_reg(ctx, mr->buf, length, + mr->umem = mlx5_os_umem_reg(ctx, mr->buf, length, IBV_ACCESS_LOCAL_WRITE); if (!mr->umem) { DRV_LOG(ERR, "Failed to register Umem for MR by Devx."); @@ -256,12 +257,12 @@ mlx5_aso_init_sq(struct mlx5_aso_sq *sq) */ static int mlx5_aso_sq_create(void *ctx, struct mlx5_aso_sq *sq, int socket, - struct mlx5dv_devx_uar *uar, uint32_t pdn, + void *uar, uint32_t pdn, uint32_t eqn, uint16_t log_desc_n) { struct mlx5_devx_create_sq_attr attr = { 0 }; struct mlx5_devx_modify_sq_attr modify_attr = { 0 }; - size_t pgsize = sysconf(_SC_PAGESIZE); + size_t pgsize = rte_mem_page_size(); struct mlx5_devx_wq_attr *wq_attr = &attr.wq_attr; uint32_t sq_desc_n = 1 << log_desc_n; uint32_t wq_size = sizeof(struct mlx5_aso_wqe) * sq_desc_n; @@ -280,7 +281,7 @@ mlx5_aso_sq_create(void *ctx, struct mlx5_aso_sq *sq, int socket, DRV_LOG(ERR, "Can't allocate wqe buffer."); return -ENOMEM; } - sq->wqe_umem = mlx5_glue->devx_umem_reg(ctx, + sq->wqe_umem = mlx5_os_umem_reg(ctx, (void *)(uintptr_t)sq->umem_buf, wq_size + sizeof(*sq->db_rec) * 2, @@ -325,7 +326,7 @@ mlx5_aso_sq_create(void *ctx, struct mlx5_aso_sq *sq, int socket, sq->tail = 0; sq->sqn = sq->sq->id; sq->db_rec = RTE_PTR_ADD(sq->umem_buf, (uintptr_t)(wq_attr->dbr_addr)); - sq->uar_addr = (volatile uint64_t *)((uint8_t *)uar->base_addr + 0x800); + sq->uar_addr = mlx5_os_get_devx_uar_reg_addr(uar); mlx5_aso_init_sq(sq); return 0; error: From patchwork Thu Dec 17 17:30:34 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tal Shnaiderman X-Patchwork-Id: 85370 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 56FFFA09F6; Thu, 17 Dec 2020 18:44:16 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id F3AD2CCB1; Thu, 17 Dec 2020 18:33:59 +0100 (CET) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by dpdk.org (Postfix) with ESMTP id 369F8CA40 for ; Thu, 17 Dec 2020 18:33:10 +0100 (CET) Received: from Internal Mail-Server by MTLPINE1 (envelope-from talshn@nvidia.com) with SMTP; 17 Dec 2020 19:33:07 +0200 Received: from nvidia.com (l-wincomp04-vm.mtl.labs.mlnx [10.237.1.5]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 0BHHX45r021771; Thu, 17 Dec 2020 19:33:07 +0200 From: Tal Shnaiderman To: dev@dpdk.org Cc: thomas@monjalon.net, matan@nvidia.com, rasland@nvidia.com, ophirmu@nvidia.com Date: Thu, 17 Dec 2020 19:30:34 +0200 Message-Id: <20201217173037.11396-33-talshn@nvidia.com> X-Mailer: git-send-email 2.16.1.windows.4 In-Reply-To: <20201217173037.11396-1-talshn@nvidia.com> References: <20201217173037.11396-1-talshn@nvidia.com> Subject: [dpdk-dev] [PATCH 32/35] mlx5: use init function for ctx list mutex X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The mutex mlx5_dev_ctx_list_mutex was initialized with PTHREAD_MUTEX_INITIALIZER global macro however this macro is not supported on Windows OS shim implementation of pthreads in DPDK. Moved the init of this mutex to RTE_INIT to support this mutex on both OSs. Signed-off-by: Tal Shnaiderman Acked-by: Matan Azrad --- drivers/net/mlx5/mlx5.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c index 7a8cc84aaa..2aa269b13e 100644 --- a/drivers/net/mlx5/mlx5.c +++ b/drivers/net/mlx5/mlx5.c @@ -184,8 +184,7 @@ int mlx5_logtype; static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_dev_ctx_list = LIST_HEAD_INITIALIZER(); -static pthread_mutex_t mlx5_dev_ctx_list_mutex = PTHREAD_MUTEX_INITIALIZER; - +static pthread_mutex_t mlx5_dev_ctx_list_mutex; static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = { #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) [MLX5_IPOOL_DECAP_ENCAP] = { @@ -2235,6 +2234,7 @@ RTE_LOG_REGISTER(mlx5_logtype, pmd.net.mlx5, NOTICE) */ RTE_INIT(rte_mlx5_pmd_init) { + pthread_mutex_init(&mlx5_dev_ctx_list_mutex, NULL); mlx5_common_init(); /* Build the static tables for Verbs conversion. */ mlx5_set_ptype_table(); From patchwork Thu Dec 17 17:30:35 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tal Shnaiderman X-Patchwork-Id: 85368 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 16A28A09F6; Thu, 17 Dec 2020 18:43:37 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 2AA24CC77; Thu, 17 Dec 2020 18:33:57 +0100 (CET) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by dpdk.org (Postfix) with ESMTP id 3AFDACA5E for ; Thu, 17 Dec 2020 18:33:10 +0100 (CET) Received: from Internal Mail-Server by MTLPINE1 (envelope-from talshn@nvidia.com) with SMTP; 17 Dec 2020 19:33:07 +0200 Received: from nvidia.com (l-wincomp04-vm.mtl.labs.mlnx [10.237.1.5]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 0BHHX45s021771; Thu, 17 Dec 2020 19:33:08 +0200 From: Tal Shnaiderman To: dev@dpdk.org Cc: thomas@monjalon.net, matan@nvidia.com, rasland@nvidia.com, ophirmu@nvidia.com Date: Thu, 17 Dec 2020 19:30:35 +0200 Message-Id: <20201217173037.11396-34-talshn@nvidia.com> X-Mailer: git-send-email 2.16.1.windows.4 In-Reply-To: <20201217173037.11396-1-talshn@nvidia.com> References: <20201217173037.11396-1-talshn@nvidia.com> Subject: [dpdk-dev] [PATCH 33/35] mlx5: use OS function for dr_sync_domain X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" use OS functions for flow_dv_sync_domain to compile Windows. mlx5_os_flow_dr_sync_domain is unsupported for Windows. Signed-off-by: Tal Shnaiderman Acked-by: Matan Azrad --- drivers/net/mlx5/linux/mlx5_flow_os.h | 6 ++++++ drivers/net/mlx5/mlx5_flow_dv.c | 6 +++--- drivers/net/mlx5/windows/mlx5_flow_os.h | 9 +++++++++ 3 files changed, 18 insertions(+), 3 deletions(-) diff --git a/drivers/net/mlx5/linux/mlx5_flow_os.h b/drivers/net/mlx5/linux/mlx5_flow_os.h index 6f3b7324ff..45b7b9f001 100644 --- a/drivers/net/mlx5/linux/mlx5_flow_os.h +++ b/drivers/net/mlx5/linux/mlx5_flow_os.h @@ -427,4 +427,10 @@ mlx5_os_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority, { return mlx5_flow_adjust_priority(dev, priority, subpriority); } + +static inline int +mlx5_os_flow_dr_sync_domain(void *domain, uint32_t flags) +{ + return mlx5_glue->dr_sync_domain(domain, flags); +} #endif /* RTE_PMD_MLX5_FLOW_OS_H_ */ diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index b73ee8401c..51b5e5a2e3 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -12680,18 +12680,18 @@ flow_dv_sync_domain(struct rte_eth_dev *dev, uint32_t domains, uint32_t flags) int ret = 0; if ((domains & MLX5_DOMAIN_BIT_NIC_RX) && priv->sh->rx_domain != NULL) { - ret = mlx5_glue->dr_sync_domain(priv->sh->rx_domain, + ret = mlx5_os_flow_dr_sync_domain(priv->sh->rx_domain, flags); if (ret != 0) return ret; } if ((domains & MLX5_DOMAIN_BIT_NIC_TX) && priv->sh->tx_domain != NULL) { - ret = mlx5_glue->dr_sync_domain(priv->sh->tx_domain, flags); + ret = mlx5_os_flow_dr_sync_domain(priv->sh->tx_domain, flags); if (ret != 0) return ret; } if ((domains & MLX5_DOMAIN_BIT_FDB) && priv->sh->fdb_domain != NULL) { - ret = mlx5_glue->dr_sync_domain(priv->sh->fdb_domain, flags); + ret = mlx5_os_flow_dr_sync_domain(priv->sh->fdb_domain, flags); if (ret != 0) return ret; } diff --git a/drivers/net/mlx5/windows/mlx5_flow_os.h b/drivers/net/mlx5/windows/mlx5_flow_os.h index 50185669cf..630b2148b9 100644 --- a/drivers/net/mlx5/windows/mlx5_flow_os.h +++ b/drivers/net/mlx5/windows/mlx5_flow_os.h @@ -345,6 +345,15 @@ mlx5_os_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority, return 0; } +static inline int +mlx5_os_flow_dr_sync_domain(void *domain, uint32_t flags) +{ + RTE_SET_USED(domain); + RTE_SET_USED(flags); + errno = ENOTSUP; + return errno; +} + int mlx5_flow_os_validate_flow_attributes(struct rte_eth_dev *dev, const struct rte_flow_attr *attributes, bool external, From patchwork Thu Dec 17 17:30:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tal Shnaiderman X-Patchwork-Id: 85371 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3D0FEA09F6; Thu, 17 Dec 2020 18:44:35 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 59321CCBB; Thu, 17 Dec 2020 18:34:01 +0100 (CET) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by dpdk.org (Postfix) with ESMTP id 3B2B7CA62 for ; Thu, 17 Dec 2020 18:33:10 +0100 (CET) Received: from Internal Mail-Server by MTLPINE1 (envelope-from talshn@nvidia.com) with SMTP; 17 Dec 2020 19:33:08 +0200 Received: from nvidia.com (l-wincomp04-vm.mtl.labs.mlnx [10.237.1.5]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 0BHHX45t021771; Thu, 17 Dec 2020 19:33:08 +0200 From: Tal Shnaiderman To: dev@dpdk.org Cc: thomas@monjalon.net, matan@nvidia.com, rasland@nvidia.com, ophirmu@nvidia.com Date: Thu, 17 Dec 2020 19:30:36 +0200 Message-Id: <20201217173037.11396-35-talshn@nvidia.com> X-Mailer: git-send-email 2.16.1.windows.4 In-Reply-To: <20201217173037.11396-1-talshn@nvidia.com> References: <20201217173037.11396-1-talshn@nvidia.com> Subject: [dpdk-dev] [PATCH 34/35] mlx5: do not fail on IPv6 broadcast flow creation failure X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" IPv6 broadcast flow creation is unsupported in Windows. do not fail on IPv6 broadcast flow creation on this mast to avoid entire default rules creation failure. Signed-off-by: Tal Shnaiderman Acked-by: Matan Azrad --- drivers/net/mlx5/mlx5_trigger.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/net/mlx5/mlx5_trigger.c b/drivers/net/mlx5/mlx5_trigger.c index 646f29b923..48210bf0b2 100644 --- a/drivers/net/mlx5/mlx5_trigger.c +++ b/drivers/net/mlx5/mlx5_trigger.c @@ -1316,8 +1316,12 @@ mlx5_traffic_enable(struct rte_eth_dev *dev) goto error; ret = mlx5_ctrl_flow(dev, &ipv6_multi_spec, &ipv6_multi_mask); - if (ret) - goto error; + if (ret) { + /* Do not fail on IPv6 broadcast creation failure. */ + DRV_LOG(WARNING, + "IPv6 broadcast is not supported"); + ret = 0; + } } } /* Add MAC address flows. */ From patchwork Thu Dec 17 17:30:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tal Shnaiderman X-Patchwork-Id: 85373 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 61E04A09F6; Thu, 17 Dec 2020 18:45:10 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id C5D54CD05; Thu, 17 Dec 2020 18:34:03 +0100 (CET) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by dpdk.org (Postfix) with ESMTP id 5115BCA3E for ; Thu, 17 Dec 2020 18:33:10 +0100 (CET) Received: from Internal Mail-Server by MTLPINE1 (envelope-from talshn@nvidia.com) with SMTP; 17 Dec 2020 19:33:08 +0200 Received: from nvidia.com (l-wincomp04-vm.mtl.labs.mlnx [10.237.1.5]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 0BHHX45u021771; Thu, 17 Dec 2020 19:33:08 +0200 From: Tal Shnaiderman To: dev@dpdk.org Cc: thomas@monjalon.net, matan@nvidia.com, rasland@nvidia.com, ophirmu@nvidia.com, stable@dpdk.org Date: Thu, 17 Dec 2020 19:30:37 +0200 Message-Id: <20201217173037.11396-36-talshn@nvidia.com> X-Mailer: git-send-email 2.16.1.windows.4 In-Reply-To: <20201217173037.11396-1-talshn@nvidia.com> References: <20201217173037.11396-1-talshn@nvidia.com> Subject: [dpdk-dev] [PATCH 35/35] net/mlx5: fix warnings on comparison sign mismatch X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The clang compiler warns on size mismatches of several comparisons. warning: comparison of integers of different signs To resolve those the right types is used/cast to. Cc: stable@dpdk.org Signed-off-by: Tal Shnaiderman Acked-by: Matan Azrad --- drivers/net/mlx5/mlx5_flow.c | 4 ++-- drivers/net/mlx5/mlx5_flow_dv.c | 2 +- drivers/net/mlx5/windows/mlx5_flow_os.c | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c index b1c061a3f0..f110c6b714 100644 --- a/drivers/net/mlx5/mlx5_flow.c +++ b/drivers/net/mlx5/mlx5_flow.c @@ -798,7 +798,7 @@ mlx5_flow_get_reg_id(struct rte_eth_dev *dev, start_reg = priv->mtr_color_reg != REG_C_2 ? REG_C_2 : (priv->mtr_reg_share ? REG_C_3 : REG_C_4); skip_mtr_reg = !!(priv->mtr_en && start_reg == REG_C_2); - if (id > (REG_C_7 - start_reg)) + if (id > (uint32_t)(REG_C_7 - start_reg)) return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM, NULL, "invalid tag id"); @@ -814,7 +814,7 @@ mlx5_flow_get_reg_id(struct rte_eth_dev *dev, */ if (skip_mtr_reg && config->flow_mreg_c [id + start_reg - REG_C_0] >= priv->mtr_color_reg) { - if (id >= (REG_C_7 - start_reg)) + if (id >= (uint32_t)(REG_C_7 - start_reg)) return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM, NULL, "invalid tag id"); diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index 51b5e5a2e3..ab5f0ed9e2 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -955,7 +955,7 @@ flow_dv_convert_action_set_reg RTE_FLOW_ERROR_TYPE_ACTION, NULL, "too many items to modify"); MLX5_ASSERT(conf->id != REG_NON); - MLX5_ASSERT(conf->id < RTE_DIM(reg_to_field)); + MLX5_ASSERT(conf->id < (enum modify_reg)RTE_DIM(reg_to_field)); actions[i] = (struct mlx5_modification_cmd) { .action_type = MLX5_MODIFICATION_TYPE_SET, .field = reg_to_field[conf->id], diff --git a/drivers/net/mlx5/windows/mlx5_flow_os.c b/drivers/net/mlx5/windows/mlx5_flow_os.c index daf4e15ddb..acd7de61e0 100644 --- a/drivers/net/mlx5/windows/mlx5_flow_os.c +++ b/drivers/net/mlx5/windows/mlx5_flow_os.c @@ -188,7 +188,7 @@ mlx5_flow_os_create_flow(void *matcher, void *match_value, void *actions[], void **flow) { struct mlx5_action *action; - int i; + size_t i; struct mlx5_matcher *mlx5_matcher = matcher; struct mlx5_flow_dv_match_params *mlx5_match_value = match_value; uint32_t in[MLX5_ST_SZ_DW(devx_fs_rule_add_in)] = {0};