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GET /api/patches/63156/?format=api
{ "id": 63156, "url": "http://patches.dpdk.org/api/patches/63156/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1574244727-6003-3-git-send-email-joyce.kong@arm.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1574244727-6003-3-git-send-email-joyce.kong@arm.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1574244727-6003-3-git-send-email-joyce.kong@arm.com", "date": "2019-11-20T10:12:03", "name": "[v4,2/6] test/bitops: add bit operation test case", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "d1dae05056b01794553693d0e3576002f4973955", "submitter": { "id": 970, "url": "http://patches.dpdk.org/api/people/970/?format=api", "name": "Joyce Kong", "email": "joyce.kong@arm.com" }, "delegate": { "id": 24651, "url": "http://patches.dpdk.org/api/users/24651/?format=api", "username": "dmarchand", "first_name": "David", "last_name": "Marchand", "email": "david.marchand@redhat.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1574244727-6003-3-git-send-email-joyce.kong@arm.com/mbox/", "series": [ { "id": 7544, "url": "http://patches.dpdk.org/api/series/7544/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=7544", "date": "2019-11-20T10:12:01", "name": "implement common rte bit operation APIs in PMDs", "version": 4, "mbox": "http://patches.dpdk.org/series/7544/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/63156/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/63156/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 08CFFA04C1;\n\tWed, 20 Nov 2019 11:12:44 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 99EE11BE0C;\n\tWed, 20 Nov 2019 11:12:34 +0100 (CET)", "from foss.arm.com (foss.arm.com [217.140.110.172])\n by dpdk.org (Postfix) with ESMTP id 210B41B994\n for <dev@dpdk.org>; Wed, 20 Nov 2019 11:12:33 +0100 (CET)", "from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14])\n by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7E6C91FB;\n Wed, 20 Nov 2019 02:12:32 -0800 (PST)", "from net-arm-thunderx2-01.test.ast.arm.com\n (net-arm-thunderx2-01.shanghai.arm.com [10.169.40.40])\n by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id C10763F52E;\n Wed, 20 Nov 2019 02:12:28 -0800 (PST)" ], "From": "Joyce Kong <joyce.kong@arm.com>", "To": "dev@dpdk.org", "Cc": "nd@arm.com, thomas@monjalon.net, jerinj@marvell.com,\n stephen@networkplumber.org, mb@smartsharesystems.com,\n david.marchand@redhat.com, honnappa.nagarahalli@arm.com, gavin.hu@arm.com,\n ravi1.kumar@amd.com, rmody@marvell.com, shshaikh@marvell.com,\n xuanziyang2@huawei.com, cloud.wangxiaoyun@huawei.com,\n zhouguoyang@huawei.com", "Date": "Wed, 20 Nov 2019 18:12:03 +0800", "Message-Id": "<1574244727-6003-3-git-send-email-joyce.kong@arm.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": [ "<1574244727-6003-1-git-send-email-joyce.kong@arm.com>", "<1571125801-45773-1-git-send-email-joyce.kong@arm.com>" ], "References": [ "<1574244727-6003-1-git-send-email-joyce.kong@arm.com>", "<1571125801-45773-1-git-send-email-joyce.kong@arm.com>" ], "Subject": "[dpdk-dev] [PATCH v4 2/6] test/bitops: add bit operation test case", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add test cases for set bit, clear bit, test and set bit,\ntest and clear bit operations.\n\nSigned-off-by: Joyce Kong <joyce.kong@arm.com>\nReviewed-by: Gavin Hu <gavin.hu@arm.com>\nReviewed-by: Phil Yang <phil.yang@arm.com>\n---\n app/test/Makefile | 1 +\n app/test/autotest_data.py | 6 +\n app/test/meson.build | 2 +\n app/test/test_bitops.c | 305 ++++++++++++++++++++++++++++++++++++++++++++++\n 4 files changed, 314 insertions(+)\n create mode 100644 app/test/test_bitops.c", "diff": "diff --git a/app/test/Makefile b/app/test/Makefile\nindex 57930c0..4f33274 100644\n--- a/app/test/Makefile\n+++ b/app/test/Makefile\n@@ -70,6 +70,7 @@ SRCS-y += test_ticketlock.c\n SRCS-y += test_memory.c\n SRCS-y += test_memzone.c\n SRCS-y += test_bitmap.c\n+SRCS-y += test_bitops.c\n SRCS-y += test_reciprocal_division.c\n SRCS-y += test_reciprocal_division_perf.c\n SRCS-y += test_fbarray.c\ndiff --git a/app/test/autotest_data.py b/app/test/autotest_data.py\nindex 6deb97b..7db2df1 100644\n--- a/app/test/autotest_data.py\n+++ b/app/test/autotest_data.py\n@@ -405,6 +405,12 @@\n \"Report\": None,\n },\n {\n+ \"Name\": \"Bitops test\",\n+ \"Command\": \"bitops_autotest\",\n+ \"Func\": default_autotest,\n+ \"Report\": None,\n+ },\n+ {\n \"Name\": \"Hash multiwriter autotest\",\n \"Command\": \"hash_multiwriter_autotest\",\n \"Func\": default_autotest,\ndiff --git a/app/test/meson.build b/app/test/meson.build\nindex ff59c31..33b4135 100644\n--- a/app/test/meson.build\n+++ b/app/test/meson.build\n@@ -14,6 +14,7 @@ test_sources = files('commands.c',\n \t'test_atomic.c',\n \t'test_barrier.c',\n \t'test_bitratestats.c',\n+\t'test_bitops.c',\n \t'test_bpf.c',\n \t'test_byteorder.c',\n \t'test_cmdline.c',\n@@ -167,6 +168,7 @@ fast_test_names = [\n 'alarm_autotest',\n 'atomic_autotest',\n 'byteorder_autotest',\n+ 'bitops_autotest',\n 'cmdline_autotest',\n 'common_autotest',\n 'cpuflags_autotest',\ndiff --git a/app/test/test_bitops.c b/app/test/test_bitops.c\nnew file mode 100644\nindex 0000000..3859ca8\n--- /dev/null\n+++ b/app/test/test_bitops.c\n@@ -0,0 +1,305 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2019 Arm Limited\n+ */\n+\n+#include <rte_bitops.h>\n+#include <rte_launch.h>\n+#include \"test.h\"\n+\n+uint32_t val32;\n+uint64_t val64;\n+unsigned int synchro;\n+unsigned int count32;\n+unsigned int count64;\n+\n+#define MAX_BITS_32 32\n+#define MAX_BITS_64 64\n+/*\n+ * Bitops functions\n+ * ================\n+ *\n+ * - The main test function performs several subtests.\n+ * - For relaxed version, check bit operations on one core.\n+ * - Initialize valXX to specified values, then set each bit of valXX\n+ * to 1 one by one in \"test_bitops_set_relaxed\".\n+ *\n+ * - Clear each bit of valXX to 0 one by one in \"test_bitops_clear_relaxed\".\n+ *\n+ * - Function \"test_bitops_test_set_clear_relaxed\" checks whether each bit\n+ * of valXX can do \"test and set\" and \"test and clear\" correctly.\n+ *\n+ * - For C11 atomic barrier version, check bit operations on multi cores.\n+ * - Per bit of valXX is set to 1, then cleared to 0 on each core in\n+ * \"test_bitops_set_clear\". The function checks that once all lcores finish\n+ * their set_clear, the value of valXX would still be zero.\n+ *\n+ * - The cores are waiting for a synchro which is triggered by the main test\n+ * function. Then all cores would do \"rte_test_and_set_bitXX\" or\n+ * \"rte_test_and_clear_bitXX\" at the same time, \"countXX\" which is checked\n+ * as the result later would inc by one or not according to the original\n+ * bit value.\n+ *\n+ */\n+\n+static int\n+test_bitops_set_relaxed(void)\n+{\n+\tunsigned int i;\n+\n+\tfor (i = 0; i < MAX_BITS_32; i++)\n+\t\trte_set_bit32_relaxed(i, &val32);\n+\n+\tfor (i = 0; i < MAX_BITS_32; i++)\n+\t\tif (!rte_get_bit32_relaxed(i, &val32)) {\n+\t\t\tprintf(\"Failed to set bit in relaxed version.\\n\");\n+\t\t\treturn TEST_FAILED;\n+\t\t}\n+\n+\tfor (i = 0; i < MAX_BITS_64; i++)\n+\t\trte_set_bit64_relaxed(i, &val64);\n+\n+\tfor (i = 0; i < MAX_BITS_64; i++)\n+\t\tif (!rte_get_bit64_relaxed(i, &val64)) {\n+\t\t\tprintf(\"Failed to set bit in relaxed version.\\n\");\n+\t\t\treturn TEST_FAILED;\n+\t\t}\n+\n+\treturn TEST_SUCCESS;\n+}\n+\n+static int\n+test_bitops_clear_relaxed(void)\n+{\n+\tunsigned int i;\n+\n+\tfor (i = 0; i < MAX_BITS_32; i++)\n+\t\trte_clear_bit32_relaxed(i, &val32);\n+\n+\tfor (i = 0; i < MAX_BITS_32; i++)\n+\t\tif (rte_get_bit32_relaxed(i, &val32)) {\n+\t\t\tprintf(\"Failed to clear bit in relaxed version.\\n\");\n+\t\t\treturn TEST_FAILED;\n+\t\t}\n+\n+\tfor (i = 0; i < MAX_BITS_64; i++)\n+\t\trte_clear_bit64_relaxed(i, &val64);\n+\n+\tfor (i = 0; i < MAX_BITS_64; i++)\n+\t\tif (rte_get_bit64_relaxed(i, &val64)) {\n+\t\t\tprintf(\"Failed to clear bit in relaxed version.\\n\");\n+\t\t\treturn TEST_FAILED;\n+\t\t}\n+\n+\treturn TEST_SUCCESS;\n+}\n+\n+static int\n+test_bitops_test_set_clear_relaxed(void)\n+{\n+\tunsigned int i;\n+\n+\tfor (i = 0; i < MAX_BITS_32; i++)\n+\t\trte_test_and_set_bit32_relaxed(i, &val32);\n+\n+\tfor (i = 0; i < MAX_BITS_32; i++)\n+\t\tif (!rte_test_and_clear_bit32_relaxed(i, &val32)) {\n+\t\t\tprintf(\"Failed to set and test bit in relaxed version.\\n\");\n+\t\t\treturn TEST_FAILED;\n+\t}\n+\n+\tfor (i = 0; i < MAX_BITS_32; i++)\n+\t\tif (rte_get_bit32_relaxed(i, &val32)) {\n+\t\t\tprintf(\"Failed to test and clear bit in relaxed version.\\n\");\n+\t\t\treturn TEST_FAILED;\n+\t\t}\n+\n+\tfor (i = 0; i < MAX_BITS_64; i++)\n+\t\trte_test_and_set_bit64_relaxed(i, &val64);\n+\n+\tfor (i = 0; i < MAX_BITS_64; i++)\n+\t\tif (!rte_test_and_clear_bit64_relaxed(i, &val64)) {\n+\t\t\tprintf(\"Failed to set and test bit in relaxed version.\\n\");\n+\t\t\treturn TEST_FAILED;\n+\t\t}\n+\n+\tfor (i = 0; i < MAX_BITS_64; i++)\n+\t\tif (rte_get_bit64_relaxed(i, &val64)) {\n+\t\t\tprintf(\"Failed to test and clear bit in relaxed version.\\n\");\n+\t\t\treturn TEST_FAILED;\n+\t\t}\n+\n+\treturn TEST_SUCCESS;\n+}\n+\n+static int\n+test_bitops_set_clear(__attribute__((unused)) void *arg)\n+{\n+\twhile (__atomic_load_n(&synchro, __ATOMIC_RELAXED) == 0)\n+\t\t;\n+\n+\tunsigned int i;\n+\n+\tfor (i = 0; i < MAX_BITS_32; i++)\n+\t\trte_set_bit32(i, &val32);\n+\tfor (i = 0; i < MAX_BITS_32; i++)\n+\t\trte_clear_bit32(i, &val32);\n+\n+\tfor (i = 0; i < MAX_BITS_64; i++)\n+\t\trte_set_bit64(i, &val64);\n+\tfor (i = 0; i < MAX_BITS_64; i++)\n+\t\trte_clear_bit64(i, &val64);\n+\n+\treturn TEST_SUCCESS;\n+}\n+\n+/*\n+ * rte_test_and_set_bitXX() returns the original bit value, then set it to 1.\n+ * This functions checks that if the target bit is equal to 0, set it to 1 and\n+ * increase the variable of \"countXX\" by one. If it is equal to 1, do nothing\n+ * for \"countXX\". The value of \"countXX\" would be checked as the result later.\n+ */\n+static int\n+test_bitops_test_set(__attribute__((unused)) void *arg)\n+\n+{\n+\twhile (__atomic_load_n(&synchro, __ATOMIC_RELAXED) == 0)\n+\t\t;\n+\n+\tunsigned int i;\n+\n+\tfor (i = 0; i < MAX_BITS_32; i++)\n+\t\tif (!rte_test_and_set_bit32(i, &val32))\n+\t\t\t__atomic_fetch_add(&count32, 1, __ATOMIC_ACQ_REL);\n+\n+\tfor (i = 0; i < MAX_BITS_64; i++)\n+\t\tif (!rte_test_and_set_bit64(i, &val64))\n+\t\t\t__atomic_fetch_add(&count64, 1, __ATOMIC_ACQ_REL);\n+\n+\treturn TEST_SUCCESS;\n+}\n+\n+/*\n+ * rte_test_and_set_bitXX() returns the original bit value, then clear it to 0.\n+ * This functions checks that if the target bit is equal to 1, clear it to 0 and\n+ * increase the variable of \"countXX\" by one. If it is equal to 0, do nothing\n+ * for \"countXX\". The value of \"countXX\" would be checked as the result later.\n+ */\n+static int\n+test_bitops_test_clear(__attribute__((unused)) void *arg)\n+\n+{\n+\twhile (__atomic_load_n(&synchro, __ATOMIC_RELAXED) == 0)\n+\t\t;\n+\n+\tunsigned int i;\n+\n+\tfor (i = 0; i < MAX_BITS_32; i++)\n+\t\tif (rte_test_and_clear_bit32(i, &val32))\n+\t\t\t__atomic_fetch_add(&count32, 1, __ATOMIC_ACQ_REL);\n+\n+\tfor (i = 0; i < MAX_BITS_64; i++)\n+\t\tif (rte_test_and_clear_bit64(i, &val64))\n+\t\t\t__atomic_fetch_add(&count64, 1, __ATOMIC_ACQ_REL);\n+\n+\treturn TEST_SUCCESS;\n+}\n+\n+static int\n+test_bitops(void)\n+{\n+\t__atomic_store_n(&val32, 0, __ATOMIC_RELAXED);\n+\t__atomic_store_n(&val64, 0, __ATOMIC_RELAXED);\n+\t__atomic_store_n(&synchro, 0, __ATOMIC_RELAXED);\n+\t__atomic_store_n(&count32, 0, __ATOMIC_RELAXED);\n+\t__atomic_store_n(&count64, 0, __ATOMIC_RTELAXED);\n+\n+\tif (test_bitops_set_relaxed() < 0)\n+\t\treturn TEST_FAILED;\n+\n+\tif (test_bitops_clear_relaxed() < 0)\n+\t\treturn TEST_FAILED;\n+\n+\tif (test_bitops_test_set_clear_relaxed() < 0)\n+\t\treturn TEST_FAILED;\n+\n+\n+\trte_eal_mp_remote_launch(test_bitops_set_clear, NULL, SKIP_MASTER);\n+\t__atomic_store_n(&synchro, 1, __ATOMIC_RELAXED);\n+\trte_eal_mp_wait_lcore();\n+\t__atomic_store_n(&synchro, 0, __ATOMIC_RELAXED);\n+\n+\tunsigned int i;\n+\n+\tfor (i = 0; i < MAX_BITS_32; i++)\n+\t\tif (rte_get_bit32(i, &val32)) {\n+\t\t\tprintf(\"Failed to set and clear bit on multi cores.\\n\");\n+\t\t\treturn TEST_FAILED;\n+\t\t}\n+\n+\tfor (i = 0; i < MAX_BITS_64; i++)\n+\t\tif (rte_get_bit64(i, &val64)) {\n+\t\t\tprintf(\"Failed to set and clear bit on multi cores.\\n\");\n+\t\t\treturn TEST_FAILED;\n+\t\t}\n+\n+\t/*\n+\t * Launch all slave lcores to do \"rte_bitops_test_and_set_bitXX\"\n+\t * respectively.\n+\t * Each lcore should have MAX_BITS_XX chances to check the target bit.\n+\t * If it's equal to 0, set it to 1 and \"countXX (which is initialized\n+\t * to 0)\" would be increased by one. If the target bit is 1, still set\n+\t * it to 1 and do nothing for \"countXX\". There would be only one lcore\n+\t * that finds the target bit is 0.\n+\t * If the final value of \"countXX\" is equal to MAX_BITS_XX, all slave\n+\t * lcores performed \"rte_bitops_test_and_set_bitXX\" correctly.\n+\t */\n+\t__atomic_store_n(&count32, 0, __ATOMIC_RELAXED);\n+\t__atomic_store_n(&count64, 0, __ATOMIC_RELAXED);\n+\n+\trte_eal_mp_remote_launch(test_bitops_test_set, NULL, SKIP_MASTER);\n+\t__atomic_store_n(&synchro, 1, __ATOMIC_RELAXED);\n+\trte_eal_mp_wait_lcore();\n+\t__atomic_store_n(&synchro, 0, __ATOMIC_RELAXED);\n+\n+\tif (__atomic_load_n(&count32, __ATOMIC_RELAXED) != MAX_BITS_32) {\n+\t\tprintf(\"Failed to test and set on multi cores.\\n\");\n+\t\treturn TEST_FAILED;\n+\t}\n+\tif (__atomic_load_n(&count64, __ATOMIC_RELAXED) != MAX_BITS_64) {\n+\t\tprintf(\"Failed to test and set on multi cores.\\n\");\n+\t\treturn TEST_FAILED;\n+\t}\n+\n+\t/*\n+\t * Launch all slave lcores to do \"rte_bitops_test_and_clear_bitXX\"\n+\t * respectively.\n+\t * Each lcore should have MAX_BITS_XX chances to check the target bit.\n+\t * If it's equal to 1, clear it to 0 and \"countXX (which is initialized\n+\t * to 0)\" would be increased by one. If the target bit is 0, still clear\n+\t * it to 0 and do nothing for \"countXX\". There would be only one lcore\n+\t * that finds the target bit is 1.\n+\t * If the final value of \"countXX\" is equal to MAX_BITS_XX, all slave\n+\t * lcores performed \"rte_bitops_test_and_clear_bitXX\" correctly.\n+\t */\n+\n+\t__atomic_store_n(&count32, 0, __ATOMIC_RELAXED);\n+\t__atomic_store_n(&count64, 0, __ATOMIC_RELAXED);\n+\n+\trte_eal_mp_remote_launch(test_bitops_test_clear, NULL, SKIP_MASTER);\n+\t__atomic_store_n(&synchro, 1, __ATOMIC_RELAXED);\n+\trte_eal_mp_wait_lcore();\n+\t__atomic_store_n(&synchro, 0, __ATOMIC_RELAXED);\n+\n+\tif (__atomic_load_n(&count32, __ATOMIC_RELAXED) != MAX_BITS_32) {\n+\t\tprintf(\"Failed to test and clear on multi cores.\\n\");\n+\t\treturn TEST_FAILED;\n+\t}\n+\tif (__atomic_load_n(&count64, __ATOMIC_RELAXED) != MAX_BITS_64) {\n+\t\tprintf(\"Failed to test and clear on multi cores.\\n\");\n+\t\treturn TEST_FAILED;\n+\t}\n+\n+\treturn TEST_SUCCESS;\n+}\n+\n+REGISTER_TEST_COMMAND(bitops_autotest, test_bitops);\n", "prefixes": [ "v4", "2/6" ] }