From patchwork Wed Nov 20 10:12:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Joyce Kong X-Patchwork-Id: 63155 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 014E0A04C1; Wed, 20 Nov 2019 11:12:33 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 5F9A67CBC; Wed, 20 Nov 2019 11:12:30 +0100 (CET) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by dpdk.org (Postfix) with ESMTP id EFB9E5F13 for ; Wed, 20 Nov 2019 11:12:28 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5825C31B; Wed, 20 Nov 2019 02:12:28 -0800 (PST) Received: from net-arm-thunderx2-01.test.ast.arm.com (net-arm-thunderx2-01.shanghai.arm.com [10.169.40.40]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id A79FC3F52E; Wed, 20 Nov 2019 02:12:24 -0800 (PST) From: Joyce Kong To: dev@dpdk.org Cc: nd@arm.com, thomas@monjalon.net, jerinj@marvell.com, stephen@networkplumber.org, mb@smartsharesystems.com, david.marchand@redhat.com, honnappa.nagarahalli@arm.com, gavin.hu@arm.com, ravi1.kumar@amd.com, rmody@marvell.com, shshaikh@marvell.com, xuanziyang2@huawei.com, cloud.wangxiaoyun@huawei.com, zhouguoyang@huawei.com Date: Wed, 20 Nov 2019 18:12:02 +0800 Message-Id: <1574244727-6003-2-git-send-email-joyce.kong@arm.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1574244727-6003-1-git-send-email-joyce.kong@arm.com> References: <1574244727-6003-1-git-send-email-joyce.kong@arm.com> In-Reply-To: <1571125801-45773-1-git-send-email-joyce.kong@arm.com> References: <1571125801-45773-1-git-send-email-joyce.kong@arm.com> Subject: [dpdk-dev] [PATCH v4 1/6] lib/eal: implement the family of rte bit operation APIs X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" There are a lot functions of bit operations scattered and duplicated in PMDs, consolidating them into a common API family is necessary. Furthermore, when the bit operation is applied to the IO devices, use __ATOMIC_ACQ_REL to ensure the ordering for io bit operation. Signed-off-by: Joyce Kong Reviewed-by: Gavin Hu Reviewed-by: Phil Yang Acked-by: Morten Brørup --- MAINTAINERS | 5 + doc/api/doxy-api-index.md | 5 +- lib/librte_eal/common/Makefile | 1 + lib/librte_eal/common/include/rte_bitops.h | 474 +++++++++++++++++++++++++++++ lib/librte_eal/common/meson.build | 3 +- 5 files changed, 485 insertions(+), 3 deletions(-) create mode 100644 lib/librte_eal/common/include/rte_bitops.h diff --git a/MAINTAINERS b/MAINTAINERS index f2fdb93..4ee2712 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -233,6 +233,11 @@ M: Cristian Dumitrescu F: lib/librte_eal/common/include/rte_bitmap.h F: app/test/test_bitmap.c +Bitops +M: Joyce Kong +F: lib/librte_eal/common/include/rte_bitops.h +F: app/test/test_bitops.c + MCSlock - EXPERIMENTAL M: Phil Yang F: lib/librte_eal/common/include/generic/rte_mcslock.h diff --git a/doc/api/doxy-api-index.md b/doc/api/doxy-api-index.md index dff496b..ade7c01 100644 --- a/doc/api/doxy-api-index.md +++ b/doc/api/doxy-api-index.md @@ -133,12 +133,13 @@ The public API headers are grouped by topics: [BPF] (@ref rte_bpf.h) - **containers**: + [bitmap] (@ref rte_bitmap.h), + [bitops] (@ref rte_bitops.h), [mbuf] (@ref rte_mbuf.h), [mbuf pool ops] (@ref rte_mbuf_pool_ops.h), [ring] (@ref rte_ring.h), [stack] (@ref rte_stack.h), - [tailq] (@ref rte_tailq.h), - [bitmap] (@ref rte_bitmap.h) + [tailq] (@ref rte_tailq.h) - **packet framework**: * [port] (@ref rte_port.h): diff --git a/lib/librte_eal/common/Makefile b/lib/librte_eal/common/Makefile index c2c6d92..dd025c1 100644 --- a/lib/librte_eal/common/Makefile +++ b/lib/librte_eal/common/Makefile @@ -19,6 +19,7 @@ INC += rte_malloc.h rte_keepalive.h rte_time.h INC += rte_service.h rte_service_component.h INC += rte_bitmap.h rte_vfio.h rte_hypervisor.h rte_test.h INC += rte_reciprocal.h rte_fbarray.h rte_uuid.h +INC += rte_bitops.h GENERIC_INC := rte_atomic.h rte_byteorder.h rte_cycles.h rte_prefetch.h GENERIC_INC += rte_memcpy.h rte_cpuflags.h diff --git a/lib/librte_eal/common/include/rte_bitops.h b/lib/librte_eal/common/include/rte_bitops.h new file mode 100644 index 0000000..34158d1 --- /dev/null +++ b/lib/librte_eal/common/include/rte_bitops.h @@ -0,0 +1,474 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2019 Arm Limited + */ + +#ifndef _RTE_BITOPS_H_ +#define _RTE_BITOPS_H_ + +/** + * @file + * Bit Operations + * + * This file defines a API for bit operations without/with memory ordering. + */ + +#include +#include +#include + +/*---------------------------- 32 bit operations ----------------------------*/ + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Get the target bit from a 32-bit value without memory ordering. + * + * @param nr + * The target bit to get. + * @param addr + * The address holding the bit. + * @return + * The target bit. + */ +__rte_experimental +static inline uint32_t +rte_get_bit32_relaxed(unsigned int nr, uint32_t *addr) +{ + RTE_ASSERT(nr < 32); + + uint32_t mask = UINT32_C(1) << nr; + return __atomic_load_n(addr, __ATOMIC_RELAXED) & mask; +} + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Set the target bit in a 32-bit value to 1 without memory ordering. + * + * @param nr + * The target bit to set. + * @param addr + * The address holding the bit. + */ +__rte_experimental +static inline void +rte_set_bit32_relaxed(unsigned int nr, uint32_t *addr) +{ + RTE_ASSERT(nr < 32); + + uint32_t mask = UINT32_C(1) << nr; + __atomic_fetch_or(addr, mask, __ATOMIC_RELAXED); +} + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Clear the target bit in a 32-bit value to 0 without memory ordering. + * + * @param nr + * The target bit to clear. + * @param addr + * The address holding the bit. + */ +__rte_experimental +static inline void +rte_clear_bit32_relaxed(unsigned int nr, uint32_t *addr) +{ + RTE_ASSERT(nr < 32); + + uint32_t mask = UINT32_C(1) << nr; + __atomic_fetch_and(addr, ~mask, __ATOMIC_RELAXED); +} + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Return the original bit from a 32-bit value, then set it to 1 without + * memory ordering. + * + * @param nr + * The target bit to get and set. + * @param addr + * The address holding the bit. + * @return + * The original bit. + */ +__rte_experimental +static inline uint32_t +rte_test_and_set_bit32_relaxed(unsigned int nr, uint32_t *addr) +{ + RTE_ASSERT(nr < 32); + + uint32_t mask = UINT32_C(1) << nr; + return __atomic_fetch_or(addr, mask, __ATOMIC_RELAXED) & mask; +} + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Return the original bit from a 32-bit value, then clear it to 0 without + * memory ordering. + * + * @param nr + * The target bit to get and clear. + * @param addr + * The address holding the bit. + * @return + * The original bit. + */ +__rte_experimental +static inline uint32_t +rte_test_and_clear_bit32_relaxed(unsigned int nr, uint32_t *addr) +{ + RTE_ASSERT(nr < 32); + + uint32_t mask = UINT32_C(1) << nr; + return __atomic_fetch_and(addr, ~mask, __ATOMIC_RELAXED) & mask; +} + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Get the target bit from a 32-bit value with memory ordering. + * + * @param nr + * The target bit to get. + * @param addr + * The address holding the bit. + * @return + * The target bit. + */ +__rte_experimental +static inline uint32_t +rte_get_bit32(unsigned int nr, uint32_t *addr) +{ + RTE_ASSERT(nr < 32); + + uint32_t mask = UINT32_C(1) << nr; + return __atomic_load_n(addr, __ATOMIC_ACQUIRE) & mask; +} + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Set the target bit in a 32-bit value to 1 with memory ordering. + * + * @param nr + * The target bit to set. + * @param addr + * The address holding the bit. + */ +__rte_experimental +static inline void +rte_set_bit32(unsigned int nr, uint32_t *addr) +{ + RTE_ASSERT(nr < 32); + + uint32_t mask = UINT32_C(1) << nr; + __atomic_fetch_or(addr, mask, __ATOMIC_ACQ_REL); +} + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Clear the target bit in a 32-bit value to 0 with memory ordering. + * + * @param nr + * The target bit to clear. + * @param addr + * The address holding the bit. + */ +__rte_experimental +static inline void +rte_clear_bit32(unsigned int nr, uint32_t *addr) +{ + RTE_ASSERT(nr < 32); + + uint32_t mask = UINT32_C(1) << nr; + __atomic_fetch_and(addr, ~mask, __ATOMIC_ACQ_REL); +} + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Return the original bit from a 32-bit value, then set it to 1 with + * memory ordering. + * + * @param nr + * The target bit to get and set. + * @param addr + * The address holding the bit. + * @return + * The original bit. + */ +__rte_experimental +static inline uint32_t +rte_test_and_set_bit32(unsigned int nr, uint32_t *addr) +{ + RTE_ASSERT(nr < 32); + + uint32_t mask = UINT32_C(1) << nr; + return __atomic_fetch_or(addr, mask, __ATOMIC_ACQ_REL) & mask; +} + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Return the original bit from a 32-bit value, then clear it to 0 with + * memory ordering. + * + * @param nr + * The target bit to get and clear. + * @param addr + * The address holding the bit. + * @return + * The original bit. + */ +__rte_experimental +static inline uint32_t +rte_test_and_clear_bit32(unsigned int nr, uint32_t *addr) +{ + RTE_ASSERT(nr < 32); + + uint32_t mask = UINT32_C(1) << nr; + return __atomic_fetch_and(addr, ~mask, __ATOMIC_ACQ_REL) & mask; +} + +/*---------------------------- 64 bit operations ----------------------------*/ + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Get the target bit from a 64-bit value without memory ordering. + * + * @param nr + * The target bit to get. + * @param addr + * The address holding the bit. + * @return + * The target bit. + */ +__rte_experimental +static inline uint64_t +rte_get_bit64_relaxed(unsigned int nr, uint64_t *addr) +{ + RTE_ASSERT(nr < 64); + + uint64_t mask = UINT64_C(1) << nr; + return __atomic_load_n(addr, __ATOMIC_RELAXED) & mask; +} + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Set the target bit in a 64-bit value to 1 without memory ordering. + * + * @param nr + * The target bit to set. + * @param addr + * The address holding the bit. + */ +__rte_experimental +static inline void +rte_set_bit64_relaxed(unsigned int nr, uint64_t *addr) +{ + RTE_ASSERT(nr < 64); + + uint64_t mask = UINT64_C(1) << nr; + __atomic_fetch_or(addr, mask, __ATOMIC_RELAXED); +} + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Clear the target bit in a 64-bit value to 0 without memory ordering. + * + * @param nr + * The target bit to clear. + * @param addr + * The address holding the bit. + */ +__rte_experimental +static inline void +rte_clear_bit64_relaxed(unsigned int nr, uint64_t *addr) +{ + RTE_ASSERT(nr < 64); + + uint64_t mask = UINT64_C(1) << nr; + __atomic_fetch_and(addr, ~mask, __ATOMIC_RELAXED); +} + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Return the original bit from a 64-bit value, then set it to 1 without + * memory ordering. + * + * @param nr + * The target bit to get and set. + * @param addr + * The address holding the bit. + * @return + * The original bit. + */ +__rte_experimental +static inline uint64_t +rte_test_and_set_bit64_relaxed(unsigned int nr, uint64_t *addr) +{ + RTE_ASSERT(nr < 64); + + uint64_t mask = UINT64_C(1) << nr; + return __atomic_fetch_or(addr, mask, __ATOMIC_RELAXED) & mask; +} + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Return the original bit from a 64-bit value, then clear it to 0 without + * memory ordering. + * + * @param nr + * The target bit to get and clear. + * @param addr + * The address holding the bit. + * @return + * The original bit. + */ +__rte_experimental +static inline uint64_t +rte_test_and_clear_bit64_relaxed(unsigned int nr, uint64_t *addr) +{ + RTE_ASSERT(nr < 64); + + uint64_t mask = UINT64_C(1) << nr; + return __atomic_fetch_and(addr, ~mask, __ATOMIC_RELAXED) & mask; +} + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Get the target bit from a 64-bit value with memory ordering. + * + * @param nr + * The target bit to get. + * @param addr + * The address holding the bit. + * @return + * The target bit. + */ +__rte_experimental +static inline uint64_t +rte_get_bit64(unsigned int nr, uint64_t *addr) +{ + RTE_ASSERT(nr < 64); + + uint64_t mask = UINT64_C(1) << nr; + return __atomic_load_n(addr, __ATOMIC_ACQUIRE) & mask; +} + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Set the target bit in a 64-bit value to 1 with memory ordering. + * + * @param nr + * The target bit to set. + * @param addr + * The address holding the bit. + */ +__rte_experimental +static inline void +rte_set_bit64(unsigned int nr, uint64_t *addr) +{ + RTE_ASSERT(nr < 64); + + uint64_t mask = UINT64_C(1) << nr; + __atomic_fetch_or(addr, mask, __ATOMIC_ACQ_REL); +} + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Clear the target bit in a 64-bit value to 0 with memory ordering. + * + * @param nr + * The target bit to clear. + * @param addr + * The address holding the bit. + */ +__rte_experimental +static inline void +rte_clear_bit64(unsigned int nr, uint64_t *addr) +{ + RTE_ASSERT(nr < 64); + + uint64_t mask = UINT64_C(1) << nr; + __atomic_fetch_and(addr, ~mask, __ATOMIC_ACQ_REL); +} + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Return the original bit from a 64-bit value, then set it to 1 with + * memory ordering. + * + * @param nr + * The target bit to get and set. + * @param addr + * The address holding the bit. + * @return + * The original bit. + */ +__rte_experimental +static inline uint64_t +rte_test_and_set_bit64(unsigned int nr, uint64_t *addr) +{ + RTE_ASSERT(nr < 64); + + uint64_t mask = UINT64_C(1) << nr; + return __atomic_fetch_or(addr, mask, __ATOMIC_ACQ_REL) & mask; +} + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Return the original bit from a 64-bit value, then clear it to 0 with + * memory ordering. + * + * @param nr + * The target bit to get and clear. + * @param addr + * The address holding the bit. + * @return + * The original bit. + */ +__rte_experimental +static inline uint64_t +rte_test_and_clear_bit64(unsigned int nr, uint64_t *addr) +{ + RTE_ASSERT(nr < 64); + + uint64_t mask = UINT64_C(1) << nr; + return __atomic_fetch_and(addr, ~mask, __ATOMIC_ACQ_REL) & mask; +} +#endif /* _RTE_BITOPS_H_ */ diff --git a/lib/librte_eal/common/meson.build b/lib/librte_eal/common/meson.build index d6a149b..8a5197b 100644 --- a/lib/librte_eal/common/meson.build +++ b/lib/librte_eal/common/meson.build @@ -50,9 +50,10 @@ common_objs += eal_common_arch_objs common_headers = files( 'include/rte_alarm.h', + 'include/rte_bitmap.h', + 'include/rte_bitops.h', 'include/rte_branch_prediction.h', 'include/rte_bus.h', - 'include/rte_bitmap.h', 'include/rte_class.h', 'include/rte_common.h', 'include/rte_compat.h', From patchwork Wed Nov 20 10:12:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joyce Kong X-Patchwork-Id: 63156 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 08CFFA04C1; Wed, 20 Nov 2019 11:12:44 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 99EE11BE0C; Wed, 20 Nov 2019 11:12:34 +0100 (CET) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by dpdk.org (Postfix) with ESMTP id 210B41B994 for ; Wed, 20 Nov 2019 11:12:33 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7E6C91FB; Wed, 20 Nov 2019 02:12:32 -0800 (PST) Received: from net-arm-thunderx2-01.test.ast.arm.com (net-arm-thunderx2-01.shanghai.arm.com [10.169.40.40]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id C10763F52E; Wed, 20 Nov 2019 02:12:28 -0800 (PST) From: Joyce Kong To: dev@dpdk.org Cc: nd@arm.com, thomas@monjalon.net, jerinj@marvell.com, stephen@networkplumber.org, mb@smartsharesystems.com, david.marchand@redhat.com, honnappa.nagarahalli@arm.com, gavin.hu@arm.com, ravi1.kumar@amd.com, rmody@marvell.com, shshaikh@marvell.com, xuanziyang2@huawei.com, cloud.wangxiaoyun@huawei.com, zhouguoyang@huawei.com Date: Wed, 20 Nov 2019 18:12:03 +0800 Message-Id: <1574244727-6003-3-git-send-email-joyce.kong@arm.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1574244727-6003-1-git-send-email-joyce.kong@arm.com> References: <1574244727-6003-1-git-send-email-joyce.kong@arm.com> In-Reply-To: <1571125801-45773-1-git-send-email-joyce.kong@arm.com> References: <1571125801-45773-1-git-send-email-joyce.kong@arm.com> Subject: [dpdk-dev] [PATCH v4 2/6] test/bitops: add bit operation test case X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add test cases for set bit, clear bit, test and set bit, test and clear bit operations. Signed-off-by: Joyce Kong Reviewed-by: Gavin Hu Reviewed-by: Phil Yang --- app/test/Makefile | 1 + app/test/autotest_data.py | 6 + app/test/meson.build | 2 + app/test/test_bitops.c | 305 ++++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 314 insertions(+) create mode 100644 app/test/test_bitops.c diff --git a/app/test/Makefile b/app/test/Makefile index 57930c0..4f33274 100644 --- a/app/test/Makefile +++ b/app/test/Makefile @@ -70,6 +70,7 @@ SRCS-y += test_ticketlock.c SRCS-y += test_memory.c SRCS-y += test_memzone.c SRCS-y += test_bitmap.c +SRCS-y += test_bitops.c SRCS-y += test_reciprocal_division.c SRCS-y += test_reciprocal_division_perf.c SRCS-y += test_fbarray.c diff --git a/app/test/autotest_data.py b/app/test/autotest_data.py index 6deb97b..7db2df1 100644 --- a/app/test/autotest_data.py +++ b/app/test/autotest_data.py @@ -405,6 +405,12 @@ "Report": None, }, { + "Name": "Bitops test", + "Command": "bitops_autotest", + "Func": default_autotest, + "Report": None, + }, + { "Name": "Hash multiwriter autotest", "Command": "hash_multiwriter_autotest", "Func": default_autotest, diff --git a/app/test/meson.build b/app/test/meson.build index ff59c31..33b4135 100644 --- a/app/test/meson.build +++ b/app/test/meson.build @@ -14,6 +14,7 @@ test_sources = files('commands.c', 'test_atomic.c', 'test_barrier.c', 'test_bitratestats.c', + 'test_bitops.c', 'test_bpf.c', 'test_byteorder.c', 'test_cmdline.c', @@ -167,6 +168,7 @@ fast_test_names = [ 'alarm_autotest', 'atomic_autotest', 'byteorder_autotest', + 'bitops_autotest', 'cmdline_autotest', 'common_autotest', 'cpuflags_autotest', diff --git a/app/test/test_bitops.c b/app/test/test_bitops.c new file mode 100644 index 0000000..3859ca8 --- /dev/null +++ b/app/test/test_bitops.c @@ -0,0 +1,305 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2019 Arm Limited + */ + +#include +#include +#include "test.h" + +uint32_t val32; +uint64_t val64; +unsigned int synchro; +unsigned int count32; +unsigned int count64; + +#define MAX_BITS_32 32 +#define MAX_BITS_64 64 +/* + * Bitops functions + * ================ + * + * - The main test function performs several subtests. + * - For relaxed version, check bit operations on one core. + * - Initialize valXX to specified values, then set each bit of valXX + * to 1 one by one in "test_bitops_set_relaxed". + * + * - Clear each bit of valXX to 0 one by one in "test_bitops_clear_relaxed". + * + * - Function "test_bitops_test_set_clear_relaxed" checks whether each bit + * of valXX can do "test and set" and "test and clear" correctly. + * + * - For C11 atomic barrier version, check bit operations on multi cores. + * - Per bit of valXX is set to 1, then cleared to 0 on each core in + * "test_bitops_set_clear". The function checks that once all lcores finish + * their set_clear, the value of valXX would still be zero. + * + * - The cores are waiting for a synchro which is triggered by the main test + * function. Then all cores would do "rte_test_and_set_bitXX" or + * "rte_test_and_clear_bitXX" at the same time, "countXX" which is checked + * as the result later would inc by one or not according to the original + * bit value. + * + */ + +static int +test_bitops_set_relaxed(void) +{ + unsigned int i; + + for (i = 0; i < MAX_BITS_32; i++) + rte_set_bit32_relaxed(i, &val32); + + for (i = 0; i < MAX_BITS_32; i++) + if (!rte_get_bit32_relaxed(i, &val32)) { + printf("Failed to set bit in relaxed version.\n"); + return TEST_FAILED; + } + + for (i = 0; i < MAX_BITS_64; i++) + rte_set_bit64_relaxed(i, &val64); + + for (i = 0; i < MAX_BITS_64; i++) + if (!rte_get_bit64_relaxed(i, &val64)) { + printf("Failed to set bit in relaxed version.\n"); + return TEST_FAILED; + } + + return TEST_SUCCESS; +} + +static int +test_bitops_clear_relaxed(void) +{ + unsigned int i; + + for (i = 0; i < MAX_BITS_32; i++) + rte_clear_bit32_relaxed(i, &val32); + + for (i = 0; i < MAX_BITS_32; i++) + if (rte_get_bit32_relaxed(i, &val32)) { + printf("Failed to clear bit in relaxed version.\n"); + return TEST_FAILED; + } + + for (i = 0; i < MAX_BITS_64; i++) + rte_clear_bit64_relaxed(i, &val64); + + for (i = 0; i < MAX_BITS_64; i++) + if (rte_get_bit64_relaxed(i, &val64)) { + printf("Failed to clear bit in relaxed version.\n"); + return TEST_FAILED; + } + + return TEST_SUCCESS; +} + +static int +test_bitops_test_set_clear_relaxed(void) +{ + unsigned int i; + + for (i = 0; i < MAX_BITS_32; i++) + rte_test_and_set_bit32_relaxed(i, &val32); + + for (i = 0; i < MAX_BITS_32; i++) + if (!rte_test_and_clear_bit32_relaxed(i, &val32)) { + printf("Failed to set and test bit in relaxed version.\n"); + return TEST_FAILED; + } + + for (i = 0; i < MAX_BITS_32; i++) + if (rte_get_bit32_relaxed(i, &val32)) { + printf("Failed to test and clear bit in relaxed version.\n"); + return TEST_FAILED; + } + + for (i = 0; i < MAX_BITS_64; i++) + rte_test_and_set_bit64_relaxed(i, &val64); + + for (i = 0; i < MAX_BITS_64; i++) + if (!rte_test_and_clear_bit64_relaxed(i, &val64)) { + printf("Failed to set and test bit in relaxed version.\n"); + return TEST_FAILED; + } + + for (i = 0; i < MAX_BITS_64; i++) + if (rte_get_bit64_relaxed(i, &val64)) { + printf("Failed to test and clear bit in relaxed version.\n"); + return TEST_FAILED; + } + + return TEST_SUCCESS; +} + +static int +test_bitops_set_clear(__attribute__((unused)) void *arg) +{ + while (__atomic_load_n(&synchro, __ATOMIC_RELAXED) == 0) + ; + + unsigned int i; + + for (i = 0; i < MAX_BITS_32; i++) + rte_set_bit32(i, &val32); + for (i = 0; i < MAX_BITS_32; i++) + rte_clear_bit32(i, &val32); + + for (i = 0; i < MAX_BITS_64; i++) + rte_set_bit64(i, &val64); + for (i = 0; i < MAX_BITS_64; i++) + rte_clear_bit64(i, &val64); + + return TEST_SUCCESS; +} + +/* + * rte_test_and_set_bitXX() returns the original bit value, then set it to 1. + * This functions checks that if the target bit is equal to 0, set it to 1 and + * increase the variable of "countXX" by one. If it is equal to 1, do nothing + * for "countXX". The value of "countXX" would be checked as the result later. + */ +static int +test_bitops_test_set(__attribute__((unused)) void *arg) + +{ + while (__atomic_load_n(&synchro, __ATOMIC_RELAXED) == 0) + ; + + unsigned int i; + + for (i = 0; i < MAX_BITS_32; i++) + if (!rte_test_and_set_bit32(i, &val32)) + __atomic_fetch_add(&count32, 1, __ATOMIC_ACQ_REL); + + for (i = 0; i < MAX_BITS_64; i++) + if (!rte_test_and_set_bit64(i, &val64)) + __atomic_fetch_add(&count64, 1, __ATOMIC_ACQ_REL); + + return TEST_SUCCESS; +} + +/* + * rte_test_and_set_bitXX() returns the original bit value, then clear it to 0. + * This functions checks that if the target bit is equal to 1, clear it to 0 and + * increase the variable of "countXX" by one. If it is equal to 0, do nothing + * for "countXX". The value of "countXX" would be checked as the result later. + */ +static int +test_bitops_test_clear(__attribute__((unused)) void *arg) + +{ + while (__atomic_load_n(&synchro, __ATOMIC_RELAXED) == 0) + ; + + unsigned int i; + + for (i = 0; i < MAX_BITS_32; i++) + if (rte_test_and_clear_bit32(i, &val32)) + __atomic_fetch_add(&count32, 1, __ATOMIC_ACQ_REL); + + for (i = 0; i < MAX_BITS_64; i++) + if (rte_test_and_clear_bit64(i, &val64)) + __atomic_fetch_add(&count64, 1, __ATOMIC_ACQ_REL); + + return TEST_SUCCESS; +} + +static int +test_bitops(void) +{ + __atomic_store_n(&val32, 0, __ATOMIC_RELAXED); + __atomic_store_n(&val64, 0, __ATOMIC_RELAXED); + __atomic_store_n(&synchro, 0, __ATOMIC_RELAXED); + __atomic_store_n(&count32, 0, __ATOMIC_RELAXED); + __atomic_store_n(&count64, 0, __ATOMIC_RTELAXED); + + if (test_bitops_set_relaxed() < 0) + return TEST_FAILED; + + if (test_bitops_clear_relaxed() < 0) + return TEST_FAILED; + + if (test_bitops_test_set_clear_relaxed() < 0) + return TEST_FAILED; + + + rte_eal_mp_remote_launch(test_bitops_set_clear, NULL, SKIP_MASTER); + __atomic_store_n(&synchro, 1, __ATOMIC_RELAXED); + rte_eal_mp_wait_lcore(); + __atomic_store_n(&synchro, 0, __ATOMIC_RELAXED); + + unsigned int i; + + for (i = 0; i < MAX_BITS_32; i++) + if (rte_get_bit32(i, &val32)) { + printf("Failed to set and clear bit on multi cores.\n"); + return TEST_FAILED; + } + + for (i = 0; i < MAX_BITS_64; i++) + if (rte_get_bit64(i, &val64)) { + printf("Failed to set and clear bit on multi cores.\n"); + return TEST_FAILED; + } + + /* + * Launch all slave lcores to do "rte_bitops_test_and_set_bitXX" + * respectively. + * Each lcore should have MAX_BITS_XX chances to check the target bit. + * If it's equal to 0, set it to 1 and "countXX (which is initialized + * to 0)" would be increased by one. If the target bit is 1, still set + * it to 1 and do nothing for "countXX". There would be only one lcore + * that finds the target bit is 0. + * If the final value of "countXX" is equal to MAX_BITS_XX, all slave + * lcores performed "rte_bitops_test_and_set_bitXX" correctly. + */ + __atomic_store_n(&count32, 0, __ATOMIC_RELAXED); + __atomic_store_n(&count64, 0, __ATOMIC_RELAXED); + + rte_eal_mp_remote_launch(test_bitops_test_set, NULL, SKIP_MASTER); + __atomic_store_n(&synchro, 1, __ATOMIC_RELAXED); + rte_eal_mp_wait_lcore(); + __atomic_store_n(&synchro, 0, __ATOMIC_RELAXED); + + if (__atomic_load_n(&count32, __ATOMIC_RELAXED) != MAX_BITS_32) { + printf("Failed to test and set on multi cores.\n"); + return TEST_FAILED; + } + if (__atomic_load_n(&count64, __ATOMIC_RELAXED) != MAX_BITS_64) { + printf("Failed to test and set on multi cores.\n"); + return TEST_FAILED; + } + + /* + * Launch all slave lcores to do "rte_bitops_test_and_clear_bitXX" + * respectively. + * Each lcore should have MAX_BITS_XX chances to check the target bit. + * If it's equal to 1, clear it to 0 and "countXX (which is initialized + * to 0)" would be increased by one. If the target bit is 0, still clear + * it to 0 and do nothing for "countXX". There would be only one lcore + * that finds the target bit is 1. + * If the final value of "countXX" is equal to MAX_BITS_XX, all slave + * lcores performed "rte_bitops_test_and_clear_bitXX" correctly. + */ + + __atomic_store_n(&count32, 0, __ATOMIC_RELAXED); + __atomic_store_n(&count64, 0, __ATOMIC_RELAXED); + + rte_eal_mp_remote_launch(test_bitops_test_clear, NULL, SKIP_MASTER); + __atomic_store_n(&synchro, 1, __ATOMIC_RELAXED); + rte_eal_mp_wait_lcore(); + __atomic_store_n(&synchro, 0, __ATOMIC_RELAXED); + + if (__atomic_load_n(&count32, __ATOMIC_RELAXED) != MAX_BITS_32) { + printf("Failed to test and clear on multi cores.\n"); + return TEST_FAILED; + } + if (__atomic_load_n(&count64, __ATOMIC_RELAXED) != MAX_BITS_64) { + printf("Failed to test and clear on multi cores.\n"); + return TEST_FAILED; + } + + return TEST_SUCCESS; +} + +REGISTER_TEST_COMMAND(bitops_autotest, test_bitops); From patchwork Wed Nov 20 10:12:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joyce Kong X-Patchwork-Id: 63157 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 60349A04C1; Wed, 20 Nov 2019 11:12:52 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 920971BE89; Wed, 20 Nov 2019 11:12:38 +0100 (CET) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by dpdk.org (Postfix) with ESMTP id 37AC01BE86 for ; Wed, 20 Nov 2019 11:12:37 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9A284101E; Wed, 20 Nov 2019 02:12:36 -0800 (PST) Received: from net-arm-thunderx2-01.test.ast.arm.com (net-arm-thunderx2-01.shanghai.arm.com [10.169.40.40]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id E955F3F52E; Wed, 20 Nov 2019 02:12:32 -0800 (PST) From: Joyce Kong To: dev@dpdk.org Cc: nd@arm.com, thomas@monjalon.net, jerinj@marvell.com, stephen@networkplumber.org, mb@smartsharesystems.com, david.marchand@redhat.com, honnappa.nagarahalli@arm.com, gavin.hu@arm.com, ravi1.kumar@amd.com, rmody@marvell.com, shshaikh@marvell.com, xuanziyang2@huawei.com, cloud.wangxiaoyun@huawei.com, zhouguoyang@huawei.com Date: Wed, 20 Nov 2019 18:12:04 +0800 Message-Id: <1574244727-6003-4-git-send-email-joyce.kong@arm.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1574244727-6003-1-git-send-email-joyce.kong@arm.com> References: <1574244727-6003-1-git-send-email-joyce.kong@arm.com> In-Reply-To: <1571125801-45773-1-git-send-email-joyce.kong@arm.com> References: <1571125801-45773-1-git-send-email-joyce.kong@arm.com> Subject: [dpdk-dev] [PATCH v4 3/6] net/axgbe: use common rte bit operation APIs instead X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Remove its own bit operation APIs and use the common one, this can reduce the code duplication largely. Signed-off-by: Joyce Kong Reviewed-by: Gavin Hu --- drivers/net/axgbe/axgbe_common.h | 29 +---------------------------- drivers/net/axgbe/axgbe_ethdev.c | 14 +++++++------- drivers/net/axgbe/axgbe_mdio.c | 14 +++++++------- 3 files changed, 15 insertions(+), 42 deletions(-) diff --git a/drivers/net/axgbe/axgbe_common.h b/drivers/net/axgbe/axgbe_common.h index 34f60f1..9cabda8 100644 --- a/drivers/net/axgbe/axgbe_common.h +++ b/drivers/net/axgbe/axgbe_common.h @@ -22,6 +22,7 @@ #include #include +#include #include #include #include @@ -1674,34 +1675,6 @@ do { \ #define time_after_eq(a, b) ((long)((a) - (b)) >= 0) #define time_before_eq(a, b) time_after_eq(b, a) -/*---bitmap support apis---*/ -static inline int axgbe_test_bit(int nr, volatile unsigned long *addr) -{ - int res; - - rte_mb(); - res = ((*addr) & (1UL << nr)) != 0; - rte_mb(); - return res; -} - -static inline void axgbe_set_bit(unsigned int nr, volatile unsigned long *addr) -{ - __sync_fetch_and_or(addr, (1UL << nr)); -} - -static inline void axgbe_clear_bit(int nr, volatile unsigned long *addr) -{ - __sync_fetch_and_and(addr, ~(1UL << nr)); -} - -static inline int axgbe_test_and_clear_bit(int nr, volatile unsigned long *addr) -{ - unsigned long mask = (1UL << nr); - - return __sync_fetch_and_and(addr, ~mask) & mask; -} - static inline unsigned long msecs_to_timer_cycles(unsigned int m) { return rte_get_timer_hz() * (m / 1000); diff --git a/drivers/net/axgbe/axgbe_ethdev.c b/drivers/net/axgbe/axgbe_ethdev.c index d1f160e..fa597f3 100644 --- a/drivers/net/axgbe/axgbe_ethdev.c +++ b/drivers/net/axgbe/axgbe_ethdev.c @@ -201,8 +201,8 @@ axgbe_dev_start(struct rte_eth_dev *dev) axgbe_dev_enable_tx(dev); axgbe_dev_enable_rx(dev); - axgbe_clear_bit(AXGBE_STOPPED, &pdata->dev_state); - axgbe_clear_bit(AXGBE_DOWN, &pdata->dev_state); + rte_clear_bit64(AXGBE_STOPPED, &pdata->dev_state); + rte_clear_bit64(AXGBE_DOWN, &pdata->dev_state); return 0; } @@ -216,17 +216,17 @@ axgbe_dev_stop(struct rte_eth_dev *dev) rte_intr_disable(&pdata->pci_dev->intr_handle); - if (axgbe_test_bit(AXGBE_STOPPED, &pdata->dev_state)) + if (rte_get_bit64(AXGBE_STOPPED, &pdata->dev_state)) return; - axgbe_set_bit(AXGBE_STOPPED, &pdata->dev_state); + rte_set_bit64(AXGBE_STOPPED, &pdata->dev_state); axgbe_dev_disable_tx(dev); axgbe_dev_disable_rx(dev); pdata->phy_if.phy_stop(pdata); pdata->hw_if.exit(pdata); memset(&dev->data->dev_link, 0, sizeof(struct rte_eth_link)); - axgbe_set_bit(AXGBE_DOWN, &pdata->dev_state); + rte_set_bit64(AXGBE_DOWN, &pdata->dev_state); } /* Clear all resources like TX/RX queues. */ @@ -598,8 +598,8 @@ eth_axgbe_dev_init(struct rte_eth_dev *eth_dev) pdata = eth_dev->data->dev_private; /* initial state */ - axgbe_set_bit(AXGBE_DOWN, &pdata->dev_state); - axgbe_set_bit(AXGBE_STOPPED, &pdata->dev_state); + rte_set_bit64(AXGBE_DOWN, &pdata->dev_state); + rte_set_bit64(AXGBE_STOPPED, &pdata->dev_state); pdata->eth_dev = eth_dev; pci_dev = RTE_DEV_TO_PCI(eth_dev->device); diff --git a/drivers/net/axgbe/axgbe_mdio.c b/drivers/net/axgbe/axgbe_mdio.c index 2721e5c..00394a7 100644 --- a/drivers/net/axgbe/axgbe_mdio.c +++ b/drivers/net/axgbe/axgbe_mdio.c @@ -743,7 +743,7 @@ static int __axgbe_phy_config_aneg(struct axgbe_port *pdata) { int ret; - axgbe_set_bit(AXGBE_LINK_INIT, &pdata->dev_state); + rte_set_bit64(AXGBE_LINK_INIT, &pdata->dev_state); pdata->link_check = rte_get_timer_cycles(); ret = pdata->phy_if.phy_impl.an_config(pdata); @@ -807,9 +807,9 @@ static int axgbe_phy_config_aneg(struct axgbe_port *pdata) ret = __axgbe_phy_config_aneg(pdata); if (ret) - axgbe_set_bit(AXGBE_LINK_ERR, &pdata->dev_state); + rte_set_bit64(AXGBE_LINK_ERR, &pdata->dev_state); else - axgbe_clear_bit(AXGBE_LINK_ERR, &pdata->dev_state); + rte_clear_bit64(AXGBE_LINK_ERR, &pdata->dev_state); pthread_mutex_unlock(&pdata->an_mutex); @@ -880,7 +880,7 @@ static void axgbe_phy_status(struct axgbe_port *pdata) unsigned int link_aneg; int an_restart; - if (axgbe_test_bit(AXGBE_LINK_ERR, &pdata->dev_state)) { + if (rte_get_bit64(AXGBE_LINK_ERR, &pdata->dev_state)) { pdata->phy.link = 0; goto adjust_link; } @@ -900,10 +900,10 @@ static void axgbe_phy_status(struct axgbe_port *pdata) return; } axgbe_phy_status_result(pdata); - if (axgbe_test_bit(AXGBE_LINK_INIT, &pdata->dev_state)) - axgbe_clear_bit(AXGBE_LINK_INIT, &pdata->dev_state); + if (rte_get_bit64(AXGBE_LINK_INIT, &pdata->dev_state)) + rte_clear_bit64(AXGBE_LINK_INIT, &pdata->dev_state); } else { - if (axgbe_test_bit(AXGBE_LINK_INIT, &pdata->dev_state)) { + if (rte_get_bit64(AXGBE_LINK_INIT, &pdata->dev_state)) { axgbe_check_link_timeout(pdata); if (link_aneg) From patchwork Wed Nov 20 10:12:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joyce Kong X-Patchwork-Id: 63158 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0D570A04C1; Wed, 20 Nov 2019 11:13:02 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id CB2EA5F13; Wed, 20 Nov 2019 11:12:43 +0100 (CET) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by dpdk.org (Postfix) with ESMTP id 267D02BA3 for ; Wed, 20 Nov 2019 11:12:42 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A82A331B; Wed, 20 Nov 2019 02:12:41 -0800 (PST) Received: from net-arm-thunderx2-01.test.ast.arm.com (net-arm-thunderx2-01.shanghai.arm.com [10.169.40.40]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 39FB23F52E; Wed, 20 Nov 2019 02:12:36 -0800 (PST) From: Joyce Kong To: dev@dpdk.org Cc: nd@arm.com, thomas@monjalon.net, jerinj@marvell.com, stephen@networkplumber.org, mb@smartsharesystems.com, david.marchand@redhat.com, honnappa.nagarahalli@arm.com, gavin.hu@arm.com, ravi1.kumar@amd.com, rmody@marvell.com, shshaikh@marvell.com, xuanziyang2@huawei.com, cloud.wangxiaoyun@huawei.com, zhouguoyang@huawei.com Date: Wed, 20 Nov 2019 18:12:05 +0800 Message-Id: <1574244727-6003-5-git-send-email-joyce.kong@arm.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1574244727-6003-1-git-send-email-joyce.kong@arm.com> References: <1574244727-6003-1-git-send-email-joyce.kong@arm.com> In-Reply-To: <1571125801-45773-1-git-send-email-joyce.kong@arm.com> References: <1571125801-45773-1-git-send-email-joyce.kong@arm.com> Subject: [dpdk-dev] [PATCH v4 4/6] net/bnx2x: use common rte bit operation APIs instead X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Remove its own bit operation APIs and use the common one, this can reduce the code duplication largely. Signed-off-by: Joyce Kong Reviewed-by: Gavin Hu --- drivers/net/bnx2x/bnx2x.c | 209 +++++++++++++++++++------------------------ drivers/net/bnx2x/bnx2x.h | 4 - drivers/net/bnx2x/ecore_sp.h | 9 +- 3 files changed, 98 insertions(+), 124 deletions(-) diff --git a/drivers/net/bnx2x/bnx2x.c b/drivers/net/bnx2x/bnx2x.c index ed31335..1c00a67 100644 --- a/drivers/net/bnx2x/bnx2x.c +++ b/drivers/net/bnx2x/bnx2x.c @@ -26,6 +26,7 @@ #include #include #include +#include #define BNX2X_PMD_VER_PREFIX "BNX2X PMD" #define BNX2X_PMD_VERSION_MAJOR 1 @@ -129,32 +130,6 @@ static void bnx2x_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id, uint8_t storm, uint16_t index, uint8_t op, uint8_t update); -int bnx2x_test_bit(int nr, volatile unsigned long *addr) -{ - int res; - - mb(); - res = ((*addr) & (1UL << nr)) != 0; - mb(); - return res; -} - -void bnx2x_set_bit(unsigned int nr, volatile unsigned long *addr) -{ - __sync_fetch_and_or(addr, (1UL << nr)); -} - -void bnx2x_clear_bit(int nr, volatile unsigned long *addr) -{ - __sync_fetch_and_and(addr, ~(1UL << nr)); -} - -int bnx2x_test_and_clear_bit(int nr, volatile unsigned long *addr) -{ - unsigned long mask = (1UL << nr); - return __sync_fetch_and_and(addr, ~mask) & mask; -} - int bnx2x_cmpxchg(volatile int *addr, int old, int new) { return __sync_val_compare_and_swap(addr, old, new); @@ -1427,11 +1402,11 @@ bnx2x_del_all_macs(struct bnx2x_softc *sc, struct ecore_vlan_mac_obj *mac_obj, /* wait for completion of requested */ if (wait_for_comp) { - bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags); + rte_set_bit64(RAMROD_COMP_WAIT, &ramrod_flags); } /* Set the mac type of addresses we want to clear */ - bnx2x_set_bit(mac_type, &vlan_mac_flags); + rte_set_bit64(mac_type, &vlan_mac_flags); rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags); if (rc < 0) @@ -1458,26 +1433,26 @@ bnx2x_fill_accept_flags(struct bnx2x_softc *sc, uint32_t rx_mode, break; case BNX2X_RX_MODE_NORMAL: - bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags); - bnx2x_set_bit(ECORE_ACCEPT_MULTICAST, rx_accept_flags); - bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags); + rte_set_bit64(ECORE_ACCEPT_UNICAST, rx_accept_flags); + rte_set_bit64(ECORE_ACCEPT_MULTICAST, rx_accept_flags); + rte_set_bit64(ECORE_ACCEPT_BROADCAST, rx_accept_flags); /* internal switching mode */ - bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags); - bnx2x_set_bit(ECORE_ACCEPT_MULTICAST, tx_accept_flags); - bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags); + rte_set_bit64(ECORE_ACCEPT_UNICAST, tx_accept_flags); + rte_set_bit64(ECORE_ACCEPT_MULTICAST, tx_accept_flags); + rte_set_bit64(ECORE_ACCEPT_BROADCAST, tx_accept_flags); break; case BNX2X_RX_MODE_ALLMULTI: - bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags); - bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags); - bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags); + rte_set_bit64(ECORE_ACCEPT_UNICAST, rx_accept_flags); + rte_set_bit64(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags); + rte_set_bit64(ECORE_ACCEPT_BROADCAST, rx_accept_flags); /* internal switching mode */ - bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags); - bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags); - bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags); + rte_set_bit64(ECORE_ACCEPT_UNICAST, tx_accept_flags); + rte_set_bit64(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags); + rte_set_bit64(ECORE_ACCEPT_BROADCAST, tx_accept_flags); break; @@ -1488,19 +1463,20 @@ bnx2x_fill_accept_flags(struct bnx2x_softc *sc, uint32_t rx_mode, * should receive matched and unmatched (in resolution of port) * unicast packets. */ - bnx2x_set_bit(ECORE_ACCEPT_UNMATCHED, rx_accept_flags); - bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags); - bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags); - bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags); + rte_set_bit64(ECORE_ACCEPT_UNMATCHED, rx_accept_flags); + rte_set_bit64(ECORE_ACCEPT_UNICAST, rx_accept_flags); + rte_set_bit64(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags); + rte_set_bit64(ECORE_ACCEPT_BROADCAST, rx_accept_flags); /* internal switching mode */ - bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags); - bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags); + rte_set_bit64(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags); + rte_set_bit64(ECORE_ACCEPT_BROADCAST, tx_accept_flags); if (IS_MF_SI(sc)) { - bnx2x_set_bit(ECORE_ACCEPT_ALL_UNICAST, tx_accept_flags); + rte_set_bit64(ECORE_ACCEPT_ALL_UNICAST, + tx_accept_flags); } else { - bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags); + rte_set_bit64(ECORE_ACCEPT_UNICAST, tx_accept_flags); } break; @@ -1512,8 +1488,8 @@ bnx2x_fill_accept_flags(struct bnx2x_softc *sc, uint32_t rx_mode, /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */ if (rx_mode != BNX2X_RX_MODE_NONE) { - bnx2x_set_bit(ECORE_ACCEPT_ANY_VLAN, rx_accept_flags); - bnx2x_set_bit(ECORE_ACCEPT_ANY_VLAN, tx_accept_flags); + rte_set_bit64(ECORE_ACCEPT_ANY_VLAN, rx_accept_flags); + rte_set_bit64(ECORE_ACCEPT_ANY_VLAN, tx_accept_flags); } return 0; @@ -1542,7 +1518,7 @@ bnx2x_set_q_rx_mode(struct bnx2x_softc *sc, uint8_t cl_id, ramrod_param.rdata = BNX2X_SP(sc, rx_mode_rdata); ramrod_param.rdata_mapping = (rte_iova_t)BNX2X_SP_MAPPING(sc, rx_mode_rdata), - bnx2x_set_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state); + rte_set_bit64(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state); ramrod_param.ramrod_flags = ramrod_flags; ramrod_param.rx_mode_flags = rx_mode_flags; @@ -1571,9 +1547,9 @@ int bnx2x_set_storm_rx_mode(struct bnx2x_softc *sc) return rc; } - bnx2x_set_bit(RAMROD_RX, &ramrod_flags); - bnx2x_set_bit(RAMROD_TX, &ramrod_flags); - bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags); + rte_set_bit64(RAMROD_RX, &ramrod_flags); + rte_set_bit64(RAMROD_TX, &ramrod_flags); + rte_set_bit64(RAMROD_COMP_WAIT, &ramrod_flags); return bnx2x_set_q_rx_mode(sc, sc->fp[0].cl_id, rx_mode_flags, rx_accept_flags, tx_accept_flags, @@ -1698,7 +1674,7 @@ static int bnx2x_func_wait_started(struct bnx2x_softc *sc) "Forcing STARTED-->TX_STOPPED-->STARTED"); func_params.f_obj = &sc->func_obj; - bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags); + rte_set_bit64(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags); /* STARTED-->TX_STOPPED */ func_params.cmd = ECORE_F_CMD_TX_STOP; @@ -1722,7 +1698,7 @@ static int bnx2x_stop_queue(struct bnx2x_softc *sc, int index) q_params.q_obj = &sc->sp_objs[fp->index].q_obj; /* We want to wait for completion in this context */ - bnx2x_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); + rte_set_bit64(RAMROD_COMP_WAIT, &q_params.ramrod_flags); /* Stop the primary connection: */ @@ -1783,7 +1759,7 @@ static int bnx2x_func_stop(struct bnx2x_softc *sc) int rc; /* prepare parameters for function state transitions */ - bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); + rte_set_bit64(RAMROD_COMP_WAIT, &func_params.ramrod_flags); func_params.f_obj = &sc->func_obj; func_params.cmd = ECORE_F_CMD_STOP; @@ -1797,7 +1773,7 @@ static int bnx2x_func_stop(struct bnx2x_softc *sc) if (rc) { PMD_DRV_LOG(NOTICE, sc, "FUNC_STOP ramrod failed. " "Running a dry transaction"); - bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags); + rte_set_bit64(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags); return ecore_func_state_change(sc, &func_params); } @@ -1809,7 +1785,7 @@ static int bnx2x_reset_hw(struct bnx2x_softc *sc, uint32_t load_code) struct ecore_func_state_params func_params = { NULL }; /* Prepare parameters for function state transitions */ - bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); + rte_set_bit64(RAMROD_COMP_WAIT, &func_params.ramrod_flags); func_params.f_obj = &sc->func_obj; func_params.cmd = ECORE_F_CMD_HW_RESET; @@ -1866,11 +1842,10 @@ bnx2x_chip_cleanup(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_li * a race between the completion code and this code. */ - if (bnx2x_test_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state)) { - bnx2x_set_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state); - } else { + if (rte_get_bit64(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state)) + rte_set_bit64(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state); + else bnx2x_set_storm_rx_mode(sc); - } /* Clean up multicast configuration */ rparam.mcast_obj = &sc->mcast_obj; @@ -1960,12 +1935,12 @@ static void bnx2x_squeeze_objects(struct bnx2x_softc *sc) /* Cleanup MACs' object first... */ /* Wait for completion of requested */ - bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags); + rte_set_bit64(RAMROD_COMP_WAIT, &ramrod_flags); /* Perform a dry cleanup */ - bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &ramrod_flags); + rte_set_bit64(RAMROD_DRV_CLR_ONLY, &ramrod_flags); /* Clean ETH primary MAC */ - bnx2x_set_bit(ECORE_ETH_MAC, &vlan_mac_flags); + rte_set_bit64(ECORE_ETH_MAC, &vlan_mac_flags); rc = mac_obj->delete_all(sc, &sc->sp_objs->mac_obj, &vlan_mac_flags, &ramrod_flags); if (rc != 0) { @@ -1974,7 +1949,7 @@ static void bnx2x_squeeze_objects(struct bnx2x_softc *sc) /* Cleanup UC list */ vlan_mac_flags = 0; - bnx2x_set_bit(ECORE_UC_LIST_MAC, &vlan_mac_flags); + rte_set_bit64(ECORE_UC_LIST_MAC, &vlan_mac_flags); rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags); if (rc != 0) { PMD_DRV_LOG(NOTICE, sc, @@ -1984,7 +1959,7 @@ static void bnx2x_squeeze_objects(struct bnx2x_softc *sc) /* Now clean mcast object... */ rparam.mcast_obj = &sc->mcast_obj; - bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &rparam.ramrod_flags); + rte_set_bit64(RAMROD_DRV_CLR_ONLY, &rparam.ramrod_flags); /* Add a DEL command... */ rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL); @@ -4288,7 +4263,7 @@ bnx2x_handle_classification_eqe(struct bnx2x_softc *sc, union event_ring_elem *e struct ecore_vlan_mac_obj *vlan_mac_obj; /* always push next commands out, don't wait here */ - bnx2x_set_bit(RAMROD_CONT, &ramrod_flags); + rte_set_bit64(RAMROD_CONT, &ramrod_flags); switch (le32toh(elem->message.data.eth_event.echo) >> BNX2X_SWCID_SHIFT) { case ECORE_FILTER_MAC_PENDING: @@ -4319,12 +4294,12 @@ bnx2x_handle_classification_eqe(struct bnx2x_softc *sc, union event_ring_elem *e static void bnx2x_handle_rx_mode_eqe(struct bnx2x_softc *sc) { - bnx2x_clear_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state); + rte_clear_bit64(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state); /* send rx_mode command again if was requested */ - if (bnx2x_test_and_clear_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state)) { + if (rte_test_and_clear_bit64(ECORE_FILTER_RX_MODE_SCHED, + &sc->sp_state)) bnx2x_set_storm_rx_mode(sc); - } } static void bnx2x_update_eq_prod(struct bnx2x_softc *sc, uint16_t prod) @@ -4693,7 +4668,7 @@ static int bnx2x_init_hw(struct bnx2x_softc *sc, uint32_t load_code) PMD_INIT_FUNC_TRACE(sc); /* prepare the parameters for function state transitions */ - bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); + rte_set_bit64(RAMROD_COMP_WAIT, &func_params.ramrod_flags); func_params.f_obj = &sc->func_obj; func_params.cmd = ECORE_F_CMD_HW_INIT; @@ -4988,8 +4963,8 @@ static void bnx2x_init_eth_fp(struct bnx2x_softc *sc, int idx) bnx2x_update_fp_sb_idx(fp); /* Configure Queue State object */ - bnx2x_set_bit(ECORE_Q_TYPE_HAS_RX, &q_type); - bnx2x_set_bit(ECORE_Q_TYPE_HAS_TX, &q_type); + rte_set_bit64(ECORE_Q_TYPE_HAS_RX, &q_type); + rte_set_bit64(ECORE_Q_TYPE_HAS_TX, &q_type); ecore_init_queue_obj(sc, &sc->sp_objs[idx].q_obj, @@ -5803,7 +5778,7 @@ static int bnx2x_func_start(struct bnx2x_softc *sc) &func_params.params.start; /* Prepare parameters for function state transitions */ - bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); + rte_set_bit64(RAMROD_COMP_WAIT, &func_params.ramrod_flags); func_params.f_obj = &sc->func_obj; func_params.cmd = ECORE_F_CMD_START; @@ -6379,11 +6354,11 @@ bnx2x_pf_q_prep_init(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp, uint8_t cos; int cxt_index, cxt_offset; - bnx2x_set_bit(ECORE_Q_FLG_HC, &init_params->rx.flags); - bnx2x_set_bit(ECORE_Q_FLG_HC, &init_params->tx.flags); + rte_set_bit64(ECORE_Q_FLG_HC, &init_params->rx.flags); + rte_set_bit64(ECORE_Q_FLG_HC, &init_params->tx.flags); - bnx2x_set_bit(ECORE_Q_FLG_HC_EN, &init_params->rx.flags); - bnx2x_set_bit(ECORE_Q_FLG_HC_EN, &init_params->tx.flags); + rte_set_bit64(ECORE_Q_FLG_HC_EN, &init_params->rx.flags); + rte_set_bit64(ECORE_Q_FLG_HC_EN, &init_params->tx.flags); /* HC rate */ init_params->rx.hc_rate = @@ -6417,7 +6392,7 @@ bnx2x_get_common_flags(struct bnx2x_softc *sc, uint8_t zero_stats) unsigned long flags = 0; /* PF driver will always initialize the Queue to an ACTIVE state */ - bnx2x_set_bit(ECORE_Q_FLG_ACTIVE, &flags); + rte_set_bit64(ECORE_Q_FLG_ACTIVE, &flags); /* * tx only connections collect statistics (on the same index as the @@ -6425,9 +6400,9 @@ bnx2x_get_common_flags(struct bnx2x_softc *sc, uint8_t zero_stats) * connection is initialized. */ - bnx2x_set_bit(ECORE_Q_FLG_STATS, &flags); + rte_set_bit64(ECORE_Q_FLG_STATS, &flags); if (zero_stats) { - bnx2x_set_bit(ECORE_Q_FLG_ZERO_STATS, &flags); + rte_set_bit64(ECORE_Q_FLG_ZERO_STATS, &flags); } /* @@ -6435,10 +6410,10 @@ bnx2x_get_common_flags(struct bnx2x_softc *sc, uint8_t zero_stats) * CoS-ness doesn't survive the loopback */ if (sc->flags & BNX2X_TX_SWITCHING) { - bnx2x_set_bit(ECORE_Q_FLG_TX_SWITCH, &flags); + rte_set_bit64(ECORE_Q_FLG_TX_SWITCH, &flags); } - bnx2x_set_bit(ECORE_Q_FLG_PCSUM_ON_PKT, &flags); + rte_set_bit64(ECORE_Q_FLG_PCSUM_ON_PKT, &flags); return flags; } @@ -6448,15 +6423,15 @@ static unsigned long bnx2x_get_q_flags(struct bnx2x_softc *sc, uint8_t leading) unsigned long flags = 0; if (IS_MF_SD(sc)) { - bnx2x_set_bit(ECORE_Q_FLG_OV, &flags); + rte_set_bit64(ECORE_Q_FLG_OV, &flags); } if (leading) { - bnx2x_set_bit(ECORE_Q_FLG_LEADING_RSS, &flags); - bnx2x_set_bit(ECORE_Q_FLG_MCAST, &flags); + rte_set_bit64(ECORE_Q_FLG_LEADING_RSS, &flags); + rte_set_bit64(ECORE_Q_FLG_MCAST, &flags); } - bnx2x_set_bit(ECORE_Q_FLG_VLAN, &flags); + rte_set_bit64(ECORE_Q_FLG_VLAN, &flags); /* merge with common flags */ return flags | bnx2x_get_common_flags(sc, TRUE); @@ -6577,7 +6552,7 @@ bnx2x_setup_queue(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp, uint8_t lea q_params.q_obj = &BNX2X_SP_OBJ(sc, fp).q_obj; /* we want to wait for completion in this context */ - bnx2x_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); + rte_set_bit64(RAMROD_COMP_WAIT, &q_params.ramrod_flags); /* prepare the INIT parameters */ bnx2x_pf_q_prep_init(sc, fp, &q_params.params.init); @@ -6645,20 +6620,20 @@ bnx2x_config_rss_pf(struct bnx2x_softc *sc, struct ecore_rss_config_obj *rss_obj params.rss_obj = rss_obj; - bnx2x_set_bit(RAMROD_COMP_WAIT, ¶ms.ramrod_flags); + rte_set_bit64(RAMROD_COMP_WAIT, ¶ms.ramrod_flags); - bnx2x_set_bit(ECORE_RSS_MODE_REGULAR, ¶ms.rss_flags); + rte_set_bit64(ECORE_RSS_MODE_REGULAR, ¶ms.rss_flags); /* RSS configuration */ - bnx2x_set_bit(ECORE_RSS_IPV4, ¶ms.rss_flags); - bnx2x_set_bit(ECORE_RSS_IPV4_TCP, ¶ms.rss_flags); - bnx2x_set_bit(ECORE_RSS_IPV6, ¶ms.rss_flags); - bnx2x_set_bit(ECORE_RSS_IPV6_TCP, ¶ms.rss_flags); + rte_set_bit64(ECORE_RSS_IPV4, ¶ms.rss_flags); + rte_set_bit64(ECORE_RSS_IPV4_TCP, ¶ms.rss_flags); + rte_set_bit64(ECORE_RSS_IPV6, ¶ms.rss_flags); + rte_set_bit64(ECORE_RSS_IPV6_TCP, ¶ms.rss_flags); if (rss_obj->udp_rss_v4) { - bnx2x_set_bit(ECORE_RSS_IPV4_UDP, ¶ms.rss_flags); + rte_set_bit64(ECORE_RSS_IPV4_UDP, ¶ms.rss_flags); } if (rss_obj->udp_rss_v6) { - bnx2x_set_bit(ECORE_RSS_IPV6_UDP, ¶ms.rss_flags); + rte_set_bit64(ECORE_RSS_IPV6_UDP, ¶ms.rss_flags); } /* Hash bits */ @@ -6673,7 +6648,7 @@ bnx2x_config_rss_pf(struct bnx2x_softc *sc, struct ecore_rss_config_obj *rss_obj params.rss_key[i] = (uint32_t) rte_rand(); } - bnx2x_set_bit(ECORE_RSS_SET_SRCH, ¶ms.rss_flags); + rte_set_bit64(ECORE_RSS_SET_SRCH, ¶ms.rss_flags); } if (IS_PF(sc)) @@ -6730,11 +6705,11 @@ bnx2x_set_mac_one(struct bnx2x_softc *sc, uint8_t * mac, ramrod_param.ramrod_flags = *ramrod_flags; /* fill a user request section if needed */ - if (!bnx2x_test_bit(RAMROD_CONT, ramrod_flags)) { + if (!rte_get_bit64(RAMROD_CONT, ramrod_flags)) { rte_memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN); - bnx2x_set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags); + rte_set_bit64(mac_type, &ramrod_param.user_req.vlan_mac_flags); /* Set the command: ADD or DEL */ ramrod_param.user_req.cmd = (set) ? ECORE_VLAN_MAC_ADD : @@ -6761,7 +6736,7 @@ static int bnx2x_set_eth_mac(struct bnx2x_softc *sc, uint8_t set) PMD_DRV_LOG(DEBUG, sc, "Adding Ethernet MAC"); - bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags); + rte_set_bit64(RAMROD_COMP_WAIT, &ramrod_flags); /* Eth MAC is set on RSS leading client (fp[0]) */ return bnx2x_set_mac_one(sc, sc->link_params.mac_addr, @@ -6893,24 +6868,26 @@ bnx2x_fill_report_data(struct bnx2x_softc *sc, struct bnx2x_link_report_data *da /* Link is down */ if (!sc->link_vars.link_up || (sc->flags & BNX2X_MF_FUNC_DIS)) { - bnx2x_set_bit(BNX2X_LINK_REPORT_LINK_DOWN, + rte_set_bit64(BNX2X_LINK_REPORT_LINK_DOWN, &data->link_report_flags); } /* Full DUPLEX */ if (sc->link_vars.duplex == DUPLEX_FULL) { - bnx2x_set_bit(BNX2X_LINK_REPORT_FULL_DUPLEX, + rte_set_bit64(BNX2X_LINK_REPORT_FULL_DUPLEX, &data->link_report_flags); } /* Rx Flow Control is ON */ if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_RX) { - bnx2x_set_bit(BNX2X_LINK_REPORT_RX_FC_ON, &data->link_report_flags); + rte_set_bit64(BNX2X_LINK_REPORT_RX_FC_ON, + &data->link_report_flags); } /* Tx Flow Control is ON */ if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) { - bnx2x_set_bit(BNX2X_LINK_REPORT_TX_FC_ON, &data->link_report_flags); + rte_set_bit64(BNX2X_LINK_REPORT_TX_FC_ON, + &data->link_report_flags); } } @@ -6929,9 +6906,9 @@ static void bnx2x_link_report_locked(struct bnx2x_softc *sc) /* Don't report link down or exactly the same link status twice */ if (!memcmp(&cur_data, &sc->last_reported_link, sizeof(cur_data)) || - (bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN, + (rte_get_bit64(BNX2X_LINK_REPORT_LINK_DOWN, &sc->last_reported_link.link_report_flags) && - bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN, + rte_get_bit64(BNX2X_LINK_REPORT_LINK_DOWN, &cur_data.link_report_flags))) { return; } @@ -6946,14 +6923,14 @@ static void bnx2x_link_report_locked(struct bnx2x_softc *sc) /* report new link params and remember the state for the next time */ rte_memcpy(&sc->last_reported_link, &cur_data, sizeof(cur_data)); - if (bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN, + if (rte_get_bit64(BNX2X_LINK_REPORT_LINK_DOWN, &cur_data.link_report_flags)) { ELINK_DEBUG_P0(sc, "NIC Link is Down"); } else { __rte_unused const char *duplex; __rte_unused const char *flow; - if (bnx2x_test_and_clear_bit(BNX2X_LINK_REPORT_FULL_DUPLEX, + if (rte_test_and_clear_bit64(BNX2X_LINK_REPORT_FULL_DUPLEX, &cur_data.link_report_flags)) { duplex = "full"; ELINK_DEBUG_P0(sc, "link set to full duplex"); @@ -6968,19 +6945,19 @@ static void bnx2x_link_report_locked(struct bnx2x_softc *sc) * enabled. */ if (cur_data.link_report_flags) { - if (bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON, + if (rte_get_bit64(BNX2X_LINK_REPORT_RX_FC_ON, &cur_data.link_report_flags) && - bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON, + rte_get_bit64(BNX2X_LINK_REPORT_TX_FC_ON, &cur_data.link_report_flags)) { flow = "ON - receive & transmit"; - } else if (bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON, + } else if (rte_get_bit64(BNX2X_LINK_REPORT_RX_FC_ON, &cur_data.link_report_flags) && - !bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON, + !rte_get_bit64(BNX2X_LINK_REPORT_TX_FC_ON, &cur_data.link_report_flags)) { flow = "ON - receive"; - } else if (!bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON, + } else if (!rte_get_bit64(BNX2X_LINK_REPORT_RX_FC_ON, &cur_data.link_report_flags) && - bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON, + rte_get_bit64(BNX2X_LINK_REPORT_TX_FC_ON, &cur_data.link_report_flags)) { flow = "ON - transmit"; } else { diff --git a/drivers/net/bnx2x/bnx2x.h b/drivers/net/bnx2x/bnx2x.h index 3383c76..e6e66e8 100644 --- a/drivers/net/bnx2x/bnx2x.h +++ b/drivers/net/bnx2x/bnx2x.h @@ -1809,10 +1809,6 @@ static const uint32_t dmae_reg_go_c[] = { #define PCI_PM_D0 1 #define PCI_PM_D3hot 2 -int bnx2x_test_bit(int nr, volatile unsigned long * addr); -void bnx2x_set_bit(unsigned int nr, volatile unsigned long * addr); -void bnx2x_clear_bit(int nr, volatile unsigned long * addr); -int bnx2x_test_and_clear_bit(int nr, volatile unsigned long * addr); int bnx2x_cmpxchg(volatile int *addr, int old, int new); int bnx2x_dma_alloc(struct bnx2x_softc *sc, size_t size, diff --git a/drivers/net/bnx2x/ecore_sp.h b/drivers/net/bnx2x/ecore_sp.h index cc1db37..efbfdad 100644 --- a/drivers/net/bnx2x/ecore_sp.h +++ b/drivers/net/bnx2x/ecore_sp.h @@ -15,6 +15,7 @@ #define ECORE_SP_H #include +#include #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN #ifndef __LITTLE_ENDIAN @@ -73,10 +74,10 @@ typedef rte_spinlock_t ECORE_MUTEX_SPIN; #define ECORE_SET_BIT_NA(bit, var) (*var |= (1 << bit)) #define ECORE_CLEAR_BIT_NA(bit, var) (*var &= ~(1 << bit)) -#define ECORE_TEST_BIT(bit, var) bnx2x_test_bit(bit, var) -#define ECORE_SET_BIT(bit, var) bnx2x_set_bit(bit, var) -#define ECORE_CLEAR_BIT(bit, var) bnx2x_clear_bit(bit, var) -#define ECORE_TEST_AND_CLEAR_BIT(bit, var) bnx2x_test_and_clear_bit(bit, var) +#define ECORE_TEST_BIT(bit, var) rte_get_bit64(bit, var) +#define ECORE_SET_BIT(bit, var) rte_set_bit64(bit, var) +#define ECORE_CLEAR_BIT(bit, var) rte_clear_bit64(bit, var) +#define ECORE_TEST_AND_CLEAR_BIT(bit, var) rte_test_and_clear_bit64(bit, var) #define atomic_load_acq_int (int)* #define atomic_store_rel_int(a, v) (*a = v) From patchwork Wed Nov 20 10:12:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joyce Kong X-Patchwork-Id: 63159 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9BD01A04C1; Wed, 20 Nov 2019 11:13:13 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id C7BDC1BDAC; Wed, 20 Nov 2019 11:12:48 +0100 (CET) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by dpdk.org (Postfix) with ESMTP id EB5F51BE96 for ; Wed, 20 Nov 2019 11:12:46 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 631A1101E; Wed, 20 Nov 2019 02:12:46 -0800 (PST) Received: from net-arm-thunderx2-01.test.ast.arm.com (net-arm-thunderx2-01.shanghai.arm.com [10.169.40.40]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 216AD3F52E; Wed, 20 Nov 2019 02:12:41 -0800 (PST) From: Joyce Kong To: dev@dpdk.org Cc: nd@arm.com, thomas@monjalon.net, jerinj@marvell.com, stephen@networkplumber.org, mb@smartsharesystems.com, david.marchand@redhat.com, honnappa.nagarahalli@arm.com, gavin.hu@arm.com, ravi1.kumar@amd.com, rmody@marvell.com, shshaikh@marvell.com, xuanziyang2@huawei.com, cloud.wangxiaoyun@huawei.com, zhouguoyang@huawei.com Date: Wed, 20 Nov 2019 18:12:06 +0800 Message-Id: <1574244727-6003-6-git-send-email-joyce.kong@arm.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1574244727-6003-1-git-send-email-joyce.kong@arm.com> References: <1574244727-6003-1-git-send-email-joyce.kong@arm.com> In-Reply-To: <1571125801-45773-1-git-send-email-joyce.kong@arm.com> References: <1571125801-45773-1-git-send-email-joyce.kong@arm.com> Subject: [dpdk-dev] [PATCH v4 5/6] net/qede: use common rte bit operation APIs instead X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Remove its own bit operation APIs and use the common one, this can reduce the code duplication largely. Signed-off-by: Joyce Kong Reviewed-by: Gavin Hu --- drivers/net/qede/base/bcm_osal.c | 20 -------------------- drivers/net/qede/base/bcm_osal.h | 10 ++++------ 2 files changed, 4 insertions(+), 26 deletions(-) diff --git a/drivers/net/qede/base/bcm_osal.c b/drivers/net/qede/base/bcm_osal.c index 48d016e..19457d7 100644 --- a/drivers/net/qede/base/bcm_osal.c +++ b/drivers/net/qede/base/bcm_osal.c @@ -46,26 +46,6 @@ u32 qede_osal_log2(u32 val) return log; } -inline void qede_set_bit(u32 nr, unsigned long *addr) -{ - __sync_fetch_and_or(addr, (1UL << nr)); -} - -inline void qede_clr_bit(u32 nr, unsigned long *addr) -{ - __sync_fetch_and_and(addr, ~(1UL << nr)); -} - -inline bool qede_test_bit(u32 nr, unsigned long *addr) -{ - bool res; - - rte_mb(); - res = ((*addr) & (1UL << nr)) != 0; - rte_mb(); - return res; -} - static inline u32 qede_ffb(unsigned long word) { unsigned long first_bit; diff --git a/drivers/net/qede/base/bcm_osal.h b/drivers/net/qede/base/bcm_osal.h index 0f09557..e7a7392 100644 --- a/drivers/net/qede/base/bcm_osal.h +++ b/drivers/net/qede/base/bcm_osal.h @@ -8,6 +8,7 @@ #define __BCM_OSAL_H #include +#include #include #include #include @@ -311,17 +312,14 @@ typedef struct osal_list_t { #define OSAL_BITS_PER_UL_MASK (OSAL_BITS_PER_UL - 1) /* Bitops */ -void qede_set_bit(u32, unsigned long *); #define OSAL_SET_BIT(bit, bitmap) \ - qede_set_bit(bit, bitmap) + rte_set_bit64(bit, bitmap) -void qede_clr_bit(u32, unsigned long *); #define OSAL_CLEAR_BIT(bit, bitmap) \ - qede_clr_bit(bit, bitmap) + rte_clear_bit64(bit, bitmap) -bool qede_test_bit(u32, unsigned long *); #define OSAL_TEST_BIT(bit, bitmap) \ - qede_test_bit(bit, bitmap) + rte_get_bit64(bit, bitmap) u32 qede_find_first_bit(unsigned long *, u32); #define OSAL_FIND_FIRST_BIT(bitmap, length) \ From patchwork Wed Nov 20 10:12:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joyce Kong X-Patchwork-Id: 63160 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5B193A04C1; Wed, 20 Nov 2019 11:13:22 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 124901BEA4; Wed, 20 Nov 2019 11:12:53 +0100 (CET) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by dpdk.org (Postfix) with ESMTP id 0932F1BE95 for ; Wed, 20 Nov 2019 11:12:51 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 87B491045; Wed, 20 Nov 2019 02:12:50 -0800 (PST) Received: from net-arm-thunderx2-01.test.ast.arm.com (net-arm-thunderx2-01.shanghai.arm.com [10.169.40.40]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id CC3143F52E; Wed, 20 Nov 2019 02:12:46 -0800 (PST) From: Joyce Kong To: dev@dpdk.org Cc: nd@arm.com, thomas@monjalon.net, jerinj@marvell.com, stephen@networkplumber.org, mb@smartsharesystems.com, david.marchand@redhat.com, honnappa.nagarahalli@arm.com, gavin.hu@arm.com, ravi1.kumar@amd.com, rmody@marvell.com, shshaikh@marvell.com, xuanziyang2@huawei.com, cloud.wangxiaoyun@huawei.com, zhouguoyang@huawei.com Date: Wed, 20 Nov 2019 18:12:07 +0800 Message-Id: <1574244727-6003-7-git-send-email-joyce.kong@arm.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1574244727-6003-1-git-send-email-joyce.kong@arm.com> References: <1574244727-6003-1-git-send-email-joyce.kong@arm.com> In-Reply-To: <1571125801-45773-1-git-send-email-joyce.kong@arm.com> References: <1571125801-45773-1-git-send-email-joyce.kong@arm.com> Subject: [dpdk-dev] [PATCH v4 6/6] net/hinic: use common rte bit operation APIs instead X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Remove its own bit operation APIs and use the common one, this can reduce the code duplication largely. Signed-off-by: Joyce Kong Reviewed-by: Gavin Hu --- drivers/net/hinic/Makefile | 1 + drivers/net/hinic/base/hinic_compat.h | 33 +-------------------------------- drivers/net/hinic/hinic_pmd_ethdev.c | 16 ++++++++-------- drivers/net/hinic/meson.build | 2 ++ 4 files changed, 12 insertions(+), 40 deletions(-) diff --git a/drivers/net/hinic/Makefile b/drivers/net/hinic/Makefile index b78fd8d..97f4298 100644 --- a/drivers/net/hinic/Makefile +++ b/drivers/net/hinic/Makefile @@ -9,6 +9,7 @@ include $(RTE_SDK)/mk/rte.vars.mk LIB = librte_pmd_hinic.a CFLAGS += -O3 +CFLAGS += -DALLOW_EXPERIMENTAL_API CFLAGS += $(WERROR_FLAGS) ifeq ($(CONFIG_RTE_ARCH_ARM64),y) diff --git a/drivers/net/hinic/base/hinic_compat.h b/drivers/net/hinic/base/hinic_compat.h index e4a7f12..c0a0b3e 100644 --- a/drivers/net/hinic/base/hinic_compat.h +++ b/drivers/net/hinic/base/hinic_compat.h @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -117,38 +118,6 @@ extern int hinic_logtype; #define HINIC_PAGE_SIZE_DPDK 6 -static inline int hinic_test_bit(int nr, volatile unsigned long *addr) -{ - int res; - - res = ((*addr) & (1UL << nr)) != 0; - return res; -} - -static inline void hinic_set_bit(unsigned int nr, volatile unsigned long *addr) -{ - __sync_fetch_and_or(addr, (1UL << nr)); -} - -static inline void hinic_clear_bit(int nr, volatile unsigned long *addr) -{ - __sync_fetch_and_and(addr, ~(1UL << nr)); -} - -static inline int hinic_test_and_clear_bit(int nr, volatile unsigned long *addr) -{ - unsigned long mask = (1UL << nr); - - return __sync_fetch_and_and(addr, ~mask) & mask; -} - -static inline int hinic_test_and_set_bit(int nr, volatile unsigned long *addr) -{ - unsigned long mask = (1UL << nr); - - return __sync_fetch_and_or(addr, mask) & mask; -} - void *dma_zalloc_coherent(void *dev, size_t size, dma_addr_t *dma_handle, gfp_t flag); void *dma_zalloc_coherent_aligned(void *dev, size_t size, diff --git a/drivers/net/hinic/hinic_pmd_ethdev.c b/drivers/net/hinic/hinic_pmd_ethdev.c index 072fec3..8181564 100644 --- a/drivers/net/hinic/hinic_pmd_ethdev.c +++ b/drivers/net/hinic/hinic_pmd_ethdev.c @@ -269,7 +269,7 @@ static void hinic_dev_interrupt_handler(void *param) struct rte_eth_dev *dev = param; struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); - if (!hinic_test_bit(HINIC_DEV_INTR_EN, &nic_dev->dev_status)) { + if (!rte_get_bit64(HINIC_DEV_INTR_EN, &nic_dev->dev_status)) { PMD_DRV_LOG(WARNING, "Device's interrupt is disabled, ignore interrupt event, dev_name: %s, port_id: %d", nic_dev->proc_dev_name, dev->data->port_id); return; @@ -1075,7 +1075,7 @@ static int hinic_dev_start(struct rte_eth_dev *dev) if (dev->data->dev_conf.intr_conf.lsc != 0) (void)hinic_link_update(dev, 0); - hinic_set_bit(HINIC_DEV_START, &nic_dev->dev_status); + rte_set_bit64(HINIC_DEV_START, &nic_dev->dev_status); return 0; @@ -1200,7 +1200,7 @@ static void hinic_dev_stop(struct rte_eth_dev *dev) name = dev->data->name; port_id = dev->data->port_id; - if (!hinic_test_and_clear_bit(HINIC_DEV_START, &nic_dev->dev_status)) { + if (!rte_test_and_clear_bit64(HINIC_DEV_START, &nic_dev->dev_status)) { PMD_DRV_LOG(INFO, "Device %s already stopped", name); return; } @@ -1245,7 +1245,7 @@ static void hinic_disable_interrupt(struct rte_eth_dev *dev) struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); int ret, retries = 0; - hinic_clear_bit(HINIC_DEV_INTR_EN, &nic_dev->dev_status); + rte_clear_bit64(HINIC_DEV_INTR_EN, &nic_dev->dev_status); /* disable msix interrupt in hardware */ hinic_set_msix_state(nic_dev->hwdev, 0, HINIC_MSIX_DISABLE); @@ -2844,7 +2844,7 @@ static void hinic_dev_close(struct rte_eth_dev *dev) { struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); - if (hinic_test_and_set_bit(HINIC_DEV_CLOSE, &nic_dev->dev_status)) { + if (rte_test_and_set_bit64(HINIC_DEV_CLOSE, &nic_dev->dev_status)) { PMD_DRV_LOG(WARNING, "Device %s already closed", dev->data->name); return; @@ -3045,7 +3045,7 @@ static int hinic_func_init(struct rte_eth_dev *eth_dev) eth_dev->data->name); goto enable_intr_fail; } - hinic_set_bit(HINIC_DEV_INTR_EN, &nic_dev->dev_status); + rte_set_bit64(HINIC_DEV_INTR_EN, &nic_dev->dev_status); /* initialize filter info */ filter_info = &nic_dev->filter; @@ -3057,7 +3057,7 @@ static int hinic_func_init(struct rte_eth_dev *eth_dev) TAILQ_INIT(&nic_dev->filter_fdir_rule_list); TAILQ_INIT(&nic_dev->hinic_flow_list); - hinic_set_bit(HINIC_DEV_INIT, &nic_dev->dev_status); + rte_set_bit64(HINIC_DEV_INIT, &nic_dev->dev_status); PMD_DRV_LOG(INFO, "Initialize %s in primary successfully", eth_dev->data->name); @@ -3113,7 +3113,7 @@ static int hinic_dev_uninit(struct rte_eth_dev *dev) struct hinic_nic_dev *nic_dev; nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); - hinic_clear_bit(HINIC_DEV_INIT, &nic_dev->dev_status); + rte_clear_bit64(HINIC_DEV_INIT, &nic_dev->dev_status); if (rte_eal_process_type() != RTE_PROC_PRIMARY) return 0; diff --git a/drivers/net/hinic/meson.build b/drivers/net/hinic/meson.build index bc7e246..8c7ee9d 100644 --- a/drivers/net/hinic/meson.build +++ b/drivers/net/hinic/meson.build @@ -1,6 +1,8 @@ # SPDX-License-Identifier: BSD-3-Clause # Copyright(c) 2017 Huawei Technologies Co., Ltd +allow_experimental_apis = true + subdir('base') objs = [base_objs]