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{
    "id": 57955,
    "url": "http://patches.dpdk.org/api/patches/57955/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190826105105.19121-60-qi.z.zhang@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20190826105105.19121-60-qi.z.zhang@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20190826105105.19121-60-qi.z.zhang@intel.com",
    "date": "2019-08-26T10:51:01",
    "name": "[59/63] net/ice/base: remove Rx flex descriptor programming",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "6fdc10fa2b6d63b22d75636fdb340c33572259bd",
    "submitter": {
        "id": 504,
        "url": "http://patches.dpdk.org/api/people/504/?format=api",
        "name": "Qi Zhang",
        "email": "qi.z.zhang@intel.com"
    },
    "delegate": {
        "id": 1540,
        "url": "http://patches.dpdk.org/api/users/1540/?format=api",
        "username": "qzhan15",
        "first_name": "Qi",
        "last_name": "Zhang",
        "email": "qi.z.zhang@intel.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190826105105.19121-60-qi.z.zhang@intel.com/mbox/",
    "series": [
        {
            "id": 6119,
            "url": "http://patches.dpdk.org/api/series/6119/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=6119",
            "date": "2019-08-26T10:50:02",
            "name": "net/ice/base: update base code",
            "version": 1,
            "mbox": "http://patches.dpdk.org/series/6119/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/57955/comments/",
    "check": "success",
    "checks": "http://patches.dpdk.org/api/patches/57955/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id B3F041C23A;\n\tMon, 26 Aug 2019 12:51:53 +0200 (CEST)",
            "from mga07.intel.com (mga07.intel.com [134.134.136.100])\n\tby dpdk.org (Postfix) with ESMTP id 5837D1C198\n\tfor <dev@dpdk.org>; Mon, 26 Aug 2019 12:50:13 +0200 (CEST)",
            "from orsmga003.jf.intel.com ([10.7.209.27])\n\tby orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t26 Aug 2019 03:50:12 -0700",
            "from dpdk51.sh.intel.com ([10.67.110.245])\n\tby orsmga003.jf.intel.com with ESMTP; 26 Aug 2019 03:50:11 -0700"
        ],
        "X-Amp-Result": "SKIPPED(no attachment in message)",
        "X-Amp-File-Uploaded": "False",
        "X-ExtLoop1": "1",
        "X-IronPort-AV": "E=Sophos;i=\"5.64,431,1559545200\"; d=\"scan'208\";a=\"182402636\"",
        "From": "Qi Zhang <qi.z.zhang@intel.com>",
        "To": "wenzhuo.lu@intel.com,\n\tqiming.yang@intel.com",
        "Cc": "dev@dpdk.org, xiaolong.ye@intel.com, Qi Zhang <qi.z.zhang@intel.com>,\n\tVignesh Sridhar <vignesh.sridhar@intel.com>,\n\tPaul M Stillwell Jr <paul.m.stillwell.jr@intel.com>",
        "Date": "Mon, 26 Aug 2019 18:51:01 +0800",
        "Message-Id": "<20190826105105.19121-60-qi.z.zhang@intel.com>",
        "X-Mailer": "git-send-email 2.13.6",
        "In-Reply-To": "<20190826105105.19121-1-qi.z.zhang@intel.com>",
        "References": "<20190826105105.19121-1-qi.z.zhang@intel.com>",
        "Subject": "[dpdk-dev] [PATCH 59/63] net/ice/base: remove Rx flex descriptor\n\tprogramming",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "Removing Rx flex descriptor metadata and flag programming from shared\ncode. As per HAS these registers cannot be written to as they are read\nonly. While non-secure NVMs allow write access to them, secure images\nwill not. The programming for all fields per RxDID is now handled in the\ncomms package.\n\nSigned-off-by: Vignesh Sridhar <vignesh.sridhar@intel.com>\nSigned-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\n---\n drivers/net/ice/base/ice_common.c | 195 --------------------------------------\n 1 file changed, 195 deletions(-)",
    "diff": "diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c\nindex d2f903329..11e902ea1 100644\n--- a/drivers/net/ice/base/ice_common.c\n+++ b/drivers/net/ice/base/ice_common.c\n@@ -11,35 +11,6 @@\n \n #define ICE_PF_RESET_WAIT_COUNT\t200\n \n-#define ICE_PROG_FLEX_ENTRY(hw, rxdid, mdid, idx) \\\n-\twr32((hw), GLFLXP_RXDID_FLX_WRD_##idx(rxdid), \\\n-\t     ((ICE_RX_OPC_MDID << \\\n-\t       GLFLXP_RXDID_FLX_WRD_##idx##_RXDID_OPCODE_S) & \\\n-\t      GLFLXP_RXDID_FLX_WRD_##idx##_RXDID_OPCODE_M) | \\\n-\t     (((mdid) << GLFLXP_RXDID_FLX_WRD_##idx##_PROT_MDID_S) & \\\n-\t      GLFLXP_RXDID_FLX_WRD_##idx##_PROT_MDID_M))\n-\n-#define ICE_PROG_FLEX_ENTRY_EXTRACT(hw, rxdid, protid, off, idx) \\\n-\twr32((hw), GLFLXP_RXDID_FLX_WRD_##idx(rxdid), \\\n-\t     ((ICE_RX_OPC_EXTRACT << \\\n-\t       GLFLXP_RXDID_FLX_WRD_##idx##_RXDID_OPCODE_S) & \\\n-\t      GLFLXP_RXDID_FLX_WRD_##idx##_RXDID_OPCODE_M) | \\\n-\t     (((protid) << GLFLXP_RXDID_FLX_WRD_##idx##_PROT_MDID_S) & \\\n-\t      GLFLXP_RXDID_FLX_WRD_##idx##_PROT_MDID_M) | \\\n-\t     (((off) << GLFLXP_RXDID_FLX_WRD_##idx##_EXTRACTION_OFFSET_S) & \\\n-\t      GLFLXP_RXDID_FLX_WRD_##idx##_EXTRACTION_OFFSET_M))\n-\n-#define ICE_PROG_FLG_ENTRY(hw, rxdid, flg_0, flg_1, flg_2, flg_3, idx) \\\n-\twr32((hw), GLFLXP_RXDID_FLAGS(rxdid, idx), \\\n-\t     (((flg_0) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_S) & \\\n-\t      GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_M) | \\\n-\t     (((flg_1) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_1_S) & \\\n-\t      GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_1_M) | \\\n-\t     (((flg_2) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_2_S) & \\\n-\t      GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_2_M) | \\\n-\t     (((flg_3) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_3_S) & \\\n-\t      GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_3_M))\n-\n \n /**\n  * ice_set_mac_type - Sets MAC type\n@@ -431,163 +402,6 @@ ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,\n }\n \n /**\n- * ice_init_flex_flags\n- * @hw: pointer to the hardware structure\n- * @prof_id: Rx Descriptor Builder profile ID\n- *\n- * Function to initialize Rx flex flags\n- */\n-static void ice_init_flex_flags(struct ice_hw *hw, enum ice_rxdid prof_id)\n-{\n-\tu8 idx = 0;\n-\n-\t/* Flex-flag fields (0-2) are programmed with FLG64 bits with layout:\n-\t * flexiflags0[5:0] - TCP flags, is_packet_fragmented, is_packet_UDP_GRE\n-\t * flexiflags1[3:0] - Not used for flag programming\n-\t * flexiflags2[7:0] - Tunnel and VLAN types\n-\t * 2 invalid fields in last index\n-\t */\n-\tswitch (prof_id) {\n-\t/* Rx flex flags are currently programmed for the NIC profiles only.\n-\t * Different flag bit programming configurations can be added per\n-\t * profile as needed.\n-\t */\n-\tcase ICE_RXDID_FLEX_NIC:\n-\tcase ICE_RXDID_FLEX_NIC_2:\n-\t\tICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_PKT_FRG,\n-\t\t\t\t   ICE_FLG_UDP_GRE, ICE_FLG_PKT_DSI,\n-\t\t\t\t   ICE_FLG_FIN, idx++);\n-\t\t/* flex flag 1 is not used for flexi-flag programming, skipping\n-\t\t * these four FLG64 bits.\n-\t\t */\n-\t\tICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_SYN, ICE_FLG_RST,\n-\t\t\t\t   ICE_FLG_PKT_DSI, ICE_FLG_PKT_DSI, idx++);\n-\t\tICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_PKT_DSI,\n-\t\t\t\t   ICE_FLG_PKT_DSI, ICE_FLG_EVLAN_x8100,\n-\t\t\t\t   ICE_FLG_EVLAN_x9100, idx++);\n-\t\tICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_VLAN_x8100,\n-\t\t\t\t   ICE_FLG_TNL_VLAN, ICE_FLG_TNL_MAC,\n-\t\t\t\t   ICE_FLG_TNL0, idx++);\n-\t\tICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_TNL1, ICE_FLG_TNL2,\n-\t\t\t\t   ICE_FLG_PKT_DSI, ICE_FLG_PKT_DSI, idx);\n-\t\tbreak;\n-\n-\tdefault:\n-\t\tice_debug(hw, ICE_DBG_INIT,\n-\t\t\t  \"Flag programming for profile ID %d not supported\\n\",\n-\t\t\t  prof_id);\n-\t}\n-}\n-\n-/**\n- * ice_init_flex_flds\n- * @hw: pointer to the hardware structure\n- * @prof_id: Rx Descriptor Builder profile ID\n- *\n- * Function to initialize flex descriptors\n- */\n-static void ice_init_flex_flds(struct ice_hw *hw, enum ice_rxdid prof_id)\n-{\n-\tenum ice_prot_id protid_0, protid_1;\n-\tu16 offset_0, offset_1;\n-\tenum ice_flex_mdid mdid;\n-\n-\tswitch (prof_id) {\n-\tcase ICE_RXDID_FLEX_NIC:\n-\tcase ICE_RXDID_FLEX_NIC_2:\n-\t\tICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_MDID_RX_HASH_LOW, 0);\n-\t\tICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_MDID_RX_HASH_HIGH, 1);\n-\t\tICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_MDID_FLOW_ID_LOWER, 2);\n-\n-\t\tmdid = (prof_id == ICE_RXDID_FLEX_NIC_2) ?\n-\t\t\tICE_MDID_SRC_VSI : ICE_MDID_FLOW_ID_HIGH;\n-\n-\t\tICE_PROG_FLEX_ENTRY(hw, prof_id, mdid, 3);\n-\n-\t\tice_init_flex_flags(hw, prof_id);\n-\t\tbreak;\n-\tcase ICE_RXDID_COMMS_GENERIC:\n-\tcase ICE_RXDID_COMMS_AUX_VLAN:\n-\tcase ICE_RXDID_COMMS_AUX_IPV4:\n-\tcase ICE_RXDID_COMMS_AUX_IPV6:\n-\tcase ICE_RXDID_COMMS_AUX_IPV6_FLOW:\n-\tcase ICE_RXDID_COMMS_AUX_TCP:\n-\t\tICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_MDID_RX_HASH_LOW, 0);\n-\t\tICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_MDID_RX_HASH_HIGH, 1);\n-\t\tICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_MDID_FLOW_ID_LOWER, 2);\n-\t\tICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_MDID_FLOW_ID_HIGH, 3);\n-\n-\t\tif (prof_id == ICE_RXDID_COMMS_AUX_VLAN) {\n-\t\t\t/* FlexiMD.4: VLAN1 - single or EVLAN (first for QinQ).\n-\t\t\t * FlexiMD.5: VLAN2 - C-VLAN (second for QinQ).\n-\t\t\t */\n-\t\t\tprotid_0 = ICE_PROT_EVLAN_O;\n-\t\t\toffset_0 = 0;\n-\t\t\tprotid_1 = ICE_PROT_VLAN_O;\n-\t\t\toffset_1 = 0;\n-\t\t} else if (prof_id == ICE_RXDID_COMMS_AUX_IPV4) {\n-\t\t\t/* FlexiMD.4: IPHDR1 - IPv4 header word 4, \"TTL\" and\n-\t\t\t * \"Protocol\" fields.\n-\t\t\t * FlexiMD.5: IPHDR0 - IPv4 header word 0, \"Ver\",\n-\t\t\t * \"Hdr Len\" and \"Type of Service\" fields.\n-\t\t\t */\n-\t\t\tprotid_0 = ICE_PROT_IPV4_OF_OR_S;\n-\t\t\toffset_0 = 8;\n-\t\t\tprotid_1 = ICE_PROT_IPV4_OF_OR_S;\n-\t\t\toffset_1 = 0;\n-\t\t} else if (prof_id == ICE_RXDID_COMMS_AUX_IPV6) {\n-\t\t\t/* FlexiMD.4: IPHDR1 - IPv6 header word 3,\n-\t\t\t * \"Next Header\" and \"Hop Limit\" fields.\n-\t\t\t * FlexiMD.5: IPHDR0 - IPv6 header word 0,\n-\t\t\t * \"Ver\", \"Traffic class\" and high 4 bits of\n-\t\t\t * \"Flow Label\" fields.\n-\t\t\t */\n-\t\t\tprotid_0 = ICE_PROT_IPV6_OF_OR_S;\n-\t\t\toffset_0 = 6;\n-\t\t\tprotid_1 = ICE_PROT_IPV6_OF_OR_S;\n-\t\t\toffset_1 = 0;\n-\t\t} else if (prof_id == ICE_RXDID_COMMS_AUX_IPV6_FLOW) {\n-\t\t\t/* FlexiMD.4: IPHDR1 - IPv6 header word 1,\n-\t\t\t * 16 low bits of the \"Flow Label\" field.\n-\t\t\t * FlexiMD.5: IPHDR0 - IPv6 header word 0,\n-\t\t\t * \"Ver\", \"Traffic class\" and high 4 bits\n-\t\t\t * of \"Flow Label\" fields.\n-\t\t\t */\n-\t\t\tprotid_0 = ICE_PROT_IPV6_OF_OR_S;\n-\t\t\toffset_0 = 2;\n-\t\t\tprotid_1 = ICE_PROT_IPV6_OF_OR_S;\n-\t\t\toffset_1 = 0;\n-\t\t} else if (prof_id == ICE_RXDID_COMMS_AUX_TCP) {\n-\t\t\t/* FlexiMD.4: TCPHDR - TCP header word 6,\n-\t\t\t * \"Data Offset\" and \"Flags\" fields.\n-\t\t\t * FlexiMD.5: Reserved\n-\t\t\t */\n-\t\t\tprotid_0 = ICE_PROT_TCP_IL;\n-\t\t\toffset_0 = 12;\n-\t\t\tprotid_1 = ICE_PROT_ID_INVAL;\n-\t\t\toffset_1 = 0;\n-\t\t} else {\n-\t\t\tprotid_0 = ICE_PROT_ID_INVAL;\n-\t\t\toffset_0 = 0;\n-\t\t\tprotid_1 = ICE_PROT_ID_INVAL;\n-\t\t\toffset_1 = 0;\n-\t\t}\n-\n-\t\tICE_PROG_FLEX_ENTRY_EXTRACT(hw, prof_id,\n-\t\t\t\t\t    protid_0, offset_0, 4);\n-\t\tICE_PROG_FLEX_ENTRY_EXTRACT(hw, prof_id,\n-\t\t\t\t\t    protid_1, offset_1, 5);\n-\n-\t\tice_init_flex_flags(hw, prof_id);\n-\t\tbreak;\n-\tdefault:\n-\t\tice_debug(hw, ICE_DBG_INIT,\n-\t\t\t  \"Field init for profile ID %d not supported\\n\",\n-\t\t\t  prof_id);\n-\t}\n-}\n-\n-/**\n  * ice_aq_set_mac_cfg\n  * @hw: pointer to the HW struct\n  * @max_frame_size: Maximum Frame Size to be supported\n@@ -928,15 +742,6 @@ enum ice_status ice_init_hw(struct ice_hw *hw)\n \n \tif (status)\n \t\tgoto err_unroll_fltr_mgmt_struct;\n-\n-\tice_init_flex_flds(hw, ICE_RXDID_FLEX_NIC);\n-\tice_init_flex_flds(hw, ICE_RXDID_FLEX_NIC_2);\n-\tice_init_flex_flds(hw, ICE_RXDID_COMMS_GENERIC);\n-\tice_init_flex_flds(hw, ICE_RXDID_COMMS_AUX_VLAN);\n-\tice_init_flex_flds(hw, ICE_RXDID_COMMS_AUX_IPV4);\n-\tice_init_flex_flds(hw, ICE_RXDID_COMMS_AUX_IPV6);\n-\tice_init_flex_flds(hw, ICE_RXDID_COMMS_AUX_IPV6_FLOW);\n-\tice_init_flex_flds(hw, ICE_RXDID_COMMS_AUX_TCP);\n \t/* Obtain counter base index which would be used by flow director */\n \tstatus = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base);\n \tif (status)\n",
    "prefixes": [
        "59/63"
    ]
}