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GET /api/patches/45667/?format=api
{ "id": 45667, "url": "http://patches.dpdk.org/api/patches/45667/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/c1b0a43ddce496e900aaea3e80d6695204d9b2f2.1538215990.git.igor.russkikh@aquantia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<c1b0a43ddce496e900aaea3e80d6695204d9b2f2.1538215990.git.igor.russkikh@aquantia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/c1b0a43ddce496e900aaea3e80d6695204d9b2f2.1538215990.git.igor.russkikh@aquantia.com", "date": "2018-09-29T10:30:17", "name": "[v3,03/22] net/atlantic: hardware register access routines", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "18d66df46d5689fb6e99388aa13bbd1aa1e30319", "submitter": { "id": 1124, "url": "http://patches.dpdk.org/api/people/1124/?format=api", "name": "Igor Russkikh", "email": "igor.russkikh@aquantia.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/c1b0a43ddce496e900aaea3e80d6695204d9b2f2.1538215990.git.igor.russkikh@aquantia.com/mbox/", "series": [ { "id": 1598, "url": "http://patches.dpdk.org/api/series/1598/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=1598", "date": "2018-09-29T10:30:14", "name": "net/atlantic: Aquantia aQtion 10G NIC Family DPDK PMD driver", "version": 3, "mbox": "http://patches.dpdk.org/series/1598/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/45667/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/45667/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 382B21B14F;\n\tSat, 29 Sep 2018 12:31:19 +0200 (CEST)", "from NAM05-DM3-obe.outbound.protection.outlook.com\n\t(mail-eopbgr730082.outbound.protection.outlook.com [40.107.73.82])\n\tby dpdk.org (Postfix) with ESMTP id 8BB8E1B114\n\tfor <dev@dpdk.org>; Sat, 29 Sep 2018 12:31:17 +0200 (CEST)", "from ubuntubox.rdc.aquantia.com (95.79.108.179) by\n\tBLUPR0701MB1650.namprd07.prod.outlook.com (2a01:111:e400:58c6::20)\n\twith Microsoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1185.22;\n\tSat, 29 Sep 2018 10:31:10 +0000" ], "DKIM-Signature": "v=1; a=rsa-sha256; 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"o3GXdy2jfx6ltqaxFyIMNwDR2WTRhMeEawAbJ2XbCWOJoWNkvZCfKbGdK+/MozLeYtO9VkcPvgBtnLsDw1GeLGa6o/Jkgum46Pg58njJQqTqOLxF+fratzimd1W9VVM8+kT8DBtBU0A77HtqJZzEF5ChhB//7AL3UI9Uopzra0B7E+U16vwSmKnhHz0QUpyQl8dwdh/aQnwSNQb/b3FrwgR2JX3Ak+vHnbw2dX4/p1Qwd+tcs3sYgnc7rLiOK7WKvfAogmfbiaTi1fhVC0F2UHoQvB/MARRkZa9m3DjcanPNUXttzgmArcke0AsE2oRRRadgm4m06PoEP8PDC5jOjvvFQbfmTS7+ZrJ3P2Na3Ag=", "SpamDiagnosticOutput": "1:99", "SpamDiagnosticMetadata": "NSPM", "X-OriginatorOrg": "aquantia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "29 Sep 2018 10:31:10.0928\n\t(UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "c31c9dfd-e273-4e39-d367-08d625f6afd5", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "83e2e134-991c-4ede-8ced-34d47e38e6b1", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BLUPR0701MB1650", "Subject": "[dpdk-dev] [PATCH v3 03/22] net/atlantic: hardware register access\n\troutines", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Signed-off-by: Igor Russkikh <igor.russkikh@aquantia.com>\nSigned-off-by: Pavel Belous <Pavel.Belous@aquantia.com>\n---\n drivers/net/atlantic/Makefile | 1 +\n drivers/net/atlantic/atl_hw_regs.c | 52 +++++++++++++++++++++++++++++++++++++\n drivers/net/atlantic/atl_hw_regs.h | 53 ++++++++++++++++++++++++++++++++++++++\n drivers/net/atlantic/atl_types.h | 4 +++\n drivers/net/atlantic/meson.build | 1 +\n 5 files changed, 111 insertions(+)\n create mode 100644 drivers/net/atlantic/atl_hw_regs.c\n create mode 100644 drivers/net/atlantic/atl_hw_regs.h", "diff": "diff --git a/drivers/net/atlantic/Makefile b/drivers/net/atlantic/Makefile\nindex e42ce5b178ab..8613ced71732 100644\n--- a/drivers/net/atlantic/Makefile\n+++ b/drivers/net/atlantic/Makefile\n@@ -23,5 +23,6 @@ LDLIBS += -lrte_bus_pci\n # all source are stored in SRCS-y\n #\n SRCS-$(CONFIG_RTE_LIBRTE_ATLANTIC_PMD) += atl_ethdev.c\n+SRCS-$(CONFIG_RTE_LIBRTE_ATLANTIC_PMD) += atl_hw_regs.c\n \n include $(RTE_SDK)/mk/rte.lib.mk\ndiff --git a/drivers/net/atlantic/atl_hw_regs.c b/drivers/net/atlantic/atl_hw_regs.c\nnew file mode 100644\nindex 000000000000..bd42c8341e2b\n--- /dev/null\n+++ b/drivers/net/atlantic/atl_hw_regs.c\n@@ -0,0 +1,52 @@\n+// SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)\n+/* Copyright (C) 2014-2017 aQuantia Corporation. */\n+\n+/* File aq_hw_utils.c: Definitions of helper functions used across\n+ * hardware layer.\n+ */\n+\n+#include \"atl_hw_regs.h\"\n+\n+#include <rte_io.h>\n+#include <rte_byteorder.h>\n+\n+void aq_hw_write_reg_bit(struct aq_hw_s *aq_hw, u32 addr, u32 msk,\n+\t\t\t u32 shift, u32 val)\n+{\n+\tif (msk ^ ~0) {\n+\t\tu32 reg_old, reg_new;\n+\n+\t\treg_old = aq_hw_read_reg(aq_hw, addr);\n+\t\treg_new = (reg_old & (~msk)) | (val << shift);\n+\n+\t\tif (reg_old != reg_new)\n+\t\t\taq_hw_write_reg(aq_hw, addr, reg_new);\n+\t} else {\n+\t\taq_hw_write_reg(aq_hw, addr, val);\n+\t}\n+}\n+\n+u32 aq_hw_read_reg_bit(struct aq_hw_s *aq_hw, u32 addr, u32 msk, u32 shift)\n+{\n+\treturn ((aq_hw_read_reg(aq_hw, addr) & msk) >> shift);\n+}\n+\n+u32 aq_hw_read_reg(struct aq_hw_s *hw, u32 reg)\n+{\n+\treturn rte_le_to_cpu_32(rte_read32((u8 *)hw->mmio + reg));\n+}\n+\n+void aq_hw_write_reg(struct aq_hw_s *hw, u32 reg, u32 value)\n+{\n+\trte_write32((rte_cpu_to_le_32(value)), (u8 *)hw->mmio + reg);\n+}\n+\n+int aq_hw_err_from_flags(struct aq_hw_s *hw)\n+{\n+\tint err = 0;\n+\n+\tif (aq_hw_read_reg(hw, 0x10U) == ~0U)\n+\t\treturn -ENXIO;\n+\n+\treturn err;\n+}\ndiff --git a/drivers/net/atlantic/atl_hw_regs.h b/drivers/net/atlantic/atl_hw_regs.h\nnew file mode 100644\nindex 000000000000..a2d6ca804e5e\n--- /dev/null\n+++ b/drivers/net/atlantic/atl_hw_regs.h\n@@ -0,0 +1,53 @@\n+/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) */\n+/* Copyright (C) 2014-2017 aQuantia Corporation. */\n+\n+/* File aq_hw_utils.h: Declaration of helper functions used across hardware\n+ * layer.\n+ */\n+\n+#ifndef AQ_HW_UTILS_H\n+#define AQ_HW_UTILS_H\n+\n+#include <rte_common.h>\n+#include <rte_io.h>\n+#include <rte_byteorder.h>\n+#include <rte_random.h>\n+#include <rte_cycles.h>\n+#include \"atl_common.h\"\n+#include \"atl_types.h\"\n+\n+\n+#ifndef HIDWORD\n+#define LODWORD(_qw) ((u32)(_qw))\n+#define HIDWORD(_qw) ((u32)(((_qw) >> 32) & 0xffffffff))\n+#endif\n+\n+#define AQ_HW_SLEEP(_US_) rte_delay_ms(_US_)\n+\n+#define mdelay rte_delay_ms\n+#define udelay rte_delay_us\n+#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))\n+#define BIT(x)\t(1UL << (x))\n+\n+#define AQ_HW_WAIT_FOR(_B_, _US_, _N_) \\\n+do { \\\n+\tunsigned int AQ_HW_WAIT_FOR_i; \\\n+\tfor (AQ_HW_WAIT_FOR_i = _N_; (!(_B_)) && (AQ_HW_WAIT_FOR_i);\\\n+\t--AQ_HW_WAIT_FOR_i) {\\\n+\t\tudelay(_US_); \\\n+\t} \\\n+\tif (!AQ_HW_WAIT_FOR_i) {\\\n+\t\terr = -ETIMEDOUT; \\\n+\t} \\\n+} while (0)\n+\n+#define ATL_WRITE_FLUSH(aq_hw) { (void)aq_hw_read_reg(aq_hw, 0x10); }\n+\n+void aq_hw_write_reg_bit(struct aq_hw_s *aq_hw, u32 addr, u32 msk,\n+\t\t\t u32 shift, u32 val);\n+u32 aq_hw_read_reg_bit(struct aq_hw_s *aq_hw, u32 addr, u32 msk, u32 shift);\n+u32 aq_hw_read_reg(struct aq_hw_s *hw, u32 reg);\n+void aq_hw_write_reg(struct aq_hw_s *hw, u32 reg, u32 value);\n+int aq_hw_err_from_flags(struct aq_hw_s *hw);\n+\n+#endif /* AQ_HW_UTILS_H */\ndiff --git a/drivers/net/atlantic/atl_types.h b/drivers/net/atlantic/atl_types.h\nindex 5a14c2506477..83fb377add47 100644\n--- a/drivers/net/atlantic/atl_types.h\n+++ b/drivers/net/atlantic/atl_types.h\n@@ -28,4 +28,8 @@ typedef int\t\tbool;\n #define min(a, b)\tRTE_MIN(a, b)\n #define max(a, b)\tRTE_MAX(a, b)\n \n+struct aq_hw_s {\n+\tvoid *mmio;\n+};\n+\n #endif\ndiff --git a/drivers/net/atlantic/meson.build b/drivers/net/atlantic/meson.build\nindex 90ee5288206a..7fdde358ba21 100644\n--- a/drivers/net/atlantic/meson.build\n+++ b/drivers/net/atlantic/meson.build\n@@ -3,6 +3,7 @@\n \n sources = files(\n \t'atl_ethdev.c',\n+\t'atl_hw_regs.c',\n )\n \n deps += ['eal']\n", "prefixes": [ "v3", "03/22" ] }