From patchwork Sat Sep 29 10:30:15 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Russkikh X-Patchwork-Id: 45665 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 1B2B31B123; Sat, 29 Sep 2018 12:31:07 +0200 (CEST) Received: from NAM05-DM3-obe.outbound.protection.outlook.com (mail-eopbgr730079.outbound.protection.outlook.com [40.107.73.79]) by dpdk.org (Postfix) with ESMTP id CF4BD1B123 for ; Sat, 29 Sep 2018 12:31:04 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=AQUANTIA1COM.onmicrosoft.com; s=selector1-aquantia-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=DI49s/ddsnQeo62Zwz2ipQONKT41YuWBwLXmKXtB5Oo=; b=YVdd7NwcpEAWBfXHBMLw9MgM3Em8YaXTqSpWwwpsIIifsM83FFjDVrHcQAOSYxxoW01Rt0YXwdFOJ3XW5pU87y/jBEqhaAiv22FbHrtHZmaxl2gCRsLeH9fXoyE8fnjua3TExKcY7/FYznJWa6qQItQVWlGPsAkLW8g5WOj4I2A= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Igor.Russkikh@aquantia.com; Received: from ubuntubox.rdc.aquantia.com (95.79.108.179) by BLUPR0701MB1650.namprd07.prod.outlook.com (2a01:111:e400:58c6::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1185.22; Sat, 29 Sep 2018 10:30:56 +0000 From: Igor Russkikh To: dev@dpdk.org Cc: pavel.belous@aquantia.com, igor.russkikh@aquantia.com, Pavel Belous Date: Sat, 29 Sep 2018 13:30:15 +0300 Message-Id: X-Mailer: git-send-email 2.7.4 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [95.79.108.179] X-ClientProxiedBy: VI1P193CA0009.EURP193.PROD.OUTLOOK.COM (2603:10a6:800:bd::19) To BLUPR0701MB1650.namprd07.prod.outlook.com (2a01:111:e400:58c6::20) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 2d15b29a-2620-4c8e-7812-08d625f6a7f9 X-Microsoft-Antispam: BCL:0; PCL:0; RULEID:(7020095)(4652040)(8989299)(4534165)(4627221)(201703031133081)(201702281549075)(8990200)(5600074)(711020)(2017052603328)(7153060)(7193020); SRVR:BLUPR0701MB1650; X-Microsoft-Exchange-Diagnostics: 1; BLUPR0701MB1650; 3:8wjR65/NTsXjvtMuZo2og4atH3wEzdebBFzVh7CmjQuoGetI4NxpQvTlRiRR/7NjzD70hXjRBUhrxxAAun3EhE94HULJ9JRvJ39rj1rmaJLrtKDIm5ExYodVouLixD3rcvrO/ofQpIYYtqZk6+2ik2Fc7S60wdS2IFjdDKOlohJh9y3MvHfzynwfjALHPdnhQL+ozNvEwkivKbF4+7wKm/ICY4VzaVMzmRseRMQQtENWz6pgsZPJFnuNsfl7mHQM; 25:MLo82J3oy8gXsjcAZbZjsc8FNfKUFSJrvixgiWZkkNIQMNmrUfXLeOXH+hBQ1GPs0PtFFuSIcN6uA15qDvL9ALfsf/dUJX8MQmVbaws4FGgGirPKDto2ydfwvHr6FYaRVDIZdq14CfAkjwWjnnyCpK23lIN/NoTYbec2XvvNBcoBs+joZ2TjHF3eU0ANBhJePhRAaLjr9YL/DBYDBvrZj3EJugpMx1wAyPi4lcVrjFEiGfzMoOEcyB9Ik1S8sNlh1NpKarsOoOSvPCAXS1Sty+1cGtVQCIExE25IvFHVVhdyXn8GocJStTuBwdRaC2zui6OWP+mzohi6k4jv/5xzrCiINwj44dOmi9nXM3sbULY=; 31:8EVt2qQxoofHQbwj9/kvdZQEeLfXM2s3HAKtmiMPtcfZAKKNIrG+y2sYKldxsLO3NKZgLqHQikVNGKuAXr6ior3BggAZ6Za7xUKE16/JShA4lzEBpfjaEQW848CuhdacYqTpelvUbO+NxoCd4n4W+mr+Csa4xUJxvbZxfaMR7LFzeSu6xxCqEyFZ41exYxT5qQz8vxKtS+HIR51GMpblaxxZpNToglRy78Q8HL+86SY= X-MS-TrafficTypeDiagnostic: BLUPR0701MB1650: X-Microsoft-Exchange-Diagnostics: 1; BLUPR0701MB1650; 20:CS0Sa6MTcqNwO4L6ViPNJN234KhVq+2r+oLjFRh1lc8ex2aobQfL8ftYUzRkQh7SgmopHPK+U4o1ATfQFbRYOC9MambXEmvcFyBX93gKfFeYng/ukidFKvK2JvEkFrQVO6ig4opkTNtdGJERSwI38M2lqB1fTwDznRoUvQTqRnU+1QQecRcO/dDPjw2JZAumt+eCEwgbKTY1/DRcVQuLi+k/iShC8DaxBGp5jrzCRfo7AAYS2rD2iUJO8lsnp1notEqHNUN0ILNFB4mvvb7uBCm+juy02H7WtaObEF1PHhkjvRmtXaqi4s/1vRTc+40sQ3gPY/2w4o86ZAiAd/falw68plpfeOjZ/SI8rCd98KBtoDf9vERLH0euWdxBpskOnrpm1l93O8JHfgaOlCu0pdDIPzECFa5yk1Th8cg8p7igGmVAjjs5y869PddlWMkyJZLPLO1pzE11Om0ZS6aK11i6F+t0wGa8JRRKd3tvHNOgf8FYjpHB1cSIbtQWMYOG; 4:YRTP0094/p+RJ58Zq6aZkimvZ6OvoREmGD8A4OWurRFUInIQHpQtUiN7WZd4EgVsz57wAmE08vCi9/oAn0v3N6bU6vz4PRnpV+T1HByH0SphcmTjSelDVksqz0DQeCfhbXys0Tt2sMzWCStBAheln3PnU3wxa+BvQwuBM+pLvvDH9PeXWzMJJwG06SfH8imJwa5OsOzWDKaAmwYqDObWXDzFFZSxYUyy8xs/qRgsRIxzPXEocI0BwZU/CYeBG8iEQmuyRz+lu/PwMC0IrVNDZA== X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-MS-Exchange-SenderADCheck: 1 X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(6040522)(2401047)(8121501046)(5005006)(10201501046)(3002001)(93006095)(93001095)(3231355)(944501410)(52105095)(149066)(150057)(6041310)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123558120)(20161123564045)(20161123562045)(20161123560045)(201708071742011)(7699051); SRVR:BLUPR0701MB1650; BCL:0; PCL:0; RULEID:; SRVR:BLUPR0701MB1650; X-Forefront-PRVS: 0810818DA0 X-Forefront-Antispam-Report: SFV:NSPM; SFS:(10009020)(39850400004)(366004)(376002)(346002)(396003)(136003)(189003)(199004)(6486002)(105586002)(118296001)(16586007)(6116002)(53936002)(3846002)(386003)(72206003)(2361001)(478600001)(11346002)(7736002)(2351001)(106356001)(48376002)(25786009)(305945005)(50466002)(66066001)(486006)(47776003)(44832011)(186003)(476003)(2616005)(956004)(107886003)(7696005)(51416003)(52116002)(26005)(6666003)(6916009)(2906002)(97736004)(16526019)(14444005)(76176011)(446003)(575784001)(86362001)(5660300001)(50226002)(34290500001)(68736007)(81166006)(81156014)(36756003)(8676002)(8936002)(4326008)(316002); DIR:OUT; SFP:1101; SCL:1; SRVR:BLUPR0701MB1650; H:ubuntubox.rdc.aquantia.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; Received-SPF: None (protection.outlook.com: aquantia.com does not designate permitted sender hosts) X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; BLUPR0701MB1650; 23:Q7k3LxFQ9dch9khK8plBgHwa93DJ/Vi+pNiIxFk?= IHZMW5FCA6lV9fjaBZ7NITrjTUkNpaCTYbCRgptBlZWH1OJ5rlolR+s+0oW6Xjyd9DNk8r3LhtseYqReJDIztGGWG0i2rm2UspDbXOJpwvarnZNxugPLWBnPOkFaLGt/ephz1mY+mJ8ELEyOc7RPB+jAtUHFeayQKjX1kOcBRnt7BjSjTJrN2glBaRzGRIGyqD6LV3VQfqbjMQ6la79JP1rBT2Y+4yTY6+FWxf1TlhaoGUN6m4IFxDWZlWFRNjTlwR+RSGkN/tlJdiDaKHBs6PYMH2D4Idb4xdf+IQbS/60KHXOv2Haz9bV+Xkh/iTwkTbqvQXFNE1SbYxlw1u5hr7dCu9CBv83+v0IPmYd+yf7NinBwMhUt7TWaVXOShVXwR7R2voVsa0PWVLm4Fuc8vhgmuiZNMaXeCXlJDew+nRMz249s6N3ifjUseAQL4yH7aHGCOrt0uV5mSaPO65w8JZmn2L0qTK7D0uiRQlsTi3eISTHtdFjBIYmFz6otdqOiVIYmR8gTbcKqXcIBpZP9QiiYN2ydrV7cgsEerrBOF4hxALlIIVQ5krv/nfYGJlnZjedEh7QX/P/Cd8KjKCbx2GsvMA4KvyMrg19DgRMYA3DOOi70oojBPwY9SMtCYEvgoDA2XRy6q7EIznEbNT249RPsLo6jiSTGBZ2+knKUXmWOwwpsMIdaedgV52yeSMgyttWrCEQILX7yZEn3HelJ9fub67Yl1K2vxdNgmHID+DWQcHCdTJWNMp6YXvsIu0Yk+biKBgcpN9M4QFNkRSjR7kWAfF/IP2gG0VBKiyb/8JNjSpftRH2cbmVJVG8kEDEHoGB67GDy9KcjCNfU2T0UA0JecVVyM5hO6QWroce26/d6+fHiauFo4oLo9HXvK7oUcxNrWwWbgaT2qd9K5iWCSnVZSd8QXZTAyInRBPws4sVliOfiN6yTkDf36Fa6RkOKHK+9rufXbTmCnEmMoqmvPsERKJ9UijnllF/5ZB/0JkyTTEUm4IGIu10euhPl41VlDbcuo/b/J+DrX6G5IivJIlz/Ue0l+12l2MghUEcgwt8+aONigx546onwL6hRCkdg91r7OwpmHH7kjm3FcLuZV+Z3X1Dw2sX4yvHIY8lBw1c7u4HZn5ckyh0SOg+CkIp3uqpoJea3Y3IBfbPw/VpM4TZ8DX/EtuGRGGCvU0mlSQz4pOQi/A4m5V/T4twXffRPIRMTh0+taOSPPkWPqmR0QLZ20LW7oYdyVoWl0zsl2jJapjuOGO24qCiqqKB6Pifz3lQbhJzw2wLH31c/00AOITnDb X-Microsoft-Antispam-Message-Info: tPVe+2PhQMTNNqEMAg3EBMZpf9W/HqHG1V6jUqV0j0IFH7uXOepplRWHoCd1bVBjXJcEUqAl+LkUpPHmswADTS+8p1u/LTRSbu6eY1tMxEJFkVDdCY+2T+r3p5OSgk78z2Y3Pv4GoVmbqpoZ52U8dI6v7pAeLQ9La2SOmtkBMAbBOa3RxnEn0vp2L8wcZgQx5LalzzYi+qs2LRsh/W1ckUNzDdab0zxmK4L69xRLG6pvG5QXfr4G0eHfi95mYIG+5cdfTzLjWB/c6Qf8x56/4Wngm8kRpNqYmi57Y+vskuLJm7UbJcnsLDenL24AhoNKmRiV1eYK1zpzN/RvZNC2VB2vkjWmVdICgaPq+k2tcTo= X-Microsoft-Exchange-Diagnostics: 1; BLUPR0701MB1650; 6:hMAsWmJbK6Atxy1hn+X+BZiEk7PPBtoiLZhvZpdCAou54a/38Q30LmcNl4uddnmgz742FhM2uBnzdRg2f8Db/LEXuqEn7roUQX5kD43NVHyTkNPa2KaxLF4pHVnlvMhTZU9R2mU5l2hupcc7wJJxxlfq9xbsmFWBFDzENsCRQFh/NLx5pp/Z2b2kuV0HQ20a75qBnUXd26DBY+t99nX87E8Q8TgoBclqrqRq//UmzLYcE9vS881WCRNXDpoi84ZmRNhn1rEkC3kMuTjx7+7uDFHYVX8RNFuMAOH9DPI3azID9fUxrbduKKERbSaUJ1UnXjurj4H4+BVEBhZ9fWT0gsOPaOGdlYmIkxvn/4Vo/rwdojvsj6Wj/lPav1IN2MYRFWWxHI2KuwSHgBaRDzcod6YVxlbVwaWy3W+y3ulSw+Zoleibqzw9q+FP9hFuZB4ggqvSt+TgrfnsEwZWV7xDRw==; 5:4WVKN2gaLoEMuMei2yXk/uyxxMa5Z6ASF2ItGFcq83GSBw193I1r/ZkCX3jGAsyPGeVm1nqFRhMQQlfjcAB1Ewq4U83KJiCOQgGx1cequ0Wpb2CaSV5w7dS6cupdfMTOSUflz+2OqPyBrMpazaP4k8OxQGh5lX9ou23zzxYeGlI=; 7:0I92JyY9TPoLc+Pv1fGrZ7cuTlP//uqFFZ1BeTYO+InSv7PLcB4SlvyT5Lh45kLs8M+BU4UXIGL8VJaUOcHaQHkdkPqCkyYV5rN2NUdX5BTyqRVb4AMU3NrVGgHgjV/IngN4ld33L7OMMv5kurUi67FPnGqjQmUQUmEPwSMpfcravWb08OWZEMpljZzDZqkP0EjozF23QKnW45xmswLCf+9EXconTISKaPJ0+tE4ZEe/MgFuVrbtTBgyPUaCZ8v0 SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: aquantia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Sep 2018 10:30:56.9046 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2d15b29a-2620-4c8e-7812-08d625f6a7f9 X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 83e2e134-991c-4ede-8ced-34d47e38e6b1 X-MS-Exchange-Transport-CrossTenantHeadersStamped: BLUPR0701MB1650 Subject: [dpdk-dev] [PATCH v3 01/22] net/atlantic: atlantic PMD driver skeleton X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavel Belous Makefile/meson build infrastructure, atl_ethdev minimal skeleton, header with aquantia aQtion NIC device and vendor IDs. Signed-off-by: Igor Russkikh Signed-off-by: Pavel Belous --- config/common_base | 5 + drivers/net/Makefile | 1 + drivers/net/atlantic/Makefile | 27 ++++ drivers/net/atlantic/atl_common.h | 96 ++++++++++++++ drivers/net/atlantic/atl_ethdev.c | 145 ++++++++++++++++++++++ drivers/net/atlantic/atl_ethdev.h | 15 +++ drivers/net/atlantic/meson.build | 10 ++ drivers/net/atlantic/rte_pmd_atlantic_version.map | 4 + drivers/net/meson.build | 1 + mk/rte.app.mk | 1 + 10 files changed, 305 insertions(+) create mode 100644 drivers/net/atlantic/Makefile create mode 100644 drivers/net/atlantic/atl_common.h create mode 100644 drivers/net/atlantic/atl_ethdev.c create mode 100644 drivers/net/atlantic/atl_ethdev.h create mode 100644 drivers/net/atlantic/meson.build create mode 100644 drivers/net/atlantic/rte_pmd_atlantic_version.map diff --git a/config/common_base b/config/common_base index 155c7d40ea31..ba51ffbd43ce 100644 --- a/config/common_base +++ b/config/common_base @@ -635,6 +635,11 @@ CONFIG_RTE_LIBRTE_PMD_DPAA_EVENTDEV=n CONFIG_RTE_LIBRTE_PMD_DPAA2_EVENTDEV=n # +# Compile Aquantia Atlantic PMD driver +# +CONFIG_RTE_LIBRTE_ATLANTIC_PMD=y + +# # Compile raw device support # EXPERIMENTAL: API may change without prior notice # diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 664398de983a..8ac6b9db5916 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -10,6 +10,7 @@ endif DIRS-$(CONFIG_RTE_LIBRTE_PMD_AF_PACKET) += af_packet DIRS-$(CONFIG_RTE_LIBRTE_ARK_PMD) += ark +DIRS-$(CONFIG_RTE_LIBRTE_ATLANTIC_PMD) += atlantic DIRS-$(CONFIG_RTE_LIBRTE_AVF_PMD) += avf DIRS-$(CONFIG_RTE_LIBRTE_AVP_PMD) += avp DIRS-$(CONFIG_RTE_LIBRTE_AXGBE_PMD) += axgbe diff --git a/drivers/net/atlantic/Makefile b/drivers/net/atlantic/Makefile new file mode 100644 index 000000000000..e42ce5b178ab --- /dev/null +++ b/drivers/net/atlantic/Makefile @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2018 Aquantia Corporation + +include $(RTE_SDK)/mk/rte.vars.mk + +# +# library name +# +LIB = librte_pmd_atlantic.a + +CFLAGS += -O3 +CFLAGS += $(WERROR_FLAGS) + +EXPORT_MAP := rte_pmd_atlantic_version.map + +LIBABIVER := 1 + +LDLIBS += -lrte_eal +LDLIBS += -lrte_ethdev -lrte_net +LDLIBS += -lrte_bus_pci + +# +# all source are stored in SRCS-y +# +SRCS-$(CONFIG_RTE_LIBRTE_ATLANTIC_PMD) += atl_ethdev.c + +include $(RTE_SDK)/mk/rte.lib.mk diff --git a/drivers/net/atlantic/atl_common.h b/drivers/net/atlantic/atl_common.h new file mode 100644 index 000000000000..b3a0aa5cd212 --- /dev/null +++ b/drivers/net/atlantic/atl_common.h @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2018 Aquantia Corporation + */ + +#ifndef AQ_COMMON_H +#define AQ_COMMON_H + +#define ATL_PMD_DRIVER_VERSION "0.4.1" + +#define PCI_VENDOR_ID_AQUANTIA 0x1D6A + +#define AQ_DEVICE_ID_0001 0x0001 +#define AQ_DEVICE_ID_D100 0xD100 +#define AQ_DEVICE_ID_D107 0xD107 +#define AQ_DEVICE_ID_D108 0xD108 +#define AQ_DEVICE_ID_D109 0xD109 + +#define AQ_DEVICE_ID_AQC100 0x00B1 +#define AQ_DEVICE_ID_AQC107 0x07B1 +#define AQ_DEVICE_ID_AQC108 0x08B1 +#define AQ_DEVICE_ID_AQC109 0x09B1 +#define AQ_DEVICE_ID_AQC111 0x11B1 +#define AQ_DEVICE_ID_AQC112 0x12B1 + +#define AQ_DEVICE_ID_AQC100S 0x80B1 +#define AQ_DEVICE_ID_AQC107S 0x87B1 +#define AQ_DEVICE_ID_AQC108S 0x88B1 +#define AQ_DEVICE_ID_AQC109S 0x89B1 +#define AQ_DEVICE_ID_AQC111S 0x91B1 +#define AQ_DEVICE_ID_AQC112S 0x92B1 + +#define AQ_DEVICE_ID_AQC111E 0x51B1 +#define AQ_DEVICE_ID_AQC112E 0x52B1 + +#define HW_ATL_NIC_NAME "aQuantia AQtion 10Gbit Network Adapter" + +#define AQ_HWREV_ANY 0 +#define AQ_HWREV_1 1 +#define AQ_HWREV_2 2 + +#define AQ_NIC_RATE_10G BIT(0) +#define AQ_NIC_RATE_5G BIT(1) +#define AQ_NIC_RATE_5G5R BIT(2) +#define AQ_NIC_RATE_2G5 BIT(3) +#define AQ_NIC_RATE_1G BIT(4) +#define AQ_NIC_RATE_100M BIT(5) + +#define AQ_NIC_RATE_EEE_10G BIT(6) +#define AQ_NIC_RATE_EEE_5G BIT(7) +#define AQ_NIC_RATE_EEE_2G5 BIT(8) +#define AQ_NIC_RATE_EEE_1G BIT(9) + + +#define ATL_MAX_RING_DESC (8 * 1024 - 8) +#define ATL_MIN_RING_DESC 32 +#define ATL_RXD_ALIGN 8 +#define ATL_TXD_ALIGN 8 +#define ATL_TX_MAX_SEG 16 + +#define ATL_MAX_INTR_QUEUE_NUM 15 + +#define ATL_MISC_VEC_ID 10 +#define ATL_RX_VEC_START 0 + +#define AQ_NIC_WOL_ENABLED BIT(0) + + +#define AQ_NIC_FC_OFF 0U +#define AQ_NIC_FC_TX 1U +#define AQ_NIC_FC_RX 2U +#define AQ_NIC_FC_FULL 3U +#define AQ_NIC_FC_AUTO 4U + + +#define AQ_CFG_TX_FRAME_MAX (16U * 1024U) +#define AQ_CFG_RX_FRAME_MAX (2U * 1024U) + +#define AQ_HW_MULTICAST_ADDRESS_MAX 32 +#define AQ_HW_MAX_SEGS_SIZE 40 + +#define AQ_HW_MAX_RX_QUEUES 8 +#define AQ_HW_MAX_TX_QUEUES 8 +#define AQ_HW_MIN_RX_RING_SIZE 512 +#define AQ_HW_MAX_RX_RING_SIZE 8192 +#define AQ_HW_MIN_TX_RING_SIZE 512 +#define AQ_HW_MAX_TX_RING_SIZE 8192 + +#define ATL_DEFAULT_RX_FREE_THRESH 64 +#define ATL_DEFAULT_TX_FREE_THRESH 64 + +#define ATL_IRQ_CAUSE_LINK 0x8 + +#define AQ_HW_LED_BLINK 0x2U +#define AQ_HW_LED_DEFAULT 0x0U + +#endif /* AQ_COMMON_H */ diff --git a/drivers/net/atlantic/atl_ethdev.c b/drivers/net/atlantic/atl_ethdev.c new file mode 100644 index 000000000000..5728d9037d72 --- /dev/null +++ b/drivers/net/atlantic/atl_ethdev.c @@ -0,0 +1,145 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2018 Aquantia Corporation + */ + +#include + +#include "atl_ethdev.h" +#include "atl_common.h" + +static int eth_atl_dev_init(struct rte_eth_dev *eth_dev); +static int eth_atl_dev_uninit(struct rte_eth_dev *eth_dev); + +static int atl_dev_configure(struct rte_eth_dev *dev); +static int atl_dev_start(struct rte_eth_dev *dev); +static void atl_dev_stop(struct rte_eth_dev *dev); +static void atl_dev_close(struct rte_eth_dev *dev); +static int atl_dev_reset(struct rte_eth_dev *dev); + +static int eth_atl_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, + struct rte_pci_device *pci_dev); +static int eth_atl_pci_remove(struct rte_pci_device *pci_dev); + +int atl_logtype_init; +int atl_logtype_driver; + +/* + * The set of PCI devices this driver supports + */ +static const struct rte_pci_id pci_id_atl_map[] = { + { RTE_PCI_DEVICE(PCI_VENDOR_ID_AQUANTIA, AQ_DEVICE_ID_0001) }, + { RTE_PCI_DEVICE(PCI_VENDOR_ID_AQUANTIA, AQ_DEVICE_ID_D100) }, + { RTE_PCI_DEVICE(PCI_VENDOR_ID_AQUANTIA, AQ_DEVICE_ID_D107) }, + { RTE_PCI_DEVICE(PCI_VENDOR_ID_AQUANTIA, AQ_DEVICE_ID_D108) }, + { RTE_PCI_DEVICE(PCI_VENDOR_ID_AQUANTIA, AQ_DEVICE_ID_D109) }, + + { RTE_PCI_DEVICE(PCI_VENDOR_ID_AQUANTIA, AQ_DEVICE_ID_AQC100) }, + { RTE_PCI_DEVICE(PCI_VENDOR_ID_AQUANTIA, AQ_DEVICE_ID_AQC107) }, + { RTE_PCI_DEVICE(PCI_VENDOR_ID_AQUANTIA, AQ_DEVICE_ID_AQC108) }, + { RTE_PCI_DEVICE(PCI_VENDOR_ID_AQUANTIA, AQ_DEVICE_ID_AQC109) }, + { RTE_PCI_DEVICE(PCI_VENDOR_ID_AQUANTIA, AQ_DEVICE_ID_AQC111) }, + { RTE_PCI_DEVICE(PCI_VENDOR_ID_AQUANTIA, AQ_DEVICE_ID_AQC112) }, + + { RTE_PCI_DEVICE(PCI_VENDOR_ID_AQUANTIA, AQ_DEVICE_ID_AQC100S) }, + { RTE_PCI_DEVICE(PCI_VENDOR_ID_AQUANTIA, AQ_DEVICE_ID_AQC107S) }, + { RTE_PCI_DEVICE(PCI_VENDOR_ID_AQUANTIA, AQ_DEVICE_ID_AQC108S) }, + { RTE_PCI_DEVICE(PCI_VENDOR_ID_AQUANTIA, AQ_DEVICE_ID_AQC109S) }, + { RTE_PCI_DEVICE(PCI_VENDOR_ID_AQUANTIA, AQ_DEVICE_ID_AQC111S) }, + { RTE_PCI_DEVICE(PCI_VENDOR_ID_AQUANTIA, AQ_DEVICE_ID_AQC112S) }, + + { RTE_PCI_DEVICE(PCI_VENDOR_ID_AQUANTIA, AQ_DEVICE_ID_AQC111E) }, + { RTE_PCI_DEVICE(PCI_VENDOR_ID_AQUANTIA, AQ_DEVICE_ID_AQC112E) }, + { .vendor_id = 0, /* sentinel */ }, +}; + +static struct rte_pci_driver rte_atl_pmd = { + .id_table = pci_id_atl_map, + .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC | + RTE_PCI_DRV_IOVA_AS_VA, + .probe = eth_atl_pci_probe, + .remove = eth_atl_pci_remove, +}; + +static const struct eth_dev_ops atl_eth_dev_ops = { + .dev_configure = atl_dev_configure, + .dev_start = atl_dev_start, + .dev_stop = atl_dev_stop, + .dev_close = atl_dev_close, + .dev_reset = atl_dev_reset, +}; + +static int +eth_atl_dev_init(struct rte_eth_dev *eth_dev __rte_unused) +{ + return 0; +} + +static int +eth_atl_dev_uninit(struct rte_eth_dev *eth_dev __rte_unused) +{ + return 0; +} + +static int +eth_atl_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, + struct rte_pci_device *pci_dev) +{ + return rte_eth_dev_pci_generic_probe(pci_dev, + sizeof(struct atl_adapter), eth_atl_dev_init); +} + +static int +eth_atl_pci_remove(struct rte_pci_device *pci_dev) +{ + return rte_eth_dev_pci_generic_remove(pci_dev, eth_atl_dev_uninit); +} + +static int +atl_dev_configure(struct rte_eth_dev *dev __rte_unused) +{ + return 0; +} + +/* + * Configure device link speed and setup link. + * It returns 0 on success. + */ +static int +atl_dev_start(struct rte_eth_dev *dev __rte_unused) +{ + return 0; +} + +/* + * Stop device: disable rx and tx functions to allow for reconfiguring. + */ +static void +atl_dev_stop(struct rte_eth_dev *dev __rte_unused) +{ +} + +/* + * Reset and stop device. + */ +static void +atl_dev_close(struct rte_eth_dev *dev __rte_unused) +{ +} + +static int +atl_dev_reset(struct rte_eth_dev *dev) +{ + int ret; + + ret = eth_atl_dev_uninit(dev); + if (ret) + return ret; + + ret = eth_atl_dev_init(dev); + + return ret; +} + +RTE_PMD_REGISTER_PCI(net_atlantic, rte_atl_pmd); +RTE_PMD_REGISTER_PCI_TABLE(net_atlantic, pci_id_atl_map); +RTE_PMD_REGISTER_KMOD_DEP(net_atlantic, "* igb_uio | uio_pci_generic"); diff --git a/drivers/net/atlantic/atl_ethdev.h b/drivers/net/atlantic/atl_ethdev.h new file mode 100644 index 000000000000..ae87517560de --- /dev/null +++ b/drivers/net/atlantic/atl_ethdev.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2018 Aquantia Corporation + */ + +#ifndef _ATLANTIC_ETHDEV_H_ +#define _ATLANTIC_ETHDEV_H_ +#include + +/* + * Structure to store private data for each driver instance (for each port). + */ +struct atl_adapter { +}; + +#endif /* _ATLANTIC_ETHDEV_H_ */ diff --git a/drivers/net/atlantic/meson.build b/drivers/net/atlantic/meson.build new file mode 100644 index 000000000000..90ee5288206a --- /dev/null +++ b/drivers/net/atlantic/meson.build @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2018 Aquantia Corporation + +sources = files( + 'atl_ethdev.c', +) + +deps += ['eal'] + +allow_experimental_apis = true diff --git a/drivers/net/atlantic/rte_pmd_atlantic_version.map b/drivers/net/atlantic/rte_pmd_atlantic_version.map new file mode 100644 index 000000000000..521e51f411fb --- /dev/null +++ b/drivers/net/atlantic/rte_pmd_atlantic_version.map @@ -0,0 +1,4 @@ +DPDK_18.11 { + + local: *; +}; diff --git a/drivers/net/meson.build b/drivers/net/meson.build index f59bea7905e3..8208ab101ed5 100644 --- a/drivers/net/meson.build +++ b/drivers/net/meson.build @@ -3,6 +3,7 @@ drivers = ['af_packet', 'ark', + 'atlantic', 'avp', 'axgbe', 'bonding', 'bnx2x', diff --git a/mk/rte.app.mk b/mk/rte.app.mk index 899d51a23b2c..fd06e7df014e 100644 --- a/mk/rte.app.mk +++ b/mk/rte.app.mk @@ -157,6 +157,7 @@ _LDLIBS-$(CONFIG_RTE_LIBRTE_MLX5_PMD) += -lrte_pmd_mlx5 -ldl -lmnl else _LDLIBS-$(CONFIG_RTE_LIBRTE_MLX5_PMD) += -lrte_pmd_mlx5 -libverbs -lmlx5 -lmnl endif +_LDLIBS-$(CONFIG_RTE_LIBRTE_ATLANTIC_PMD) += -lrte_pmd_atlantic _LDLIBS-$(CONFIG_RTE_LIBRTE_MVPP2_PMD) += -lrte_pmd_mvpp2 -L$(LIBMUSDK_PATH)/lib -lmusdk _LDLIBS-$(CONFIG_RTE_LIBRTE_NFP_PMD) += -lrte_pmd_nfp _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_NULL) += -lrte_pmd_null From patchwork Sat Sep 29 10:30:16 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Russkikh X-Patchwork-Id: 45666 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 42D7F1B12C; Sat, 29 Sep 2018 12:31:12 +0200 (CEST) Received: from NAM05-DM3-obe.outbound.protection.outlook.com (mail-eopbgr730067.outbound.protection.outlook.com [40.107.73.67]) by dpdk.org (Postfix) with ESMTP id C82EE1B130 for ; Sat, 29 Sep 2018 12:31:10 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=AQUANTIA1COM.onmicrosoft.com; s=selector1-aquantia-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=9huq+59qhFZHAMEhMtqzILDr6lSBHQXYwEQBTrB4w1c=; b=DAXALOlMbdsSOO5kE70lEh2VKcu1rT/iZTczPD/5a4xirDVIuoqJUKBV7ieYVNpUjl1tO/JAPfOh9SS5fbybMHGqROQBqpYhGVtKGesC4iW3Qjw2UNF8W66MglajEaz5d3SYXp+9aWQG5Y+sYNValevRqIdSoqIw3ILAtEhQhT0= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Igor.Russkikh@aquantia.com; Received: from ubuntubox.rdc.aquantia.com (95.79.108.179) by BLUPR0701MB1650.namprd07.prod.outlook.com (2a01:111:e400:58c6::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1185.22; Sat, 29 Sep 2018 10:31:03 +0000 From: Igor Russkikh To: dev@dpdk.org Cc: pavel.belous@aquantia.com, igor.russkikh@aquantia.com, Pavel Belous Date: Sat, 29 Sep 2018 13:30:16 +0300 Message-Id: <8d4e55d6fb6db2567e37c850cbae0e82f079a02d.1538215990.git.igor.russkikh@aquantia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [95.79.108.179] X-ClientProxiedBy: VI1P193CA0009.EURP193.PROD.OUTLOOK.COM (2603:10a6:800:bd::19) To BLUPR0701MB1650.namprd07.prod.outlook.com (2a01:111:e400:58c6::20) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 7a253408-8329-4ec6-0818-08d625f6abea X-Microsoft-Antispam: BCL:0; PCL:0; RULEID:(7020095)(4652040)(8989299)(4534165)(4627221)(201703031133081)(201702281549075)(8990200)(5600074)(711020)(2017052603328)(7153060)(7193020); SRVR:BLUPR0701MB1650; X-Microsoft-Exchange-Diagnostics: 1; BLUPR0701MB1650; 3:aWsl44/qiyXKfSRkngTYqYNk7q5AjjscalnSJ7opGJf2Z9E4jxBfOkw8/mq6mY4wfCVf9U6wdxyuVkmm3Wx6isLLzluh27kVl6IB3rPir7CtYIj4ff8DBX2NVxQWVx2Md+LydlXrB32KFjXfalG5YHaZq3w9BatOtfIBOnKMm/NaQDSS4mQB2qFvxDt2twBl9L+5WZJjVZe244s7dJYRq0V3HSwCh9ataf6XRxs2K8bFP1bacd335IezwrTU5wGU; 25:5117QrmCs+PcP5T67VU0AgZaY3B4QDzFq+Xx9jxMnJbpP1VvMNT60X9rUXmFoLGNEJpPlnCNcw7CyRxSTuuZtBpxNOiELoS9ipp0yq1Oy5309k4KgIN0HZ2VVo+1xEYRTPBzp6YXjUigaoGaN37tlyGSchDvxRTQjXofQrxvSB1iGPhx+edhraP1fFrtSfs8EaJ+DwIe39XryrW4JavNlh64NtIarXJi8N6Jr1vRwO4K+2uo6Z5iYviUoPMqI2A6Qsa8siGgQibyNq1mYQXcmf4PVfcmMiYdoSpQ/gVOIhf7DsBSBrhM+QbcO1oUoHswzOvRsvbrMkKE8zg15gGndeNb5uWrAdQP3XxEH2KvYkY=; 31:9yCtRN6e3mNK+rGLaBIj/4L5yIB92kVcK2cXTLt/Rzg2cCUncsNbj96sZZU2i3ZhqM8EJju2rzEnvaa4DdbzCFGUaoxAy8ZQkmiydxL7rgbR2yyI3GtiZ0d/8+4sYYo3PWVdV/6WMCiZhgJFnoo585CtAunsbKMTZvSByNKyZhY+Ihrho95FOGT6S+TwKxbLotZd2+U8Gvh6WVp/yPdBbrPDqS5XmLk5qP6Q93F39D8= X-MS-TrafficTypeDiagnostic: BLUPR0701MB1650: X-Microsoft-Exchange-Diagnostics: 1; BLUPR0701MB1650; 20:zbRzeoTIIG57Zn4zK/6yyLDkZjBnPRSF/CQRiu5LSHR1wWinb9Y0g5ZAJK8QvrYuSpxiyX/6QUAKm19jkUwAiSHn5+lMtaP7buNOmL/pI72QPj4/Mab6xpbDV273JG7DdIAILZ8E3s1Auko2nkpas3grZcs91MLhT4qPnu9vmUaPG+8WGnMV1WagZuOrJ0qlOu0/RZ1UPopB61D8jnW+HWcWA9I/B+urLjk7UZ6PpSSR+zgkHuC4dgEKUhQqBgZYSkyRdCOA3vYqSXB0ZRjpgyzGrcmagoKb3xQjbKxmh/5LKhSc92hrmVhQDvFoOYncqlHnUTFTnsfYYi1+nwxYpNoIyoVdbqIO4UxUQlwA5UG3UsbKuheWeAwZV2WhXr+cBMhAEmTYzELJt+of2Ji4LAIw2DDlBP8bvR0eLLDZSgOTavkSirsXXho+kU5gbFgjw9pwjPP3swudFLFe6JKbN6Uikqfjn8f8I8TEyv+KwJ8ATHzRyqkdqjfr9J7rp+y3; 4:XF4UcLUdqYuYOV+DwAjZuOuld95bJDoQGEsPZu/fXXydV2L8k0hFOtTCQTys23QXQc3tgwSZC9GTRmTGNGwwlt2pUSKrzZ4NYVxkhU6//f84042zmaCNAJ9+ZV7fhZIVEv/FMZZPCf1r1VeNYjWM0CIne5lQlEGcq+AFkg3lP/sbauTEJwTLoIhT7/tU1dP2THCehkM9VpK+MBz3B6zvXs2zy8Kmh58n4ieD+BltqimXcG/gS+ynDfWfzyOThsw1PDGUUSKcI+IVGjoxpMDZ9g== X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-MS-Exchange-SenderADCheck: 1 X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(6040522)(2401047)(8121501046)(5005006)(10201501046)(3002001)(93006095)(93001095)(3231355)(944501410)(52105095)(149066)(150057)(6041310)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123558120)(20161123564045)(20161123562045)(20161123560045)(201708071742011)(7699051); SRVR:BLUPR0701MB1650; BCL:0; PCL:0; RULEID:; SRVR:BLUPR0701MB1650; X-Forefront-PRVS: 0810818DA0 X-Forefront-Antispam-Report: SFV:NSPM; SFS:(10009020)(346002)(136003)(396003)(376002)(39850400004)(366004)(189003)(199004)(16526019)(446003)(76176011)(2906002)(6916009)(6666003)(97736004)(8676002)(81166006)(81156014)(36756003)(4326008)(316002)(8936002)(50226002)(34290500001)(86362001)(5660300001)(68736007)(16586007)(118296001)(72206003)(3846002)(6116002)(53936002)(386003)(105586002)(6486002)(47776003)(66066001)(486006)(25786009)(305945005)(50466002)(44832011)(956004)(2616005)(26005)(107886003)(52116002)(51416003)(7696005)(186003)(476003)(478600001)(2361001)(7736002)(2351001)(48376002)(106356001)(11346002); DIR:OUT; SFP:1101; SCL:1; SRVR:BLUPR0701MB1650; H:ubuntubox.rdc.aquantia.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; Received-SPF: None (protection.outlook.com: aquantia.com does not designate permitted sender hosts) X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; BLUPR0701MB1650; 23:Dg+Dp+r9wKnqk8GFM+nLtheHY9HnbpWDQZrecPd?= /e6XvkiVydEtiNx6bxC1Kq+nTdrZs4cV7s5JS+JW82tA+5D6fNGHX2Cfe3BQ8WLZ7DCqnhBUcheisOXwiVujR3sfyuV7Nhndtwgl4iNqDLRdDQRSNcDrix2mfLsElX653d0+Ay2kZknUmZ5o3drSYoCF9XWalcCvwQVze1R5k48tgqQ7PSVmbIeUo9hST2ATs1hA85UiAYus/txce7e/ZXRGxbeCnas0tijjXSHrgzkxOmUGg+Fz04NcTrza3wFzVLntMwDICp2TuOqV9OWQpVJtc/3IBF6jYf/hKDLnM1XR4z5EBB+04qktRztAMU6hmqD83tI300dG8JsH6ArlkPIP8Lf64DprGjEP2udYC90ao8Z55DZ3r63OaS2ZmNqoK1AB/BRWFDRSXEUYIDlnRQreCuYrmfjWT6CkXs4/Uq3ePyYvFUfFb2t66ABLCtph23PToI3Vf7ox0iFuW3BOBqEO0E89GRuBhJc++4rT0U48j4JsnE5o+5Mye/ABrpPFqKfUqWFVqOvUf9dybvLc3xSI0a6xCDSeN7oWTbwCHxLYsp76A++dStnj1RiiZ+Pf1Hzk0jJg/euh4Z8vKT1+HqJDCb3QsP9IIqcIvPG9x1pQhwi66+mI5czDPgMpZRjAy+obDJBscVaikeSX0FDlFQ1BvkmK/g0UPJnDt9b7Hj3rWYhHYJPrnpdtMA138JL/bQ91o24S5TIVRgd0hdj9zpciQa0Idji3eaKLYkj8ZAUE82j/sso6/GEajL5gWVkDbkJkgKKRbj9/3sx72AHUmtMgGjSxnZYeqprDfaQV3GRaFitZjf3o9nMC3HQyDBmPZFibKmJOhXkMAXvN5Vcw0zoT4/G22xz2ON+CGxnLkVZBNR6R7Zvz/2bBh+L0ktVkV4a2eDRyvlrU3z6oJflZOyvBJ/cKvcYr0ZNQBU+sN/4Y7HyipFkMFCeYvjfP3uuxlLVQDC0asmc+YRrUKioOBecvnlseczh00GeIoTy9uQfz/ahCF9jVgpSbhKFKtrT4uviQrBjJkn0rZc+398NDDSxBRgcO1cu38BrLeVfUCmie+q8O+K26LZTNHrKejhAbuun44kgKXS6+Glu0PH/+spMsBCOouGR1Vy6xP97lSYt+tESrDmqWukBhakp76FCl6RPst3j4bXm4z5eFI8bw8hq+UobO+sD56IY5NdZQTHP6rE4TFJGtyqsKzfNy4wAK4KVg0dFT4tNXGNkeqkl9ZIqOmqA3q3A2i4Qp6u9EzbyzulQ== X-Microsoft-Antispam-Message-Info: 6xQChyAtiOYlAHvbOhU72v+I9L7ek21WGqiEImN6EfH0yZLJfjHaiQW3HAZ+m+KFIarfPrcD5aeArKEraOwph0dzUrT/1UbYRYZTqkgy2a5shRddH/0gPM6GOXksJGGSk6x4I/fL/tA4XaZYJJHf0G9RxAVWZcA9vAaykW+IBHOSHtZNO5epeMJ8ofet+Ho1IMedF+xsR5fA7JVXsevHsn65t6vSHwE1hlcFC4+5ENAfD9wts8ma6o7YLWeom21fSp0XL1+m2Hr1sWG2GBUUbG5ZsHhNfXdnWZlE4lSKp8+MaWiyT/EXarV7Bje7ftrQww/QVuJtdGZsXxbs6y5fv1qdEyZVNgw/pY5CjAouOyo= X-Microsoft-Exchange-Diagnostics: 1; BLUPR0701MB1650; 6:2J8oShbk/pkM8/84UfD0rQuJAaKl/osCM4uW+9XwTWb9soQGTUkY0tJ78YZYb6QCndFU9BboeQQEppeX644k2+/gxEjeAfi0pDgqRUI4iFIsJtBhXQpqnUAwPM2wgOe52F/Htjffonz7rqPvCgafnJgGl9DBGw4KpgHGsC3I35cClVUoGXxyIk6qhw2mO8iUIXtKacMHiKlrsYMkwkynkDnF0MRgDL7CPr/7sBoJAjBoodscpszTISUOBwzaPpJtXjAkrkyjs9s+pbOz1F8JiVOs05Dh9c/S2nu3xt5g5IOaQ5OU4WI7U61nf3hgADZMUMzIHaMQUDIg1AX9ySVETJgIVGAdIY7zFdOMp5x2ADHfEIzDBvp7bz29vxCSY9TriSoQTksW7m+5YnCxWpA/ecDeUGET3lFjq1wReJQJ2pK6pOqgWgOMEB2ueYGv2qXNPo/jdlzyq+xRXfxTUrfEAg==; 5:Mr45rcPLaUZeS5vGm7//65+FR8KBzzsdEWYXzszLq4yTIccILLwzJrpCeQUYdBbN/Kqg7W008cZpCExhKMwZxH9xnoW60+CK8wLba0zc8bt8jRmPjZBTMopF9Zrfb9613mhtDa268//8dpDXLojBC63KOLMf3zVTmLeyBSFnDDU=; 7:gUl6DFp8GIOavU+EpeI0HlS5d2b9MDpcqKpiHdayLMgMXwJPBV4boFxYAl1nOqHbw0pXS5Dpa1QMCxkq2SxLiMsoDcqVgLfBUO64sYJ3c6tdBDfikX3ir562HZgT+GFvPOeW3/qZZb0yLQErPo0dULAY5tRSIqQ7Ozkod5NOg2w/ONVQNDA1gt3itJ1N/U5Rfbb0a0/u9l+MeEg+r0s3gLP6J9jsuKQYASdapCGif1gNLtcuJRolSVG/ccE3YgvJ SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: aquantia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Sep 2018 10:31:03.4987 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7a253408-8329-4ec6-0818-08d625f6abea X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 83e2e134-991c-4ede-8ced-34d47e38e6b1 X-MS-Exchange-Transport-CrossTenantHeadersStamped: BLUPR0701MB1650 Subject: [dpdk-dev] [PATCH v3 02/22] net/atlantic: logging macroes and some typedefs X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Signed-off-by: Igor Russkikh Signed-off-by: Pavel Belous --- drivers/net/atlantic/atl_logs.h | 31 +++++++++++++++++++++++++++++++ drivers/net/atlantic/atl_types.h | 31 +++++++++++++++++++++++++++++++ 2 files changed, 62 insertions(+) create mode 100644 drivers/net/atlantic/atl_logs.h create mode 100644 drivers/net/atlantic/atl_types.h diff --git a/drivers/net/atlantic/atl_logs.h b/drivers/net/atlantic/atl_logs.h new file mode 100644 index 000000000000..e3dba334fe92 --- /dev/null +++ b/drivers/net/atlantic/atl_logs.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2018 Aquantia Corporation + */ +#ifndef ATL_LOGS_H +#define ATL_LOGS_H + +#include + +extern int atl_logtype_init; + +#define PMD_INIT_LOG(level, fmt, args...) \ + rte_log(RTE_LOG_ ## level, atl_logtype_init, \ + "%s(): " fmt "\n", __func__, ##args) + +#define PMD_INIT_FUNC_TRACE() PMD_INIT_LOG(DEBUG, " >>") + +#define PMD_RX_LOG(level, fmt, args...) \ + RTE_LOG_DP(level, PMD, "%s(): " fmt "\n", __func__, ## args) + +#define PMD_TX_LOG(level, fmt, args...) \ + RTE_LOG_DP(level, PMD, "%s(): " fmt "\n", __func__, ## args) + +extern int atl_logtype_driver; +#define PMD_DRV_LOG_RAW(level, fmt, args...) \ + rte_log(RTE_LOG_ ## level, atl_logtype_driver, "%s(): " fmt, \ + __func__, ## args) + +#define PMD_DRV_LOG(level, fmt, args...) \ + PMD_DRV_LOG_RAW(level, fmt "\n", ## args) + +#endif diff --git a/drivers/net/atlantic/atl_types.h b/drivers/net/atlantic/atl_types.h new file mode 100644 index 000000000000..5a14c2506477 --- /dev/null +++ b/drivers/net/atlantic/atl_types.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2018 Aquantia Corporation + */ +#ifndef ATL_TYPES_H +#define ATL_TYPES_H + +#include +#include +#include +#include + +typedef uint8_t u8; +typedef int8_t s8; +typedef uint16_t u16; +typedef int16_t s16; +typedef uint32_t u32; +typedef int32_t s32; +typedef uint64_t u64; +#ifndef __cplusplus +typedef int bool; +#endif + +#define FALSE 0 +#define TRUE 1 + +#define false 0 +#define true 1 +#define min(a, b) RTE_MIN(a, b) +#define max(a, b) RTE_MAX(a, b) + +#endif From patchwork Sat Sep 29 10:30:17 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Russkikh X-Patchwork-Id: 45667 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 382B21B14F; Sat, 29 Sep 2018 12:31:19 +0200 (CEST) Received: from NAM05-DM3-obe.outbound.protection.outlook.com (mail-eopbgr730082.outbound.protection.outlook.com [40.107.73.82]) by dpdk.org (Postfix) with ESMTP id 8BB8E1B114 for ; Sat, 29 Sep 2018 12:31:17 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=AQUANTIA1COM.onmicrosoft.com; s=selector1-aquantia-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=TcChu27za5IBG2B9IS6oh2ILQY1Pif0X5fUNd11InmA=; b=ZR3KS/Q/Ddx0rnJc+S2niA8LSONu5JeMSkiCuqHUnb8KNXz+qJTCl8t+NXA4wPOmRBLxyV6gg+rKnCsFN1KuZ9PGIdG3TjJ/q0lejGX81beoMveVCGbZppOuMT5xpbRTfN6QTY19otvapwgQK/fpSpE0Viyp96zYLkoiVAYnWYU= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Igor.Russkikh@aquantia.com; Received: from ubuntubox.rdc.aquantia.com (95.79.108.179) by BLUPR0701MB1650.namprd07.prod.outlook.com (2a01:111:e400:58c6::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1185.22; Sat, 29 Sep 2018 10:31:10 +0000 From: Igor Russkikh To: dev@dpdk.org Cc: pavel.belous@aquantia.com, igor.russkikh@aquantia.com, Pavel Belous Date: Sat, 29 Sep 2018 13:30:17 +0300 Message-Id: X-Mailer: git-send-email 2.7.4 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [95.79.108.179] X-ClientProxiedBy: VI1P193CA0009.EURP193.PROD.OUTLOOK.COM (2603:10a6:800:bd::19) To BLUPR0701MB1650.namprd07.prod.outlook.com (2a01:111:e400:58c6::20) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: c31c9dfd-e273-4e39-d367-08d625f6afd5 X-Microsoft-Antispam: BCL:0; PCL:0; RULEID:(7020095)(4652040)(8989299)(4534165)(4627221)(201703031133081)(201702281549075)(8990200)(5600074)(711020)(2017052603328)(7153060)(7193020); SRVR:BLUPR0701MB1650; X-Microsoft-Exchange-Diagnostics: 1; BLUPR0701MB1650; 3:uqlb1vNDjztdZqx2mBKm+V+1/Xc8xkBopQsUdrF7bUPyFsqPb058C9m179zO7pscvadTdx/wPV4r+LrmScquBDxk0KXuZ9/QONJiefXX4UnghtSW73UncibApyn1JUGuP/2TwgSas0HWDLT3JhlqXlV4Te95PWPE+m4/5dWO/P3Vh2om4iCYDGWB9Fqso1OrzprZS064MqWYMdyslGQ1IDJ0aloNqPF3NZK6x5umiYWM5kzzf/+Z5/9vc/j+NIr1; 25:0alj8UODSxG9+JTl00lTEjp/ZabL3CYNc2eHXcihStojNsB+wdeeWpeu5S5iB2QxHmVYBqMM8TW5KQRKkO1eJrzYCWcx8Fk5dqk8pl08QVj8vUWRWmWpYc0Y34nhepVFjbChQBfneH2+N0HIufxoQ95RVAOnVM+aHFzCTfPwIv2y4Mc7L/Go1TXSkX7QEBP61o2zxzkzJ+u4JO/TGfiQQj024wowI1PdSAn6Riy9+Xj+jEo4LGi96ZTnSXirdmVoo9W4uM3D0/v+hyleeOEkA6WP4N2rSUfVXk9sAArExuX7zviXS1i07QxX0wWZ2+3r0vt6dTTo1tHPyuDc0rqwvPeOVwgt5zZQ+kAXjhQ8j2w=; 31:LMf/Eja8B+VQw480fet4761jLvC7JFYf/60xNULoYpourLIY8Du9+0TRVGRySrBmlhXL2qsJJfKhrgPFidtOlkAzvlmg0XrQFWB2mX1LpBwWJtfLlslnX5Hil5wagDIYJz7pcgKQS7+I5Qk6zvv8x+PbQAwQIhJyWUtsu5k9QQwJQse42kNgWjgIdllkNwpygQ8qrsNwg3Tk0p/x+VNhkxWKqGbGThsGNcPoh150/nQ= X-MS-TrafficTypeDiagnostic: BLUPR0701MB1650: X-Microsoft-Exchange-Diagnostics: 1; BLUPR0701MB1650; 20:XLFSNJbWsmUeGr3a/JrrLa1zLPFCg5TezXhxqp2I1QjpYHdw8jE789gN7zoLLQlMGu8qbM9GzAL5u3MY4oJyGdOfzjrrZv4sPngVUoJgT+avs0jV4gms8uZs7xKLSUQHZtQMaalck/s9UwO0JkxGmhKJ+6ibd3pLKA1JdqNhjppNwVY2KM/Yz5U7QevsZHu3Wmr9B6MmJjdQJ0pLXoPbIqPRl1xIQjhdCm+Mt4dRPsRUGDRBDDPL6OBldko++o+F0Zn3HYyCzeMyE5cRMqZHL0qwKS39vILg4rMZgye3Jr5YqfVDru+fq4cekVSi8q5wAMcnSZMCEedV7dwHGVG2sVTUXMykKGZerC3ez+K/Qnd6gBPr/KpdnAzTYaOWirrMiRFczQfHzM5eN5p14mqNRhYKsBiJtQcfZdgBpr9fcEVfV6DM84SX5AAMJjv2icEE9IzSuOatDqwrlnLOTHiUphVAys2/0bF9xtajCd06okLUyYd9Vn45Mv0upYNoHSGm; 4:Y6xzUjWe66RvMIgLPBrYDmOnE+QGPM0MOFTHuVNxslnAQw4AVnbLxZ6SlOQNxASqw4r4DKq+WtonRjflNfEx2UiiSwVq3LepT6iAHwiSuhRHP5y2ViB6FiUJZo9BpPYPL78Qt9eIQIbE4HmyXO98GoaMS4qKLh73mJgNgxwaIF/A9WXz6W/t4OLQc8g4hq6kPTOLrWyWunUi73phBDmZrcXM/6sOJLEklwbVMov3d/9ohS5/tZLrYHclJTfBbJiaE6mLapLKxEXdQKhQ/jY76g== X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-MS-Exchange-SenderADCheck: 1 X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(6040522)(2401047)(8121501046)(5005006)(10201501046)(3002001)(93006095)(93001095)(3231355)(944501410)(52105095)(149066)(150057)(6041310)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123558120)(20161123564045)(20161123562045)(20161123560045)(201708071742011)(7699051); SRVR:BLUPR0701MB1650; BCL:0; PCL:0; RULEID:; SRVR:BLUPR0701MB1650; X-Forefront-PRVS: 0810818DA0 X-Forefront-Antispam-Report: SFV:NSPM; SFS:(10009020)(346002)(136003)(396003)(376002)(39850400004)(366004)(189003)(199004)(16526019)(446003)(76176011)(2906002)(6916009)(97736004)(8676002)(81166006)(81156014)(36756003)(4326008)(316002)(8936002)(50226002)(34290500001)(86362001)(5660300001)(68736007)(16586007)(118296001)(72206003)(3846002)(6116002)(53936002)(386003)(105586002)(6486002)(47776003)(66066001)(486006)(25786009)(305945005)(50466002)(44832011)(956004)(2616005)(26005)(107886003)(52116002)(51416003)(7696005)(186003)(476003)(478600001)(2361001)(7736002)(2351001)(48376002)(106356001)(11346002); DIR:OUT; SFP:1101; SCL:1; SRVR:BLUPR0701MB1650; H:ubuntubox.rdc.aquantia.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; Received-SPF: None (protection.outlook.com: aquantia.com does not designate permitted sender hosts) X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; BLUPR0701MB1650; 23:9yyX/s8fw5BI9YzuLFeswGWf+pIXz+tZOmzS7MU?= 88/a4HNAaIMlvqEWKt3Iy9O7wiLbSfTnuJCmI24QuIAqBWLAY4EMSa7Li+ME4JTiv19iqSM0/CrGeLwDsNMltb4ki9u6fcsH9z2tz8bJogAHxG9gLWfWbvW+QSKWj2w6thPfzQUWg2AgY88DTZC0rrCfV68sDjLqilNGQP9WD1ZjozeoLiZauH+EKDOn+P1Lw9f51L9HKxsljA7UJqy3kbks7EB0u1X8ToDW7E4b6nGeVTh3TwV+H7OoQKWmMTqPMwX77ldyVVCGABAW8y7z3y09Q6AMhaqbP5YMGdDs6cyorP7R6GNyHOjNUqdwQ6+jlXgkYnsuTSntlE/2QT4bVrr/sCjuF8LraEHLwmIw+DmVbULe0LFwkTVNxB3bD6TTy7+4fIe5NqgsXHAYU8HmAlfjb2HqFw7slrLFwZsCry02PAH2R2AwGn+UlwOqLq1OpwhQC7tPrUXWB4F3QBecLaSCaC0tg5DYBXDkJRl0WWxXKol8I/wJW/3EU9n2MH7nmXO7Go68uy2/l8Ur3J7NDkXHoeERMWPsitNbJJhr+D2wXcw31s6WIGyahApOIZz5AkADtLNjEYsbn8OKCE/51CtMiitddc/i6l+K7RZ9T+M0XvNgun14lFSJwZk5zl8Ee29ar5D6anEHKd3RR2fSM2Mbg6y5BtaVfEkGmLA/ZbXpA6vwcg8X+bk7Md3cMFz/CzdFv+myKRuI/07bCE8Umb8jhHE8Z9hB0jOdjxNJGjTosBa7HcYLE9fVrLZfgEYGlIqZ5lJTDnq2QDzUtQ4lmerDD9rroh1Xc878aJ5xYJk7ev7BlwearRs3Er2HqWEqUXo2iAwxca92ccAJCTSneVPxI1C/w6ncEDj+vU8Tc9SUNr3qy4KNhCIlm4Ez2tfwTs07c/192g7D9lYJLiX5Ss7nI3rZxp3lRCJNz8wG1+Hn4O+LnVJMzdmRLDNp6Aqus+WfmHNcGC+Yl8kkNjzLuEOFa0pgfwEeR2TMRMiWPa6mw6XLh4vvbmNUA7cPbTdtbizk4U3fiD53ByhBhHOwBszqfoBS/hN+k5sfmq0bUNFq33EwumYKiHIX2qSDo0PZYydJjYcD3+Pvs6hKGNmZjX5HUVadweaKQF3F4t4DePfsGrSC4FZ/CAEWjx24xNZft9cT7QUychLn1Vuke0O9DcAusBXwKvh9g9EdYUsKiouLKSiYRgDP/NOlwjdiB1gWvvfJgfefBu9+dKyppgyJr3xZh X-Microsoft-Antispam-Message-Info: o3GXdy2jfx6ltqaxFyIMNwDR2WTRhMeEawAbJ2XbCWOJoWNkvZCfKbGdK+/MozLeYtO9VkcPvgBtnLsDw1GeLGa6o/Jkgum46Pg58njJQqTqOLxF+fratzimd1W9VVM8+kT8DBtBU0A77HtqJZzEF5ChhB//7AL3UI9Uopzra0B7E+U16vwSmKnhHz0QUpyQl8dwdh/aQnwSNQb/b3FrwgR2JX3Ak+vHnbw2dX4/p1Qwd+tcs3sYgnc7rLiOK7WKvfAogmfbiaTi1fhVC0F2UHoQvB/MARRkZa9m3DjcanPNUXttzgmArcke0AsE2oRRRadgm4m06PoEP8PDC5jOjvvFQbfmTS7+ZrJ3P2Na3Ag= X-Microsoft-Exchange-Diagnostics: 1; BLUPR0701MB1650; 6:CoP1DgbxWmDSUZRnW4MayuPrGAFiWoChizDs+D6ybZtllghqSZda1mvkJhU8A5lJ3+Dt/ggjaPi6UwkQd90y9Ws9hOlWoFLqGb5zCjC6593qRzaF8ksf+NyHfFBhi5j2fQ90ikmVL66/eEkubrmMFWOHvSGIoKpfbC2uaGf9f9+ctmM2SIB1kJ0q1lkN/I6XGQoTnMiLA6LMSNg1F/VvObfvDXmdH321NAFgRSjYPQeustql6cWK1wVOxk8lOvu64qN2NcBA8g+kr57VhmIXjGicmAov2SQCPKy6qbjF/vqYea07UBBkUzxKtGEdR1EH7LWOi7v4icebtu90HcIXCRhdpGvOfzLzleos7ff2fwXRey9b5a3MtV78VnnUZOkeriQj7HBGw9aetGTUy+jG307S2lCauJTE3DvGPmNzqQ1N5qvXIxQO8O80oCmPhLDv3rxFRTY5FPOB/SZX0fyrlw==; 5:x03N6vL3WS6/XMK4A4EyAhERqV++Rb+wbIZOLf8H0I2T9pC8j7ONtqeHK8Jed4m+4yYWX6k3F/PWQRHAO+tu6tgRUHFrMzpvGR8e7k5BDCEfY8O9zokngf5O8CM0Rtd3l3/Lk34zeNR3oS3Ai7Fq4vyyeXJc0/yZkEmJwy/qP10=; 7:4LAmkT2PawhpQaosG/7Qlf87JrgbjzcZOj1t/fQOCThTW3Fsczf4ykDcA0JRBdwWt/rGJ5DyJWzlOVVBx6h7bbtY9QyK8Wh65Eemf82tr2EAdDpKMfaG1qhBih01mclwquFDMaWqdm4Jb6XmNTsVZYU1TxNQpNtYsOUUObbYMC4p6VG3ELKCRCANY8Ni0EdIagckzs18FBrSb6Zs9PFXxzNTX2fsX63SSbK6PKfNKYXcEx1781nbUUnKsVHgj88Y SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: aquantia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Sep 2018 10:31:10.0928 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c31c9dfd-e273-4e39-d367-08d625f6afd5 X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 83e2e134-991c-4ede-8ced-34d47e38e6b1 X-MS-Exchange-Transport-CrossTenantHeadersStamped: BLUPR0701MB1650 Subject: [dpdk-dev] [PATCH v3 03/22] net/atlantic: hardware register access routines X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Signed-off-by: Igor Russkikh Signed-off-by: Pavel Belous --- drivers/net/atlantic/Makefile | 1 + drivers/net/atlantic/atl_hw_regs.c | 52 +++++++++++++++++++++++++++++++++++++ drivers/net/atlantic/atl_hw_regs.h | 53 ++++++++++++++++++++++++++++++++++++++ drivers/net/atlantic/atl_types.h | 4 +++ drivers/net/atlantic/meson.build | 1 + 5 files changed, 111 insertions(+) create mode 100644 drivers/net/atlantic/atl_hw_regs.c create mode 100644 drivers/net/atlantic/atl_hw_regs.h diff --git a/drivers/net/atlantic/Makefile b/drivers/net/atlantic/Makefile index e42ce5b178ab..8613ced71732 100644 --- a/drivers/net/atlantic/Makefile +++ b/drivers/net/atlantic/Makefile @@ -23,5 +23,6 @@ LDLIBS += -lrte_bus_pci # all source are stored in SRCS-y # SRCS-$(CONFIG_RTE_LIBRTE_ATLANTIC_PMD) += atl_ethdev.c +SRCS-$(CONFIG_RTE_LIBRTE_ATLANTIC_PMD) += atl_hw_regs.c include $(RTE_SDK)/mk/rte.lib.mk diff --git a/drivers/net/atlantic/atl_hw_regs.c b/drivers/net/atlantic/atl_hw_regs.c new file mode 100644 index 000000000000..bd42c8341e2b --- /dev/null +++ b/drivers/net/atlantic/atl_hw_regs.c @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) +/* Copyright (C) 2014-2017 aQuantia Corporation. */ + +/* File aq_hw_utils.c: Definitions of helper functions used across + * hardware layer. + */ + +#include "atl_hw_regs.h" + +#include +#include + +void aq_hw_write_reg_bit(struct aq_hw_s *aq_hw, u32 addr, u32 msk, + u32 shift, u32 val) +{ + if (msk ^ ~0) { + u32 reg_old, reg_new; + + reg_old = aq_hw_read_reg(aq_hw, addr); + reg_new = (reg_old & (~msk)) | (val << shift); + + if (reg_old != reg_new) + aq_hw_write_reg(aq_hw, addr, reg_new); + } else { + aq_hw_write_reg(aq_hw, addr, val); + } +} + +u32 aq_hw_read_reg_bit(struct aq_hw_s *aq_hw, u32 addr, u32 msk, u32 shift) +{ + return ((aq_hw_read_reg(aq_hw, addr) & msk) >> shift); +} + +u32 aq_hw_read_reg(struct aq_hw_s *hw, u32 reg) +{ + return rte_le_to_cpu_32(rte_read32((u8 *)hw->mmio + reg)); +} + +void aq_hw_write_reg(struct aq_hw_s *hw, u32 reg, u32 value) +{ + rte_write32((rte_cpu_to_le_32(value)), (u8 *)hw->mmio + reg); +} + +int aq_hw_err_from_flags(struct aq_hw_s *hw) +{ + int err = 0; + + if (aq_hw_read_reg(hw, 0x10U) == ~0U) + return -ENXIO; + + return err; +} diff --git a/drivers/net/atlantic/atl_hw_regs.h b/drivers/net/atlantic/atl_hw_regs.h new file mode 100644 index 000000000000..a2d6ca804e5e --- /dev/null +++ b/drivers/net/atlantic/atl_hw_regs.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) */ +/* Copyright (C) 2014-2017 aQuantia Corporation. */ + +/* File aq_hw_utils.h: Declaration of helper functions used across hardware + * layer. + */ + +#ifndef AQ_HW_UTILS_H +#define AQ_HW_UTILS_H + +#include +#include +#include +#include +#include +#include "atl_common.h" +#include "atl_types.h" + + +#ifndef HIDWORD +#define LODWORD(_qw) ((u32)(_qw)) +#define HIDWORD(_qw) ((u32)(((_qw) >> 32) & 0xffffffff)) +#endif + +#define AQ_HW_SLEEP(_US_) rte_delay_ms(_US_) + +#define mdelay rte_delay_ms +#define udelay rte_delay_us +#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0])) +#define BIT(x) (1UL << (x)) + +#define AQ_HW_WAIT_FOR(_B_, _US_, _N_) \ +do { \ + unsigned int AQ_HW_WAIT_FOR_i; \ + for (AQ_HW_WAIT_FOR_i = _N_; (!(_B_)) && (AQ_HW_WAIT_FOR_i);\ + --AQ_HW_WAIT_FOR_i) {\ + udelay(_US_); \ + } \ + if (!AQ_HW_WAIT_FOR_i) {\ + err = -ETIMEDOUT; \ + } \ +} while (0) + +#define ATL_WRITE_FLUSH(aq_hw) { (void)aq_hw_read_reg(aq_hw, 0x10); } + +void aq_hw_write_reg_bit(struct aq_hw_s *aq_hw, u32 addr, u32 msk, + u32 shift, u32 val); +u32 aq_hw_read_reg_bit(struct aq_hw_s *aq_hw, u32 addr, u32 msk, u32 shift); +u32 aq_hw_read_reg(struct aq_hw_s *hw, u32 reg); +void aq_hw_write_reg(struct aq_hw_s *hw, u32 reg, u32 value); +int aq_hw_err_from_flags(struct aq_hw_s *hw); + +#endif /* AQ_HW_UTILS_H */ diff --git a/drivers/net/atlantic/atl_types.h b/drivers/net/atlantic/atl_types.h index 5a14c2506477..83fb377add47 100644 --- a/drivers/net/atlantic/atl_types.h +++ b/drivers/net/atlantic/atl_types.h @@ -28,4 +28,8 @@ typedef int bool; #define min(a, b) RTE_MIN(a, b) #define max(a, b) RTE_MAX(a, b) +struct aq_hw_s { + void *mmio; +}; + #endif diff --git a/drivers/net/atlantic/meson.build b/drivers/net/atlantic/meson.build index 90ee5288206a..7fdde358ba21 100644 --- a/drivers/net/atlantic/meson.build +++ b/drivers/net/atlantic/meson.build @@ -3,6 +3,7 @@ sources = files( 'atl_ethdev.c', + 'atl_hw_regs.c', ) deps += ['eal'] From patchwork Sat Sep 29 10:30:18 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Russkikh X-Patchwork-Id: 45668 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 16F821B0FA; Sat, 29 Sep 2018 12:31:28 +0200 (CEST) Received: from NAM05-DM3-obe.outbound.protection.outlook.com (mail-eopbgr730089.outbound.protection.outlook.com [40.107.73.89]) by dpdk.org (Postfix) with ESMTP id A133B1B130 for ; Sat, 29 Sep 2018 12:31:26 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=AQUANTIA1COM.onmicrosoft.com; s=selector1-aquantia-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Qg/zIunY6IZ+ZKqIrAeMIFxUxGd/Fd2bcq6Tef4LHR8=; b=u3e5AAJMy/iwb7JyFrspq9i+qJ1aX5wdHSnK0esDgEtgzcb/Q+SuJnxvEXVCmkzqbZt3HG6lrx7OJ0VAkamU36L9+jCELFR7LLI22iVaIjbuD+K+VJElnSk5gzE0Hv/+4V5AFGbSyxUL0CMXvS4Do2zDtx20AhhGj4joizTT21E= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Igor.Russkikh@aquantia.com; Received: from ubuntubox.rdc.aquantia.com (95.79.108.179) by BLUPR0701MB1650.namprd07.prod.outlook.com (2a01:111:e400:58c6::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1185.22; Sat, 29 Sep 2018 10:31:16 +0000 From: Igor Russkikh To: dev@dpdk.org Cc: pavel.belous@aquantia.com, igor.russkikh@aquantia.com, Pavel Belous Date: Sat, 29 Sep 2018 13:30:18 +0300 Message-Id: X-Mailer: git-send-email 2.7.4 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [95.79.108.179] X-ClientProxiedBy: VI1P193CA0009.EURP193.PROD.OUTLOOK.COM (2603:10a6:800:bd::19) To BLUPR0701MB1650.namprd07.prod.outlook.com (2a01:111:e400:58c6::20) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 7f9f49cb-cb0e-4ce6-c5dd-08d625f6b3c8 X-Microsoft-Antispam: BCL:0; PCL:0; RULEID:(7020095)(4652040)(8989299)(4534165)(4627221)(201703031133081)(201702281549075)(8990200)(5600074)(711020)(2017052603328)(7153060)(7193020); SRVR:BLUPR0701MB1650; X-Microsoft-Exchange-Diagnostics: 1; BLUPR0701MB1650; 3:Av61Xt8r3CIWO3mt6TgN/gNHaSVQ4Q9/VVODVkB8nKnjMpUnQIydSjKO+LfxysCqhf2vsdoxjVQQxnu2HdQ0T3mu6tKtdZxPSrTtArDUzMCN/xdqY0UwOY9ZNBtfnidDqesYqEpTXl4+LVhqObUfZZoXJ3jdLXG5EphCf0Fg1SjomzPdok+2gaKRpqz/licxJvWAJLpTyZQRcXP7f18+rIyA7S6U1Ft6T3qLCMWOs5C5UYIGVX18ALcauiA9Gm1+; 25:WlBWCPnMhvQeoe5oFXjkbHhAKz1b+F5Tre7CWeuaz7aznbs1y3kTcjYZfxcOWywLFqXT9gsDtssaKsMAV6t5JkfvbdZjelBvuGzQ56VWJclB7mzzaUcIstK0/HqyjhBZfLwWmIMGHM+qk/0geOy+lBy7K+pQsOdlh1m4E6V6YEvBa+VmlZXRt2al/Jwk5ezAs/73vNvixtcaT2eUrLvYzNlLxRlVpSzQXaG9YSnqtyrvP29qeFLCahHlyErjz7roZ5em4/6OcgxaykW0ftKJH1G2dz1UKNu/jsqfXcQ+LET78XXWXw2P/lsPQrtgUdSrV+1XkbxkPzLA+osbzMaBCy+tU+U5PHbtYO+SDtqBdI0=; 31:ZTsPcF7CjoExy2UJAnBdVdNRmF4AiM5B2jQ2mlwjlJCo3vK9IobepHIBxSt+p7fhR4B2TXGRrrZOKtNXQSuyb/HNm8zSNLEvzlc5ntIAgiL3V+MtNMMTq1AS0HMf1P9RS6sOdV+XcQyfO5vo+S4TsVtzmT2hPTLjXjR0amkK4zhLcs+POnbT1MnW5ddICH8rR61pPwQIEAVVxOgaYeSO2cHYFfl+HJwh4nI+OycJwZk= X-MS-TrafficTypeDiagnostic: BLUPR0701MB1650: X-Microsoft-Exchange-Diagnostics: 1; BLUPR0701MB1650; 20:08Xf7yPffX0+gyRx54/1ip0BbK4F84qEcxsxWKdR8w6xFbWwoZjYTdUVDLeCvDE2ap/JBSdFyBIpgDlpePtr5OfYdY8o110YXWhcPF8Iy2/c1WhcG1EceElqElPl6COPu4i83HEJh8UfG5pfYRTsdPeNNm5HOb+DhofiiOBrXjqVIBiY3fyoBIkeZYf72E4+C6VxeelvtDYPaFT6dUZ8sq35RVSkY5Na+VADdh0FaG5fYTRdjy9+wCLUvMJ3YzlA01/JkGOcGFZjn4CCe8GW9a6D8hr33IuZG95Vm75DpghBou4X6/4GG3CNuR21WHGA6ypG4Ra+WMbkUj9hC0ArWwqrqLvoo5TEjVgRVkoGNnEhPt43OapG5LMbv5KZ2qxpM9wq1myJjlycdwRL2q5S9yARUrKie7rDZKmPJQJh6WEBmBbdr1O8/AMQW8QIfO8bqfwTFBPv4pMiQw1bUsL+Oyb7Yxma9oP92+1pIkvh8iVyj8Wiit8h4V16b1wjOLQY; 4:n2a98QNXywUqGkZyHpk7UiSebjrS0wbqggLkOlusgS/LVc03G/E77iAXnyvWJOJ/IYjcSagAjEXXTAMN3cMTjEdpvjibXbUKyZUQh6UcvUAITfZp55hINHhC7pl4Ozi9uV+KQD2KSGZFTwFGbE3lyLjPQwEGv2t62G2fm3lkK1fC3RLCTYh7FkPvGlGovFOzMJDqzfevPXaq2oO68NmFO4eZtT4cbvxCujJnxw101udVlv1KXw6DCrQYrhgh6Kfj7Zf17kF1sR7fqhawPUWsow== X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-MS-Exchange-SenderADCheck: 1 X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(6040522)(2401047)(8121501046)(5005006)(10201501046)(3002001)(93006095)(93001095)(3231355)(944501410)(52105095)(149066)(150057)(6041310)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123558120)(20161123564045)(20161123562045)(20161123560045)(201708071742011)(7699051); SRVR:BLUPR0701MB1650; BCL:0; PCL:0; RULEID:; SRVR:BLUPR0701MB1650; X-Forefront-PRVS: 0810818DA0 X-Forefront-Antispam-Report: SFV:NSPM; SFS:(10009020)(346002)(136003)(396003)(376002)(39850400004)(366004)(189003)(199004)(16526019)(14444005)(446003)(76176011)(2906002)(6916009)(97736004)(8676002)(81166006)(81156014)(36756003)(4326008)(316002)(8936002)(50226002)(34290500001)(575784001)(86362001)(5660300001)(68736007)(16586007)(118296001)(53946003)(16200700003)(72206003)(3846002)(6116002)(53936002)(386003)(105586002)(114624004)(6486002)(47776003)(66066001)(486006)(25786009)(305945005)(50466002)(44832011)(956004)(2616005)(26005)(107886003)(52116002)(51416003)(7696005)(186003)(476003)(478600001)(2361001)(7736002)(2351001)(48376002)(106356001)(11346002)(559001)(569006); DIR:OUT; SFP:1101; SCL:1; SRVR:BLUPR0701MB1650; H:ubuntubox.rdc.aquantia.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; Received-SPF: None (protection.outlook.com: aquantia.com does not designate permitted sender hosts) X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; BLUPR0701MB1650; 23:uWCKuvEc1Y/VbxUak22ucR0ubsYBxHMC3WyWFk3?= dMPjMn/iysEi2Dsurl9/96jHy1zw/DXE9zhbPLKUK68OtqnxBybrR/Hw/eL+gyGuZLGiOOsPobO/s8lAPeQUdF4YmETDD0dWfwI0sww1J4R/6PP3wXUK/6MA7EYf5pJw6fZWrm7J7cIB/+MeD2H5pzCRbIQaqKDho0jljDD0rpMdRMSAfl363R8NoJfTEbdT8UyetiTQkmT5G+9FQRKDCdsF5Ek8qJ1m/8aeLopAgBIrT4Yp/CDTc/O5RL8eT3Ass+tLOf4fBY9Q3eegNasUTilRHzrklyFWE8qeciO86KCMZMfxq1c2l8+2EfSaP+syrcfuiw0DZycLeTbmDU5dxcJlDKU3nS2+0spgTK4Ct5VncW+LQU9wuA6Tnub2Mdw3I+T8wwMLMPUIq3SJPVhu1/FLKJi51QNAayhg52PXYF8KSpV4hN87+0MEO9TsxhnKeJmYg0HTvDEGELxaimD1V8rNnOJxK3vv0MSavXRrneFbKFx8kc9Zlf172F7FnfumxHqB8pQ0cxzdqxl4M+QfeUOPl7obm7er6Z+ABbLn93Xte6FfkpfT716DvpxITd9bWRsQdJTsRb4aUCN7uBYyo3gPSgFiwNrzNVwWkz6ENpOkhCFpwDxp4IYcO2fzH72Qylu0C6Q1ha3VlD9VDlZJIuLUSWmof59jvu5Qjel55E8czLVQZ2gd000+vvyu5UHZAShdsaCfLehE5SGJXt+q8e0NowpRSQYgDzs7azoMs8cpNvhvgll85czz/H9pYMkzsHte3dPpeytrIcTUC5F9Y0YZeJGAHpv8sQowykBXtii1GbgoAJy2et2RrbhbNqIqWu0PrVpaiG/Ao5PcylT2RYCCFJnWF+fmXaDOEthrxJQmsu/3VjeKt4SJtwrxVljf1FnCeCCdMrfsObDEIHikxIU40WBfR/AvrwVotiesNfkcJSxK/OUlqg1l8U91oJRDKWOfyqjfNN3NEDsSdMBqEK41FY+HvHL9lFtF8k+BaRE1toh3MU4qwr6CEggzXzz7jbYyW/dy2OztNhQQ8U0mTM2kJNpVX7sf2aRYogSTX2cYqBqsIiTF5g2ZEi3NiI1CbNNbIk1Ft5ciHpHks7ia6AE0mvQPNU3j5uQk4YYp+C3mN/6k+ieywZ7L7xjeS1sul2e20mflFmT/+aiUu3cFg2E6ju68PuI2qbsTRJYW90guQ4X6q1R8bHvv/VSOfdnbtOSFwrBRqjdDwYpkZpNRaXpPxXrxie7gb2HXn2GtEJl4rGrlnRWL4D11sqxtFd0GtV3qx8DOSCg7BBuSVN2BGD1VWOOWUU09riVYkw5AGRy1ckQLcwWtcX7mrovmHk+vJqkMpM1Fa73wL6oQKtdQh90z/0B+3sXyjoBL4Qr1BK03Tew== X-Microsoft-Antispam-Message-Info: XVyhw+v/hUDEAnbi1LcRU8x4Id7B1VZRVJATClHAD9kGfDP5qQcLW7UIv5Gz6Xt6eAsQvPOggIByopHK7crNsvueCIYODzzWRoMZ3hS/53XtYc4ipjlkZxak+8A9Mzw9nohCpL5jXaM1nA32gDnajfzLRDNTogEn5y6mDg7ibW+5L9KY1K/KZ1GOtEQI2eLWmGdW/1GJBpCYQJiwQIW6iJ2ipoyz7Mwg2LWKDWR7eLKicBM8f488STVP4nkD3wnuKfcGH+/37KZDLkfIqtl0T6+gMc323nMVrPFllEPur1wrDevwIQJcWVAQMzA7C8sYFq2lNb0I6n92Kl+wdFfn1LlRc6c5EUCXvLgSHqAPYk4= X-Microsoft-Exchange-Diagnostics: 1; BLUPR0701MB1650; 6:SI2EybOXD70KCZjDTfbr0dXM6ZM7+CxguzVd2nbdUFnxp7GA4Z67bUrjHWKWtjCauFQHu2dUpmRL5Zky18NntP+X+NaFG6pBZZ+0Ot33YAkXezJL8dKwOlVLHetWvlAFhuSFjFLLbj+4KWHs+Wi4spVtDiw8Zl0yBOSCU5wY3vNqS8zGllh9HMCMD5dXy7qdcnAQAvlUewG5U116nuMx9kAD8vwr6vCPFT0YEtl57bJrxuBG/c266cYyOH42a6bkSsip9nSN5Cj0VmTn9R2RDqTnqVZJefVM1HB9zQWrG+l9JNDkOCMKf0t7zcY3UWJKzmJ7X3maovDitA2eV6XwddXrQKEKFG54kIf1zyNA7mnfhJ48cvuoWbE+CEug/l/owJ8Ttk40bEvzwI8pJTj8GB5jn269sqMqed+fbAqP28IAlvJgamT15cEfdaLcer9ACOkS5ocxfq+kpJKzL0dYRA==; 5:4IIfQA2qYaqx2d2BEKd+SGsFqPo76hsOG8Ic/WsXvokVawViw90yeoeD0PYGakmf5/oCfECTqHqSQ1Smo27G6kY2trxTUkXx9mLDNxI+oxWxL5n5omM9/oGfc0NwSucMekltsLWKvkPtxRhRnIy6QYN8DJzLfKpRQZDh/B4f0f0=; 7:UCZY50NNFnbnSolAE3aOhcC3/xNjYLmeFwUQtxrtcd+2DLA0NARQQFZB3APPhb/0WT/jJD+uXFY750UilNsKD9p29ooIZ6+7B1toP3k/LHrRWq4TRfDUPtzldgEPUY1SP635Kvh6mG/WUr2CaS5A0nGaYIASkgLNHoMi1JRNDNBasySePDyp0rvro0r1ESDpCIuR4L9sosV6EsNJwqVByxACRSajpVryu77BRv61XKBW8Uwn8ablBDyZ72DEo/RM SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: aquantia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Sep 2018 10:31:16.7494 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7f9f49cb-cb0e-4ce6-c5dd-08d625f6b3c8 X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 83e2e134-991c-4ede-8ced-34d47e38e6b1 X-MS-Exchange-Transport-CrossTenantHeadersStamped: BLUPR0701MB1650 Subject: [dpdk-dev] [PATCH v3 04/22] net/atlantic: hw_atl register declarations X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This hw_atl layer is maintained in sync with linux kernel driver. It will generally be in sync with linux upstream. Signed-off-by: Igor Russkikh Signed-off-by: Pavel Belous --- drivers/net/atlantic/Makefile | 3 + drivers/net/atlantic/hw_atl/hw_atl_llh.c | 1490 +++++++++++++ drivers/net/atlantic/hw_atl/hw_atl_llh.h | 714 ++++++ drivers/net/atlantic/hw_atl/hw_atl_llh_internal.h | 2407 +++++++++++++++++++++ drivers/net/atlantic/meson.build | 3 + 5 files changed, 4617 insertions(+) create mode 100644 drivers/net/atlantic/hw_atl/hw_atl_llh.c create mode 100644 drivers/net/atlantic/hw_atl/hw_atl_llh.h create mode 100644 drivers/net/atlantic/hw_atl/hw_atl_llh_internal.h diff --git a/drivers/net/atlantic/Makefile b/drivers/net/atlantic/Makefile index 8613ced71732..cae317badc0c 100644 --- a/drivers/net/atlantic/Makefile +++ b/drivers/net/atlantic/Makefile @@ -19,10 +19,13 @@ LDLIBS += -lrte_eal LDLIBS += -lrte_ethdev -lrte_net LDLIBS += -lrte_bus_pci +VPATH += $(SRCDIR)/hw_atl + # # all source are stored in SRCS-y # SRCS-$(CONFIG_RTE_LIBRTE_ATLANTIC_PMD) += atl_ethdev.c SRCS-$(CONFIG_RTE_LIBRTE_ATLANTIC_PMD) += atl_hw_regs.c +SRCS-$(CONFIG_RTE_LIBRTE_ATLANTIC_PMD) += hw_atl_llh.c include $(RTE_SDK)/mk/rte.lib.mk diff --git a/drivers/net/atlantic/hw_atl/hw_atl_llh.c b/drivers/net/atlantic/hw_atl/hw_atl_llh.c new file mode 100644 index 000000000000..d7daf57d68ed --- /dev/null +++ b/drivers/net/atlantic/hw_atl/hw_atl_llh.c @@ -0,0 +1,1490 @@ +// SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) +/* Copyright (C) 2014-2017 aQuantia Corporation. */ + +/* File hw_atl_llh.c: Definitions of bitfield and register access functions for + * Atlantic registers. + */ + +#include "hw_atl_llh.h" + +#include "../atl_hw_regs.h" +#include "hw_atl_llh_internal.h" + +/* global */ +void hw_atl_reg_glb_cpu_sem_set(struct aq_hw_s *aq_hw, u32 glb_cpu_sem, + u32 semaphore) +{ + aq_hw_write_reg(aq_hw, HW_ATL_GLB_CPU_SEM_ADR(semaphore), glb_cpu_sem); +} + +u32 hw_atl_reg_glb_cpu_sem_get(struct aq_hw_s *aq_hw, u32 semaphore) +{ + return aq_hw_read_reg(aq_hw, HW_ATL_GLB_CPU_SEM_ADR(semaphore)); +} + +void hw_atl_glb_glb_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 glb_reg_res_dis) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_GLB_REG_RES_DIS_ADR, + HW_ATL_GLB_REG_RES_DIS_MSK, + HW_ATL_GLB_REG_RES_DIS_SHIFT, + glb_reg_res_dis); +} + +void hw_atl_glb_soft_res_set(struct aq_hw_s *aq_hw, u32 soft_res) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_GLB_SOFT_RES_ADR, + HW_ATL_GLB_SOFT_RES_MSK, + HW_ATL_GLB_SOFT_RES_SHIFT, soft_res); +} + +u32 hw_atl_glb_soft_res_get(struct aq_hw_s *aq_hw) +{ + return aq_hw_read_reg_bit(aq_hw, HW_ATL_GLB_SOFT_RES_ADR, + HW_ATL_GLB_SOFT_RES_MSK, + HW_ATL_GLB_SOFT_RES_SHIFT); +} + +u32 hw_atl_reg_glb_mif_id_get(struct aq_hw_s *aq_hw) +{ + return aq_hw_read_reg(aq_hw, HW_ATL_GLB_MIF_ID_ADR); +} + +/* stats */ +u32 hw_atl_rpb_rx_dma_drop_pkt_cnt_get(struct aq_hw_s *aq_hw) +{ + return aq_hw_read_reg(aq_hw, HW_ATL_RPB_RX_DMA_DROP_PKT_CNT_ADR); +} + +u32 hw_atl_stats_rx_dma_good_octet_counterlsw_get(struct aq_hw_s *aq_hw) +{ + return aq_hw_read_reg(aq_hw, HW_ATL_STATS_RX_DMA_GOOD_OCTET_COUNTERLSW); +} + +u32 hw_atl_stats_rx_dma_good_pkt_counterlsw_get(struct aq_hw_s *aq_hw) +{ + return aq_hw_read_reg(aq_hw, HW_ATL_STATS_RX_DMA_GOOD_PKT_COUNTERLSW); +} + +u32 hw_atl_stats_tx_dma_good_octet_counterlsw_get(struct aq_hw_s *aq_hw) +{ + return aq_hw_read_reg(aq_hw, HW_ATL_STATS_TX_DMA_GOOD_OCTET_COUNTERLSW); +} + +u32 hw_atl_stats_tx_dma_good_pkt_counterlsw_get(struct aq_hw_s *aq_hw) +{ + return aq_hw_read_reg(aq_hw, HW_ATL_STATS_TX_DMA_GOOD_PKT_COUNTERLSW); +} + +u32 hw_atl_stats_rx_dma_good_octet_countermsw_get(struct aq_hw_s *aq_hw) +{ + return aq_hw_read_reg(aq_hw, HW_ATL_STATS_RX_DMA_GOOD_OCTET_COUNTERMSW); +} + +u32 hw_atl_stats_rx_dma_good_pkt_countermsw_get(struct aq_hw_s *aq_hw) +{ + return aq_hw_read_reg(aq_hw, HW_ATL_STATS_RX_DMA_GOOD_PKT_COUNTERMSW); +} + +u32 hw_atl_stats_tx_dma_good_octet_countermsw_get(struct aq_hw_s *aq_hw) +{ + return aq_hw_read_reg(aq_hw, HW_ATL_STATS_TX_DMA_GOOD_OCTET_COUNTERMSW); +} + +u32 hw_atl_stats_tx_dma_good_pkt_countermsw_get(struct aq_hw_s *aq_hw) +{ + return aq_hw_read_reg(aq_hw, HW_ATL_STATS_TX_DMA_GOOD_PKT_COUNTERMSW); +} + +/* interrupt */ +void hw_atl_itr_irq_auto_masklsw_set(struct aq_hw_s *aq_hw, + u32 irq_auto_masklsw) +{ + aq_hw_write_reg(aq_hw, HW_ATL_ITR_IAMRLSW_ADR, irq_auto_masklsw); +} + +void hw_atl_itr_irq_map_en_rx_set(struct aq_hw_s *aq_hw, u32 irq_map_en_rx, + u32 rx) +{ +/* register address for bitfield imr_rx{r}_en */ + static const u32 itr_imr_rxren_adr[32] = { + 0x00002100U, 0x00002100U, 0x00002104U, 0x00002104U, + 0x00002108U, 0x00002108U, 0x0000210CU, 0x0000210CU, + 0x00002110U, 0x00002110U, 0x00002114U, 0x00002114U, + 0x00002118U, 0x00002118U, 0x0000211CU, 0x0000211CU, + 0x00002120U, 0x00002120U, 0x00002124U, 0x00002124U, + 0x00002128U, 0x00002128U, 0x0000212CU, 0x0000212CU, + 0x00002130U, 0x00002130U, 0x00002134U, 0x00002134U, + 0x00002138U, 0x00002138U, 0x0000213CU, 0x0000213CU + }; + +/* bitmask for bitfield imr_rx{r}_en */ + static const u32 itr_imr_rxren_msk[32] = { + 0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U, + 0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U, + 0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U, + 0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U, + 0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U, + 0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U, + 0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U, + 0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U + }; + +/* lower bit position of bitfield imr_rx{r}_en */ + static const u32 itr_imr_rxren_shift[32] = { + 15U, 7U, 15U, 7U, 15U, 7U, 15U, 7U, + 15U, 7U, 15U, 7U, 15U, 7U, 15U, 7U, + 15U, 7U, 15U, 7U, 15U, 7U, 15U, 7U, + 15U, 7U, 15U, 7U, 15U, 7U, 15U, 7U + }; + + aq_hw_write_reg_bit(aq_hw, itr_imr_rxren_adr[rx], + itr_imr_rxren_msk[rx], + itr_imr_rxren_shift[rx], + irq_map_en_rx); +} + +void hw_atl_itr_irq_map_en_tx_set(struct aq_hw_s *aq_hw, u32 irq_map_en_tx, + u32 tx) +{ +/* register address for bitfield imr_tx{t}_en */ + static const u32 itr_imr_txten_adr[32] = { + 0x00002100U, 0x00002100U, 0x00002104U, 0x00002104U, + 0x00002108U, 0x00002108U, 0x0000210CU, 0x0000210CU, + 0x00002110U, 0x00002110U, 0x00002114U, 0x00002114U, + 0x00002118U, 0x00002118U, 0x0000211CU, 0x0000211CU, + 0x00002120U, 0x00002120U, 0x00002124U, 0x00002124U, + 0x00002128U, 0x00002128U, 0x0000212CU, 0x0000212CU, + 0x00002130U, 0x00002130U, 0x00002134U, 0x00002134U, + 0x00002138U, 0x00002138U, 0x0000213CU, 0x0000213CU + }; + +/* bitmask for bitfield imr_tx{t}_en */ + static const u32 itr_imr_txten_msk[32] = { + 0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U, + 0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U, + 0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U, + 0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U, + 0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U, + 0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U, + 0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U, + 0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U + }; + +/* lower bit position of bitfield imr_tx{t}_en */ + static const u32 itr_imr_txten_shift[32] = { + 31U, 23U, 31U, 23U, 31U, 23U, 31U, 23U, + 31U, 23U, 31U, 23U, 31U, 23U, 31U, 23U, + 31U, 23U, 31U, 23U, 31U, 23U, 31U, 23U, + 31U, 23U, 31U, 23U, 31U, 23U, 31U, 23U + }; + + aq_hw_write_reg_bit(aq_hw, itr_imr_txten_adr[tx], + itr_imr_txten_msk[tx], + itr_imr_txten_shift[tx], + irq_map_en_tx); +} + +void hw_atl_itr_irq_map_rx_set(struct aq_hw_s *aq_hw, u32 irq_map_rx, u32 rx) +{ +/* register address for bitfield imr_rx{r}[4:0] */ + static const u32 itr_imr_rxr_adr[32] = { + 0x00002100U, 0x00002100U, 0x00002104U, 0x00002104U, + 0x00002108U, 0x00002108U, 0x0000210CU, 0x0000210CU, + 0x00002110U, 0x00002110U, 0x00002114U, 0x00002114U, + 0x00002118U, 0x00002118U, 0x0000211CU, 0x0000211CU, + 0x00002120U, 0x00002120U, 0x00002124U, 0x00002124U, + 0x00002128U, 0x00002128U, 0x0000212CU, 0x0000212CU, + 0x00002130U, 0x00002130U, 0x00002134U, 0x00002134U, + 0x00002138U, 0x00002138U, 0x0000213CU, 0x0000213CU + }; + +/* bitmask for bitfield imr_rx{r}[4:0] */ + static const u32 itr_imr_rxr_msk[32] = { + 0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU, + 0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU, + 0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU, + 0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU, + 0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU, + 0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU, + 0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU, + 0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU + }; + +/* lower bit position of bitfield imr_rx{r}[4:0] */ + static const u32 itr_imr_rxr_shift[32] = { + 8U, 0U, 8U, 0U, 8U, 0U, 8U, 0U, + 8U, 0U, 8U, 0U, 8U, 0U, 8U, 0U, + 8U, 0U, 8U, 0U, 8U, 0U, 8U, 0U, + 8U, 0U, 8U, 0U, 8U, 0U, 8U, 0U + }; + + aq_hw_write_reg_bit(aq_hw, itr_imr_rxr_adr[rx], + itr_imr_rxr_msk[rx], + itr_imr_rxr_shift[rx], + irq_map_rx); +} + +void hw_atl_itr_irq_map_tx_set(struct aq_hw_s *aq_hw, u32 irq_map_tx, u32 tx) +{ +/* register address for bitfield imr_tx{t}[4:0] */ + static const u32 itr_imr_txt_adr[32] = { + 0x00002100U, 0x00002100U, 0x00002104U, 0x00002104U, + 0x00002108U, 0x00002108U, 0x0000210CU, 0x0000210CU, + 0x00002110U, 0x00002110U, 0x00002114U, 0x00002114U, + 0x00002118U, 0x00002118U, 0x0000211CU, 0x0000211CU, + 0x00002120U, 0x00002120U, 0x00002124U, 0x00002124U, + 0x00002128U, 0x00002128U, 0x0000212CU, 0x0000212CU, + 0x00002130U, 0x00002130U, 0x00002134U, 0x00002134U, + 0x00002138U, 0x00002138U, 0x0000213CU, 0x0000213CU + }; + +/* bitmask for bitfield imr_tx{t}[4:0] */ + static const u32 itr_imr_txt_msk[32] = { + 0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U, + 0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U, + 0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U, + 0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U, + 0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U, + 0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U, + 0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U, + 0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U + }; + +/* lower bit position of bitfield imr_tx{t}[4:0] */ + static const u32 itr_imr_txt_shift[32] = { + 24U, 16U, 24U, 16U, 24U, 16U, 24U, 16U, + 24U, 16U, 24U, 16U, 24U, 16U, 24U, 16U, + 24U, 16U, 24U, 16U, 24U, 16U, 24U, 16U, + 24U, 16U, 24U, 16U, 24U, 16U, 24U, 16U + }; + + aq_hw_write_reg_bit(aq_hw, itr_imr_txt_adr[tx], + itr_imr_txt_msk[tx], + itr_imr_txt_shift[tx], + irq_map_tx); +} + +void hw_atl_itr_irq_msk_clearlsw_set(struct aq_hw_s *aq_hw, + u32 irq_msk_clearlsw) +{ + aq_hw_write_reg(aq_hw, HW_ATL_ITR_IMCRLSW_ADR, irq_msk_clearlsw); +} + +void hw_atl_itr_irq_msk_setlsw_set(struct aq_hw_s *aq_hw, u32 irq_msk_setlsw) +{ + aq_hw_write_reg(aq_hw, HW_ATL_ITR_IMSRLSW_ADR, irq_msk_setlsw); +} + +void hw_atl_itr_irq_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 irq_reg_res_dis) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_ITR_REG_RES_DSBL_ADR, + HW_ATL_ITR_REG_RES_DSBL_MSK, + HW_ATL_ITR_REG_RES_DSBL_SHIFT, irq_reg_res_dis); +} + +void hw_atl_itr_irq_status_clearlsw_set(struct aq_hw_s *aq_hw, + u32 irq_status_clearlsw) +{ + aq_hw_write_reg(aq_hw, HW_ATL_ITR_ISCRLSW_ADR, irq_status_clearlsw); +} + +u32 hw_atl_itr_irq_statuslsw_get(struct aq_hw_s *aq_hw) +{ + return aq_hw_read_reg(aq_hw, HW_ATL_ITR_ISRLSW_ADR); +} + +u32 hw_atl_itr_res_irq_get(struct aq_hw_s *aq_hw) +{ + return aq_hw_read_reg_bit(aq_hw, HW_ATL_ITR_RES_ADR, HW_ATL_ITR_RES_MSK, + HW_ATL_ITR_RES_SHIFT); +} + +void hw_atl_itr_res_irq_set(struct aq_hw_s *aq_hw, u32 res_irq) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_ITR_RES_ADR, HW_ATL_ITR_RES_MSK, + HW_ATL_ITR_RES_SHIFT, res_irq); +} + +/* rdm */ +void hw_atl_rdm_cpu_id_set(struct aq_hw_s *aq_hw, u32 cpuid, u32 dca) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCADCPUID_ADR(dca), + HW_ATL_RDM_DCADCPUID_MSK, + HW_ATL_RDM_DCADCPUID_SHIFT, cpuid); +} + +void hw_atl_rdm_rx_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_dca_en) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCA_EN_ADR, HW_ATL_RDM_DCA_EN_MSK, + HW_ATL_RDM_DCA_EN_SHIFT, rx_dca_en); +} + +void hw_atl_rdm_rx_dca_mode_set(struct aq_hw_s *aq_hw, u32 rx_dca_mode) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCA_MODE_ADR, + HW_ATL_RDM_DCA_MODE_MSK, + HW_ATL_RDM_DCA_MODE_SHIFT, rx_dca_mode); +} + +void hw_atl_rdm_rx_desc_data_buff_size_set(struct aq_hw_s *aq_hw, + u32 rx_desc_data_buff_size, + u32 descriptor) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDDATA_SIZE_ADR(descriptor), + HW_ATL_RDM_DESCDDATA_SIZE_MSK, + HW_ATL_RDM_DESCDDATA_SIZE_SHIFT, + rx_desc_data_buff_size); +} + +void hw_atl_rdm_rx_desc_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_desc_dca_en, + u32 dca) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCADDESC_EN_ADR(dca), + HW_ATL_RDM_DCADDESC_EN_MSK, + HW_ATL_RDM_DCADDESC_EN_SHIFT, + rx_desc_dca_en); +} + +void hw_atl_rdm_rx_desc_en_set(struct aq_hw_s *aq_hw, u32 rx_desc_en, + u32 descriptor) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDEN_ADR(descriptor), + HW_ATL_RDM_DESCDEN_MSK, + HW_ATL_RDM_DESCDEN_SHIFT, + rx_desc_en); +} + +void hw_atl_rdm_rx_desc_head_buff_size_set(struct aq_hw_s *aq_hw, + u32 rx_desc_head_buff_size, + u32 descriptor) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDHDR_SIZE_ADR(descriptor), + HW_ATL_RDM_DESCDHDR_SIZE_MSK, + HW_ATL_RDM_DESCDHDR_SIZE_SHIFT, + rx_desc_head_buff_size); +} + +void hw_atl_rdm_rx_desc_head_splitting_set(struct aq_hw_s *aq_hw, + u32 rx_desc_head_splitting, + u32 descriptor) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDHDR_SPLIT_ADR(descriptor), + HW_ATL_RDM_DESCDHDR_SPLIT_MSK, + HW_ATL_RDM_DESCDHDR_SPLIT_SHIFT, + rx_desc_head_splitting); +} + +u32 hw_atl_rdm_rx_desc_head_ptr_get(struct aq_hw_s *aq_hw, u32 descriptor) +{ + return aq_hw_read_reg_bit(aq_hw, HW_ATL_RDM_DESCDHD_ADR(descriptor), + HW_ATL_RDM_DESCDHD_MSK, + HW_ATL_RDM_DESCDHD_SHIFT); +} + +void hw_atl_rdm_rx_desc_len_set(struct aq_hw_s *aq_hw, u32 rx_desc_len, + u32 descriptor) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDLEN_ADR(descriptor), + HW_ATL_RDM_DESCDLEN_MSK, HW_ATL_RDM_DESCDLEN_SHIFT, + rx_desc_len); +} + +void hw_atl_rdm_rx_desc_res_set(struct aq_hw_s *aq_hw, u32 rx_desc_res, + u32 descriptor) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDRESET_ADR(descriptor), + HW_ATL_RDM_DESCDRESET_MSK, + HW_ATL_RDM_DESCDRESET_SHIFT, + rx_desc_res); +} + +void hw_atl_rdm_rx_desc_wr_wb_irq_en_set(struct aq_hw_s *aq_hw, + u32 rx_desc_wr_wb_irq_en) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_INT_DESC_WRB_EN_ADR, + HW_ATL_RDM_INT_DESC_WRB_EN_MSK, + HW_ATL_RDM_INT_DESC_WRB_EN_SHIFT, + rx_desc_wr_wb_irq_en); +} + +void hw_atl_rdm_rx_head_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_head_dca_en, + u32 dca) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCADHDR_EN_ADR(dca), + HW_ATL_RDM_DCADHDR_EN_MSK, + HW_ATL_RDM_DCADHDR_EN_SHIFT, + rx_head_dca_en); +} + +void hw_atl_rdm_rx_pld_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_pld_dca_en, + u32 dca) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCADPAY_EN_ADR(dca), + HW_ATL_RDM_DCADPAY_EN_MSK, + HW_ATL_RDM_DCADPAY_EN_SHIFT, + rx_pld_dca_en); +} + +void hw_atl_rdm_rdm_intr_moder_en_set(struct aq_hw_s *aq_hw, + u32 rdm_intr_moder_en) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_INT_RIM_EN_ADR, + HW_ATL_RDM_INT_RIM_EN_MSK, + HW_ATL_RDM_INT_RIM_EN_SHIFT, + rdm_intr_moder_en); +} + +/* reg */ +void hw_atl_reg_gen_irq_map_set(struct aq_hw_s *aq_hw, u32 gen_intr_map, + u32 regidx) +{ + aq_hw_write_reg(aq_hw, HW_ATL_GEN_INTR_MAP_ADR(regidx), gen_intr_map); +} + +u32 hw_atl_reg_gen_irq_status_get(struct aq_hw_s *aq_hw) +{ + return aq_hw_read_reg(aq_hw, HW_ATL_GEN_INTR_STAT_ADR); +} + +void hw_atl_reg_irq_glb_ctl_set(struct aq_hw_s *aq_hw, u32 intr_glb_ctl) +{ + aq_hw_write_reg(aq_hw, HW_ATL_INTR_GLB_CTL_ADR, intr_glb_ctl); +} + +void hw_atl_reg_irq_thr_set(struct aq_hw_s *aq_hw, u32 intr_thr, u32 throttle) +{ + aq_hw_write_reg(aq_hw, HW_ATL_INTR_THR_ADR(throttle), intr_thr); +} + +void hw_atl_reg_rx_dma_desc_base_addresslswset(struct aq_hw_s *aq_hw, + u32 rx_dma_desc_base_addrlsw, + u32 descriptor) +{ + aq_hw_write_reg(aq_hw, HW_ATL_RX_DMA_DESC_BASE_ADDRLSW_ADR(descriptor), + rx_dma_desc_base_addrlsw); +} + +void hw_atl_reg_rx_dma_desc_base_addressmswset(struct aq_hw_s *aq_hw, + u32 rx_dma_desc_base_addrmsw, + u32 descriptor) +{ + aq_hw_write_reg(aq_hw, HW_ATL_RX_DMA_DESC_BASE_ADDRMSW_ADR(descriptor), + rx_dma_desc_base_addrmsw); +} + +u32 hw_atl_reg_rx_dma_desc_status_get(struct aq_hw_s *aq_hw, u32 descriptor) +{ + return aq_hw_read_reg(aq_hw, HW_ATL_RX_DMA_DESC_STAT_ADR(descriptor)); +} + +void hw_atl_reg_rx_dma_desc_tail_ptr_set(struct aq_hw_s *aq_hw, + u32 rx_dma_desc_tail_ptr, + u32 descriptor) +{ + aq_hw_write_reg(aq_hw, HW_ATL_RX_DMA_DESC_TAIL_PTR_ADR(descriptor), + rx_dma_desc_tail_ptr); +} + +void hw_atl_reg_rx_flr_mcst_flr_msk_set(struct aq_hw_s *aq_hw, + u32 rx_flr_mcst_flr_msk) +{ + aq_hw_write_reg(aq_hw, HW_ATL_RX_FLR_MCST_FLR_MSK_ADR, + rx_flr_mcst_flr_msk); +} + +void hw_atl_reg_rx_flr_mcst_flr_set(struct aq_hw_s *aq_hw, u32 rx_flr_mcst_flr, + u32 filter) +{ + aq_hw_write_reg(aq_hw, HW_ATL_RX_FLR_MCST_FLR_ADR(filter), + rx_flr_mcst_flr); +} + +void hw_atl_reg_rx_flr_rss_control1set(struct aq_hw_s *aq_hw, + u32 rx_flr_rss_control1) +{ + aq_hw_write_reg(aq_hw, HW_ATL_RX_FLR_RSS_CONTROL1_ADR, + rx_flr_rss_control1); +} + +void hw_atl_reg_rx_flr_control2_set(struct aq_hw_s *aq_hw, + u32 rx_filter_control2) +{ + aq_hw_write_reg(aq_hw, HW_ATL_RX_FLR_CONTROL2_ADR, rx_filter_control2); +} + +void hw_atl_reg_rx_intr_moder_ctrl_set(struct aq_hw_s *aq_hw, + u32 rx_intr_moderation_ctl, + u32 queue) +{ + aq_hw_write_reg(aq_hw, HW_ATL_RX_INTR_MODERATION_CTL_ADR(queue), + rx_intr_moderation_ctl); +} + +void hw_atl_reg_tx_dma_debug_ctl_set(struct aq_hw_s *aq_hw, + u32 tx_dma_debug_ctl) +{ + aq_hw_write_reg(aq_hw, HW_ATL_TX_DMA_DEBUG_CTL_ADR, tx_dma_debug_ctl); +} + +void hw_atl_reg_tx_dma_desc_base_addresslswset(struct aq_hw_s *aq_hw, + u32 tx_dma_desc_base_addrlsw, + u32 descriptor) +{ + aq_hw_write_reg(aq_hw, HW_ATL_TX_DMA_DESC_BASE_ADDRLSW_ADR(descriptor), + tx_dma_desc_base_addrlsw); +} + +void hw_atl_reg_tx_dma_desc_base_addressmswset(struct aq_hw_s *aq_hw, + u32 tx_dma_desc_base_addrmsw, + u32 descriptor) +{ + aq_hw_write_reg(aq_hw, HW_ATL_TX_DMA_DESC_BASE_ADDRMSW_ADR(descriptor), + tx_dma_desc_base_addrmsw); +} + +void hw_atl_reg_tx_dma_desc_tail_ptr_set(struct aq_hw_s *aq_hw, + u32 tx_dma_desc_tail_ptr, + u32 descriptor) +{ + rte_wmb(); + + aq_hw_write_reg(aq_hw, HW_ATL_TX_DMA_DESC_TAIL_PTR_ADR(descriptor), + tx_dma_desc_tail_ptr); +} + +void hw_atl_reg_tx_intr_moder_ctrl_set(struct aq_hw_s *aq_hw, + u32 tx_intr_moderation_ctl, + u32 queue) +{ + aq_hw_write_reg(aq_hw, HW_ATL_TX_INTR_MODERATION_CTL_ADR(queue), + tx_intr_moderation_ctl); +} + +/* RPB: rx packet buffer */ +void hw_atl_rpb_dma_sys_lbk_set(struct aq_hw_s *aq_hw, u32 dma_sys_lbk) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_DMA_SYS_LBK_ADR, + HW_ATL_RPB_DMA_SYS_LBK_MSK, + HW_ATL_RPB_DMA_SYS_LBK_SHIFT, dma_sys_lbk); +} + +void hw_atl_rpb_rpf_rx_traf_class_mode_set(struct aq_hw_s *aq_hw, + u32 rx_traf_class_mode) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RPF_RX_TC_MODE_ADR, + HW_ATL_RPB_RPF_RX_TC_MODE_MSK, + HW_ATL_RPB_RPF_RX_TC_MODE_SHIFT, + rx_traf_class_mode); +} + +u32 hw_atl_rpb_rpf_rx_traf_class_mode_get(struct aq_hw_s *aq_hw) +{ + return aq_hw_read_reg_bit(aq_hw, HW_ATL_RPB_RPF_RX_TC_MODE_ADR, + HW_ATL_RPB_RPF_RX_TC_MODE_MSK, + HW_ATL_RPB_RPF_RX_TC_MODE_SHIFT); +} + +void hw_atl_rpb_rx_buff_en_set(struct aq_hw_s *aq_hw, u32 rx_buff_en) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RX_BUF_EN_ADR, + HW_ATL_RPB_RX_BUF_EN_MSK, + HW_ATL_RPB_RX_BUF_EN_SHIFT, rx_buff_en); +} + +void hw_atl_rpb_rx_buff_hi_threshold_per_tc_set(struct aq_hw_s *aq_hw, + u32 rx_buff_hi_threshold_per_tc, + u32 buffer) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RXBHI_THRESH_ADR(buffer), + HW_ATL_RPB_RXBHI_THRESH_MSK, + HW_ATL_RPB_RXBHI_THRESH_SHIFT, + rx_buff_hi_threshold_per_tc); +} + +void hw_atl_rpb_rx_buff_lo_threshold_per_tc_set(struct aq_hw_s *aq_hw, + u32 rx_buff_lo_threshold_per_tc, + u32 buffer) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RXBLO_THRESH_ADR(buffer), + HW_ATL_RPB_RXBLO_THRESH_MSK, + HW_ATL_RPB_RXBLO_THRESH_SHIFT, + rx_buff_lo_threshold_per_tc); +} + +void hw_atl_rpb_rx_flow_ctl_mode_set(struct aq_hw_s *aq_hw, + u32 rx_flow_ctl_mode) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RX_FC_MODE_ADR, + HW_ATL_RPB_RX_FC_MODE_MSK, + HW_ATL_RPB_RX_FC_MODE_SHIFT, rx_flow_ctl_mode); +} + +void hw_atl_rpb_rx_pkt_buff_size_per_tc_set(struct aq_hw_s *aq_hw, + u32 rx_pkt_buff_size_per_tc, + u32 buffer) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RXBBUF_SIZE_ADR(buffer), + HW_ATL_RPB_RXBBUF_SIZE_MSK, + HW_ATL_RPB_RXBBUF_SIZE_SHIFT, + rx_pkt_buff_size_per_tc); +} + +void hw_atl_rpb_rx_xoff_en_per_tc_set(struct aq_hw_s *aq_hw, + u32 rx_xoff_en_per_tc, + u32 buffer) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RXBXOFF_EN_ADR(buffer), + HW_ATL_RPB_RXBXOFF_EN_MSK, + HW_ATL_RPB_RXBXOFF_EN_SHIFT, + rx_xoff_en_per_tc); +} + +/* rpf */ + +void hw_atl_rpfl2broadcast_count_threshold_set(struct aq_hw_s *aq_hw, + u32 l2broadcast_count_threshold) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2BC_THRESH_ADR, + HW_ATL_RPFL2BC_THRESH_MSK, + HW_ATL_RPFL2BC_THRESH_SHIFT, + l2broadcast_count_threshold); +} + +void hw_atl_rpfl2broadcast_en_set(struct aq_hw_s *aq_hw, u32 l2broadcast_en) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2BC_EN_ADR, HW_ATL_RPFL2BC_EN_MSK, + HW_ATL_RPFL2BC_EN_SHIFT, l2broadcast_en); +} + +void hw_atl_rpfl2broadcast_flr_act_set(struct aq_hw_s *aq_hw, + u32 l2broadcast_flr_act) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2BC_ACT_ADR, + HW_ATL_RPFL2BC_ACT_MSK, + HW_ATL_RPFL2BC_ACT_SHIFT, l2broadcast_flr_act); +} + +void hw_atl_rpfl2multicast_flr_en_set(struct aq_hw_s *aq_hw, + u32 l2multicast_flr_en, + u32 filter) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2MC_ENF_ADR(filter), + HW_ATL_RPFL2MC_ENF_MSK, + HW_ATL_RPFL2MC_ENF_SHIFT, l2multicast_flr_en); +} + +void hw_atl_rpfl2promiscuous_mode_en_set(struct aq_hw_s *aq_hw, + u32 l2promiscuous_mode_en) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2PROMIS_MODE_ADR, + HW_ATL_RPFL2PROMIS_MODE_MSK, + HW_ATL_RPFL2PROMIS_MODE_SHIFT, + l2promiscuous_mode_en); +} + +void hw_atl_rpfl2unicast_flr_act_set(struct aq_hw_s *aq_hw, + u32 l2unicast_flr_act, + u32 filter) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2UC_ACTF_ADR(filter), + HW_ATL_RPFL2UC_ACTF_MSK, HW_ATL_RPFL2UC_ACTF_SHIFT, + l2unicast_flr_act); +} + +void hw_atl_rpfl2_uc_flr_en_set(struct aq_hw_s *aq_hw, u32 l2unicast_flr_en, + u32 filter) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2UC_ENF_ADR(filter), + HW_ATL_RPFL2UC_ENF_MSK, + HW_ATL_RPFL2UC_ENF_SHIFT, l2unicast_flr_en); +} + +void hw_atl_rpfl2unicast_dest_addresslsw_set(struct aq_hw_s *aq_hw, + u32 l2unicast_dest_addresslsw, + u32 filter) +{ + aq_hw_write_reg(aq_hw, HW_ATL_RPFL2UC_DAFLSW_ADR(filter), + l2unicast_dest_addresslsw); +} + +void hw_atl_rpfl2unicast_dest_addressmsw_set(struct aq_hw_s *aq_hw, + u32 l2unicast_dest_addressmsw, + u32 filter) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2UC_DAFMSW_ADR(filter), + HW_ATL_RPFL2UC_DAFMSW_MSK, + HW_ATL_RPFL2UC_DAFMSW_SHIFT, + l2unicast_dest_addressmsw); +} + +void hw_atl_rpfl2_accept_all_mc_packets_set(struct aq_hw_s *aq_hw, + u32 l2_accept_all_mc_packets) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2MC_ACCEPT_ALL_ADR, + HW_ATL_RPFL2MC_ACCEPT_ALL_MSK, + HW_ATL_RPFL2MC_ACCEPT_ALL_SHIFT, + l2_accept_all_mc_packets); +} + +void hw_atl_rpf_rpb_user_priority_tc_map_set(struct aq_hw_s *aq_hw, + u32 user_priority_tc_map, u32 tc) +{ +/* register address for bitfield rx_tc_up{t}[2:0] */ + static const u32 rpf_rpb_rx_tc_upt_adr[8] = { + 0x000054c4U, 0x000054C4U, 0x000054C4U, 0x000054C4U, + 0x000054c4U, 0x000054C4U, 0x000054C4U, 0x000054C4U + }; + +/* bitmask for bitfield rx_tc_up{t}[2:0] */ + static const u32 rpf_rpb_rx_tc_upt_msk[8] = { + 0x00000007U, 0x00000070U, 0x00000700U, 0x00007000U, + 0x00070000U, 0x00700000U, 0x07000000U, 0x70000000U + }; + +/* lower bit position of bitfield rx_tc_up{t}[2:0] */ + static const u32 rpf_rpb_rx_tc_upt_shft[8] = { + 0U, 4U, 8U, 12U, 16U, 20U, 24U, 28U + }; + + aq_hw_write_reg_bit(aq_hw, rpf_rpb_rx_tc_upt_adr[tc], + rpf_rpb_rx_tc_upt_msk[tc], + rpf_rpb_rx_tc_upt_shft[tc], + user_priority_tc_map); +} + +void hw_atl_rpf_rss_key_addr_set(struct aq_hw_s *aq_hw, u32 rss_key_addr) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_RSS_KEY_ADDR_ADR, + HW_ATL_RPF_RSS_KEY_ADDR_MSK, + HW_ATL_RPF_RSS_KEY_ADDR_SHIFT, + rss_key_addr); +} + +void hw_atl_rpf_rss_key_wr_data_set(struct aq_hw_s *aq_hw, u32 rss_key_wr_data) +{ + aq_hw_write_reg(aq_hw, HW_ATL_RPF_RSS_KEY_WR_DATA_ADR, + rss_key_wr_data); +} + +u32 hw_atl_rpf_rss_key_wr_en_get(struct aq_hw_s *aq_hw) +{ + return aq_hw_read_reg_bit(aq_hw, HW_ATL_RPF_RSS_KEY_WR_ENI_ADR, + HW_ATL_RPF_RSS_KEY_WR_ENI_MSK, + HW_ATL_RPF_RSS_KEY_WR_ENI_SHIFT); +} + +void hw_atl_rpf_rss_key_wr_en_set(struct aq_hw_s *aq_hw, u32 rss_key_wr_en) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_RSS_KEY_WR_ENI_ADR, + HW_ATL_RPF_RSS_KEY_WR_ENI_MSK, + HW_ATL_RPF_RSS_KEY_WR_ENI_SHIFT, + rss_key_wr_en); +} + +void hw_atl_rpf_rss_redir_tbl_addr_set(struct aq_hw_s *aq_hw, + u32 rss_redir_tbl_addr) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_RSS_REDIR_ADDR_ADR, + HW_ATL_RPF_RSS_REDIR_ADDR_MSK, + HW_ATL_RPF_RSS_REDIR_ADDR_SHIFT, + rss_redir_tbl_addr); +} + +void hw_atl_rpf_rss_redir_tbl_wr_data_set(struct aq_hw_s *aq_hw, + u32 rss_redir_tbl_wr_data) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_RSS_REDIR_WR_DATA_ADR, + HW_ATL_RPF_RSS_REDIR_WR_DATA_MSK, + HW_ATL_RPF_RSS_REDIR_WR_DATA_SHIFT, + rss_redir_tbl_wr_data); +} + +u32 hw_atl_rpf_rss_redir_wr_en_get(struct aq_hw_s *aq_hw) +{ + return aq_hw_read_reg_bit(aq_hw, HW_ATL_RPF_RSS_REDIR_WR_ENI_ADR, + HW_ATL_RPF_RSS_REDIR_WR_ENI_MSK, + HW_ATL_RPF_RSS_REDIR_WR_ENI_SHIFT); +} + +void hw_atl_rpf_rss_redir_wr_en_set(struct aq_hw_s *aq_hw, u32 rss_redir_wr_en) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_RSS_REDIR_WR_ENI_ADR, + HW_ATL_RPF_RSS_REDIR_WR_ENI_MSK, + HW_ATL_RPF_RSS_REDIR_WR_ENI_SHIFT, rss_redir_wr_en); +} + +void hw_atl_rpf_tpo_to_rpf_sys_lbk_set(struct aq_hw_s *aq_hw, + u32 tpo_to_rpf_sys_lbk) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_TPO_RPF_SYS_LBK_ADR, + HW_ATL_RPF_TPO_RPF_SYS_LBK_MSK, + HW_ATL_RPF_TPO_RPF_SYS_LBK_SHIFT, + tpo_to_rpf_sys_lbk); +} + +void hw_atl_rpf_vlan_inner_etht_set(struct aq_hw_s *aq_hw, u32 vlan_inner_etht) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_INNER_TPID_ADR, + HW_ATL_RPF_VL_INNER_TPID_MSK, + HW_ATL_RPF_VL_INNER_TPID_SHIFT, + vlan_inner_etht); +} + +void hw_atl_rpf_vlan_outer_etht_set(struct aq_hw_s *aq_hw, u32 vlan_outer_etht) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_OUTER_TPID_ADR, + HW_ATL_RPF_VL_OUTER_TPID_MSK, + HW_ATL_RPF_VL_OUTER_TPID_SHIFT, + vlan_outer_etht); +} + +void hw_atl_rpf_vlan_prom_mode_en_set(struct aq_hw_s *aq_hw, + u32 vlan_prom_mode_en) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_PROMIS_MODE_ADR, + HW_ATL_RPF_VL_PROMIS_MODE_MSK, + HW_ATL_RPF_VL_PROMIS_MODE_SHIFT, + vlan_prom_mode_en); +} + +void hw_atl_rpf_vlan_accept_untagged_packets_set(struct aq_hw_s *aq_hw, + u32 vlan_acc_untagged_packets) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_ADR, + HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_MSK, + HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_SHIFT, + vlan_acc_untagged_packets); +} + +void hw_atl_rpf_vlan_untagged_act_set(struct aq_hw_s *aq_hw, + u32 vlan_untagged_act) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_UNTAGGED_ACT_ADR, + HW_ATL_RPF_VL_UNTAGGED_ACT_MSK, + HW_ATL_RPF_VL_UNTAGGED_ACT_SHIFT, + vlan_untagged_act); +} + +void hw_atl_rpf_vlan_flr_en_set(struct aq_hw_s *aq_hw, u32 vlan_flr_en, + u32 filter) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_EN_F_ADR(filter), + HW_ATL_RPF_VL_EN_F_MSK, + HW_ATL_RPF_VL_EN_F_SHIFT, + vlan_flr_en); +} + +void hw_atl_rpf_vlan_flr_act_set(struct aq_hw_s *aq_hw, u32 vlan_flr_act, + u32 filter) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_ACT_F_ADR(filter), + HW_ATL_RPF_VL_ACT_F_MSK, + HW_ATL_RPF_VL_ACT_F_SHIFT, + vlan_flr_act); +} + +void hw_atl_rpf_vlan_id_flr_set(struct aq_hw_s *aq_hw, u32 vlan_id_flr, + u32 filter) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_ID_F_ADR(filter), + HW_ATL_RPF_VL_ID_F_MSK, + HW_ATL_RPF_VL_ID_F_SHIFT, + vlan_id_flr); +} + +void hw_atl_rpf_etht_flr_en_set(struct aq_hw_s *aq_hw, u32 etht_flr_en, + u32 filter) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_ENF_ADR(filter), + HW_ATL_RPF_ET_ENF_MSK, + HW_ATL_RPF_ET_ENF_SHIFT, etht_flr_en); +} + +void hw_atl_rpf_etht_user_priority_en_set(struct aq_hw_s *aq_hw, + u32 etht_user_priority_en, u32 filter) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_UPFEN_ADR(filter), + HW_ATL_RPF_ET_UPFEN_MSK, HW_ATL_RPF_ET_UPFEN_SHIFT, + etht_user_priority_en); +} + +void hw_atl_rpf_etht_rx_queue_en_set(struct aq_hw_s *aq_hw, + u32 etht_rx_queue_en, + u32 filter) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_RXQFEN_ADR(filter), + HW_ATL_RPF_ET_RXQFEN_MSK, + HW_ATL_RPF_ET_RXQFEN_SHIFT, + etht_rx_queue_en); +} + +void hw_atl_rpf_etht_user_priority_set(struct aq_hw_s *aq_hw, + u32 etht_user_priority, + u32 filter) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_UPF_ADR(filter), + HW_ATL_RPF_ET_UPF_MSK, + HW_ATL_RPF_ET_UPF_SHIFT, etht_user_priority); +} + +void hw_atl_rpf_etht_rx_queue_set(struct aq_hw_s *aq_hw, u32 etht_rx_queue, + u32 filter) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_RXQF_ADR(filter), + HW_ATL_RPF_ET_RXQF_MSK, + HW_ATL_RPF_ET_RXQF_SHIFT, etht_rx_queue); +} + +void hw_atl_rpf_etht_mgt_queue_set(struct aq_hw_s *aq_hw, u32 etht_mgt_queue, + u32 filter) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_MNG_RXQF_ADR(filter), + HW_ATL_RPF_ET_MNG_RXQF_MSK, + HW_ATL_RPF_ET_MNG_RXQF_SHIFT, + etht_mgt_queue); +} + +void hw_atl_rpf_etht_flr_act_set(struct aq_hw_s *aq_hw, u32 etht_flr_act, + u32 filter) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_ACTF_ADR(filter), + HW_ATL_RPF_ET_ACTF_MSK, + HW_ATL_RPF_ET_ACTF_SHIFT, etht_flr_act); +} + +void hw_atl_rpf_etht_flr_set(struct aq_hw_s *aq_hw, u32 etht_flr, u32 filter) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_VALF_ADR(filter), + HW_ATL_RPF_ET_VALF_MSK, + HW_ATL_RPF_ET_VALF_SHIFT, etht_flr); +} + +/* RPO: rx packet offload */ +void hw_atl_rpo_ipv4header_crc_offload_en_set(struct aq_hw_s *aq_hw, + u32 ipv4header_crc_offload_en) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_IPV4CHK_EN_ADR, + HW_ATL_RPO_IPV4CHK_EN_MSK, + HW_ATL_RPO_IPV4CHK_EN_SHIFT, + ipv4header_crc_offload_en); +} + +void hw_atl_rpo_rx_desc_vlan_stripping_set(struct aq_hw_s *aq_hw, + u32 rx_desc_vlan_stripping, + u32 descriptor) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_DESCDVL_STRIP_ADR(descriptor), + HW_ATL_RPO_DESCDVL_STRIP_MSK, + HW_ATL_RPO_DESCDVL_STRIP_SHIFT, + rx_desc_vlan_stripping); +} + +void hw_atl_rpo_tcp_udp_crc_offload_en_set(struct aq_hw_s *aq_hw, + u32 tcp_udp_crc_offload_en) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPOL4CHK_EN_ADR, + HW_ATL_RPOL4CHK_EN_MSK, + HW_ATL_RPOL4CHK_EN_SHIFT, tcp_udp_crc_offload_en); +} + +void hw_atl_rpo_lro_en_set(struct aq_hw_s *aq_hw, u32 lro_en) +{ + aq_hw_write_reg(aq_hw, HW_ATL_RPO_LRO_EN_ADR, lro_en); +} + +void hw_atl_rpo_lro_patch_optimization_en_set(struct aq_hw_s *aq_hw, + u32 lro_patch_optimization_en) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_PTOPT_EN_ADR, + HW_ATL_RPO_LRO_PTOPT_EN_MSK, + HW_ATL_RPO_LRO_PTOPT_EN_SHIFT, + lro_patch_optimization_en); +} + +void hw_atl_rpo_lro_qsessions_lim_set(struct aq_hw_s *aq_hw, + u32 lro_qsessions_lim) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_QSES_LMT_ADR, + HW_ATL_RPO_LRO_QSES_LMT_MSK, + HW_ATL_RPO_LRO_QSES_LMT_SHIFT, + lro_qsessions_lim); +} + +void hw_atl_rpo_lro_total_desc_lim_set(struct aq_hw_s *aq_hw, + u32 lro_total_desc_lim) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_TOT_DSC_LMT_ADR, + HW_ATL_RPO_LRO_TOT_DSC_LMT_MSK, + HW_ATL_RPO_LRO_TOT_DSC_LMT_SHIFT, + lro_total_desc_lim); +} + +void hw_atl_rpo_lro_min_pay_of_first_pkt_set(struct aq_hw_s *aq_hw, + u32 lro_min_pld_of_first_pkt) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_PKT_MIN_ADR, + HW_ATL_RPO_LRO_PKT_MIN_MSK, + HW_ATL_RPO_LRO_PKT_MIN_SHIFT, + lro_min_pld_of_first_pkt); +} + +void hw_atl_rpo_lro_pkt_lim_set(struct aq_hw_s *aq_hw, u32 lro_pkt_lim) +{ + aq_hw_write_reg(aq_hw, HW_ATL_RPO_LRO_RSC_MAX_ADR, lro_pkt_lim); +} + +void hw_atl_rpo_lro_max_num_of_descriptors_set(struct aq_hw_s *aq_hw, + u32 lro_max_number_of_descriptors, + u32 lro) +{ +/* Register address for bitfield lro{L}_des_max[1:0] */ + static const u32 rpo_lro_ldes_max_adr[32] = { + 0x000055A0U, 0x000055A0U, 0x000055A0U, 0x000055A0U, + 0x000055A0U, 0x000055A0U, 0x000055A0U, 0x000055A0U, + 0x000055A4U, 0x000055A4U, 0x000055A4U, 0x000055A4U, + 0x000055A4U, 0x000055A4U, 0x000055A4U, 0x000055A4U, + 0x000055A8U, 0x000055A8U, 0x000055A8U, 0x000055A8U, + 0x000055A8U, 0x000055A8U, 0x000055A8U, 0x000055A8U, + 0x000055ACU, 0x000055ACU, 0x000055ACU, 0x000055ACU, + 0x000055ACU, 0x000055ACU, 0x000055ACU, 0x000055ACU + }; + +/* Bitmask for bitfield lro{L}_des_max[1:0] */ + static const u32 rpo_lro_ldes_max_msk[32] = { + 0x00000003U, 0x00000030U, 0x00000300U, 0x00003000U, + 0x00030000U, 0x00300000U, 0x03000000U, 0x30000000U, + 0x00000003U, 0x00000030U, 0x00000300U, 0x00003000U, + 0x00030000U, 0x00300000U, 0x03000000U, 0x30000000U, + 0x00000003U, 0x00000030U, 0x00000300U, 0x00003000U, + 0x00030000U, 0x00300000U, 0x03000000U, 0x30000000U, + 0x00000003U, 0x00000030U, 0x00000300U, 0x00003000U, + 0x00030000U, 0x00300000U, 0x03000000U, 0x30000000U + }; + +/* Lower bit position of bitfield lro{L}_des_max[1:0] */ + static const u32 rpo_lro_ldes_max_shift[32] = { + 0U, 4U, 8U, 12U, 16U, 20U, 24U, 28U, + 0U, 4U, 8U, 12U, 16U, 20U, 24U, 28U, + 0U, 4U, 8U, 12U, 16U, 20U, 24U, 28U, + 0U, 4U, 8U, 12U, 16U, 20U, 24U, 28U + }; + + aq_hw_write_reg_bit(aq_hw, rpo_lro_ldes_max_adr[lro], + rpo_lro_ldes_max_msk[lro], + rpo_lro_ldes_max_shift[lro], + lro_max_number_of_descriptors); +} + +void hw_atl_rpo_lro_time_base_divider_set(struct aq_hw_s *aq_hw, + u32 lro_time_base_divider) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_TB_DIV_ADR, + HW_ATL_RPO_LRO_TB_DIV_MSK, + HW_ATL_RPO_LRO_TB_DIV_SHIFT, + lro_time_base_divider); +} + +void hw_atl_rpo_lro_inactive_interval_set(struct aq_hw_s *aq_hw, + u32 lro_inactive_interval) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_INA_IVAL_ADR, + HW_ATL_RPO_LRO_INA_IVAL_MSK, + HW_ATL_RPO_LRO_INA_IVAL_SHIFT, + lro_inactive_interval); +} + +void hw_atl_rpo_lro_max_coalescing_interval_set(struct aq_hw_s *aq_hw, + u32 lro_max_coal_interval) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_MAX_IVAL_ADR, + HW_ATL_RPO_LRO_MAX_IVAL_MSK, + HW_ATL_RPO_LRO_MAX_IVAL_SHIFT, + lro_max_coal_interval); +} + +/* rx */ +void hw_atl_rx_rx_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 rx_reg_res_dis) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_RX_REG_RES_DSBL_ADR, + HW_ATL_RX_REG_RES_DSBL_MSK, + HW_ATL_RX_REG_RES_DSBL_SHIFT, + rx_reg_res_dis); +} + +/* tdm */ +void hw_atl_tdm_cpu_id_set(struct aq_hw_s *aq_hw, u32 cpuid, u32 dca) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DCADCPUID_ADR(dca), + HW_ATL_TDM_DCADCPUID_MSK, + HW_ATL_TDM_DCADCPUID_SHIFT, cpuid); +} + +void hw_atl_tdm_large_send_offload_en_set(struct aq_hw_s *aq_hw, + u32 large_send_offload_en) +{ + aq_hw_write_reg(aq_hw, HW_ATL_TDM_LSO_EN_ADR, large_send_offload_en); +} + +void hw_atl_tdm_tx_dca_en_set(struct aq_hw_s *aq_hw, u32 tx_dca_en) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DCA_EN_ADR, HW_ATL_TDM_DCA_EN_MSK, + HW_ATL_TDM_DCA_EN_SHIFT, tx_dca_en); +} + +void hw_atl_tdm_tx_dca_mode_set(struct aq_hw_s *aq_hw, u32 tx_dca_mode) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DCA_MODE_ADR, + HW_ATL_TDM_DCA_MODE_MSK, + HW_ATL_TDM_DCA_MODE_SHIFT, tx_dca_mode); +} + +void hw_atl_tdm_tx_desc_dca_en_set(struct aq_hw_s *aq_hw, u32 tx_desc_dca_en, + u32 dca) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DCADDESC_EN_ADR(dca), + HW_ATL_TDM_DCADDESC_EN_MSK, + HW_ATL_TDM_DCADDESC_EN_SHIFT, + tx_desc_dca_en); +} + +void hw_atl_tdm_tx_desc_en_set(struct aq_hw_s *aq_hw, u32 tx_desc_en, + u32 descriptor) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DESCDEN_ADR(descriptor), + HW_ATL_TDM_DESCDEN_MSK, + HW_ATL_TDM_DESCDEN_SHIFT, + tx_desc_en); +} + +u32 hw_atl_tdm_tx_desc_head_ptr_get(struct aq_hw_s *aq_hw, u32 descriptor) +{ + return aq_hw_read_reg_bit(aq_hw, HW_ATL_TDM_DESCDHD_ADR(descriptor), + HW_ATL_TDM_DESCDHD_MSK, + HW_ATL_TDM_DESCDHD_SHIFT); +} + +void hw_atl_tdm_tx_desc_len_set(struct aq_hw_s *aq_hw, u32 tx_desc_len, + u32 descriptor) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DESCDLEN_ADR(descriptor), + HW_ATL_TDM_DESCDLEN_MSK, + HW_ATL_TDM_DESCDLEN_SHIFT, + tx_desc_len); +} + +void hw_atl_tdm_tx_desc_wr_wb_irq_en_set(struct aq_hw_s *aq_hw, + u32 tx_desc_wr_wb_irq_en) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_INT_DESC_WRB_EN_ADR, + HW_ATL_TDM_INT_DESC_WRB_EN_MSK, + HW_ATL_TDM_INT_DESC_WRB_EN_SHIFT, + tx_desc_wr_wb_irq_en); +} + +void hw_atl_tdm_tx_desc_wr_wb_threshold_set(struct aq_hw_s *aq_hw, + u32 tx_desc_wr_wb_threshold, + u32 descriptor) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DESCDWRB_THRESH_ADR(descriptor), + HW_ATL_TDM_DESCDWRB_THRESH_MSK, + HW_ATL_TDM_DESCDWRB_THRESH_SHIFT, + tx_desc_wr_wb_threshold); +} + +void hw_atl_tdm_tdm_intr_moder_en_set(struct aq_hw_s *aq_hw, + u32 tdm_irq_moderation_en) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_INT_MOD_EN_ADR, + HW_ATL_TDM_INT_MOD_EN_MSK, + HW_ATL_TDM_INT_MOD_EN_SHIFT, + tdm_irq_moderation_en); +} + +/* thm */ +void hw_atl_thm_lso_tcp_flag_of_first_pkt_set(struct aq_hw_s *aq_hw, + u32 lso_tcp_flag_of_first_pkt) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_THM_LSO_TCP_FLAG_FIRST_ADR, + HW_ATL_THM_LSO_TCP_FLAG_FIRST_MSK, + HW_ATL_THM_LSO_TCP_FLAG_FIRST_SHIFT, + lso_tcp_flag_of_first_pkt); +} + +void hw_atl_thm_lso_tcp_flag_of_last_pkt_set(struct aq_hw_s *aq_hw, + u32 lso_tcp_flag_of_last_pkt) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_THM_LSO_TCP_FLAG_LAST_ADR, + HW_ATL_THM_LSO_TCP_FLAG_LAST_MSK, + HW_ATL_THM_LSO_TCP_FLAG_LAST_SHIFT, + lso_tcp_flag_of_last_pkt); +} + +void hw_atl_thm_lso_tcp_flag_of_middle_pkt_set(struct aq_hw_s *aq_hw, + u32 lso_tcp_flag_of_middle_pkt) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_THM_LSO_TCP_FLAG_MID_ADR, + HW_ATL_THM_LSO_TCP_FLAG_MID_MSK, + HW_ATL_THM_LSO_TCP_FLAG_MID_SHIFT, + lso_tcp_flag_of_middle_pkt); +} + +/* TPB: tx packet buffer */ +void hw_atl_tpb_tx_buff_en_set(struct aq_hw_s *aq_hw, u32 tx_buff_en) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TX_BUF_EN_ADR, + HW_ATL_TPB_TX_BUF_EN_MSK, + HW_ATL_TPB_TX_BUF_EN_SHIFT, tx_buff_en); +} + +u32 hw_atl_rpb_tps_tx_tc_mode_get(struct aq_hw_s *aq_hw) +{ + return aq_hw_read_reg_bit(aq_hw, HW_ATL_TPB_TX_TC_MODE_ADDR, + HW_ATL_TPB_TX_TC_MODE_MSK, + HW_ATL_TPB_TX_TC_MODE_SHIFT); +} + +void hw_atl_rpb_tps_tx_tc_mode_set(struct aq_hw_s *aq_hw, + u32 tx_traf_class_mode) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TX_TC_MODE_ADDR, + HW_ATL_TPB_TX_TC_MODE_MSK, + HW_ATL_TPB_TX_TC_MODE_SHIFT, + tx_traf_class_mode); +} + +void hw_atl_tpb_tx_buff_hi_threshold_per_tc_set(struct aq_hw_s *aq_hw, + u32 tx_buff_hi_threshold_per_tc, + u32 buffer) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TXBHI_THRESH_ADR(buffer), + HW_ATL_TPB_TXBHI_THRESH_MSK, + HW_ATL_TPB_TXBHI_THRESH_SHIFT, + tx_buff_hi_threshold_per_tc); +} + +void hw_atl_tpb_tx_buff_lo_threshold_per_tc_set(struct aq_hw_s *aq_hw, + u32 tx_buff_lo_threshold_per_tc, + u32 buffer) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TXBLO_THRESH_ADR(buffer), + HW_ATL_TPB_TXBLO_THRESH_MSK, + HW_ATL_TPB_TXBLO_THRESH_SHIFT, + tx_buff_lo_threshold_per_tc); +} + +void hw_atl_tpb_tx_dma_sys_lbk_en_set(struct aq_hw_s *aq_hw, + u32 tx_dma_sys_lbk_en) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_DMA_SYS_LBK_ADR, + HW_ATL_TPB_DMA_SYS_LBK_MSK, + HW_ATL_TPB_DMA_SYS_LBK_SHIFT, + tx_dma_sys_lbk_en); +} + +void hw_atl_tpb_tx_pkt_buff_size_per_tc_set(struct aq_hw_s *aq_hw, + u32 tx_pkt_buff_size_per_tc, + u32 buffer) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TXBBUF_SIZE_ADR(buffer), + HW_ATL_TPB_TXBBUF_SIZE_MSK, + HW_ATL_TPB_TXBBUF_SIZE_SHIFT, + tx_pkt_buff_size_per_tc); +} + +void hw_atl_tpb_tx_path_scp_ins_en_set(struct aq_hw_s *aq_hw, + u32 tx_path_scp_ins_en) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TX_SCP_INS_EN_ADR, + HW_ATL_TPB_TX_SCP_INS_EN_MSK, + HW_ATL_TPB_TX_SCP_INS_EN_SHIFT, + tx_path_scp_ins_en); +} + +/* TPO: tx packet offload */ +void hw_atl_tpo_ipv4header_crc_offload_en_set(struct aq_hw_s *aq_hw, + u32 ipv4header_crc_offload_en) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_TPO_IPV4CHK_EN_ADR, + HW_ATL_TPO_IPV4CHK_EN_MSK, + HW_ATL_TPO_IPV4CHK_EN_SHIFT, + ipv4header_crc_offload_en); +} + +void hw_atl_tpo_tcp_udp_crc_offload_en_set(struct aq_hw_s *aq_hw, + u32 tcp_udp_crc_offload_en) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_TPOL4CHK_EN_ADR, + HW_ATL_TPOL4CHK_EN_MSK, + HW_ATL_TPOL4CHK_EN_SHIFT, + tcp_udp_crc_offload_en); +} + +void hw_atl_tpo_tx_pkt_sys_lbk_en_set(struct aq_hw_s *aq_hw, + u32 tx_pkt_sys_lbk_en) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_TPO_PKT_SYS_LBK_ADR, + HW_ATL_TPO_PKT_SYS_LBK_MSK, + HW_ATL_TPO_PKT_SYS_LBK_SHIFT, + tx_pkt_sys_lbk_en); +} + +/* TPS: tx packet scheduler */ +void hw_atl_tps_tx_pkt_shed_data_arb_mode_set(struct aq_hw_s *aq_hw, + u32 tx_pkt_shed_data_arb_mode) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DATA_TC_ARB_MODE_ADR, + HW_ATL_TPS_DATA_TC_ARB_MODE_MSK, + HW_ATL_TPS_DATA_TC_ARB_MODE_SHIFT, + tx_pkt_shed_data_arb_mode); +} + +void hw_atl_tps_tx_pkt_shed_desc_rate_curr_time_res_set(struct aq_hw_s *aq_hw, + u32 curr_time_res) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_RATE_TA_RST_ADR, + HW_ATL_TPS_DESC_RATE_TA_RST_MSK, + HW_ATL_TPS_DESC_RATE_TA_RST_SHIFT, + curr_time_res); +} + +void hw_atl_tps_tx_pkt_shed_desc_rate_lim_set(struct aq_hw_s *aq_hw, + u32 tx_pkt_shed_desc_rate_lim) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_RATE_LIM_ADR, + HW_ATL_TPS_DESC_RATE_LIM_MSK, + HW_ATL_TPS_DESC_RATE_LIM_SHIFT, + tx_pkt_shed_desc_rate_lim); +} + +void hw_atl_tps_tx_pkt_shed_desc_tc_arb_mode_set(struct aq_hw_s *aq_hw, + u32 arb_mode) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_TC_ARB_MODE_ADR, + HW_ATL_TPS_DESC_TC_ARB_MODE_MSK, + HW_ATL_TPS_DESC_TC_ARB_MODE_SHIFT, + arb_mode); +} + +void hw_atl_tps_tx_pkt_shed_desc_tc_max_credit_set(struct aq_hw_s *aq_hw, + u32 max_credit, + u32 tc) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_TCTCREDIT_MAX_ADR(tc), + HW_ATL_TPS_DESC_TCTCREDIT_MAX_MSK, + HW_ATL_TPS_DESC_TCTCREDIT_MAX_SHIFT, + max_credit); +} + +void hw_atl_tps_tx_pkt_shed_desc_tc_weight_set(struct aq_hw_s *aq_hw, + u32 tx_pkt_shed_desc_tc_weight, + u32 tc) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_TCTWEIGHT_ADR(tc), + HW_ATL_TPS_DESC_TCTWEIGHT_MSK, + HW_ATL_TPS_DESC_TCTWEIGHT_SHIFT, + tx_pkt_shed_desc_tc_weight); +} + +void hw_atl_tps_tx_pkt_shed_desc_vm_arb_mode_set(struct aq_hw_s *aq_hw, + u32 arb_mode) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_VM_ARB_MODE_ADR, + HW_ATL_TPS_DESC_VM_ARB_MODE_MSK, + HW_ATL_TPS_DESC_VM_ARB_MODE_SHIFT, + arb_mode); +} + +void hw_atl_tps_tx_pkt_shed_tc_data_max_credit_set(struct aq_hw_s *aq_hw, + u32 max_credit, + u32 tc) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DATA_TCTCREDIT_MAX_ADR(tc), + HW_ATL_TPS_DATA_TCTCREDIT_MAX_MSK, + HW_ATL_TPS_DATA_TCTCREDIT_MAX_SHIFT, + max_credit); +} + +void hw_atl_tps_tx_pkt_shed_tc_data_weight_set(struct aq_hw_s *aq_hw, + u32 tx_pkt_shed_tc_data_weight, + u32 tc) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DATA_TCTWEIGHT_ADR(tc), + HW_ATL_TPS_DATA_TCTWEIGHT_MSK, + HW_ATL_TPS_DATA_TCTWEIGHT_SHIFT, + tx_pkt_shed_tc_data_weight); +} + +/* tx */ +void hw_atl_tx_tx_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 tx_reg_res_dis) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_TX_REG_RES_DSBL_ADR, + HW_ATL_TX_REG_RES_DSBL_MSK, + HW_ATL_TX_REG_RES_DSBL_SHIFT, tx_reg_res_dis); +} + +/* msm */ +u32 hw_atl_msm_reg_access_status_get(struct aq_hw_s *aq_hw) +{ + return aq_hw_read_reg_bit(aq_hw, HW_ATL_MSM_REG_ACCESS_BUSY_ADR, + HW_ATL_MSM_REG_ACCESS_BUSY_MSK, + HW_ATL_MSM_REG_ACCESS_BUSY_SHIFT); +} + +void hw_atl_msm_reg_addr_for_indirect_addr_set(struct aq_hw_s *aq_hw, + u32 reg_addr_for_indirect_addr) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_MSM_REG_ADDR_ADR, + HW_ATL_MSM_REG_ADDR_MSK, + HW_ATL_MSM_REG_ADDR_SHIFT, + reg_addr_for_indirect_addr); +} + +void hw_atl_msm_reg_rd_strobe_set(struct aq_hw_s *aq_hw, u32 reg_rd_strobe) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_MSM_REG_RD_STROBE_ADR, + HW_ATL_MSM_REG_RD_STROBE_MSK, + HW_ATL_MSM_REG_RD_STROBE_SHIFT, + reg_rd_strobe); +} + +u32 hw_atl_msm_reg_rd_data_get(struct aq_hw_s *aq_hw) +{ + return aq_hw_read_reg(aq_hw, HW_ATL_MSM_REG_RD_DATA_ADR); +} + +void hw_atl_msm_reg_wr_data_set(struct aq_hw_s *aq_hw, u32 reg_wr_data) +{ + aq_hw_write_reg(aq_hw, HW_ATL_MSM_REG_WR_DATA_ADR, reg_wr_data); +} + +void hw_atl_msm_reg_wr_strobe_set(struct aq_hw_s *aq_hw, u32 reg_wr_strobe) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_MSM_REG_WR_STROBE_ADR, + HW_ATL_MSM_REG_WR_STROBE_MSK, + HW_ATL_MSM_REG_WR_STROBE_SHIFT, + reg_wr_strobe); +} + +/* pci */ +void hw_atl_pci_pci_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 pci_reg_res_dis) +{ + aq_hw_write_reg_bit(aq_hw, HW_ATL_PCI_REG_RES_DSBL_ADR, + HW_ATL_PCI_REG_RES_DSBL_MSK, + HW_ATL_PCI_REG_RES_DSBL_SHIFT, + pci_reg_res_dis); +} + +void hw_atl_reg_glb_cpu_scratch_scp_set(struct aq_hw_s *aq_hw, + u32 glb_cpu_scratch_scp, + u32 scratch_scp) +{ + aq_hw_write_reg(aq_hw, HW_ATL_GLB_CPU_SCRATCH_SCP_ADR(scratch_scp), + glb_cpu_scratch_scp); +} + +void mcp_up_force_intr_set(struct aq_hw_s *aq_hw, u32 up_force_intr) +{ + aq_hw_write_reg_bit(aq_hw, mcp_up_force_interrupt_adr, + mcp_up_force_interrupt_msk, + mcp_up_force_interrupt_shift, up_force_intr); +} diff --git a/drivers/net/atlantic/hw_atl/hw_atl_llh.h b/drivers/net/atlantic/hw_atl/hw_atl_llh.h new file mode 100644 index 000000000000..f80d493d9fe0 --- /dev/null +++ b/drivers/net/atlantic/hw_atl/hw_atl_llh.h @@ -0,0 +1,714 @@ +/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) */ +/* Copyright (C) 2014-2017 aQuantia Corporation. */ + +/* File hw_atl_llh.h: Declarations of bitfield and register access functions for + * Atlantic registers. + */ + +#ifndef HW_ATL_LLH_H +#define HW_ATL_LLH_H + +#include "../atl_types.h" + +struct aq_hw_s; + +/* global */ + +/* set global microprocessor semaphore */ +void hw_atl_reg_glb_cpu_sem_set(struct aq_hw_s *aq_hw, u32 glb_cpu_sem, + u32 semaphore); + +/* get global microprocessor semaphore */ +u32 hw_atl_reg_glb_cpu_sem_get(struct aq_hw_s *aq_hw, u32 semaphore); + +/* set global register reset disable */ +void hw_atl_glb_glb_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 glb_reg_res_dis); + +/* set soft reset */ +void hw_atl_glb_soft_res_set(struct aq_hw_s *aq_hw, u32 soft_res); + +/* get soft reset */ +u32 hw_atl_glb_soft_res_get(struct aq_hw_s *aq_hw); + +/* stats */ + +u32 hw_atl_rpb_rx_dma_drop_pkt_cnt_get(struct aq_hw_s *aq_hw); + +/* get rx dma good octet counter lsw */ +u32 hw_atl_stats_rx_dma_good_octet_counterlsw_get(struct aq_hw_s *aq_hw); + +/* get rx dma good packet counter lsw */ +u32 hw_atl_stats_rx_dma_good_pkt_counterlsw_get(struct aq_hw_s *aq_hw); + +/* get tx dma good octet counter lsw */ +u32 hw_atl_stats_tx_dma_good_octet_counterlsw_get(struct aq_hw_s *aq_hw); + +/* get tx dma good packet counter lsw */ +u32 hw_atl_stats_tx_dma_good_pkt_counterlsw_get(struct aq_hw_s *aq_hw); + +/* get rx dma good octet counter msw */ +u32 hw_atl_stats_rx_dma_good_octet_countermsw_get(struct aq_hw_s *aq_hw); + +/* get rx dma good packet counter msw */ +u32 hw_atl_stats_rx_dma_good_pkt_countermsw_get(struct aq_hw_s *aq_hw); + +/* get tx dma good octet counter msw */ +u32 hw_atl_stats_tx_dma_good_octet_countermsw_get(struct aq_hw_s *aq_hw); + +/* get tx dma good packet counter msw */ +u32 hw_atl_stats_tx_dma_good_pkt_countermsw_get(struct aq_hw_s *aq_hw); + +/* get msm rx errors counter register */ +u32 hw_atl_reg_mac_msm_rx_errs_cnt_get(struct aq_hw_s *aq_hw); + +/* get msm rx unicast frames counter register */ +u32 hw_atl_reg_mac_msm_rx_ucst_frm_cnt_get(struct aq_hw_s *aq_hw); + +/* get msm rx multicast frames counter register */ +u32 hw_atl_reg_mac_msm_rx_mcst_frm_cnt_get(struct aq_hw_s *aq_hw); + +/* get msm rx broadcast frames counter register */ +u32 hw_atl_reg_mac_msm_rx_bcst_frm_cnt_get(struct aq_hw_s *aq_hw); + +/* get msm rx broadcast octets counter register 1 */ +u32 hw_atl_reg_mac_msm_rx_bcst_octets_counter1get(struct aq_hw_s *aq_hw); + +/* get msm rx unicast octets counter register 0 */ +u32 hw_atl_reg_mac_msm_rx_ucst_octets_counter0get(struct aq_hw_s *aq_hw); + +/* get rx dma statistics counter 7 */ +u32 hw_atl_reg_rx_dma_stat_counter7get(struct aq_hw_s *aq_hw); + +/* get msm tx errors counter register */ +u32 hw_atl_reg_mac_msm_tx_errs_cnt_get(struct aq_hw_s *aq_hw); + +/* get msm tx unicast frames counter register */ +u32 hw_atl_reg_mac_msm_tx_ucst_frm_cnt_get(struct aq_hw_s *aq_hw); + +/* get msm tx multicast frames counter register */ +u32 hw_atl_reg_mac_msm_tx_mcst_frm_cnt_get(struct aq_hw_s *aq_hw); + +/* get msm tx broadcast frames counter register */ +u32 hw_atl_reg_mac_msm_tx_bcst_frm_cnt_get(struct aq_hw_s *aq_hw); + +/* get msm tx multicast octets counter register 1 */ +u32 hw_atl_reg_mac_msm_tx_mcst_octets_counter1get(struct aq_hw_s *aq_hw); + +/* get msm tx broadcast octets counter register 1 */ +u32 hw_atl_reg_mac_msm_tx_bcst_octets_counter1get(struct aq_hw_s *aq_hw); + +/* get msm tx unicast octets counter register 0 */ +u32 hw_atl_reg_mac_msm_tx_ucst_octets_counter0get(struct aq_hw_s *aq_hw); + +/* get global mif identification */ +u32 hw_atl_reg_glb_mif_id_get(struct aq_hw_s *aq_hw); + +/* interrupt */ + +/* set interrupt auto mask lsw */ +void hw_atl_itr_irq_auto_masklsw_set(struct aq_hw_s *aq_hw, + u32 irq_auto_masklsw); + +/* set interrupt mapping enable rx */ +void hw_atl_itr_irq_map_en_rx_set(struct aq_hw_s *aq_hw, u32 irq_map_en_rx, + u32 rx); + +/* set interrupt mapping enable tx */ +void hw_atl_itr_irq_map_en_tx_set(struct aq_hw_s *aq_hw, u32 irq_map_en_tx, + u32 tx); + +/* set interrupt mapping rx */ +void hw_atl_itr_irq_map_rx_set(struct aq_hw_s *aq_hw, u32 irq_map_rx, u32 rx); + +/* set interrupt mapping tx */ +void hw_atl_itr_irq_map_tx_set(struct aq_hw_s *aq_hw, u32 irq_map_tx, u32 tx); + +/* set interrupt mask clear lsw */ +void hw_atl_itr_irq_msk_clearlsw_set(struct aq_hw_s *aq_hw, + u32 irq_msk_clearlsw); + +/* set interrupt mask set lsw */ +void hw_atl_itr_irq_msk_setlsw_set(struct aq_hw_s *aq_hw, u32 irq_msk_setlsw); + +/* set interrupt register reset disable */ +void hw_atl_itr_irq_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 irq_reg_res_dis); + +/* set interrupt status clear lsw */ +void hw_atl_itr_irq_status_clearlsw_set(struct aq_hw_s *aq_hw, + u32 irq_status_clearlsw); + +/* get interrupt status lsw */ +u32 hw_atl_itr_irq_statuslsw_get(struct aq_hw_s *aq_hw); + +/* get reset interrupt */ +u32 hw_atl_itr_res_irq_get(struct aq_hw_s *aq_hw); + +/* set reset interrupt */ +void hw_atl_itr_res_irq_set(struct aq_hw_s *aq_hw, u32 res_irq); + +/* rdm */ + +/* set cpu id */ +void hw_atl_rdm_cpu_id_set(struct aq_hw_s *aq_hw, u32 cpuid, u32 dca); + +/* set rx dca enable */ +void hw_atl_rdm_rx_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_dca_en); + +/* set rx dca mode */ +void hw_atl_rdm_rx_dca_mode_set(struct aq_hw_s *aq_hw, u32 rx_dca_mode); + +/* set rx descriptor data buffer size */ +void hw_atl_rdm_rx_desc_data_buff_size_set(struct aq_hw_s *aq_hw, + u32 rx_desc_data_buff_size, + u32 descriptor); + +/* set rx descriptor dca enable */ +void hw_atl_rdm_rx_desc_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_desc_dca_en, + u32 dca); + +/* set rx descriptor enable */ +void hw_atl_rdm_rx_desc_en_set(struct aq_hw_s *aq_hw, u32 rx_desc_en, + u32 descriptor); + +/* set rx descriptor header splitting */ +void hw_atl_rdm_rx_desc_head_splitting_set(struct aq_hw_s *aq_hw, + u32 rx_desc_head_splitting, + u32 descriptor); + +/* get rx descriptor head pointer */ +u32 hw_atl_rdm_rx_desc_head_ptr_get(struct aq_hw_s *aq_hw, u32 descriptor); + +/* set rx descriptor length */ +void hw_atl_rdm_rx_desc_len_set(struct aq_hw_s *aq_hw, u32 rx_desc_len, + u32 descriptor); + +/* set rx descriptor write-back interrupt enable */ +void hw_atl_rdm_rx_desc_wr_wb_irq_en_set(struct aq_hw_s *aq_hw, + u32 rx_desc_wr_wb_irq_en); + +/* set rx header dca enable */ +void hw_atl_rdm_rx_head_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_head_dca_en, + u32 dca); + +/* set rx payload dca enable */ +void hw_atl_rdm_rx_pld_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_pld_dca_en, + u32 dca); + +/* set rx descriptor header buffer size */ +void hw_atl_rdm_rx_desc_head_buff_size_set(struct aq_hw_s *aq_hw, + u32 rx_desc_head_buff_size, + u32 descriptor); + +/* set rx descriptor reset */ +void hw_atl_rdm_rx_desc_res_set(struct aq_hw_s *aq_hw, u32 rx_desc_res, + u32 descriptor); + +/* Set RDM Interrupt Moderation Enable */ +void hw_atl_rdm_rdm_intr_moder_en_set(struct aq_hw_s *aq_hw, + u32 rdm_intr_moder_en); + +/* reg */ + +/* set general interrupt mapping register */ +void hw_atl_reg_gen_irq_map_set(struct aq_hw_s *aq_hw, u32 gen_intr_map, + u32 regidx); + +/* get general interrupt status register */ +u32 hw_atl_reg_gen_irq_status_get(struct aq_hw_s *aq_hw); + +/* set interrupt global control register */ +void hw_atl_reg_irq_glb_ctl_set(struct aq_hw_s *aq_hw, u32 intr_glb_ctl); + +/* set interrupt throttle register */ +void hw_atl_reg_irq_thr_set(struct aq_hw_s *aq_hw, u32 intr_thr, u32 throttle); + +/* set rx dma descriptor base address lsw */ +void hw_atl_reg_rx_dma_desc_base_addresslswset(struct aq_hw_s *aq_hw, + u32 rx_dma_desc_base_addrlsw, + u32 descriptor); + +/* set rx dma descriptor base address msw */ +void hw_atl_reg_rx_dma_desc_base_addressmswset(struct aq_hw_s *aq_hw, + u32 rx_dma_desc_base_addrmsw, + u32 descriptor); + +/* get rx dma descriptor status register */ +u32 hw_atl_reg_rx_dma_desc_status_get(struct aq_hw_s *aq_hw, u32 descriptor); + +/* set rx dma descriptor tail pointer register */ +void hw_atl_reg_rx_dma_desc_tail_ptr_set(struct aq_hw_s *aq_hw, + u32 rx_dma_desc_tail_ptr, + u32 descriptor); + +/* set rx filter multicast filter mask register */ +void hw_atl_reg_rx_flr_mcst_flr_msk_set(struct aq_hw_s *aq_hw, + u32 rx_flr_mcst_flr_msk); + +/* set rx filter multicast filter register */ +void hw_atl_reg_rx_flr_mcst_flr_set(struct aq_hw_s *aq_hw, u32 rx_flr_mcst_flr, + u32 filter); + +/* set rx filter rss control register 1 */ +void hw_atl_reg_rx_flr_rss_control1set(struct aq_hw_s *aq_hw, + u32 rx_flr_rss_control1); + +/* Set RX Filter Control Register 2 */ +void hw_atl_reg_rx_flr_control2_set(struct aq_hw_s *aq_hw, u32 rx_flr_control2); + +/* Set RX Interrupt Moderation Control Register */ +void hw_atl_reg_rx_intr_moder_ctrl_set(struct aq_hw_s *aq_hw, + u32 rx_intr_moderation_ctl, + u32 queue); + +/* set tx dma debug control */ +void hw_atl_reg_tx_dma_debug_ctl_set(struct aq_hw_s *aq_hw, + u32 tx_dma_debug_ctl); + +/* set tx dma descriptor base address lsw */ +void hw_atl_reg_tx_dma_desc_base_addresslswset(struct aq_hw_s *aq_hw, + u32 tx_dma_desc_base_addrlsw, + u32 descriptor); + +/* set tx dma descriptor base address msw */ +void hw_atl_reg_tx_dma_desc_base_addressmswset(struct aq_hw_s *aq_hw, + u32 tx_dma_desc_base_addrmsw, + u32 descriptor); + +/* set tx dma descriptor tail pointer register */ +void hw_atl_reg_tx_dma_desc_tail_ptr_set(struct aq_hw_s *aq_hw, + u32 tx_dma_desc_tail_ptr, + u32 descriptor); + +/* Set TX Interrupt Moderation Control Register */ +void hw_atl_reg_tx_intr_moder_ctrl_set(struct aq_hw_s *aq_hw, + u32 tx_intr_moderation_ctl, + u32 queue); + +/* set global microprocessor scratch pad */ +void hw_atl_reg_glb_cpu_scratch_scp_set(struct aq_hw_s *aq_hw, + u32 glb_cpu_scratch_scp, + u32 scratch_scp); + +/* rpb */ + +/* set dma system loopback */ +void hw_atl_rpb_dma_sys_lbk_set(struct aq_hw_s *aq_hw, u32 dma_sys_lbk); + +/* set rx traffic class mode */ +void hw_atl_rpb_rpf_rx_traf_class_mode_set(struct aq_hw_s *aq_hw, + u32 rx_traf_class_mode); + +/* get rx traffic class mode */ +u32 hw_atl_rpb_rpf_rx_traf_class_mode_get(struct aq_hw_s *aq_hw); + +/* set rx buffer enable */ +void hw_atl_rpb_rx_buff_en_set(struct aq_hw_s *aq_hw, u32 rx_buff_en); + +/* set rx buffer high threshold (per tc) */ +void hw_atl_rpb_rx_buff_hi_threshold_per_tc_set(struct aq_hw_s *aq_hw, + u32 rx_buff_hi_threshold_per_tc, + u32 buffer); + +/* set rx buffer low threshold (per tc) */ +void hw_atl_rpb_rx_buff_lo_threshold_per_tc_set(struct aq_hw_s *aq_hw, + u32 rx_buff_lo_threshold_per_tc, + u32 buffer); + +/* set rx flow control mode */ +void hw_atl_rpb_rx_flow_ctl_mode_set(struct aq_hw_s *aq_hw, + u32 rx_flow_ctl_mode); + +/* set rx packet buffer size (per tc) */ +void hw_atl_rpb_rx_pkt_buff_size_per_tc_set(struct aq_hw_s *aq_hw, + u32 rx_pkt_buff_size_per_tc, + u32 buffer); + +/* set rx xoff enable (per tc) */ +void hw_atl_rpb_rx_xoff_en_per_tc_set(struct aq_hw_s *aq_hw, + u32 rx_xoff_en_per_tc, + u32 buffer); + +/* rpf */ + +/* set l2 broadcast count threshold */ +void hw_atl_rpfl2broadcast_count_threshold_set(struct aq_hw_s *aq_hw, + u32 l2broadcast_count_threshold); + +/* set l2 broadcast enable */ +void hw_atl_rpfl2broadcast_en_set(struct aq_hw_s *aq_hw, u32 l2broadcast_en); + +/* set l2 broadcast filter action */ +void hw_atl_rpfl2broadcast_flr_act_set(struct aq_hw_s *aq_hw, + u32 l2broadcast_flr_act); + +/* set l2 multicast filter enable */ +void hw_atl_rpfl2multicast_flr_en_set(struct aq_hw_s *aq_hw, + u32 l2multicast_flr_en, + u32 filter); + +/* set l2 promiscuous mode enable */ +void hw_atl_rpfl2promiscuous_mode_en_set(struct aq_hw_s *aq_hw, + u32 l2promiscuous_mode_en); + +/* set l2 unicast filter action */ +void hw_atl_rpfl2unicast_flr_act_set(struct aq_hw_s *aq_hw, + u32 l2unicast_flr_act, + u32 filter); + +/* set l2 unicast filter enable */ +void hw_atl_rpfl2_uc_flr_en_set(struct aq_hw_s *aq_hw, u32 l2unicast_flr_en, + u32 filter); + +/* set l2 unicast destination address lsw */ +void hw_atl_rpfl2unicast_dest_addresslsw_set(struct aq_hw_s *aq_hw, + u32 l2unicast_dest_addresslsw, + u32 filter); + +/* set l2 unicast destination address msw */ +void hw_atl_rpfl2unicast_dest_addressmsw_set(struct aq_hw_s *aq_hw, + u32 l2unicast_dest_addressmsw, + u32 filter); + +/* Set L2 Accept all Multicast packets */ +void hw_atl_rpfl2_accept_all_mc_packets_set(struct aq_hw_s *aq_hw, + u32 l2_accept_all_mc_packets); + +/* set user-priority tc mapping */ +void hw_atl_rpf_rpb_user_priority_tc_map_set(struct aq_hw_s *aq_hw, + u32 user_priority_tc_map, u32 tc); + +/* set rss key address */ +void hw_atl_rpf_rss_key_addr_set(struct aq_hw_s *aq_hw, u32 rss_key_addr); + +/* set rss key write data */ +void hw_atl_rpf_rss_key_wr_data_set(struct aq_hw_s *aq_hw, u32 rss_key_wr_data); + +/* get rss key write enable */ +u32 hw_atl_rpf_rss_key_wr_en_get(struct aq_hw_s *aq_hw); + +/* set rss key write enable */ +void hw_atl_rpf_rss_key_wr_en_set(struct aq_hw_s *aq_hw, u32 rss_key_wr_en); + +/* set rss redirection table address */ +void hw_atl_rpf_rss_redir_tbl_addr_set(struct aq_hw_s *aq_hw, + u32 rss_redir_tbl_addr); + +/* set rss redirection table write data */ +void hw_atl_rpf_rss_redir_tbl_wr_data_set(struct aq_hw_s *aq_hw, + u32 rss_redir_tbl_wr_data); + +/* get rss redirection write enable */ +u32 hw_atl_rpf_rss_redir_wr_en_get(struct aq_hw_s *aq_hw); + +/* set rss redirection write enable */ +void hw_atl_rpf_rss_redir_wr_en_set(struct aq_hw_s *aq_hw, u32 rss_redir_wr_en); + +/* set tpo to rpf system loopback */ +void hw_atl_rpf_tpo_to_rpf_sys_lbk_set(struct aq_hw_s *aq_hw, + u32 tpo_to_rpf_sys_lbk); + +/* set vlan inner ethertype */ +void hw_atl_rpf_vlan_inner_etht_set(struct aq_hw_s *aq_hw, u32 vlan_inner_etht); + +/* set vlan outer ethertype */ +void hw_atl_rpf_vlan_outer_etht_set(struct aq_hw_s *aq_hw, u32 vlan_outer_etht); + +/* set vlan promiscuous mode enable */ +void hw_atl_rpf_vlan_prom_mode_en_set(struct aq_hw_s *aq_hw, + u32 vlan_prom_mode_en); + +/* Set VLAN untagged action */ +void hw_atl_rpf_vlan_untagged_act_set(struct aq_hw_s *aq_hw, + u32 vlan_untagged_act); + +/* Set VLAN accept untagged packets */ +void hw_atl_rpf_vlan_accept_untagged_packets_set(struct aq_hw_s *aq_hw, + u32 vlan_acc_untagged_packets); + +/* Set VLAN filter enable */ +void hw_atl_rpf_vlan_flr_en_set(struct aq_hw_s *aq_hw, u32 vlan_flr_en, + u32 filter); + +/* Set VLAN Filter Action */ +void hw_atl_rpf_vlan_flr_act_set(struct aq_hw_s *aq_hw, u32 vlan_filter_act, + u32 filter); + +/* Set VLAN ID Filter */ +void hw_atl_rpf_vlan_id_flr_set(struct aq_hw_s *aq_hw, u32 vlan_id_flr, + u32 filter); + +/* set ethertype filter enable */ +void hw_atl_rpf_etht_flr_en_set(struct aq_hw_s *aq_hw, u32 etht_flr_en, + u32 filter); + +/* set ethertype user-priority enable */ +void hw_atl_rpf_etht_user_priority_en_set(struct aq_hw_s *aq_hw, + u32 etht_user_priority_en, + u32 filter); + +/* set ethertype rx queue enable */ +void hw_atl_rpf_etht_rx_queue_en_set(struct aq_hw_s *aq_hw, + u32 etht_rx_queue_en, + u32 filter); + +/* set ethertype rx queue */ +void hw_atl_rpf_etht_rx_queue_set(struct aq_hw_s *aq_hw, u32 etht_rx_queue, + u32 filter); + +/* set ethertype user-priority */ +void hw_atl_rpf_etht_user_priority_set(struct aq_hw_s *aq_hw, + u32 etht_user_priority, + u32 filter); + +/* set ethertype management queue */ +void hw_atl_rpf_etht_mgt_queue_set(struct aq_hw_s *aq_hw, u32 etht_mgt_queue, + u32 filter); + +/* set ethertype filter action */ +void hw_atl_rpf_etht_flr_act_set(struct aq_hw_s *aq_hw, u32 etht_flr_act, + u32 filter); + +/* set ethertype filter */ +void hw_atl_rpf_etht_flr_set(struct aq_hw_s *aq_hw, u32 etht_flr, u32 filter); + +/* rpo */ + +/* set ipv4 header checksum offload enable */ +void hw_atl_rpo_ipv4header_crc_offload_en_set(struct aq_hw_s *aq_hw, + u32 ipv4header_crc_offload_en); + +/* set rx descriptor vlan stripping */ +void hw_atl_rpo_rx_desc_vlan_stripping_set(struct aq_hw_s *aq_hw, + u32 rx_desc_vlan_stripping, + u32 descriptor); + +/* set tcp/udp checksum offload enable */ +void hw_atl_rpo_tcp_udp_crc_offload_en_set(struct aq_hw_s *aq_hw, + u32 tcp_udp_crc_offload_en); + +/* Set LRO Patch Optimization Enable. */ +void hw_atl_rpo_lro_patch_optimization_en_set(struct aq_hw_s *aq_hw, + u32 lro_patch_optimization_en); + +/* Set Large Receive Offload Enable */ +void hw_atl_rpo_lro_en_set(struct aq_hw_s *aq_hw, u32 lro_en); + +/* Set LRO Q Sessions Limit */ +void hw_atl_rpo_lro_qsessions_lim_set(struct aq_hw_s *aq_hw, + u32 lro_qsessions_lim); + +/* Set LRO Total Descriptor Limit */ +void hw_atl_rpo_lro_total_desc_lim_set(struct aq_hw_s *aq_hw, + u32 lro_total_desc_lim); + +/* Set LRO Min Payload of First Packet */ +void hw_atl_rpo_lro_min_pay_of_first_pkt_set(struct aq_hw_s *aq_hw, + u32 lro_min_pld_of_first_pkt); + +/* Set LRO Packet Limit */ +void hw_atl_rpo_lro_pkt_lim_set(struct aq_hw_s *aq_hw, u32 lro_packet_lim); + +/* Set LRO Max Number of Descriptors */ +void hw_atl_rpo_lro_max_num_of_descriptors_set(struct aq_hw_s *aq_hw, + u32 lro_max_desc_num, u32 lro); + +/* Set LRO Time Base Divider */ +void hw_atl_rpo_lro_time_base_divider_set(struct aq_hw_s *aq_hw, + u32 lro_time_base_divider); + +/*Set LRO Inactive Interval */ +void hw_atl_rpo_lro_inactive_interval_set(struct aq_hw_s *aq_hw, + u32 lro_inactive_interval); + +/*Set LRO Max Coalescing Interval */ +void hw_atl_rpo_lro_max_coalescing_interval_set(struct aq_hw_s *aq_hw, + u32 lro_max_coal_interval); + +/* rx */ + +/* set rx register reset disable */ +void hw_atl_rx_rx_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 rx_reg_res_dis); + +/* tdm */ + +/* set cpu id */ +void hw_atl_tdm_cpu_id_set(struct aq_hw_s *aq_hw, u32 cpuid, u32 dca); + +/* set large send offload enable */ +void hw_atl_tdm_large_send_offload_en_set(struct aq_hw_s *aq_hw, + u32 large_send_offload_en); + +/* set tx descriptor enable */ +void hw_atl_tdm_tx_desc_en_set(struct aq_hw_s *aq_hw, u32 tx_desc_en, + u32 descriptor); + +/* set tx dca enable */ +void hw_atl_tdm_tx_dca_en_set(struct aq_hw_s *aq_hw, u32 tx_dca_en); + +/* set tx dca mode */ +void hw_atl_tdm_tx_dca_mode_set(struct aq_hw_s *aq_hw, u32 tx_dca_mode); + +/* set tx descriptor dca enable */ +void hw_atl_tdm_tx_desc_dca_en_set(struct aq_hw_s *aq_hw, u32 tx_desc_dca_en, + u32 dca); + +/* get tx descriptor head pointer */ +u32 hw_atl_tdm_tx_desc_head_ptr_get(struct aq_hw_s *aq_hw, u32 descriptor); + +/* set tx descriptor length */ +void hw_atl_tdm_tx_desc_len_set(struct aq_hw_s *aq_hw, u32 tx_desc_len, + u32 descriptor); + +/* set tx descriptor write-back interrupt enable */ +void hw_atl_tdm_tx_desc_wr_wb_irq_en_set(struct aq_hw_s *aq_hw, + u32 tx_desc_wr_wb_irq_en); + +/* set tx descriptor write-back threshold */ +void hw_atl_tdm_tx_desc_wr_wb_threshold_set(struct aq_hw_s *aq_hw, + u32 tx_desc_wr_wb_threshold, + u32 descriptor); + +/* Set TDM Interrupt Moderation Enable */ +void hw_atl_tdm_tdm_intr_moder_en_set(struct aq_hw_s *aq_hw, + u32 tdm_irq_moderation_en); +/* thm */ + +/* set lso tcp flag of first packet */ +void hw_atl_thm_lso_tcp_flag_of_first_pkt_set(struct aq_hw_s *aq_hw, + u32 lso_tcp_flag_of_first_pkt); + +/* set lso tcp flag of last packet */ +void hw_atl_thm_lso_tcp_flag_of_last_pkt_set(struct aq_hw_s *aq_hw, + u32 lso_tcp_flag_of_last_pkt); + +/* set lso tcp flag of middle packet */ +void hw_atl_thm_lso_tcp_flag_of_middle_pkt_set(struct aq_hw_s *aq_hw, + u32 lso_tcp_flag_of_middle_pkt); + +/* tpb */ + +/* set TX Traffic Class Mode */ +void hw_atl_rpb_tps_tx_tc_mode_set(struct aq_hw_s *aq_hw, + u32 tx_traf_class_mode); + +/* get TX Traffic Class Mode */ +u32 hw_atl_rpb_tps_tx_tc_mode_get(struct aq_hw_s *aq_hw); + +/* set tx buffer enable */ +void hw_atl_tpb_tx_buff_en_set(struct aq_hw_s *aq_hw, u32 tx_buff_en); + +/* set tx buffer high threshold (per tc) */ +void hw_atl_tpb_tx_buff_hi_threshold_per_tc_set(struct aq_hw_s *aq_hw, + u32 tx_buff_hi_threshold_per_tc, + u32 buffer); + +/* set tx buffer low threshold (per tc) */ +void hw_atl_tpb_tx_buff_lo_threshold_per_tc_set(struct aq_hw_s *aq_hw, + u32 tx_buff_lo_threshold_per_tc, + u32 buffer); + +/* set tx dma system loopback enable */ +void hw_atl_tpb_tx_dma_sys_lbk_en_set(struct aq_hw_s *aq_hw, + u32 tx_dma_sys_lbk_en); + +/* set tx packet buffer size (per tc) */ +void hw_atl_tpb_tx_pkt_buff_size_per_tc_set(struct aq_hw_s *aq_hw, + u32 tx_pkt_buff_size_per_tc, + u32 buffer); + +/* set tx path pad insert enable */ +void hw_atl_tpb_tx_path_scp_ins_en_set(struct aq_hw_s *aq_hw, + u32 tx_path_scp_ins_en); + +/* tpo */ + +/* set ipv4 header checksum offload enable */ +void hw_atl_tpo_ipv4header_crc_offload_en_set(struct aq_hw_s *aq_hw, + u32 ipv4header_crc_offload_en); + +/* set tcp/udp checksum offload enable */ +void hw_atl_tpo_tcp_udp_crc_offload_en_set(struct aq_hw_s *aq_hw, + u32 tcp_udp_crc_offload_en); + +/* set tx pkt system loopback enable */ +void hw_atl_tpo_tx_pkt_sys_lbk_en_set(struct aq_hw_s *aq_hw, + u32 tx_pkt_sys_lbk_en); + +/* tps */ + +/* set tx packet scheduler data arbitration mode */ +void hw_atl_tps_tx_pkt_shed_data_arb_mode_set(struct aq_hw_s *aq_hw, + u32 tx_pkt_shed_data_arb_mode); + +/* set tx packet scheduler descriptor rate current time reset */ +void hw_atl_tps_tx_pkt_shed_desc_rate_curr_time_res_set(struct aq_hw_s *aq_hw, + u32 curr_time_res); + +/* set tx packet scheduler descriptor rate limit */ +void hw_atl_tps_tx_pkt_shed_desc_rate_lim_set(struct aq_hw_s *aq_hw, + u32 tx_pkt_shed_desc_rate_lim); + +/* set tx packet scheduler descriptor tc arbitration mode */ +void hw_atl_tps_tx_pkt_shed_desc_tc_arb_mode_set(struct aq_hw_s *aq_hw, + u32 arb_mode); + +/* set tx packet scheduler descriptor tc max credit */ +void hw_atl_tps_tx_pkt_shed_desc_tc_max_credit_set(struct aq_hw_s *aq_hw, + u32 max_credit, + u32 tc); + +/* set tx packet scheduler descriptor tc weight */ +void hw_atl_tps_tx_pkt_shed_desc_tc_weight_set(struct aq_hw_s *aq_hw, + u32 tx_pkt_shed_desc_tc_weight, + u32 tc); + +/* set tx packet scheduler descriptor vm arbitration mode */ +void hw_atl_tps_tx_pkt_shed_desc_vm_arb_mode_set(struct aq_hw_s *aq_hw, + u32 arb_mode); + +/* set tx packet scheduler tc data max credit */ +void hw_atl_tps_tx_pkt_shed_tc_data_max_credit_set(struct aq_hw_s *aq_hw, + u32 max_credit, + u32 tc); + +/* set tx packet scheduler tc data weight */ +void hw_atl_tps_tx_pkt_shed_tc_data_weight_set(struct aq_hw_s *aq_hw, + u32 tx_pkt_shed_tc_data_weight, + u32 tc); + +/* tx */ + +/* set tx register reset disable */ +void hw_atl_tx_tx_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 tx_reg_res_dis); + +/* msm */ + +/* get register access status */ +u32 hw_atl_msm_reg_access_status_get(struct aq_hw_s *aq_hw); + +/* set register address for indirect address */ +void hw_atl_msm_reg_addr_for_indirect_addr_set(struct aq_hw_s *aq_hw, + u32 reg_addr_for_indirect_addr); + +/* set register read strobe */ +void hw_atl_msm_reg_rd_strobe_set(struct aq_hw_s *aq_hw, u32 reg_rd_strobe); + +/* get register read data */ +u32 hw_atl_msm_reg_rd_data_get(struct aq_hw_s *aq_hw); + +/* set register write data */ +void hw_atl_msm_reg_wr_data_set(struct aq_hw_s *aq_hw, u32 reg_wr_data); + +/* set register write strobe */ +void hw_atl_msm_reg_wr_strobe_set(struct aq_hw_s *aq_hw, u32 reg_wr_strobe); + +/* pci */ + +/* set pci register reset disable */ +void hw_atl_pci_pci_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 pci_reg_res_dis); + +/* set uP Force Interrupt */ +void mcp_up_force_intr_set(struct aq_hw_s *aq_hw, u32 up_force_intr); + + +#endif /* HW_ATL_LLH_H */ diff --git a/drivers/net/atlantic/hw_atl/hw_atl_llh_internal.h b/drivers/net/atlantic/hw_atl/hw_atl_llh_internal.h new file mode 100644 index 000000000000..b6d431eb67c8 --- /dev/null +++ b/drivers/net/atlantic/hw_atl/hw_atl_llh_internal.h @@ -0,0 +1,2407 @@ +/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) */ +/* Copyright (C) 2014-2017 aQuantia Corporation. */ + +/* File hw_atl_llh_internal.h: Preprocessor definitions + * for Atlantic registers. + */ + +#ifndef HW_ATL_LLH_INTERNAL_H +#define HW_ATL_LLH_INTERNAL_H + +/* global microprocessor semaphore definitions + * base address: 0x000003a0 + * parameter: semaphore {s} | stride size 0x4 | range [0, 15] + */ +#define HW_ATL_GLB_CPU_SEM_ADR(semaphore) (0x000003a0u + (semaphore) * 0x4) +/* register address for bitfield rx dma good octet counter lsw [1f:0] */ +#define HW_ATL_STATS_RX_DMA_GOOD_OCTET_COUNTERLSW 0x00006808 +/* register address for bitfield rx dma good packet counter lsw [1f:0] */ +#define HW_ATL_STATS_RX_DMA_GOOD_PKT_COUNTERLSW 0x00006800 +/* register address for bitfield tx dma good octet counter lsw [1f:0] */ +#define HW_ATL_STATS_TX_DMA_GOOD_OCTET_COUNTERLSW 0x00008808 +/* register address for bitfield tx dma good packet counter lsw [1f:0] */ +#define HW_ATL_STATS_TX_DMA_GOOD_PKT_COUNTERLSW 0x00008800 + +/* register address for bitfield rx dma good octet counter msw [3f:20] */ +#define HW_ATL_STATS_RX_DMA_GOOD_OCTET_COUNTERMSW 0x0000680c +/* register address for bitfield rx dma good packet counter msw [3f:20] */ +#define HW_ATL_STATS_RX_DMA_GOOD_PKT_COUNTERMSW 0x00006804 +/* register address for bitfield tx dma good octet counter msw [3f:20] */ +#define HW_ATL_STATS_TX_DMA_GOOD_OCTET_COUNTERMSW 0x0000880c +/* register address for bitfield tx dma good packet counter msw [3f:20] */ +#define HW_ATL_STATS_TX_DMA_GOOD_PKT_COUNTERMSW 0x00008804 + +/* preprocessor definitions for msm rx errors counter register */ +#define HW_ATL_MAC_MSM_RX_ERRS_CNT_ADR 0x00000120u + +/* preprocessor definitions for msm rx unicast frames counter register */ +#define HW_ATL_MAC_MSM_RX_UCST_FRM_CNT_ADR 0x000000e0u + +/* preprocessor definitions for msm rx multicast frames counter register */ +#define HW_ATL_MAC_MSM_RX_MCST_FRM_CNT_ADR 0x000000e8u + +/* preprocessor definitions for msm rx broadcast frames counter register */ +#define HW_ATL_MAC_MSM_RX_BCST_FRM_CNT_ADR 0x000000f0u + +/* preprocessor definitions for msm rx broadcast octets counter register 1 */ +#define HW_ATL_MAC_MSM_RX_BCST_OCTETS_COUNTER1_ADR 0x000001b0u + +/* preprocessor definitions for msm rx broadcast octets counter register 2 */ +#define HW_ATL_MAC_MSM_RX_BCST_OCTETS_COUNTER2_ADR 0x000001b4u + +/* preprocessor definitions for msm rx unicast octets counter register 0 */ +#define HW_ATL_MAC_MSM_RX_UCST_OCTETS_COUNTER0_ADR 0x000001b8u + +/* preprocessor definitions for msm tx unicast frames counter register */ +#define HW_ATL_MAC_MSM_TX_UCST_FRM_CNT_ADR 0x00000108u + +/* preprocessor definitions for msm tx multicast frames counter register */ +#define HW_ATL_MAC_MSM_TX_MCST_FRM_CNT_ADR 0x00000110u + +/* preprocessor definitions for global mif identification */ +#define HW_ATL_GLB_MIF_ID_ADR 0x0000001cu + +/* register address for bitfield iamr_lsw[1f:0] */ +#define HW_ATL_ITR_IAMRLSW_ADR 0x00002090 +/* register address for bitfield rx dma drop packet counter [1f:0] */ +#define HW_ATL_RPB_RX_DMA_DROP_PKT_CNT_ADR 0x00006818 + +/* register address for bitfield imcr_lsw[1f:0] */ +#define HW_ATL_ITR_IMCRLSW_ADR 0x00002070 +/* register address for bitfield imsr_lsw[1f:0] */ +#define HW_ATL_ITR_IMSRLSW_ADR 0x00002060 +/* register address for bitfield itr_reg_res_dsbl */ +#define HW_ATL_ITR_REG_RES_DSBL_ADR 0x00002300 +/* bitmask for bitfield itr_reg_res_dsbl */ +#define HW_ATL_ITR_REG_RES_DSBL_MSK 0x20000000 +/* lower bit position of bitfield itr_reg_res_dsbl */ +#define HW_ATL_ITR_REG_RES_DSBL_SHIFT 29 +/* register address for bitfield iscr_lsw[1f:0] */ +#define HW_ATL_ITR_ISCRLSW_ADR 0x00002050 +/* register address for bitfield isr_lsw[1f:0] */ +#define HW_ATL_ITR_ISRLSW_ADR 0x00002000 +/* register address for bitfield itr_reset */ +#define HW_ATL_ITR_RES_ADR 0x00002300 +/* bitmask for bitfield itr_reset */ +#define HW_ATL_ITR_RES_MSK 0x80000000 +/* lower bit position of bitfield itr_reset */ +#define HW_ATL_ITR_RES_SHIFT 31 +/* register address for bitfield dca{d}_cpuid[7:0] */ +#define HW_ATL_RDM_DCADCPUID_ADR(dca) (0x00006100 + (dca) * 0x4) +/* bitmask for bitfield dca{d}_cpuid[7:0] */ +#define HW_ATL_RDM_DCADCPUID_MSK 0x000000ff +/* lower bit position of bitfield dca{d}_cpuid[7:0] */ +#define HW_ATL_RDM_DCADCPUID_SHIFT 0 +/* register address for bitfield dca_en */ +#define HW_ATL_RDM_DCA_EN_ADR 0x00006180 + +/* rx dca_en bitfield definitions + * preprocessor definitions for the bitfield "dca_en". + * port="pif_rdm_dca_en_i" + */ + +/* register address for bitfield dca_en */ +#define HW_ATL_RDM_DCA_EN_ADR 0x00006180 +/* bitmask for bitfield dca_en */ +#define HW_ATL_RDM_DCA_EN_MSK 0x80000000 +/* inverted bitmask for bitfield dca_en */ +#define HW_ATL_RDM_DCA_EN_MSKN 0x7fffffff +/* lower bit position of bitfield dca_en */ +#define HW_ATL_RDM_DCA_EN_SHIFT 31 +/* width of bitfield dca_en */ +#define HW_ATL_RDM_DCA_EN_WIDTH 1 +/* default value of bitfield dca_en */ +#define HW_ATL_RDM_DCA_EN_DEFAULT 0x1 + +/* rx dca_mode[3:0] bitfield definitions + * preprocessor definitions for the bitfield "dca_mode[3:0]". + * port="pif_rdm_dca_mode_i[3:0]" + */ + +/* register address for bitfield dca_mode[3:0] */ +#define HW_ATL_RDM_DCA_MODE_ADR 0x00006180 +/* bitmask for bitfield dca_mode[3:0] */ +#define HW_ATL_RDM_DCA_MODE_MSK 0x0000000f +/* inverted bitmask for bitfield dca_mode[3:0] */ +#define HW_ATL_RDM_DCA_MODE_MSKN 0xfffffff0 +/* lower bit position of bitfield dca_mode[3:0] */ +#define HW_ATL_RDM_DCA_MODE_SHIFT 0 +/* width of bitfield dca_mode[3:0] */ +#define HW_ATL_RDM_DCA_MODE_WIDTH 4 +/* default value of bitfield dca_mode[3:0] */ +#define HW_ATL_RDM_DCA_MODE_DEFAULT 0x0 + +/* rx desc{d}_data_size[4:0] bitfield definitions + * preprocessor definitions for the bitfield "desc{d}_data_size[4:0]". + * parameter: descriptor {d} | stride size 0x20 | range [0, 31] + * port="pif_rdm_desc0_data_size_i[4:0]" + */ + +/* register address for bitfield desc{d}_data_size[4:0] */ +#define HW_ATL_RDM_DESCDDATA_SIZE_ADR(descriptor) \ + (0x00005b18 + (descriptor) * 0x20) +/* bitmask for bitfield desc{d}_data_size[4:0] */ +#define HW_ATL_RDM_DESCDDATA_SIZE_MSK 0x0000001f +/* inverted bitmask for bitfield desc{d}_data_size[4:0] */ +#define HW_ATL_RDM_DESCDDATA_SIZE_MSKN 0xffffffe0 +/* lower bit position of bitfield desc{d}_data_size[4:0] */ +#define HW_ATL_RDM_DESCDDATA_SIZE_SHIFT 0 +/* width of bitfield desc{d}_data_size[4:0] */ +#define HW_ATL_RDM_DESCDDATA_SIZE_WIDTH 5 +/* default value of bitfield desc{d}_data_size[4:0] */ +#define HW_ATL_RDM_DESCDDATA_SIZE_DEFAULT 0x0 + +/* rx dca{d}_desc_en bitfield definitions + * preprocessor definitions for the bitfield "dca{d}_desc_en". + * parameter: dca {d} | stride size 0x4 | range [0, 31] + * port="pif_rdm_dca_desc_en_i[0]" + */ + +/* register address for bitfield dca{d}_desc_en */ +#define HW_ATL_RDM_DCADDESC_EN_ADR(dca) (0x00006100 + (dca) * 0x4) +/* bitmask for bitfield dca{d}_desc_en */ +#define HW_ATL_RDM_DCADDESC_EN_MSK 0x80000000 +/* inverted bitmask for bitfield dca{d}_desc_en */ +#define HW_ATL_RDM_DCADDESC_EN_MSKN 0x7fffffff +/* lower bit position of bitfield dca{d}_desc_en */ +#define HW_ATL_RDM_DCADDESC_EN_SHIFT 31 +/* width of bitfield dca{d}_desc_en */ +#define HW_ATL_RDM_DCADDESC_EN_WIDTH 1 +/* default value of bitfield dca{d}_desc_en */ +#define HW_ATL_RDM_DCADDESC_EN_DEFAULT 0x0 + +/* rx desc{d}_en bitfield definitions + * preprocessor definitions for the bitfield "desc{d}_en". + * parameter: descriptor {d} | stride size 0x20 | range [0, 31] + * port="pif_rdm_desc_en_i[0]" + */ + +/* register address for bitfield desc{d}_en */ +#define HW_ATL_RDM_DESCDEN_ADR(descriptor) (0x00005b08 + (descriptor) * 0x20) +/* bitmask for bitfield desc{d}_en */ +#define HW_ATL_RDM_DESCDEN_MSK 0x80000000 +/* inverted bitmask for bitfield desc{d}_en */ +#define HW_ATL_RDM_DESCDEN_MSKN 0x7fffffff +/* lower bit position of bitfield desc{d}_en */ +#define HW_ATL_RDM_DESCDEN_SHIFT 31 +/* width of bitfield desc{d}_en */ +#define HW_ATL_RDM_DESCDEN_WIDTH 1 +/* default value of bitfield desc{d}_en */ +#define HW_ATL_RDM_DESCDEN_DEFAULT 0x0 + +/* rx desc{d}_hdr_size[4:0] bitfield definitions + * preprocessor definitions for the bitfield "desc{d}_hdr_size[4:0]". + * parameter: descriptor {d} | stride size 0x20 | range [0, 31] + * port="pif_rdm_desc0_hdr_size_i[4:0]" + */ + +/* register address for bitfield desc{d}_hdr_size[4:0] */ +#define HW_ATL_RDM_DESCDHDR_SIZE_ADR(descriptor) \ + (0x00005b18 + (descriptor) * 0x20) +/* bitmask for bitfield desc{d}_hdr_size[4:0] */ +#define HW_ATL_RDM_DESCDHDR_SIZE_MSK 0x00001f00 +/* inverted bitmask for bitfield desc{d}_hdr_size[4:0] */ +#define HW_ATL_RDM_DESCDHDR_SIZE_MSKN 0xffffe0ff +/* lower bit position of bitfield desc{d}_hdr_size[4:0] */ +#define HW_ATL_RDM_DESCDHDR_SIZE_SHIFT 8 +/* width of bitfield desc{d}_hdr_size[4:0] */ +#define HW_ATL_RDM_DESCDHDR_SIZE_WIDTH 5 +/* default value of bitfield desc{d}_hdr_size[4:0] */ +#define HW_ATL_RDM_DESCDHDR_SIZE_DEFAULT 0x0 + +/* rx desc{d}_hdr_split bitfield definitions + * preprocessor definitions for the bitfield "desc{d}_hdr_split". + * parameter: descriptor {d} | stride size 0x20 | range [0, 31] + * port="pif_rdm_desc_hdr_split_i[0]" + */ + +/* register address for bitfield desc{d}_hdr_split */ +#define HW_ATL_RDM_DESCDHDR_SPLIT_ADR(descriptor) \ + (0x00005b08 + (descriptor) * 0x20) +/* bitmask for bitfield desc{d}_hdr_split */ +#define HW_ATL_RDM_DESCDHDR_SPLIT_MSK 0x10000000 +/* inverted bitmask for bitfield desc{d}_hdr_split */ +#define HW_ATL_RDM_DESCDHDR_SPLIT_MSKN 0xefffffff +/* lower bit position of bitfield desc{d}_hdr_split */ +#define HW_ATL_RDM_DESCDHDR_SPLIT_SHIFT 28 +/* width of bitfield desc{d}_hdr_split */ +#define HW_ATL_RDM_DESCDHDR_SPLIT_WIDTH 1 +/* default value of bitfield desc{d}_hdr_split */ +#define HW_ATL_RDM_DESCDHDR_SPLIT_DEFAULT 0x0 + +/* rx desc{d}_hd[c:0] bitfield definitions + * preprocessor definitions for the bitfield "desc{d}_hd[c:0]". + * parameter: descriptor {d} | stride size 0x20 | range [0, 31] + * port="rdm_pif_desc0_hd_o[12:0]" + */ + +/* register address for bitfield desc{d}_hd[c:0] */ +#define HW_ATL_RDM_DESCDHD_ADR(descriptor) (0x00005b0c + (descriptor) * 0x20) +/* bitmask for bitfield desc{d}_hd[c:0] */ +#define HW_ATL_RDM_DESCDHD_MSK 0x00001fff +/* inverted bitmask for bitfield desc{d}_hd[c:0] */ +#define HW_ATL_RDM_DESCDHD_MSKN 0xffffe000 +/* lower bit position of bitfield desc{d}_hd[c:0] */ +#define HW_ATL_RDM_DESCDHD_SHIFT 0 +/* width of bitfield desc{d}_hd[c:0] */ +#define HW_ATL_RDM_DESCDHD_WIDTH 13 + +/* rx desc{d}_len[9:0] bitfield definitions + * preprocessor definitions for the bitfield "desc{d}_len[9:0]". + * parameter: descriptor {d} | stride size 0x20 | range [0, 31] + * port="pif_rdm_desc0_len_i[9:0]" + */ + +/* register address for bitfield desc{d}_len[9:0] */ +#define HW_ATL_RDM_DESCDLEN_ADR(descriptor) (0x00005b08 + (descriptor) * 0x20) +/* bitmask for bitfield desc{d}_len[9:0] */ +#define HW_ATL_RDM_DESCDLEN_MSK 0x00001ff8 +/* inverted bitmask for bitfield desc{d}_len[9:0] */ +#define HW_ATL_RDM_DESCDLEN_MSKN 0xffffe007 +/* lower bit position of bitfield desc{d}_len[9:0] */ +#define HW_ATL_RDM_DESCDLEN_SHIFT 3 +/* width of bitfield desc{d}_len[9:0] */ +#define HW_ATL_RDM_DESCDLEN_WIDTH 10 +/* default value of bitfield desc{d}_len[9:0] */ +#define HW_ATL_RDM_DESCDLEN_DEFAULT 0x0 + +/* rx desc{d}_reset bitfield definitions + * preprocessor definitions for the bitfield "desc{d}_reset". + * parameter: descriptor {d} | stride size 0x20 | range [0, 31] + * port="pif_rdm_q_pf_res_i[0]" + */ + +/* register address for bitfield desc{d}_reset */ +#define HW_ATL_RDM_DESCDRESET_ADR(descriptor) (0x00005b08 + (descriptor) * 0x20) +/* bitmask for bitfield desc{d}_reset */ +#define HW_ATL_RDM_DESCDRESET_MSK 0x02000000 +/* inverted bitmask for bitfield desc{d}_reset */ +#define HW_ATL_RDM_DESCDRESET_MSKN 0xfdffffff +/* lower bit position of bitfield desc{d}_reset */ +#define HW_ATL_RDM_DESCDRESET_SHIFT 25 +/* width of bitfield desc{d}_reset */ +#define HW_ATL_RDM_DESCDRESET_WIDTH 1 +/* default value of bitfield desc{d}_reset */ +#define HW_ATL_RDM_DESCDRESET_DEFAULT 0x0 + +/* rx int_desc_wrb_en bitfield definitions + * preprocessor definitions for the bitfield "int_desc_wrb_en". + * port="pif_rdm_int_desc_wrb_en_i" + */ + +/* register address for bitfield int_desc_wrb_en */ +#define HW_ATL_RDM_INT_DESC_WRB_EN_ADR 0x00005a30 +/* bitmask for bitfield int_desc_wrb_en */ +#define HW_ATL_RDM_INT_DESC_WRB_EN_MSK 0x00000004 +/* inverted bitmask for bitfield int_desc_wrb_en */ +#define HW_ATL_RDM_INT_DESC_WRB_EN_MSKN 0xfffffffb +/* lower bit position of bitfield int_desc_wrb_en */ +#define HW_ATL_RDM_INT_DESC_WRB_EN_SHIFT 2 +/* width of bitfield int_desc_wrb_en */ +#define HW_ATL_RDM_INT_DESC_WRB_EN_WIDTH 1 +/* default value of bitfield int_desc_wrb_en */ +#define HW_ATL_RDM_INT_DESC_WRB_EN_DEFAULT 0x0 + +/* rx dca{d}_hdr_en bitfield definitions + * preprocessor definitions for the bitfield "dca{d}_hdr_en". + * parameter: dca {d} | stride size 0x4 | range [0, 31] + * port="pif_rdm_dca_hdr_en_i[0]" + */ + +/* register address for bitfield dca{d}_hdr_en */ +#define HW_ATL_RDM_DCADHDR_EN_ADR(dca) (0x00006100 + (dca) * 0x4) +/* bitmask for bitfield dca{d}_hdr_en */ +#define HW_ATL_RDM_DCADHDR_EN_MSK 0x40000000 +/* inverted bitmask for bitfield dca{d}_hdr_en */ +#define HW_ATL_RDM_DCADHDR_EN_MSKN 0xbfffffff +/* lower bit position of bitfield dca{d}_hdr_en */ +#define HW_ATL_RDM_DCADHDR_EN_SHIFT 30 +/* width of bitfield dca{d}_hdr_en */ +#define HW_ATL_RDM_DCADHDR_EN_WIDTH 1 +/* default value of bitfield dca{d}_hdr_en */ +#define HW_ATL_RDM_DCADHDR_EN_DEFAULT 0x0 + +/* rx dca{d}_pay_en bitfield definitions + * preprocessor definitions for the bitfield "dca{d}_pay_en". + * parameter: dca {d} | stride size 0x4 | range [0, 31] + * port="pif_rdm_dca_pay_en_i[0]" + */ + +/* register address for bitfield dca{d}_pay_en */ +#define HW_ATL_RDM_DCADPAY_EN_ADR(dca) (0x00006100 + (dca) * 0x4) +/* bitmask for bitfield dca{d}_pay_en */ +#define HW_ATL_RDM_DCADPAY_EN_MSK 0x20000000 +/* inverted bitmask for bitfield dca{d}_pay_en */ +#define HW_ATL_RDM_DCADPAY_EN_MSKN 0xdfffffff +/* lower bit position of bitfield dca{d}_pay_en */ +#define HW_ATL_RDM_DCADPAY_EN_SHIFT 29 +/* width of bitfield dca{d}_pay_en */ +#define HW_ATL_RDM_DCADPAY_EN_WIDTH 1 +/* default value of bitfield dca{d}_pay_en */ +#define HW_ATL_RDM_DCADPAY_EN_DEFAULT 0x0 + +/* RX rdm_int_rim_en Bitfield Definitions + * Preprocessor definitions for the bitfield "rdm_int_rim_en". + * PORT="pif_rdm_int_rim_en_i" + */ + +/* Register address for bitfield rdm_int_rim_en */ +#define HW_ATL_RDM_INT_RIM_EN_ADR 0x00005A30 +/* Bitmask for bitfield rdm_int_rim_en */ +#define HW_ATL_RDM_INT_RIM_EN_MSK 0x00000008 +/* Inverted bitmask for bitfield rdm_int_rim_en */ +#define HW_ATL_RDM_INT_RIM_EN_MSKN 0xFFFFFFF7 +/* Lower bit position of bitfield rdm_int_rim_en */ +#define HW_ATL_RDM_INT_RIM_EN_SHIFT 3 +/* Width of bitfield rdm_int_rim_en */ +#define HW_ATL_RDM_INT_RIM_EN_WIDTH 1 +/* Default value of bitfield rdm_int_rim_en */ +#define HW_ATL_RDM_INT_RIM_EN_DEFAULT 0x0 + +/* general interrupt mapping register definitions + * preprocessor definitions for general interrupt mapping register + * base address: 0x00002180 + * parameter: regidx {f} | stride size 0x4 | range [0, 3] + */ +#define HW_ATL_GEN_INTR_MAP_ADR(regidx) (0x00002180u + (regidx) * 0x4) + +/* general interrupt status register definitions + * preprocessor definitions for general interrupt status register + * address: 0x000021A0 + */ + +#define HW_ATL_GEN_INTR_STAT_ADR 0x000021A4U + +/* interrupt global control register definitions + * preprocessor definitions for interrupt global control register + * address: 0x00002300 + */ +#define HW_ATL_INTR_GLB_CTL_ADR 0x00002300u + +/* interrupt throttle register definitions + * preprocessor definitions for interrupt throttle register + * base address: 0x00002800 + * parameter: throttle {t} | stride size 0x4 | range [0, 31] + */ +#define HW_ATL_INTR_THR_ADR(throttle) (0x00002800u + (throttle) * 0x4) + +/* rx dma descriptor base address lsw definitions + * preprocessor definitions for rx dma descriptor base address lsw + * base address: 0x00005b00 + * parameter: descriptor {d} | stride size 0x20 | range [0, 31] + */ +#define HW_ATL_RX_DMA_DESC_BASE_ADDRLSW_ADR(descriptor) \ +(0x00005b00u + (descriptor) * 0x20) + +/* rx dma descriptor base address msw definitions + * preprocessor definitions for rx dma descriptor base address msw + * base address: 0x00005b04 + * parameter: descriptor {d} | stride size 0x20 | range [0, 31] + */ +#define HW_ATL_RX_DMA_DESC_BASE_ADDRMSW_ADR(descriptor) \ +(0x00005b04u + (descriptor) * 0x20) + +/* rx dma descriptor status register definitions + * preprocessor definitions for rx dma descriptor status register + * base address: 0x00005b14 + * parameter: descriptor {d} | stride size 0x20 | range [0, 31] + */ +#define HW_ATL_RX_DMA_DESC_STAT_ADR(descriptor) \ + (0x00005b14u + (descriptor) * 0x20) + +/* rx dma descriptor tail pointer register definitions + * preprocessor definitions for rx dma descriptor tail pointer register + * base address: 0x00005b10 + * parameter: descriptor {d} | stride size 0x20 | range [0, 31] + */ +#define HW_ATL_RX_DMA_DESC_TAIL_PTR_ADR(descriptor) \ + (0x00005b10u + (descriptor) * 0x20) + +/* rx interrupt moderation control register definitions + * Preprocessor definitions for RX Interrupt Moderation Control Register + * Base Address: 0x00005A40 + * Parameter: RIM {R} | stride size 0x4 | range [0, 31] + */ +#define HW_ATL_RX_INTR_MODERATION_CTL_ADR(rim) (0x00005A40u + (rim) * 0x4) + +/* rx filter multicast filter mask register definitions + * preprocessor definitions for rx filter multicast filter mask register + * address: 0x00005270 + */ +#define HW_ATL_RX_FLR_MCST_FLR_MSK_ADR 0x00005270u + +/* rx filter multicast filter register definitions + * preprocessor definitions for rx filter multicast filter register + * base address: 0x00005250 + * parameter: filter {f} | stride size 0x4 | range [0, 7] + */ +#define HW_ATL_RX_FLR_MCST_FLR_ADR(filter) (0x00005250u + (filter) * 0x4) + +/* RX Filter RSS Control Register 1 Definitions + * Preprocessor definitions for RX Filter RSS Control Register 1 + * Address: 0x000054C0 + */ +#define HW_ATL_RX_FLR_RSS_CONTROL1_ADR 0x000054C0u + +/* RX Filter Control Register 2 Definitions + * Preprocessor definitions for RX Filter Control Register 2 + * Address: 0x00005104 + */ +#define HW_ATL_RX_FLR_CONTROL2_ADR 0x00005104u + +/* tx tx dma debug control [1f:0] bitfield definitions + * preprocessor definitions for the bitfield "tx dma debug control [1f:0]". + * port="pif_tdm_debug_cntl_i[31:0]" + */ + +/* register address for bitfield tx dma debug control [1f:0] */ +#define HW_ATL_TDM_TX_DMA_DEBUG_CTL_ADR 0x00008920 +/* bitmask for bitfield tx dma debug control [1f:0] */ +#define HW_ATL_TDM_TX_DMA_DEBUG_CTL_MSK 0xffffffff +/* inverted bitmask for bitfield tx dma debug control [1f:0] */ +#define HW_ATL_TDM_TX_DMA_DEBUG_CTL_MSKN 0x00000000 +/* lower bit position of bitfield tx dma debug control [1f:0] */ +#define HW_ATL_TDM_TX_DMA_DEBUG_CTL_SHIFT 0 +/* width of bitfield tx dma debug control [1f:0] */ +#define HW_ATL_TDM_TX_DMA_DEBUG_CTL_WIDTH 32 +/* default value of bitfield tx dma debug control [1f:0] */ +#define HW_ATL_TDM_TX_DMA_DEBUG_CTL_DEFAULT 0x0 + +/* tx dma descriptor base address lsw definitions + * preprocessor definitions for tx dma descriptor base address lsw + * base address: 0x00007c00 + * parameter: descriptor {d} | stride size 0x40 | range [0, 31] + */ +#define HW_ATL_TX_DMA_DESC_BASE_ADDRLSW_ADR(descriptor) \ + (0x00007c00u + (descriptor) * 0x40) + +/* tx dma descriptor tail pointer register definitions + * preprocessor definitions for tx dma descriptor tail pointer register + * base address: 0x00007c10 + * parameter: descriptor {d} | stride size 0x40 | range [0, 31] + */ +#define HW_ATL_TX_DMA_DESC_TAIL_PTR_ADR(descriptor) \ + (0x00007c10u + (descriptor) * 0x40) + +/* rx dma_sys_loopback bitfield definitions + * preprocessor definitions for the bitfield "dma_sys_loopback". + * port="pif_rpb_dma_sys_lbk_i" + */ + +/* register address for bitfield dma_sys_loopback */ +#define HW_ATL_RPB_DMA_SYS_LBK_ADR 0x00005000 +/* bitmask for bitfield dma_sys_loopback */ +#define HW_ATL_RPB_DMA_SYS_LBK_MSK 0x00000040 +/* inverted bitmask for bitfield dma_sys_loopback */ +#define HW_ATL_RPB_DMA_SYS_LBK_MSKN 0xffffffbf +/* lower bit position of bitfield dma_sys_loopback */ +#define HW_ATL_RPB_DMA_SYS_LBK_SHIFT 6 +/* width of bitfield dma_sys_loopback */ +#define HW_ATL_RPB_DMA_SYS_LBK_WIDTH 1 +/* default value of bitfield dma_sys_loopback */ +#define HW_ATL_RPB_DMA_SYS_LBK_DEFAULT 0x0 + +/* rx rx_tc_mode bitfield definitions + * preprocessor definitions for the bitfield "rx_tc_mode". + * port="pif_rpb_rx_tc_mode_i,pif_rpf_rx_tc_mode_i" + */ + +/* register address for bitfield rx_tc_mode */ +#define HW_ATL_RPB_RPF_RX_TC_MODE_ADR 0x00005700 +/* bitmask for bitfield rx_tc_mode */ +#define HW_ATL_RPB_RPF_RX_TC_MODE_MSK 0x00000100 +/* inverted bitmask for bitfield rx_tc_mode */ +#define HW_ATL_RPB_RPF_RX_TC_MODE_MSKN 0xfffffeff +/* lower bit position of bitfield rx_tc_mode */ +#define HW_ATL_RPB_RPF_RX_TC_MODE_SHIFT 8 +/* width of bitfield rx_tc_mode */ +#define HW_ATL_RPB_RPF_RX_TC_MODE_WIDTH 1 +/* default value of bitfield rx_tc_mode */ +#define HW_ATL_RPB_RPF_RX_TC_MODE_DEFAULT 0x0 + +/* rx rx_buf_en bitfield definitions + * preprocessor definitions for the bitfield "rx_buf_en". + * port="pif_rpb_rx_buf_en_i" + */ + +/* register address for bitfield rx_buf_en */ +#define HW_ATL_RPB_RX_BUF_EN_ADR 0x00005700 +/* bitmask for bitfield rx_buf_en */ +#define HW_ATL_RPB_RX_BUF_EN_MSK 0x00000001 +/* inverted bitmask for bitfield rx_buf_en */ +#define HW_ATL_RPB_RX_BUF_EN_MSKN 0xfffffffe +/* lower bit position of bitfield rx_buf_en */ +#define HW_ATL_RPB_RX_BUF_EN_SHIFT 0 +/* width of bitfield rx_buf_en */ +#define HW_ATL_RPB_RX_BUF_EN_WIDTH 1 +/* default value of bitfield rx_buf_en */ +#define HW_ATL_RPB_RX_BUF_EN_DEFAULT 0x0 + +/* rx rx{b}_hi_thresh[d:0] bitfield definitions + * preprocessor definitions for the bitfield "rx{b}_hi_thresh[d:0]". + * parameter: buffer {b} | stride size 0x10 | range [0, 7] + * port="pif_rpb_rx0_hi_thresh_i[13:0]" + */ + +/* register address for bitfield rx{b}_hi_thresh[d:0] */ +#define HW_ATL_RPB_RXBHI_THRESH_ADR(buffer) (0x00005714 + (buffer) * 0x10) +/* bitmask for bitfield rx{b}_hi_thresh[d:0] */ +#define HW_ATL_RPB_RXBHI_THRESH_MSK 0x3fff0000 +/* inverted bitmask for bitfield rx{b}_hi_thresh[d:0] */ +#define HW_ATL_RPB_RXBHI_THRESH_MSKN 0xc000ffff +/* lower bit position of bitfield rx{b}_hi_thresh[d:0] */ +#define HW_ATL_RPB_RXBHI_THRESH_SHIFT 16 +/* width of bitfield rx{b}_hi_thresh[d:0] */ +#define HW_ATL_RPB_RXBHI_THRESH_WIDTH 14 +/* default value of bitfield rx{b}_hi_thresh[d:0] */ +#define HW_ATL_RPB_RXBHI_THRESH_DEFAULT 0x0 + +/* rx rx{b}_lo_thresh[d:0] bitfield definitions + * preprocessor definitions for the bitfield "rx{b}_lo_thresh[d:0]". + * parameter: buffer {b} | stride size 0x10 | range [0, 7] + * port="pif_rpb_rx0_lo_thresh_i[13:0]" + */ + +/* register address for bitfield rx{b}_lo_thresh[d:0] */ +#define HW_ATL_RPB_RXBLO_THRESH_ADR(buffer) (0x00005714 + (buffer) * 0x10) +/* bitmask for bitfield rx{b}_lo_thresh[d:0] */ +#define HW_ATL_RPB_RXBLO_THRESH_MSK 0x00003fff +/* inverted bitmask for bitfield rx{b}_lo_thresh[d:0] */ +#define HW_ATL_RPB_RXBLO_THRESH_MSKN 0xffffc000 +/* lower bit position of bitfield rx{b}_lo_thresh[d:0] */ +#define HW_ATL_RPB_RXBLO_THRESH_SHIFT 0 +/* width of bitfield rx{b}_lo_thresh[d:0] */ +#define HW_ATL_RPB_RXBLO_THRESH_WIDTH 14 +/* default value of bitfield rx{b}_lo_thresh[d:0] */ +#define HW_ATL_RPB_RXBLO_THRESH_DEFAULT 0x0 + +/* rx rx_fc_mode[1:0] bitfield definitions + * preprocessor definitions for the bitfield "rx_fc_mode[1:0]". + * port="pif_rpb_rx_fc_mode_i[1:0]" + */ + +/* register address for bitfield rx_fc_mode[1:0] */ +#define HW_ATL_RPB_RX_FC_MODE_ADR 0x00005700 +/* bitmask for bitfield rx_fc_mode[1:0] */ +#define HW_ATL_RPB_RX_FC_MODE_MSK 0x00000030 +/* inverted bitmask for bitfield rx_fc_mode[1:0] */ +#define HW_ATL_RPB_RX_FC_MODE_MSKN 0xffffffcf +/* lower bit position of bitfield rx_fc_mode[1:0] */ +#define HW_ATL_RPB_RX_FC_MODE_SHIFT 4 +/* width of bitfield rx_fc_mode[1:0] */ +#define HW_ATL_RPB_RX_FC_MODE_WIDTH 2 +/* default value of bitfield rx_fc_mode[1:0] */ +#define HW_ATL_RPB_RX_FC_MODE_DEFAULT 0x0 + +/* rx rx{b}_buf_size[8:0] bitfield definitions + * preprocessor definitions for the bitfield "rx{b}_buf_size[8:0]". + * parameter: buffer {b} | stride size 0x10 | range [0, 7] + * port="pif_rpb_rx0_buf_size_i[8:0]" + */ + +/* register address for bitfield rx{b}_buf_size[8:0] */ +#define HW_ATL_RPB_RXBBUF_SIZE_ADR(buffer) (0x00005710 + (buffer) * 0x10) +/* bitmask for bitfield rx{b}_buf_size[8:0] */ +#define HW_ATL_RPB_RXBBUF_SIZE_MSK 0x000001ff +/* inverted bitmask for bitfield rx{b}_buf_size[8:0] */ +#define HW_ATL_RPB_RXBBUF_SIZE_MSKN 0xfffffe00 +/* lower bit position of bitfield rx{b}_buf_size[8:0] */ +#define HW_ATL_RPB_RXBBUF_SIZE_SHIFT 0 +/* width of bitfield rx{b}_buf_size[8:0] */ +#define HW_ATL_RPB_RXBBUF_SIZE_WIDTH 9 +/* default value of bitfield rx{b}_buf_size[8:0] */ +#define HW_ATL_RPB_RXBBUF_SIZE_DEFAULT 0x0 + +/* rx rx{b}_xoff_en bitfield definitions + * preprocessor definitions for the bitfield "rx{b}_xoff_en". + * parameter: buffer {b} | stride size 0x10 | range [0, 7] + * port="pif_rpb_rx_xoff_en_i[0]" + */ + +/* register address for bitfield rx{b}_xoff_en */ +#define HW_ATL_RPB_RXBXOFF_EN_ADR(buffer) (0x00005714 + (buffer) * 0x10) +/* bitmask for bitfield rx{b}_xoff_en */ +#define HW_ATL_RPB_RXBXOFF_EN_MSK 0x80000000 +/* inverted bitmask for bitfield rx{b}_xoff_en */ +#define HW_ATL_RPB_RXBXOFF_EN_MSKN 0x7fffffff +/* lower bit position of bitfield rx{b}_xoff_en */ +#define HW_ATL_RPB_RXBXOFF_EN_SHIFT 31 +/* width of bitfield rx{b}_xoff_en */ +#define HW_ATL_RPB_RXBXOFF_EN_WIDTH 1 +/* default value of bitfield rx{b}_xoff_en */ +#define HW_ATL_RPB_RXBXOFF_EN_DEFAULT 0x0 + +/* rx l2_bc_thresh[f:0] bitfield definitions + * preprocessor definitions for the bitfield "l2_bc_thresh[f:0]". + * port="pif_rpf_l2_bc_thresh_i[15:0]" + */ + +/* register address for bitfield l2_bc_thresh[f:0] */ +#define HW_ATL_RPFL2BC_THRESH_ADR 0x00005100 +/* bitmask for bitfield l2_bc_thresh[f:0] */ +#define HW_ATL_RPFL2BC_THRESH_MSK 0xffff0000 +/* inverted bitmask for bitfield l2_bc_thresh[f:0] */ +#define HW_ATL_RPFL2BC_THRESH_MSKN 0x0000ffff +/* lower bit position of bitfield l2_bc_thresh[f:0] */ +#define HW_ATL_RPFL2BC_THRESH_SHIFT 16 +/* width of bitfield l2_bc_thresh[f:0] */ +#define HW_ATL_RPFL2BC_THRESH_WIDTH 16 +/* default value of bitfield l2_bc_thresh[f:0] */ +#define HW_ATL_RPFL2BC_THRESH_DEFAULT 0x0 + +/* rx l2_bc_en bitfield definitions + * preprocessor definitions for the bitfield "l2_bc_en". + * port="pif_rpf_l2_bc_en_i" + */ + +/* register address for bitfield l2_bc_en */ +#define HW_ATL_RPFL2BC_EN_ADR 0x00005100 +/* bitmask for bitfield l2_bc_en */ +#define HW_ATL_RPFL2BC_EN_MSK 0x00000001 +/* inverted bitmask for bitfield l2_bc_en */ +#define HW_ATL_RPFL2BC_EN_MSKN 0xfffffffe +/* lower bit position of bitfield l2_bc_en */ +#define HW_ATL_RPFL2BC_EN_SHIFT 0 +/* width of bitfield l2_bc_en */ +#define HW_ATL_RPFL2BC_EN_WIDTH 1 +/* default value of bitfield l2_bc_en */ +#define HW_ATL_RPFL2BC_EN_DEFAULT 0x0 + +/* rx l2_bc_act[2:0] bitfield definitions + * preprocessor definitions for the bitfield "l2_bc_act[2:0]". + * port="pif_rpf_l2_bc_act_i[2:0]" + */ + +/* register address for bitfield l2_bc_act[2:0] */ +#define HW_ATL_RPFL2BC_ACT_ADR 0x00005100 +/* bitmask for bitfield l2_bc_act[2:0] */ +#define HW_ATL_RPFL2BC_ACT_MSK 0x00007000 +/* inverted bitmask for bitfield l2_bc_act[2:0] */ +#define HW_ATL_RPFL2BC_ACT_MSKN 0xffff8fff +/* lower bit position of bitfield l2_bc_act[2:0] */ +#define HW_ATL_RPFL2BC_ACT_SHIFT 12 +/* width of bitfield l2_bc_act[2:0] */ +#define HW_ATL_RPFL2BC_ACT_WIDTH 3 +/* default value of bitfield l2_bc_act[2:0] */ +#define HW_ATL_RPFL2BC_ACT_DEFAULT 0x0 + +/* rx l2_mc_en{f} bitfield definitions + * preprocessor definitions for the bitfield "l2_mc_en{f}". + * parameter: filter {f} | stride size 0x4 | range [0, 7] + * port="pif_rpf_l2_mc_en_i[0]" + */ + +/* register address for bitfield l2_mc_en{f} */ +#define HW_ATL_RPFL2MC_ENF_ADR(filter) (0x00005250 + (filter) * 0x4) +/* bitmask for bitfield l2_mc_en{f} */ +#define HW_ATL_RPFL2MC_ENF_MSK 0x80000000 +/* inverted bitmask for bitfield l2_mc_en{f} */ +#define HW_ATL_RPFL2MC_ENF_MSKN 0x7fffffff +/* lower bit position of bitfield l2_mc_en{f} */ +#define HW_ATL_RPFL2MC_ENF_SHIFT 31 +/* width of bitfield l2_mc_en{f} */ +#define HW_ATL_RPFL2MC_ENF_WIDTH 1 +/* default value of bitfield l2_mc_en{f} */ +#define HW_ATL_RPFL2MC_ENF_DEFAULT 0x0 + +/* rx l2_promis_mode bitfield definitions + * preprocessor definitions for the bitfield "l2_promis_mode". + * port="pif_rpf_l2_promis_mode_i" + */ + +/* register address for bitfield l2_promis_mode */ +#define HW_ATL_RPFL2PROMIS_MODE_ADR 0x00005100 +/* bitmask for bitfield l2_promis_mode */ +#define HW_ATL_RPFL2PROMIS_MODE_MSK 0x00000008 +/* inverted bitmask for bitfield l2_promis_mode */ +#define HW_ATL_RPFL2PROMIS_MODE_MSKN 0xfffffff7 +/* lower bit position of bitfield l2_promis_mode */ +#define HW_ATL_RPFL2PROMIS_MODE_SHIFT 3 +/* width of bitfield l2_promis_mode */ +#define HW_ATL_RPFL2PROMIS_MODE_WIDTH 1 +/* default value of bitfield l2_promis_mode */ +#define HW_ATL_RPFL2PROMIS_MODE_DEFAULT 0x0 + +/* rx l2_uc_act{f}[2:0] bitfield definitions + * preprocessor definitions for the bitfield "l2_uc_act{f}[2:0]". + * parameter: filter {f} | stride size 0x8 | range [0, 37] + * port="pif_rpf_l2_uc_act0_i[2:0]" + */ + +/* register address for bitfield l2_uc_act{f}[2:0] */ +#define HW_ATL_RPFL2UC_ACTF_ADR(filter) (0x00005114 + (filter) * 0x8) +/* bitmask for bitfield l2_uc_act{f}[2:0] */ +#define HW_ATL_RPFL2UC_ACTF_MSK 0x00070000 +/* inverted bitmask for bitfield l2_uc_act{f}[2:0] */ +#define HW_ATL_RPFL2UC_ACTF_MSKN 0xfff8ffff +/* lower bit position of bitfield l2_uc_act{f}[2:0] */ +#define HW_ATL_RPFL2UC_ACTF_SHIFT 16 +/* width of bitfield l2_uc_act{f}[2:0] */ +#define HW_ATL_RPFL2UC_ACTF_WIDTH 3 +/* default value of bitfield l2_uc_act{f}[2:0] */ +#define HW_ATL_RPFL2UC_ACTF_DEFAULT 0x0 + +/* rx l2_uc_en{f} bitfield definitions + * preprocessor definitions for the bitfield "l2_uc_en{f}". + * parameter: filter {f} | stride size 0x8 | range [0, 37] + * port="pif_rpf_l2_uc_en_i[0]" + */ + +/* register address for bitfield l2_uc_en{f} */ +#define HW_ATL_RPFL2UC_ENF_ADR(filter) (0x00005114 + (filter) * 0x8) +/* bitmask for bitfield l2_uc_en{f} */ +#define HW_ATL_RPFL2UC_ENF_MSK 0x80000000 +/* inverted bitmask for bitfield l2_uc_en{f} */ +#define HW_ATL_RPFL2UC_ENF_MSKN 0x7fffffff +/* lower bit position of bitfield l2_uc_en{f} */ +#define HW_ATL_RPFL2UC_ENF_SHIFT 31 +/* width of bitfield l2_uc_en{f} */ +#define HW_ATL_RPFL2UC_ENF_WIDTH 1 +/* default value of bitfield l2_uc_en{f} */ +#define HW_ATL_RPFL2UC_ENF_DEFAULT 0x0 + +/* register address for bitfield l2_uc_da{f}_lsw[1f:0] */ +#define HW_ATL_RPFL2UC_DAFLSW_ADR(filter) (0x00005110 + (filter) * 0x8) +/* register address for bitfield l2_uc_da{f}_msw[f:0] */ +#define HW_ATL_RPFL2UC_DAFMSW_ADR(filter) (0x00005114 + (filter) * 0x8) +/* bitmask for bitfield l2_uc_da{f}_msw[f:0] */ +#define HW_ATL_RPFL2UC_DAFMSW_MSK 0x0000ffff +/* lower bit position of bitfield l2_uc_da{f}_msw[f:0] */ +#define HW_ATL_RPFL2UC_DAFMSW_SHIFT 0 + +/* rx l2_mc_accept_all bitfield definitions + * Preprocessor definitions for the bitfield "l2_mc_accept_all". + * PORT="pif_rpf_l2_mc_all_accept_i" + */ + +/* Register address for bitfield l2_mc_accept_all */ +#define HW_ATL_RPFL2MC_ACCEPT_ALL_ADR 0x00005270 +/* Bitmask for bitfield l2_mc_accept_all */ +#define HW_ATL_RPFL2MC_ACCEPT_ALL_MSK 0x00004000 +/* Inverted bitmask for bitfield l2_mc_accept_all */ +#define HW_ATL_RPFL2MC_ACCEPT_ALL_MSKN 0xFFFFBFFF +/* Lower bit position of bitfield l2_mc_accept_all */ +#define HW_ATL_RPFL2MC_ACCEPT_ALL_SHIFT 14 +/* Width of bitfield l2_mc_accept_all */ +#define HW_ATL_RPFL2MC_ACCEPT_ALL_WIDTH 1 +/* Default value of bitfield l2_mc_accept_all */ +#define HW_ATL_RPFL2MC_ACCEPT_ALL_DEFAULT 0x0 + +/* width of bitfield rx_tc_up{t}[2:0] */ +#define HW_ATL_RPF_RPB_RX_TC_UPT_WIDTH 3 +/* default value of bitfield rx_tc_up{t}[2:0] */ +#define HW_ATL_RPF_RPB_RX_TC_UPT_DEFAULT 0x0 + +/* rx rss_key_addr[4:0] bitfield definitions + * preprocessor definitions for the bitfield "rss_key_addr[4:0]". + * port="pif_rpf_rss_key_addr_i[4:0]" + */ + +/* register address for bitfield rss_key_addr[4:0] */ +#define HW_ATL_RPF_RSS_KEY_ADDR_ADR 0x000054d0 +/* bitmask for bitfield rss_key_addr[4:0] */ +#define HW_ATL_RPF_RSS_KEY_ADDR_MSK 0x0000001f +/* inverted bitmask for bitfield rss_key_addr[4:0] */ +#define HW_ATL_RPF_RSS_KEY_ADDR_MSKN 0xffffffe0 +/* lower bit position of bitfield rss_key_addr[4:0] */ +#define HW_ATL_RPF_RSS_KEY_ADDR_SHIFT 0 +/* width of bitfield rss_key_addr[4:0] */ +#define HW_ATL_RPF_RSS_KEY_ADDR_WIDTH 5 +/* default value of bitfield rss_key_addr[4:0] */ +#define HW_ATL_RPF_RSS_KEY_ADDR_DEFAULT 0x0 + +/* rx rss_key_wr_data[1f:0] bitfield definitions + * preprocessor definitions for the bitfield "rss_key_wr_data[1f:0]". + * port="pif_rpf_rss_key_wr_data_i[31:0]" + */ + +/* register address for bitfield rss_key_wr_data[1f:0] */ +#define HW_ATL_RPF_RSS_KEY_WR_DATA_ADR 0x000054d4 +/* bitmask for bitfield rss_key_wr_data[1f:0] */ +#define HW_ATL_RPF_RSS_KEY_WR_DATA_MSK 0xffffffff +/* inverted bitmask for bitfield rss_key_wr_data[1f:0] */ +#define HW_ATL_RPF_RSS_KEY_WR_DATA_MSKN 0x00000000 +/* lower bit position of bitfield rss_key_wr_data[1f:0] */ +#define HW_ATL_RPF_RSS_KEY_WR_DATA_SHIFT 0 +/* width of bitfield rss_key_wr_data[1f:0] */ +#define HW_ATL_RPF_RSS_KEY_WR_DATA_WIDTH 32 +/* default value of bitfield rss_key_wr_data[1f:0] */ +#define HW_ATL_RPF_RSS_KEY_WR_DATA_DEFAULT 0x0 + +/* rx rss_key_wr_en_i bitfield definitions + * preprocessor definitions for the bitfield "rss_key_wr_en_i". + * port="pif_rpf_rss_key_wr_en_i" + */ + +/* register address for bitfield rss_key_wr_en_i */ +#define HW_ATL_RPF_RSS_KEY_WR_ENI_ADR 0x000054d0 +/* bitmask for bitfield rss_key_wr_en_i */ +#define HW_ATL_RPF_RSS_KEY_WR_ENI_MSK 0x00000020 +/* inverted bitmask for bitfield rss_key_wr_en_i */ +#define HW_ATL_RPF_RSS_KEY_WR_ENI_MSKN 0xffffffdf +/* lower bit position of bitfield rss_key_wr_en_i */ +#define HW_ATL_RPF_RSS_KEY_WR_ENI_SHIFT 5 +/* width of bitfield rss_key_wr_en_i */ +#define HW_ATL_RPF_RSS_KEY_WR_ENI_WIDTH 1 +/* default value of bitfield rss_key_wr_en_i */ +#define HW_ATL_RPF_RSS_KEY_WR_ENI_DEFAULT 0x0 + +/* rx rss_redir_addr[3:0] bitfield definitions + * preprocessor definitions for the bitfield "rss_redir_addr[3:0]". + * port="pif_rpf_rss_redir_addr_i[3:0]" + */ + +/* register address for bitfield rss_redir_addr[3:0] */ +#define HW_ATL_RPF_RSS_REDIR_ADDR_ADR 0x000054e0 +/* bitmask for bitfield rss_redir_addr[3:0] */ +#define HW_ATL_RPF_RSS_REDIR_ADDR_MSK 0x0000000f +/* inverted bitmask for bitfield rss_redir_addr[3:0] */ +#define HW_ATL_RPF_RSS_REDIR_ADDR_MSKN 0xfffffff0 +/* lower bit position of bitfield rss_redir_addr[3:0] */ +#define HW_ATL_RPF_RSS_REDIR_ADDR_SHIFT 0 +/* width of bitfield rss_redir_addr[3:0] */ +#define HW_ATL_RPF_RSS_REDIR_ADDR_WIDTH 4 +/* default value of bitfield rss_redir_addr[3:0] */ +#define HW_ATL_RPF_RSS_REDIR_ADDR_DEFAULT 0x0 + +/* rx rss_redir_wr_data[f:0] bitfield definitions + * preprocessor definitions for the bitfield "rss_redir_wr_data[f:0]". + * port="pif_rpf_rss_redir_wr_data_i[15:0]" + */ + +/* register address for bitfield rss_redir_wr_data[f:0] */ +#define HW_ATL_RPF_RSS_REDIR_WR_DATA_ADR 0x000054e4 +/* bitmask for bitfield rss_redir_wr_data[f:0] */ +#define HW_ATL_RPF_RSS_REDIR_WR_DATA_MSK 0x0000ffff +/* inverted bitmask for bitfield rss_redir_wr_data[f:0] */ +#define HW_ATL_RPF_RSS_REDIR_WR_DATA_MSKN 0xffff0000 +/* lower bit position of bitfield rss_redir_wr_data[f:0] */ +#define HW_ATL_RPF_RSS_REDIR_WR_DATA_SHIFT 0 +/* width of bitfield rss_redir_wr_data[f:0] */ +#define HW_ATL_RPF_RSS_REDIR_WR_DATA_WIDTH 16 +/* default value of bitfield rss_redir_wr_data[f:0] */ +#define HW_ATL_RPF_RSS_REDIR_WR_DATA_DEFAULT 0x0 + +/* rx rss_redir_wr_en_i bitfield definitions + * preprocessor definitions for the bitfield "rss_redir_wr_en_i". + * port="pif_rpf_rss_redir_wr_en_i" + */ + +/* register address for bitfield rss_redir_wr_en_i */ +#define HW_ATL_RPF_RSS_REDIR_WR_ENI_ADR 0x000054e0 +/* bitmask for bitfield rss_redir_wr_en_i */ +#define HW_ATL_RPF_RSS_REDIR_WR_ENI_MSK 0x00000010 +/* inverted bitmask for bitfield rss_redir_wr_en_i */ +#define HW_ATL_RPF_RSS_REDIR_WR_ENI_MSKN 0xffffffef +/* lower bit position of bitfield rss_redir_wr_en_i */ +#define HW_ATL_RPF_RSS_REDIR_WR_ENI_SHIFT 4 +/* width of bitfield rss_redir_wr_en_i */ +#define HW_ATL_RPF_RSS_REDIR_WR_ENI_WIDTH 1 +/* default value of bitfield rss_redir_wr_en_i */ +#define HW_ATL_RPF_RSS_REDIR_WR_ENI_DEFAULT 0x0 + +/* rx tpo_rpf_sys_loopback bitfield definitions + * preprocessor definitions for the bitfield "tpo_rpf_sys_loopback". + * port="pif_rpf_tpo_pkt_sys_lbk_i" + */ + +/* register address for bitfield tpo_rpf_sys_loopback */ +#define HW_ATL_RPF_TPO_RPF_SYS_LBK_ADR 0x00005000 +/* bitmask for bitfield tpo_rpf_sys_loopback */ +#define HW_ATL_RPF_TPO_RPF_SYS_LBK_MSK 0x00000100 +/* inverted bitmask for bitfield tpo_rpf_sys_loopback */ +#define HW_ATL_RPF_TPO_RPF_SYS_LBK_MSKN 0xfffffeff +/* lower bit position of bitfield tpo_rpf_sys_loopback */ +#define HW_ATL_RPF_TPO_RPF_SYS_LBK_SHIFT 8 +/* width of bitfield tpo_rpf_sys_loopback */ +#define HW_ATL_RPF_TPO_RPF_SYS_LBK_WIDTH 1 +/* default value of bitfield tpo_rpf_sys_loopback */ +#define HW_ATL_RPF_TPO_RPF_SYS_LBK_DEFAULT 0x0 + +/* rx vl_inner_tpid[f:0] bitfield definitions + * preprocessor definitions for the bitfield "vl_inner_tpid[f:0]". + * port="pif_rpf_vl_inner_tpid_i[15:0]" + */ + +/* register address for bitfield vl_inner_tpid[f:0] */ +#define HW_ATL_RPF_VL_INNER_TPID_ADR 0x00005284 +/* bitmask for bitfield vl_inner_tpid[f:0] */ +#define HW_ATL_RPF_VL_INNER_TPID_MSK 0x0000ffff +/* inverted bitmask for bitfield vl_inner_tpid[f:0] */ +#define HW_ATL_RPF_VL_INNER_TPID_MSKN 0xffff0000 +/* lower bit position of bitfield vl_inner_tpid[f:0] */ +#define HW_ATL_RPF_VL_INNER_TPID_SHIFT 0 +/* width of bitfield vl_inner_tpid[f:0] */ +#define HW_ATL_RPF_VL_INNER_TPID_WIDTH 16 +/* default value of bitfield vl_inner_tpid[f:0] */ +#define HW_ATL_RPF_VL_INNER_TPID_DEFAULT 0x8100 + +/* rx vl_outer_tpid[f:0] bitfield definitions + * preprocessor definitions for the bitfield "vl_outer_tpid[f:0]". + * port="pif_rpf_vl_outer_tpid_i[15:0]" + */ + +/* register address for bitfield vl_outer_tpid[f:0] */ +#define HW_ATL_RPF_VL_OUTER_TPID_ADR 0x00005284 +/* bitmask for bitfield vl_outer_tpid[f:0] */ +#define HW_ATL_RPF_VL_OUTER_TPID_MSK 0xffff0000 +/* inverted bitmask for bitfield vl_outer_tpid[f:0] */ +#define HW_ATL_RPF_VL_OUTER_TPID_MSKN 0x0000ffff +/* lower bit position of bitfield vl_outer_tpid[f:0] */ +#define HW_ATL_RPF_VL_OUTER_TPID_SHIFT 16 +/* width of bitfield vl_outer_tpid[f:0] */ +#define HW_ATL_RPF_VL_OUTER_TPID_WIDTH 16 +/* default value of bitfield vl_outer_tpid[f:0] */ +#define HW_ATL_RPF_VL_OUTER_TPID_DEFAULT 0x88a8 + +/* rx vl_promis_mode bitfield definitions + * preprocessor definitions for the bitfield "vl_promis_mode". + * port="pif_rpf_vl_promis_mode_i" + */ + +/* register address for bitfield vl_promis_mode */ +#define HW_ATL_RPF_VL_PROMIS_MODE_ADR 0x00005280 +/* bitmask for bitfield vl_promis_mode */ +#define HW_ATL_RPF_VL_PROMIS_MODE_MSK 0x00000002 +/* inverted bitmask for bitfield vl_promis_mode */ +#define HW_ATL_RPF_VL_PROMIS_MODE_MSKN 0xfffffffd +/* lower bit position of bitfield vl_promis_mode */ +#define HW_ATL_RPF_VL_PROMIS_MODE_SHIFT 1 +/* width of bitfield vl_promis_mode */ +#define HW_ATL_RPF_VL_PROMIS_MODE_WIDTH 1 +/* default value of bitfield vl_promis_mode */ +#define HW_ATL_RPF_VL_PROMIS_MODE_DEFAULT 0x0 + +/* RX vl_accept_untagged_mode Bitfield Definitions + * Preprocessor definitions for the bitfield "vl_accept_untagged_mode". + * PORT="pif_rpf_vl_accept_untagged_i" + */ + +/* Register address for bitfield vl_accept_untagged_mode */ +#define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_ADR 0x00005280 +/* Bitmask for bitfield vl_accept_untagged_mode */ +#define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_MSK 0x00000004 +/* Inverted bitmask for bitfield vl_accept_untagged_mode */ +#define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_MSKN 0xFFFFFFFB +/* Lower bit position of bitfield vl_accept_untagged_mode */ +#define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_SHIFT 2 +/* Width of bitfield vl_accept_untagged_mode */ +#define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_WIDTH 1 +/* Default value of bitfield vl_accept_untagged_mode */ +#define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_DEFAULT 0x0 + +/* rX vl_untagged_act[2:0] Bitfield Definitions + * Preprocessor definitions for the bitfield "vl_untagged_act[2:0]". + * PORT="pif_rpf_vl_untagged_act_i[2:0]" + */ + +/* Register address for bitfield vl_untagged_act[2:0] */ +#define HW_ATL_RPF_VL_UNTAGGED_ACT_ADR 0x00005280 +/* Bitmask for bitfield vl_untagged_act[2:0] */ +#define HW_ATL_RPF_VL_UNTAGGED_ACT_MSK 0x00000038 +/* Inverted bitmask for bitfield vl_untagged_act[2:0] */ +#define HW_ATL_RPF_VL_UNTAGGED_ACT_MSKN 0xFFFFFFC7 +/* Lower bit position of bitfield vl_untagged_act[2:0] */ +#define HW_ATL_RPF_VL_UNTAGGED_ACT_SHIFT 3 +/* Width of bitfield vl_untagged_act[2:0] */ +#define HW_ATL_RPF_VL_UNTAGGED_ACT_WIDTH 3 +/* Default value of bitfield vl_untagged_act[2:0] */ +#define HW_ATL_RPF_VL_UNTAGGED_ACT_DEFAULT 0x0 + +/* RX vl_en{F} Bitfield Definitions + * Preprocessor definitions for the bitfield "vl_en{F}". + * Parameter: filter {F} | stride size 0x4 | range [0, 15] + * PORT="pif_rpf_vl_en_i[0]" + */ + +/* Register address for bitfield vl_en{F} */ +#define HW_ATL_RPF_VL_EN_F_ADR(filter) (0x00005290 + (filter) * 0x4) +/* Bitmask for bitfield vl_en{F} */ +#define HW_ATL_RPF_VL_EN_F_MSK 0x80000000 +/* Inverted bitmask for bitfield vl_en{F} */ +#define HW_ATL_RPF_VL_EN_F_MSKN 0x7FFFFFFF +/* Lower bit position of bitfield vl_en{F} */ +#define HW_ATL_RPF_VL_EN_F_SHIFT 31 +/* Width of bitfield vl_en{F} */ +#define HW_ATL_RPF_VL_EN_F_WIDTH 1 +/* Default value of bitfield vl_en{F} */ +#define HW_ATL_RPF_VL_EN_F_DEFAULT 0x0 + +/* RX vl_act{F}[2:0] Bitfield Definitions + * Preprocessor definitions for the bitfield "vl_act{F}[2:0]". + * Parameter: filter {F} | stride size 0x4 | range [0, 15] + * PORT="pif_rpf_vl_act0_i[2:0]" + */ + +/* Register address for bitfield vl_act{F}[2:0] */ +#define HW_ATL_RPF_VL_ACT_F_ADR(filter) (0x00005290 + (filter) * 0x4) +/* Bitmask for bitfield vl_act{F}[2:0] */ +#define HW_ATL_RPF_VL_ACT_F_MSK 0x00070000 +/* Inverted bitmask for bitfield vl_act{F}[2:0] */ +#define HW_ATL_RPF_VL_ACT_F_MSKN 0xFFF8FFFF +/* Lower bit position of bitfield vl_act{F}[2:0] */ +#define HW_ATL_RPF_VL_ACT_F_SHIFT 16 +/* Width of bitfield vl_act{F}[2:0] */ +#define HW_ATL_RPF_VL_ACT_F_WIDTH 3 +/* Default value of bitfield vl_act{F}[2:0] */ +#define HW_ATL_RPF_VL_ACT_F_DEFAULT 0x0 + +/* RX vl_id{F}[B:0] Bitfield Definitions + * Preprocessor definitions for the bitfield "vl_id{F}[B:0]". + * Parameter: filter {F} | stride size 0x4 | range [0, 15] + * PORT="pif_rpf_vl_id0_i[11:0]" + */ + +/* Register address for bitfield vl_id{F}[B:0] */ +#define HW_ATL_RPF_VL_ID_F_ADR(filter) (0x00005290 + (filter) * 0x4) +/* Bitmask for bitfield vl_id{F}[B:0] */ +#define HW_ATL_RPF_VL_ID_F_MSK 0x00000FFF +/* Inverted bitmask for bitfield vl_id{F}[B:0] */ +#define HW_ATL_RPF_VL_ID_F_MSKN 0xFFFFF000 +/* Lower bit position of bitfield vl_id{F}[B:0] */ +#define HW_ATL_RPF_VL_ID_F_SHIFT 0 +/* Width of bitfield vl_id{F}[B:0] */ +#define HW_ATL_RPF_VL_ID_F_WIDTH 12 +/* Default value of bitfield vl_id{F}[B:0] */ +#define HW_ATL_RPF_VL_ID_F_DEFAULT 0x0 + +/* RX et_en{F} Bitfield Definitions + * Preprocessor definitions for the bitfield "et_en{F}". + * Parameter: filter {F} | stride size 0x4 | range [0, 15] + * PORT="pif_rpf_et_en_i[0]" + */ + +/* Register address for bitfield et_en{F} */ +#define HW_ATL_RPF_ET_EN_F_ADR(filter) (0x00005300 + (filter) * 0x4) +/* Bitmask for bitfield et_en{F} */ +#define HW_ATL_RPF_ET_EN_F_MSK 0x80000000 +/* Inverted bitmask for bitfield et_en{F} */ +#define HW_ATL_RPF_ET_EN_F_MSKN 0x7FFFFFFF +/* Lower bit position of bitfield et_en{F} */ +#define HW_ATL_RPF_ET_EN_F_SHIFT 31 +/* Width of bitfield et_en{F} */ +#define HW_ATL_RPF_ET_EN_F_WIDTH 1 +/* Default value of bitfield et_en{F} */ +#define HW_ATL_RPF_ET_EN_F_DEFAULT 0x0 + +/* rx et_en{f} bitfield definitions + * preprocessor definitions for the bitfield "et_en{f}". + * parameter: filter {f} | stride size 0x4 | range [0, 15] + * port="pif_rpf_et_en_i[0]" + */ + +/* register address for bitfield et_en{f} */ +#define HW_ATL_RPF_ET_ENF_ADR(filter) (0x00005300 + (filter) * 0x4) +/* bitmask for bitfield et_en{f} */ +#define HW_ATL_RPF_ET_ENF_MSK 0x80000000 +/* inverted bitmask for bitfield et_en{f} */ +#define HW_ATL_RPF_ET_ENF_MSKN 0x7fffffff +/* lower bit position of bitfield et_en{f} */ +#define HW_ATL_RPF_ET_ENF_SHIFT 31 +/* width of bitfield et_en{f} */ +#define HW_ATL_RPF_ET_ENF_WIDTH 1 +/* default value of bitfield et_en{f} */ +#define HW_ATL_RPF_ET_ENF_DEFAULT 0x0 + +/* rx et_up{f}_en bitfield definitions + * preprocessor definitions for the bitfield "et_up{f}_en". + * parameter: filter {f} | stride size 0x4 | range [0, 15] + * port="pif_rpf_et_up_en_i[0]" + */ + +/* register address for bitfield et_up{f}_en */ +#define HW_ATL_RPF_ET_UPFEN_ADR(filter) (0x00005300 + (filter) * 0x4) +/* bitmask for bitfield et_up{f}_en */ +#define HW_ATL_RPF_ET_UPFEN_MSK 0x40000000 +/* inverted bitmask for bitfield et_up{f}_en */ +#define HW_ATL_RPF_ET_UPFEN_MSKN 0xbfffffff +/* lower bit position of bitfield et_up{f}_en */ +#define HW_ATL_RPF_ET_UPFEN_SHIFT 30 +/* width of bitfield et_up{f}_en */ +#define HW_ATL_RPF_ET_UPFEN_WIDTH 1 +/* default value of bitfield et_up{f}_en */ +#define HW_ATL_RPF_ET_UPFEN_DEFAULT 0x0 + +/* rx et_rxq{f}_en bitfield definitions + * preprocessor definitions for the bitfield "et_rxq{f}_en". + * parameter: filter {f} | stride size 0x4 | range [0, 15] + * port="pif_rpf_et_rxq_en_i[0]" + */ + +/* register address for bitfield et_rxq{f}_en */ +#define HW_ATL_RPF_ET_RXQFEN_ADR(filter) (0x00005300 + (filter) * 0x4) +/* bitmask for bitfield et_rxq{f}_en */ +#define HW_ATL_RPF_ET_RXQFEN_MSK 0x20000000 +/* inverted bitmask for bitfield et_rxq{f}_en */ +#define HW_ATL_RPF_ET_RXQFEN_MSKN 0xdfffffff +/* lower bit position of bitfield et_rxq{f}_en */ +#define HW_ATL_RPF_ET_RXQFEN_SHIFT 29 +/* width of bitfield et_rxq{f}_en */ +#define HW_ATL_RPF_ET_RXQFEN_WIDTH 1 +/* default value of bitfield et_rxq{f}_en */ +#define HW_ATL_RPF_ET_RXQFEN_DEFAULT 0x0 + +/* rx et_up{f}[2:0] bitfield definitions + * preprocessor definitions for the bitfield "et_up{f}[2:0]". + * parameter: filter {f} | stride size 0x4 | range [0, 15] + * port="pif_rpf_et_up0_i[2:0]" + */ + +/* register address for bitfield et_up{f}[2:0] */ +#define HW_ATL_RPF_ET_UPF_ADR(filter) (0x00005300 + (filter) * 0x4) +/* bitmask for bitfield et_up{f}[2:0] */ +#define HW_ATL_RPF_ET_UPF_MSK 0x1c000000 +/* inverted bitmask for bitfield et_up{f}[2:0] */ +#define HW_ATL_RPF_ET_UPF_MSKN 0xe3ffffff +/* lower bit position of bitfield et_up{f}[2:0] */ +#define HW_ATL_RPF_ET_UPF_SHIFT 26 +/* width of bitfield et_up{f}[2:0] */ +#define HW_ATL_RPF_ET_UPF_WIDTH 3 +/* default value of bitfield et_up{f}[2:0] */ +#define HW_ATL_RPF_ET_UPF_DEFAULT 0x0 + +/* rx et_rxq{f}[4:0] bitfield definitions + * preprocessor definitions for the bitfield "et_rxq{f}[4:0]". + * parameter: filter {f} | stride size 0x4 | range [0, 15] + * port="pif_rpf_et_rxq0_i[4:0]" + */ + +/* register address for bitfield et_rxq{f}[4:0] */ +#define HW_ATL_RPF_ET_RXQF_ADR(filter) (0x00005300 + (filter) * 0x4) +/* bitmask for bitfield et_rxq{f}[4:0] */ +#define HW_ATL_RPF_ET_RXQF_MSK 0x01f00000 +/* inverted bitmask for bitfield et_rxq{f}[4:0] */ +#define HW_ATL_RPF_ET_RXQF_MSKN 0xfe0fffff +/* lower bit position of bitfield et_rxq{f}[4:0] */ +#define HW_ATL_RPF_ET_RXQF_SHIFT 20 +/* width of bitfield et_rxq{f}[4:0] */ +#define HW_ATL_RPF_ET_RXQF_WIDTH 5 +/* default value of bitfield et_rxq{f}[4:0] */ +#define HW_ATL_RPF_ET_RXQF_DEFAULT 0x0 + +/* rx et_mng_rxq{f} bitfield definitions + * preprocessor definitions for the bitfield "et_mng_rxq{f}". + * parameter: filter {f} | stride size 0x4 | range [0, 15] + * port="pif_rpf_et_mng_rxq_i[0]" + */ + +/* register address for bitfield et_mng_rxq{f} */ +#define HW_ATL_RPF_ET_MNG_RXQF_ADR(filter) (0x00005300 + (filter) * 0x4) +/* bitmask for bitfield et_mng_rxq{f} */ +#define HW_ATL_RPF_ET_MNG_RXQF_MSK 0x00080000 +/* inverted bitmask for bitfield et_mng_rxq{f} */ +#define HW_ATL_RPF_ET_MNG_RXQF_MSKN 0xfff7ffff +/* lower bit position of bitfield et_mng_rxq{f} */ +#define HW_ATL_RPF_ET_MNG_RXQF_SHIFT 19 +/* width of bitfield et_mng_rxq{f} */ +#define HW_ATL_RPF_ET_MNG_RXQF_WIDTH 1 +/* default value of bitfield et_mng_rxq{f} */ +#define HW_ATL_RPF_ET_MNG_RXQF_DEFAULT 0x0 + +/* rx et_act{f}[2:0] bitfield definitions + * preprocessor definitions for the bitfield "et_act{f}[2:0]". + * parameter: filter {f} | stride size 0x4 | range [0, 15] + * port="pif_rpf_et_act0_i[2:0]" + */ + +/* register address for bitfield et_act{f}[2:0] */ +#define HW_ATL_RPF_ET_ACTF_ADR(filter) (0x00005300 + (filter) * 0x4) +/* bitmask for bitfield et_act{f}[2:0] */ +#define HW_ATL_RPF_ET_ACTF_MSK 0x00070000 +/* inverted bitmask for bitfield et_act{f}[2:0] */ +#define HW_ATL_RPF_ET_ACTF_MSKN 0xfff8ffff +/* lower bit position of bitfield et_act{f}[2:0] */ +#define HW_ATL_RPF_ET_ACTF_SHIFT 16 +/* width of bitfield et_act{f}[2:0] */ +#define HW_ATL_RPF_ET_ACTF_WIDTH 3 +/* default value of bitfield et_act{f}[2:0] */ +#define HW_ATL_RPF_ET_ACTF_DEFAULT 0x0 + +/* rx et_val{f}[f:0] bitfield definitions + * preprocessor definitions for the bitfield "et_val{f}[f:0]". + * parameter: filter {f} | stride size 0x4 | range [0, 15] + * port="pif_rpf_et_val0_i[15:0]" + */ + +/* register address for bitfield et_val{f}[f:0] */ +#define HW_ATL_RPF_ET_VALF_ADR(filter) (0x00005300 + (filter) * 0x4) +/* bitmask for bitfield et_val{f}[f:0] */ +#define HW_ATL_RPF_ET_VALF_MSK 0x0000ffff +/* inverted bitmask for bitfield et_val{f}[f:0] */ +#define HW_ATL_RPF_ET_VALF_MSKN 0xffff0000 +/* lower bit position of bitfield et_val{f}[f:0] */ +#define HW_ATL_RPF_ET_VALF_SHIFT 0 +/* width of bitfield et_val{f}[f:0] */ +#define HW_ATL_RPF_ET_VALF_WIDTH 16 +/* default value of bitfield et_val{f}[f:0] */ +#define HW_ATL_RPF_ET_VALF_DEFAULT 0x0 + +/* rx ipv4_chk_en bitfield definitions + * preprocessor definitions for the bitfield "ipv4_chk_en". + * port="pif_rpo_ipv4_chk_en_i" + */ + +/* register address for bitfield ipv4_chk_en */ +#define HW_ATL_RPO_IPV4CHK_EN_ADR 0x00005580 +/* bitmask for bitfield ipv4_chk_en */ +#define HW_ATL_RPO_IPV4CHK_EN_MSK 0x00000002 +/* inverted bitmask for bitfield ipv4_chk_en */ +#define HW_ATL_RPO_IPV4CHK_EN_MSKN 0xfffffffd +/* lower bit position of bitfield ipv4_chk_en */ +#define HW_ATL_RPO_IPV4CHK_EN_SHIFT 1 +/* width of bitfield ipv4_chk_en */ +#define HW_ATL_RPO_IPV4CHK_EN_WIDTH 1 +/* default value of bitfield ipv4_chk_en */ +#define HW_ATL_RPO_IPV4CHK_EN_DEFAULT 0x0 + +/* rx desc{d}_vl_strip bitfield definitions + * preprocessor definitions for the bitfield "desc{d}_vl_strip". + * parameter: descriptor {d} | stride size 0x20 | range [0, 31] + * port="pif_rpo_desc_vl_strip_i[0]" + */ + +/* register address for bitfield desc{d}_vl_strip */ +#define HW_ATL_RPO_DESCDVL_STRIP_ADR(descriptor) \ + (0x00005b08 + (descriptor) * 0x20) +/* bitmask for bitfield desc{d}_vl_strip */ +#define HW_ATL_RPO_DESCDVL_STRIP_MSK 0x20000000 +/* inverted bitmask for bitfield desc{d}_vl_strip */ +#define HW_ATL_RPO_DESCDVL_STRIP_MSKN 0xdfffffff +/* lower bit position of bitfield desc{d}_vl_strip */ +#define HW_ATL_RPO_DESCDVL_STRIP_SHIFT 29 +/* width of bitfield desc{d}_vl_strip */ +#define HW_ATL_RPO_DESCDVL_STRIP_WIDTH 1 +/* default value of bitfield desc{d}_vl_strip */ +#define HW_ATL_RPO_DESCDVL_STRIP_DEFAULT 0x0 + +/* rx l4_chk_en bitfield definitions + * preprocessor definitions for the bitfield "l4_chk_en". + * port="pif_rpo_l4_chk_en_i" + */ + +/* register address for bitfield l4_chk_en */ +#define HW_ATL_RPOL4CHK_EN_ADR 0x00005580 +/* bitmask for bitfield l4_chk_en */ +#define HW_ATL_RPOL4CHK_EN_MSK 0x00000001 +/* inverted bitmask for bitfield l4_chk_en */ +#define HW_ATL_RPOL4CHK_EN_MSKN 0xfffffffe +/* lower bit position of bitfield l4_chk_en */ +#define HW_ATL_RPOL4CHK_EN_SHIFT 0 +/* width of bitfield l4_chk_en */ +#define HW_ATL_RPOL4CHK_EN_WIDTH 1 +/* default value of bitfield l4_chk_en */ +#define HW_ATL_RPOL4CHK_EN_DEFAULT 0x0 + +/* rx reg_res_dsbl bitfield definitions + * preprocessor definitions for the bitfield "reg_res_dsbl". + * port="pif_rx_reg_res_dsbl_i" + */ + +/* register address for bitfield reg_res_dsbl */ +#define HW_ATL_RX_REG_RES_DSBL_ADR 0x00005000 +/* bitmask for bitfield reg_res_dsbl */ +#define HW_ATL_RX_REG_RES_DSBL_MSK 0x20000000 +/* inverted bitmask for bitfield reg_res_dsbl */ +#define HW_ATL_RX_REG_RES_DSBL_MSKN 0xdfffffff +/* lower bit position of bitfield reg_res_dsbl */ +#define HW_ATL_RX_REG_RES_DSBL_SHIFT 29 +/* width of bitfield reg_res_dsbl */ +#define HW_ATL_RX_REG_RES_DSBL_WIDTH 1 +/* default value of bitfield reg_res_dsbl */ +#define HW_ATL_RX_REG_RES_DSBL_DEFAULT 0x1 + +/* tx dca{d}_cpuid[7:0] bitfield definitions + * preprocessor definitions for the bitfield "dca{d}_cpuid[7:0]". + * parameter: dca {d} | stride size 0x4 | range [0, 31] + * port="pif_tdm_dca0_cpuid_i[7:0]" + */ + +/* register address for bitfield dca{d}_cpuid[7:0] */ +#define HW_ATL_TDM_DCADCPUID_ADR(dca) (0x00008400 + (dca) * 0x4) +/* bitmask for bitfield dca{d}_cpuid[7:0] */ +#define HW_ATL_TDM_DCADCPUID_MSK 0x000000ff +/* inverted bitmask for bitfield dca{d}_cpuid[7:0] */ +#define HW_ATL_TDM_DCADCPUID_MSKN 0xffffff00 +/* lower bit position of bitfield dca{d}_cpuid[7:0] */ +#define HW_ATL_TDM_DCADCPUID_SHIFT 0 +/* width of bitfield dca{d}_cpuid[7:0] */ +#define HW_ATL_TDM_DCADCPUID_WIDTH 8 +/* default value of bitfield dca{d}_cpuid[7:0] */ +#define HW_ATL_TDM_DCADCPUID_DEFAULT 0x0 + +/* tx lso_en[1f:0] bitfield definitions + * preprocessor definitions for the bitfield "lso_en[1f:0]". + * port="pif_tdm_lso_en_i[31:0]" + */ + +/* register address for bitfield lso_en[1f:0] */ +#define HW_ATL_TDM_LSO_EN_ADR 0x00007810 +/* bitmask for bitfield lso_en[1f:0] */ +#define HW_ATL_TDM_LSO_EN_MSK 0xffffffff +/* inverted bitmask for bitfield lso_en[1f:0] */ +#define HW_ATL_TDM_LSO_EN_MSKN 0x00000000 +/* lower bit position of bitfield lso_en[1f:0] */ +#define HW_ATL_TDM_LSO_EN_SHIFT 0 +/* width of bitfield lso_en[1f:0] */ +#define HW_ATL_TDM_LSO_EN_WIDTH 32 +/* default value of bitfield lso_en[1f:0] */ +#define HW_ATL_TDM_LSO_EN_DEFAULT 0x0 + +/* tx dca_en bitfield definitions + * preprocessor definitions for the bitfield "dca_en". + * port="pif_tdm_dca_en_i" + */ + +/* register address for bitfield dca_en */ +#define HW_ATL_TDM_DCA_EN_ADR 0x00008480 +/* bitmask for bitfield dca_en */ +#define HW_ATL_TDM_DCA_EN_MSK 0x80000000 +/* inverted bitmask for bitfield dca_en */ +#define HW_ATL_TDM_DCA_EN_MSKN 0x7fffffff +/* lower bit position of bitfield dca_en */ +#define HW_ATL_TDM_DCA_EN_SHIFT 31 +/* width of bitfield dca_en */ +#define HW_ATL_TDM_DCA_EN_WIDTH 1 +/* default value of bitfield dca_en */ +#define HW_ATL_TDM_DCA_EN_DEFAULT 0x1 + +/* tx dca_mode[3:0] bitfield definitions + * preprocessor definitions for the bitfield "dca_mode[3:0]". + * port="pif_tdm_dca_mode_i[3:0]" + */ + +/* register address for bitfield dca_mode[3:0] */ +#define HW_ATL_TDM_DCA_MODE_ADR 0x00008480 +/* bitmask for bitfield dca_mode[3:0] */ +#define HW_ATL_TDM_DCA_MODE_MSK 0x0000000f +/* inverted bitmask for bitfield dca_mode[3:0] */ +#define HW_ATL_TDM_DCA_MODE_MSKN 0xfffffff0 +/* lower bit position of bitfield dca_mode[3:0] */ +#define HW_ATL_TDM_DCA_MODE_SHIFT 0 +/* width of bitfield dca_mode[3:0] */ +#define HW_ATL_TDM_DCA_MODE_WIDTH 4 +/* default value of bitfield dca_mode[3:0] */ +#define HW_ATL_TDM_DCA_MODE_DEFAULT 0x0 + +/* tx dca{d}_desc_en bitfield definitions + * preprocessor definitions for the bitfield "dca{d}_desc_en". + * parameter: dca {d} | stride size 0x4 | range [0, 31] + * port="pif_tdm_dca_desc_en_i[0]" + */ + +/* register address for bitfield dca{d}_desc_en */ +#define HW_ATL_TDM_DCADDESC_EN_ADR(dca) (0x00008400 + (dca) * 0x4) +/* bitmask for bitfield dca{d}_desc_en */ +#define HW_ATL_TDM_DCADDESC_EN_MSK 0x80000000 +/* inverted bitmask for bitfield dca{d}_desc_en */ +#define HW_ATL_TDM_DCADDESC_EN_MSKN 0x7fffffff +/* lower bit position of bitfield dca{d}_desc_en */ +#define HW_ATL_TDM_DCADDESC_EN_SHIFT 31 +/* width of bitfield dca{d}_desc_en */ +#define HW_ATL_TDM_DCADDESC_EN_WIDTH 1 +/* default value of bitfield dca{d}_desc_en */ +#define HW_ATL_TDM_DCADDESC_EN_DEFAULT 0x0 + +/* tx desc{d}_en bitfield definitions + * preprocessor definitions for the bitfield "desc{d}_en". + * parameter: descriptor {d} | stride size 0x40 | range [0, 31] + * port="pif_tdm_desc_en_i[0]" + */ + +/* register address for bitfield desc{d}_en */ +#define HW_ATL_TDM_DESCDEN_ADR(descriptor) (0x00007c08 + (descriptor) * 0x40) +/* bitmask for bitfield desc{d}_en */ +#define HW_ATL_TDM_DESCDEN_MSK 0x80000000 +/* inverted bitmask for bitfield desc{d}_en */ +#define HW_ATL_TDM_DESCDEN_MSKN 0x7fffffff +/* lower bit position of bitfield desc{d}_en */ +#define HW_ATL_TDM_DESCDEN_SHIFT 31 +/* width of bitfield desc{d}_en */ +#define HW_ATL_TDM_DESCDEN_WIDTH 1 +/* default value of bitfield desc{d}_en */ +#define HW_ATL_TDM_DESCDEN_DEFAULT 0x0 + +/* tx desc{d}_hd[c:0] bitfield definitions + * preprocessor definitions for the bitfield "desc{d}_hd[c:0]". + * parameter: descriptor {d} | stride size 0x40 | range [0, 31] + * port="tdm_pif_desc0_hd_o[12:0]" + */ + +/* register address for bitfield desc{d}_hd[c:0] */ +#define HW_ATL_TDM_DESCDHD_ADR(descriptor) (0x00007c0c + (descriptor) * 0x40) +/* bitmask for bitfield desc{d}_hd[c:0] */ +#define HW_ATL_TDM_DESCDHD_MSK 0x00001fff +/* inverted bitmask for bitfield desc{d}_hd[c:0] */ +#define HW_ATL_TDM_DESCDHD_MSKN 0xffffe000 +/* lower bit position of bitfield desc{d}_hd[c:0] */ +#define HW_ATL_TDM_DESCDHD_SHIFT 0 +/* width of bitfield desc{d}_hd[c:0] */ +#define HW_ATL_TDM_DESCDHD_WIDTH 13 + +/* tx desc{d}_len[9:0] bitfield definitions + * preprocessor definitions for the bitfield "desc{d}_len[9:0]". + * parameter: descriptor {d} | stride size 0x40 | range [0, 31] + * port="pif_tdm_desc0_len_i[9:0]" + */ + +/* register address for bitfield desc{d}_len[9:0] */ +#define HW_ATL_TDM_DESCDLEN_ADR(descriptor) (0x00007c08 + (descriptor) * 0x40) +/* bitmask for bitfield desc{d}_len[9:0] */ +#define HW_ATL_TDM_DESCDLEN_MSK 0x00001ff8 +/* inverted bitmask for bitfield desc{d}_len[9:0] */ +#define HW_ATL_TDM_DESCDLEN_MSKN 0xffffe007 +/* lower bit position of bitfield desc{d}_len[9:0] */ +#define HW_ATL_TDM_DESCDLEN_SHIFT 3 +/* width of bitfield desc{d}_len[9:0] */ +#define HW_ATL_TDM_DESCDLEN_WIDTH 10 +/* default value of bitfield desc{d}_len[9:0] */ +#define HW_ATL_TDM_DESCDLEN_DEFAULT 0x0 + +/* tx int_desc_wrb_en bitfield definitions + * preprocessor definitions for the bitfield "int_desc_wrb_en". + * port="pif_tdm_int_desc_wrb_en_i" + */ + +/* register address for bitfield int_desc_wrb_en */ +#define HW_ATL_TDM_INT_DESC_WRB_EN_ADR 0x00007b40 +/* bitmask for bitfield int_desc_wrb_en */ +#define HW_ATL_TDM_INT_DESC_WRB_EN_MSK 0x00000002 +/* inverted bitmask for bitfield int_desc_wrb_en */ +#define HW_ATL_TDM_INT_DESC_WRB_EN_MSKN 0xfffffffd +/* lower bit position of bitfield int_desc_wrb_en */ +#define HW_ATL_TDM_INT_DESC_WRB_EN_SHIFT 1 +/* width of bitfield int_desc_wrb_en */ +#define HW_ATL_TDM_INT_DESC_WRB_EN_WIDTH 1 +/* default value of bitfield int_desc_wrb_en */ +#define HW_ATL_TDM_INT_DESC_WRB_EN_DEFAULT 0x0 + +/* tx desc{d}_wrb_thresh[6:0] bitfield definitions + * preprocessor definitions for the bitfield "desc{d}_wrb_thresh[6:0]". + * parameter: descriptor {d} | stride size 0x40 | range [0, 31] + * port="pif_tdm_desc0_wrb_thresh_i[6:0]" + */ + +/* register address for bitfield desc{d}_wrb_thresh[6:0] */ +#define HW_ATL_TDM_DESCDWRB_THRESH_ADR(descriptor) \ + (0x00007c18 + (descriptor) * 0x40) +/* bitmask for bitfield desc{d}_wrb_thresh[6:0] */ +#define HW_ATL_TDM_DESCDWRB_THRESH_MSK 0x00007f00 +/* inverted bitmask for bitfield desc{d}_wrb_thresh[6:0] */ +#define HW_ATL_TDM_DESCDWRB_THRESH_MSKN 0xffff80ff +/* lower bit position of bitfield desc{d}_wrb_thresh[6:0] */ +#define HW_ATL_TDM_DESCDWRB_THRESH_SHIFT 8 +/* width of bitfield desc{d}_wrb_thresh[6:0] */ +#define HW_ATL_TDM_DESCDWRB_THRESH_WIDTH 7 +/* default value of bitfield desc{d}_wrb_thresh[6:0] */ +#define HW_ATL_TDM_DESCDWRB_THRESH_DEFAULT 0x0 + +/* tx lso_tcp_flag_first[b:0] bitfield definitions + * preprocessor definitions for the bitfield "lso_tcp_flag_first[b:0]". + * port="pif_thm_lso_tcp_flag_first_i[11:0]" + */ + +/* register address for bitfield lso_tcp_flag_first[b:0] */ +#define HW_ATL_THM_LSO_TCP_FLAG_FIRST_ADR 0x00007820 +/* bitmask for bitfield lso_tcp_flag_first[b:0] */ +#define HW_ATL_THM_LSO_TCP_FLAG_FIRST_MSK 0x00000fff +/* inverted bitmask for bitfield lso_tcp_flag_first[b:0] */ +#define HW_ATL_THM_LSO_TCP_FLAG_FIRST_MSKN 0xfffff000 +/* lower bit position of bitfield lso_tcp_flag_first[b:0] */ +#define HW_ATL_THM_LSO_TCP_FLAG_FIRST_SHIFT 0 +/* width of bitfield lso_tcp_flag_first[b:0] */ +#define HW_ATL_THM_LSO_TCP_FLAG_FIRST_WIDTH 12 +/* default value of bitfield lso_tcp_flag_first[b:0] */ +#define HW_ATL_THM_LSO_TCP_FLAG_FIRST_DEFAULT 0x0 + +/* tx lso_tcp_flag_last[b:0] bitfield definitions + * preprocessor definitions for the bitfield "lso_tcp_flag_last[b:0]". + * port="pif_thm_lso_tcp_flag_last_i[11:0]" + */ + +/* register address for bitfield lso_tcp_flag_last[b:0] */ +#define HW_ATL_THM_LSO_TCP_FLAG_LAST_ADR 0x00007824 +/* bitmask for bitfield lso_tcp_flag_last[b:0] */ +#define HW_ATL_THM_LSO_TCP_FLAG_LAST_MSK 0x00000fff +/* inverted bitmask for bitfield lso_tcp_flag_last[b:0] */ +#define HW_ATL_THM_LSO_TCP_FLAG_LAST_MSKN 0xfffff000 +/* lower bit position of bitfield lso_tcp_flag_last[b:0] */ +#define HW_ATL_THM_LSO_TCP_FLAG_LAST_SHIFT 0 +/* width of bitfield lso_tcp_flag_last[b:0] */ +#define HW_ATL_THM_LSO_TCP_FLAG_LAST_WIDTH 12 +/* default value of bitfield lso_tcp_flag_last[b:0] */ +#define HW_ATL_THM_LSO_TCP_FLAG_LAST_DEFAULT 0x0 + +/* tx lso_tcp_flag_mid[b:0] bitfield definitions + * preprocessor definitions for the bitfield "lso_tcp_flag_mid[b:0]". + * port="pif_thm_lso_tcp_flag_mid_i[11:0]" + */ + +/* Register address for bitfield lro_rsc_max[1F:0] */ +#define HW_ATL_RPO_LRO_RSC_MAX_ADR 0x00005598 +/* Bitmask for bitfield lro_rsc_max[1F:0] */ +#define HW_ATL_RPO_LRO_RSC_MAX_MSK 0xFFFFFFFF +/* Inverted bitmask for bitfield lro_rsc_max[1F:0] */ +#define HW_ATL_RPO_LRO_RSC_MAX_MSKN 0x00000000 +/* Lower bit position of bitfield lro_rsc_max[1F:0] */ +#define HW_ATL_RPO_LRO_RSC_MAX_SHIFT 0 +/* Width of bitfield lro_rsc_max[1F:0] */ +#define HW_ATL_RPO_LRO_RSC_MAX_WIDTH 32 +/* Default value of bitfield lro_rsc_max[1F:0] */ +#define HW_ATL_RPO_LRO_RSC_MAX_DEFAULT 0x0 + +/* RX lro_en[1F:0] Bitfield Definitions + * Preprocessor definitions for the bitfield "lro_en[1F:0]". + * PORT="pif_rpo_lro_en_i[31:0]" + */ + +/* Register address for bitfield lro_en[1F:0] */ +#define HW_ATL_RPO_LRO_EN_ADR 0x00005590 +/* Bitmask for bitfield lro_en[1F:0] */ +#define HW_ATL_RPO_LRO_EN_MSK 0xFFFFFFFF +/* Inverted bitmask for bitfield lro_en[1F:0] */ +#define HW_ATL_RPO_LRO_EN_MSKN 0x00000000 +/* Lower bit position of bitfield lro_en[1F:0] */ +#define HW_ATL_RPO_LRO_EN_SHIFT 0 +/* Width of bitfield lro_en[1F:0] */ +#define HW_ATL_RPO_LRO_EN_WIDTH 32 +/* Default value of bitfield lro_en[1F:0] */ +#define HW_ATL_RPO_LRO_EN_DEFAULT 0x0 + +/* RX lro_ptopt_en Bitfield Definitions + * Preprocessor definitions for the bitfield "lro_ptopt_en". + * PORT="pif_rpo_lro_ptopt_en_i" + */ + +/* Register address for bitfield lro_ptopt_en */ +#define HW_ATL_RPO_LRO_PTOPT_EN_ADR 0x00005594 +/* Bitmask for bitfield lro_ptopt_en */ +#define HW_ATL_RPO_LRO_PTOPT_EN_MSK 0x00008000 +/* Inverted bitmask for bitfield lro_ptopt_en */ +#define HW_ATL_RPO_LRO_PTOPT_EN_MSKN 0xFFFF7FFF +/* Lower bit position of bitfield lro_ptopt_en */ +#define HW_ATL_RPO_LRO_PTOPT_EN_SHIFT 15 +/* Width of bitfield lro_ptopt_en */ +#define HW_ATL_RPO_LRO_PTOPT_EN_WIDTH 1 +/* Default value of bitfield lro_ptopt_en */ +#define HW_ATL_RPO_LRO_PTOPT_EN_DEFALT 0x1 + +/* RX lro_q_ses_lmt Bitfield Definitions + * Preprocessor definitions for the bitfield "lro_q_ses_lmt". + * PORT="pif_rpo_lro_q_ses_lmt_i[1:0]" + */ + +/* Register address for bitfield lro_q_ses_lmt */ +#define HW_ATL_RPO_LRO_QSES_LMT_ADR 0x00005594 +/* Bitmask for bitfield lro_q_ses_lmt */ +#define HW_ATL_RPO_LRO_QSES_LMT_MSK 0x00003000 +/* Inverted bitmask for bitfield lro_q_ses_lmt */ +#define HW_ATL_RPO_LRO_QSES_LMT_MSKN 0xFFFFCFFF +/* Lower bit position of bitfield lro_q_ses_lmt */ +#define HW_ATL_RPO_LRO_QSES_LMT_SHIFT 12 +/* Width of bitfield lro_q_ses_lmt */ +#define HW_ATL_RPO_LRO_QSES_LMT_WIDTH 2 +/* Default value of bitfield lro_q_ses_lmt */ +#define HW_ATL_RPO_LRO_QSES_LMT_DEFAULT 0x1 + +/* RX lro_tot_dsc_lmt[1:0] Bitfield Definitions + * Preprocessor definitions for the bitfield "lro_tot_dsc_lmt[1:0]". + * PORT="pif_rpo_lro_tot_dsc_lmt_i[1:0]" + */ + +/* Register address for bitfield lro_tot_dsc_lmt[1:0] */ +#define HW_ATL_RPO_LRO_TOT_DSC_LMT_ADR 0x00005594 +/* Bitmask for bitfield lro_tot_dsc_lmt[1:0] */ +#define HW_ATL_RPO_LRO_TOT_DSC_LMT_MSK 0x00000060 +/* Inverted bitmask for bitfield lro_tot_dsc_lmt[1:0] */ +#define HW_ATL_RPO_LRO_TOT_DSC_LMT_MSKN 0xFFFFFF9F +/* Lower bit position of bitfield lro_tot_dsc_lmt[1:0] */ +#define HW_ATL_RPO_LRO_TOT_DSC_LMT_SHIFT 5 +/* Width of bitfield lro_tot_dsc_lmt[1:0] */ +#define HW_ATL_RPO_LRO_TOT_DSC_LMT_WIDTH 2 +/* Default value of bitfield lro_tot_dsc_lmt[1:0] */ +#define HW_ATL_RPO_LRO_TOT_DSC_LMT_DEFALT 0x1 + +/* RX lro_pkt_min[4:0] Bitfield Definitions + * Preprocessor definitions for the bitfield "lro_pkt_min[4:0]". + * PORT="pif_rpo_lro_pkt_min_i[4:0]" + */ + +/* Register address for bitfield lro_pkt_min[4:0] */ +#define HW_ATL_RPO_LRO_PKT_MIN_ADR 0x00005594 +/* Bitmask for bitfield lro_pkt_min[4:0] */ +#define HW_ATL_RPO_LRO_PKT_MIN_MSK 0x0000001F +/* Inverted bitmask for bitfield lro_pkt_min[4:0] */ +#define HW_ATL_RPO_LRO_PKT_MIN_MSKN 0xFFFFFFE0 +/* Lower bit position of bitfield lro_pkt_min[4:0] */ +#define HW_ATL_RPO_LRO_PKT_MIN_SHIFT 0 +/* Width of bitfield lro_pkt_min[4:0] */ +#define HW_ATL_RPO_LRO_PKT_MIN_WIDTH 5 +/* Default value of bitfield lro_pkt_min[4:0] */ +#define HW_ATL_RPO_LRO_PKT_MIN_DEFAULT 0x8 + +/* Width of bitfield lro{L}_des_max[1:0] */ +#define HW_ATL_RPO_LRO_LDES_MAX_WIDTH 2 +/* Default value of bitfield lro{L}_des_max[1:0] */ +#define HW_ATL_RPO_LRO_LDES_MAX_DEFAULT 0x0 + +/* RX lro_tb_div[11:0] Bitfield Definitions + * Preprocessor definitions for the bitfield "lro_tb_div[11:0]". + * PORT="pif_rpo_lro_tb_div_i[11:0]" + */ + +/* Register address for bitfield lro_tb_div[11:0] */ +#define HW_ATL_RPO_LRO_TB_DIV_ADR 0x00005620 +/* Bitmask for bitfield lro_tb_div[11:0] */ +#define HW_ATL_RPO_LRO_TB_DIV_MSK 0xFFF00000 +/* Inverted bitmask for bitfield lro_tb_div[11:0] */ +#define HW_ATL_RPO_LRO_TB_DIV_MSKN 0x000FFFFF +/* Lower bit position of bitfield lro_tb_div[11:0] */ +#define HW_ATL_RPO_LRO_TB_DIV_SHIFT 20 +/* Width of bitfield lro_tb_div[11:0] */ +#define HW_ATL_RPO_LRO_TB_DIV_WIDTH 12 +/* Default value of bitfield lro_tb_div[11:0] */ +#define HW_ATL_RPO_LRO_TB_DIV_DEFAULT 0xC35 + +/* RX lro_ina_ival[9:0] Bitfield Definitions + * Preprocessor definitions for the bitfield "lro_ina_ival[9:0]". + * PORT="pif_rpo_lro_ina_ival_i[9:0]" + */ + +/* Register address for bitfield lro_ina_ival[9:0] */ +#define HW_ATL_RPO_LRO_INA_IVAL_ADR 0x00005620 +/* Bitmask for bitfield lro_ina_ival[9:0] */ +#define HW_ATL_RPO_LRO_INA_IVAL_MSK 0x000FFC00 +/* Inverted bitmask for bitfield lro_ina_ival[9:0] */ +#define HW_ATL_RPO_LRO_INA_IVAL_MSKN 0xFFF003FF +/* Lower bit position of bitfield lro_ina_ival[9:0] */ +#define HW_ATL_RPO_LRO_INA_IVAL_SHIFT 10 +/* Width of bitfield lro_ina_ival[9:0] */ +#define HW_ATL_RPO_LRO_INA_IVAL_WIDTH 10 +/* Default value of bitfield lro_ina_ival[9:0] */ +#define HW_ATL_RPO_LRO_INA_IVAL_DEFAULT 0xA + +/* RX lro_max_ival[9:0] Bitfield Definitions + * Preprocessor definitions for the bitfield "lro_max_ival[9:0]". + * PORT="pif_rpo_lro_max_ival_i[9:0]" + */ + +/* Register address for bitfield lro_max_ival[9:0] */ +#define HW_ATL_RPO_LRO_MAX_IVAL_ADR 0x00005620 +/* Bitmask for bitfield lro_max_ival[9:0] */ +#define HW_ATL_RPO_LRO_MAX_IVAL_MSK 0x000003FF +/* Inverted bitmask for bitfield lro_max_ival[9:0] */ +#define HW_ATL_RPO_LRO_MAX_IVAL_MSKN 0xFFFFFC00 +/* Lower bit position of bitfield lro_max_ival[9:0] */ +#define HW_ATL_RPO_LRO_MAX_IVAL_SHIFT 0 +/* Width of bitfield lro_max_ival[9:0] */ +#define HW_ATL_RPO_LRO_MAX_IVAL_WIDTH 10 +/* Default value of bitfield lro_max_ival[9:0] */ +#define HW_ATL_RPO_LRO_MAX_IVAL_DEFAULT 0x19 + +/* TX dca{D}_cpuid[7:0] Bitfield Definitions + * Preprocessor definitions for the bitfield "dca{D}_cpuid[7:0]". + * Parameter: DCA {D} | stride size 0x4 | range [0, 31] + * PORT="pif_tdm_dca0_cpuid_i[7:0]" + */ + +/* Register address for bitfield dca{D}_cpuid[7:0] */ +#define HW_ATL_TDM_DCA_DCPUID_ADR(dca) (0x00008400 + (dca) * 0x4) +/* Bitmask for bitfield dca{D}_cpuid[7:0] */ +#define HW_ATL_TDM_DCA_DCPUID_MSK 0x000000FF +/* Inverted bitmask for bitfield dca{D}_cpuid[7:0] */ +#define HW_ATL_TDM_DCA_DCPUID_MSKN 0xFFFFFF00 +/* Lower bit position of bitfield dca{D}_cpuid[7:0] */ +#define HW_ATL_TDM_DCA_DCPUID_SHIFT 0 +/* Width of bitfield dca{D}_cpuid[7:0] */ +#define HW_ATL_TDM_DCA_DCPUID_WIDTH 8 +/* Default value of bitfield dca{D}_cpuid[7:0] */ +#define HW_ATL_TDM_DCA_DCPUID_DEFAULT 0x0 + +/* TX dca{D}_desc_en Bitfield Definitions + * Preprocessor definitions for the bitfield "dca{D}_desc_en". + * Parameter: DCA {D} | stride size 0x4 | range [0, 31] + * PORT="pif_tdm_dca_desc_en_i[0]" + */ + +/* Register address for bitfield dca{D}_desc_en */ +#define HW_ATL_TDM_DCA_DDESC_EN_ADR(dca) (0x00008400 + (dca) * 0x4) +/* Bitmask for bitfield dca{D}_desc_en */ +#define HW_ATL_TDM_DCA_DDESC_EN_MSK 0x80000000 +/* Inverted bitmask for bitfield dca{D}_desc_en */ +#define HW_ATL_TDM_DCA_DDESC_EN_MSKN 0x7FFFFFFF +/* Lower bit position of bitfield dca{D}_desc_en */ +#define HW_ATL_TDM_DCA_DDESC_EN_SHIFT 31 +/* Width of bitfield dca{D}_desc_en */ +#define HW_ATL_TDM_DCA_DDESC_EN_WIDTH 1 +/* Default value of bitfield dca{D}_desc_en */ +#define HW_ATL_TDM_DCA_DDESC_EN_DEFAULT 0x0 + +/* TX desc{D}_en Bitfield Definitions + * Preprocessor definitions for the bitfield "desc{D}_en". + * Parameter: descriptor {D} | stride size 0x40 | range [0, 31] + * PORT="pif_tdm_desc_en_i[0]" + */ + +/* Register address for bitfield desc{D}_en */ +#define HW_ATL_TDM_DESC_DEN_ADR(descriptor) (0x00007C08 + (descriptor) * 0x40) +/* Bitmask for bitfield desc{D}_en */ +#define HW_ATL_TDM_DESC_DEN_MSK 0x80000000 +/* Inverted bitmask for bitfield desc{D}_en */ +#define HW_ATL_TDM_DESC_DEN_MSKN 0x7FFFFFFF +/* Lower bit position of bitfield desc{D}_en */ +#define HW_ATL_TDM_DESC_DEN_SHIFT 31 +/* Width of bitfield desc{D}_en */ +#define HW_ATL_TDM_DESC_DEN_WIDTH 1 +/* Default value of bitfield desc{D}_en */ +#define HW_ATL_TDM_DESC_DEN_DEFAULT 0x0 + +/* TX desc{D}_hd[C:0] Bitfield Definitions + * Preprocessor definitions for the bitfield "desc{D}_hd[C:0]". + * Parameter: descriptor {D} | stride size 0x40 | range [0, 31] + * PORT="tdm_pif_desc0_hd_o[12:0]" + */ + +/* Register address for bitfield desc{D}_hd[C:0] */ +#define HW_ATL_TDM_DESC_DHD_ADR(descriptor) (0x00007C0C + (descriptor) * 0x40) +/* Bitmask for bitfield desc{D}_hd[C:0] */ +#define HW_ATL_TDM_DESC_DHD_MSK 0x00001FFF +/* Inverted bitmask for bitfield desc{D}_hd[C:0] */ +#define HW_ATL_TDM_DESC_DHD_MSKN 0xFFFFE000 +/* Lower bit position of bitfield desc{D}_hd[C:0] */ +#define HW_ATL_TDM_DESC_DHD_SHIFT 0 +/* Width of bitfield desc{D}_hd[C:0] */ +#define HW_ATL_TDM_DESC_DHD_WIDTH 13 + +/* TX desc{D}_len[9:0] Bitfield Definitions + * Preprocessor definitions for the bitfield "desc{D}_len[9:0]". + * Parameter: descriptor {D} | stride size 0x40 | range [0, 31] + * PORT="pif_tdm_desc0_len_i[9:0]" + */ + +/* Register address for bitfield desc{D}_len[9:0] */ +#define HW_ATL_TDM_DESC_DLEN_ADR(descriptor) (0x00007C08 + (descriptor) * 0x40) +/* Bitmask for bitfield desc{D}_len[9:0] */ +#define HW_ATL_TDM_DESC_DLEN_MSK 0x00001FF8 +/* Inverted bitmask for bitfield desc{D}_len[9:0] */ +#define HW_ATL_TDM_DESC_DLEN_MSKN 0xFFFFE007 +/* Lower bit position of bitfield desc{D}_len[9:0] */ +#define HW_ATL_TDM_DESC_DLEN_SHIFT 3 +/* Width of bitfield desc{D}_len[9:0] */ +#define HW_ATL_TDM_DESC_DLEN_WIDTH 10 +/* Default value of bitfield desc{D}_len[9:0] */ +#define HW_ATL_TDM_DESC_DLEN_DEFAULT 0x0 + +/* TX desc{D}_wrb_thresh[6:0] Bitfield Definitions + * Preprocessor definitions for the bitfield "desc{D}_wrb_thresh[6:0]". + * Parameter: descriptor {D} | stride size 0x40 | range [0, 31] + * PORT="pif_tdm_desc0_wrb_thresh_i[6:0]" + */ + +/* Register address for bitfield desc{D}_wrb_thresh[6:0] */ +#define HW_ATL_TDM_DESC_DWRB_THRESH_ADR(descriptor) \ + (0x00007C18 + (descriptor) * 0x40) +/* Bitmask for bitfield desc{D}_wrb_thresh[6:0] */ +#define HW_ATL_TDM_DESC_DWRB_THRESH_MSK 0x00007F00 +/* Inverted bitmask for bitfield desc{D}_wrb_thresh[6:0] */ +#define HW_ATL_TDM_DESC_DWRB_THRESH_MSKN 0xFFFF80FF +/* Lower bit position of bitfield desc{D}_wrb_thresh[6:0] */ +#define HW_ATL_TDM_DESC_DWRB_THRESH_SHIFT 8 +/* Width of bitfield desc{D}_wrb_thresh[6:0] */ +#define HW_ATL_TDM_DESC_DWRB_THRESH_WIDTH 7 +/* Default value of bitfield desc{D}_wrb_thresh[6:0] */ +#define HW_ATL_TDM_DESC_DWRB_THRESH_DEFAULT 0x0 + +/* TX tdm_int_mod_en Bitfield Definitions + * Preprocessor definitions for the bitfield "tdm_int_mod_en". + * PORT="pif_tdm_int_mod_en_i" + */ + +/* Register address for bitfield tdm_int_mod_en */ +#define HW_ATL_TDM_INT_MOD_EN_ADR 0x00007B40 +/* Bitmask for bitfield tdm_int_mod_en */ +#define HW_ATL_TDM_INT_MOD_EN_MSK 0x00000010 +/* Inverted bitmask for bitfield tdm_int_mod_en */ +#define HW_ATL_TDM_INT_MOD_EN_MSKN 0xFFFFFFEF +/* Lower bit position of bitfield tdm_int_mod_en */ +#define HW_ATL_TDM_INT_MOD_EN_SHIFT 4 +/* Width of bitfield tdm_int_mod_en */ +#define HW_ATL_TDM_INT_MOD_EN_WIDTH 1 +/* Default value of bitfield tdm_int_mod_en */ +#define HW_ATL_TDM_INT_MOD_EN_DEFAULT 0x0 + +/* TX lso_tcp_flag_mid[B:0] Bitfield Definitions + * Preprocessor definitions for the bitfield "lso_tcp_flag_mid[B:0]". + * PORT="pif_thm_lso_tcp_flag_mid_i[11:0]" + */ +/* register address for bitfield lso_tcp_flag_mid[b:0] */ +#define HW_ATL_THM_LSO_TCP_FLAG_MID_ADR 0x00007820 +/* bitmask for bitfield lso_tcp_flag_mid[b:0] */ +#define HW_ATL_THM_LSO_TCP_FLAG_MID_MSK 0x0fff0000 +/* inverted bitmask for bitfield lso_tcp_flag_mid[b:0] */ +#define HW_ATL_THM_LSO_TCP_FLAG_MID_MSKN 0xf000ffff +/* lower bit position of bitfield lso_tcp_flag_mid[b:0] */ +#define HW_ATL_THM_LSO_TCP_FLAG_MID_SHIFT 16 +/* width of bitfield lso_tcp_flag_mid[b:0] */ +#define HW_ATL_THM_LSO_TCP_FLAG_MID_WIDTH 12 +/* default value of bitfield lso_tcp_flag_mid[b:0] */ +#define HW_ATL_THM_LSO_TCP_FLAG_MID_DEFAULT 0x0 + +/* tx tx_buf_en bitfield definitions + * preprocessor definitions for the bitfield "tx_buf_en". + * port="pif_tpb_tx_buf_en_i" + */ + +/* register address for bitfield tx_buf_en */ +#define HW_ATL_TPB_TX_BUF_EN_ADR 0x00007900 +/* bitmask for bitfield tx_buf_en */ +#define HW_ATL_TPB_TX_BUF_EN_MSK 0x00000001 +/* inverted bitmask for bitfield tx_buf_en */ +#define HW_ATL_TPB_TX_BUF_EN_MSKN 0xfffffffe +/* lower bit position of bitfield tx_buf_en */ +#define HW_ATL_TPB_TX_BUF_EN_SHIFT 0 +/* width of bitfield tx_buf_en */ +#define HW_ATL_TPB_TX_BUF_EN_WIDTH 1 +/* default value of bitfield tx_buf_en */ +#define HW_ATL_TPB_TX_BUF_EN_DEFAULT 0x0 + +/* register address for bitfield tx_tc_mode */ +#define HW_ATL_TPB_TX_TC_MODE_ADDR 0x00007900 +/* bitmask for bitfield tx_tc_mode */ +#define HW_ATL_TPB_TX_TC_MODE_MSK 0x00000100 +/* inverted bitmask for bitfield tx_tc_mode */ +#define HW_ATL_TPB_TX_TC_MODE_MSKN 0xFFFFFEFF +/* lower bit position of bitfield tx_tc_mode */ +#define HW_ATL_TPB_TX_TC_MODE_SHIFT 8 +/* width of bitfield tx_tc_mode */ +#define HW_ATL_TPB_TX_TC_MODE_WIDTH 1 +/* default value of bitfield tx_tc_mode */ +#define HW_ATL_TPB_TX_TC_MODE_DEFAULT 0x0 + +/* tx tx{b}_hi_thresh[c:0] bitfield definitions + * preprocessor definitions for the bitfield "tx{b}_hi_thresh[c:0]". + * parameter: buffer {b} | stride size 0x10 | range [0, 7] + * port="pif_tpb_tx0_hi_thresh_i[12:0]" + */ + +/* register address for bitfield tx{b}_hi_thresh[c:0] */ +#define HW_ATL_TPB_TXBHI_THRESH_ADR(buffer) (0x00007914 + (buffer) * 0x10) +/* bitmask for bitfield tx{b}_hi_thresh[c:0] */ +#define HW_ATL_TPB_TXBHI_THRESH_MSK 0x1fff0000 +/* inverted bitmask for bitfield tx{b}_hi_thresh[c:0] */ +#define HW_ATL_TPB_TXBHI_THRESH_MSKN 0xe000ffff +/* lower bit position of bitfield tx{b}_hi_thresh[c:0] */ +#define HW_ATL_TPB_TXBHI_THRESH_SHIFT 16 +/* width of bitfield tx{b}_hi_thresh[c:0] */ +#define HW_ATL_TPB_TXBHI_THRESH_WIDTH 13 +/* default value of bitfield tx{b}_hi_thresh[c:0] */ +#define HW_ATL_TPB_TXBHI_THRESH_DEFAULT 0x0 + +/* tx tx{b}_lo_thresh[c:0] bitfield definitions + * preprocessor definitions for the bitfield "tx{b}_lo_thresh[c:0]". + * parameter: buffer {b} | stride size 0x10 | range [0, 7] + * port="pif_tpb_tx0_lo_thresh_i[12:0]" + */ + +/* register address for bitfield tx{b}_lo_thresh[c:0] */ +#define HW_ATL_TPB_TXBLO_THRESH_ADR(buffer) (0x00007914 + (buffer) * 0x10) +/* bitmask for bitfield tx{b}_lo_thresh[c:0] */ +#define HW_ATL_TPB_TXBLO_THRESH_MSK 0x00001fff +/* inverted bitmask for bitfield tx{b}_lo_thresh[c:0] */ +#define HW_ATL_TPB_TXBLO_THRESH_MSKN 0xffffe000 +/* lower bit position of bitfield tx{b}_lo_thresh[c:0] */ +#define HW_ATL_TPB_TXBLO_THRESH_SHIFT 0 +/* width of bitfield tx{b}_lo_thresh[c:0] */ +#define HW_ATL_TPB_TXBLO_THRESH_WIDTH 13 +/* default value of bitfield tx{b}_lo_thresh[c:0] */ +#define HW_ATL_TPB_TXBLO_THRESH_DEFAULT 0x0 + +/* tx dma_sys_loopback bitfield definitions + * preprocessor definitions for the bitfield "dma_sys_loopback". + * port="pif_tpb_dma_sys_lbk_i" + */ + +/* register address for bitfield dma_sys_loopback */ +#define HW_ATL_TPB_DMA_SYS_LBK_ADR 0x00007000 +/* bitmask for bitfield dma_sys_loopback */ +#define HW_ATL_TPB_DMA_SYS_LBK_MSK 0x00000040 +/* inverted bitmask for bitfield dma_sys_loopback */ +#define HW_ATL_TPB_DMA_SYS_LBK_MSKN 0xffffffbf +/* lower bit position of bitfield dma_sys_loopback */ +#define HW_ATL_TPB_DMA_SYS_LBK_SHIFT 6 +/* width of bitfield dma_sys_loopback */ +#define HW_ATL_TPB_DMA_SYS_LBK_WIDTH 1 +/* default value of bitfield dma_sys_loopback */ +#define HW_ATL_TPB_DMA_SYS_LBK_DEFAULT 0x0 + +/* tx tx{b}_buf_size[7:0] bitfield definitions + * preprocessor definitions for the bitfield "tx{b}_buf_size[7:0]". + * parameter: buffer {b} | stride size 0x10 | range [0, 7] + * port="pif_tpb_tx0_buf_size_i[7:0]" + */ + +/* register address for bitfield tx{b}_buf_size[7:0] */ +#define HW_ATL_TPB_TXBBUF_SIZE_ADR(buffer) (0x00007910 + (buffer) * 0x10) +/* bitmask for bitfield tx{b}_buf_size[7:0] */ +#define HW_ATL_TPB_TXBBUF_SIZE_MSK 0x000000ff +/* inverted bitmask for bitfield tx{b}_buf_size[7:0] */ +#define HW_ATL_TPB_TXBBUF_SIZE_MSKN 0xffffff00 +/* lower bit position of bitfield tx{b}_buf_size[7:0] */ +#define HW_ATL_TPB_TXBBUF_SIZE_SHIFT 0 +/* width of bitfield tx{b}_buf_size[7:0] */ +#define HW_ATL_TPB_TXBBUF_SIZE_WIDTH 8 +/* default value of bitfield tx{b}_buf_size[7:0] */ +#define HW_ATL_TPB_TXBBUF_SIZE_DEFAULT 0x0 + +/* tx tx_scp_ins_en bitfield definitions + * preprocessor definitions for the bitfield "tx_scp_ins_en". + * port="pif_tpb_scp_ins_en_i" + */ + +/* register address for bitfield tx_scp_ins_en */ +#define HW_ATL_TPB_TX_SCP_INS_EN_ADR 0x00007900 +/* bitmask for bitfield tx_scp_ins_en */ +#define HW_ATL_TPB_TX_SCP_INS_EN_MSK 0x00000004 +/* inverted bitmask for bitfield tx_scp_ins_en */ +#define HW_ATL_TPB_TX_SCP_INS_EN_MSKN 0xfffffffb +/* lower bit position of bitfield tx_scp_ins_en */ +#define HW_ATL_TPB_TX_SCP_INS_EN_SHIFT 2 +/* width of bitfield tx_scp_ins_en */ +#define HW_ATL_TPB_TX_SCP_INS_EN_WIDTH 1 +/* default value of bitfield tx_scp_ins_en */ +#define HW_ATL_TPB_TX_SCP_INS_EN_DEFAULT 0x0 + +/* tx ipv4_chk_en bitfield definitions + * preprocessor definitions for the bitfield "ipv4_chk_en". + * port="pif_tpo_ipv4_chk_en_i" + */ + +/* register address for bitfield ipv4_chk_en */ +#define HW_ATL_TPO_IPV4CHK_EN_ADR 0x00007800 +/* bitmask for bitfield ipv4_chk_en */ +#define HW_ATL_TPO_IPV4CHK_EN_MSK 0x00000002 +/* inverted bitmask for bitfield ipv4_chk_en */ +#define HW_ATL_TPO_IPV4CHK_EN_MSKN 0xfffffffd +/* lower bit position of bitfield ipv4_chk_en */ +#define HW_ATL_TPO_IPV4CHK_EN_SHIFT 1 +/* width of bitfield ipv4_chk_en */ +#define HW_ATL_TPO_IPV4CHK_EN_WIDTH 1 +/* default value of bitfield ipv4_chk_en */ +#define HW_ATL_TPO_IPV4CHK_EN_DEFAULT 0x0 + +/* tx l4_chk_en bitfield definitions + * preprocessor definitions for the bitfield "l4_chk_en". + * port="pif_tpo_l4_chk_en_i" + */ + +/* register address for bitfield l4_chk_en */ +#define HW_ATL_TPOL4CHK_EN_ADR 0x00007800 +/* bitmask for bitfield l4_chk_en */ +#define HW_ATL_TPOL4CHK_EN_MSK 0x00000001 +/* inverted bitmask for bitfield l4_chk_en */ +#define HW_ATL_TPOL4CHK_EN_MSKN 0xfffffffe +/* lower bit position of bitfield l4_chk_en */ +#define HW_ATL_TPOL4CHK_EN_SHIFT 0 +/* width of bitfield l4_chk_en */ +#define HW_ATL_TPOL4CHK_EN_WIDTH 1 +/* default value of bitfield l4_chk_en */ +#define HW_ATL_TPOL4CHK_EN_DEFAULT 0x0 + +/* tx pkt_sys_loopback bitfield definitions + * preprocessor definitions for the bitfield "pkt_sys_loopback". + * port="pif_tpo_pkt_sys_lbk_i" + */ + +/* register address for bitfield pkt_sys_loopback */ +#define HW_ATL_TPO_PKT_SYS_LBK_ADR 0x00007000 +/* bitmask for bitfield pkt_sys_loopback */ +#define HW_ATL_TPO_PKT_SYS_LBK_MSK 0x00000080 +/* inverted bitmask for bitfield pkt_sys_loopback */ +#define HW_ATL_TPO_PKT_SYS_LBK_MSKN 0xffffff7f +/* lower bit position of bitfield pkt_sys_loopback */ +#define HW_ATL_TPO_PKT_SYS_LBK_SHIFT 7 +/* width of bitfield pkt_sys_loopback */ +#define HW_ATL_TPO_PKT_SYS_LBK_WIDTH 1 +/* default value of bitfield pkt_sys_loopback */ +#define HW_ATL_TPO_PKT_SYS_LBK_DEFAULT 0x0 + +/* tx data_tc_arb_mode bitfield definitions + * preprocessor definitions for the bitfield "data_tc_arb_mode". + * port="pif_tps_data_tc_arb_mode_i" + */ + +/* register address for bitfield data_tc_arb_mode */ +#define HW_ATL_TPS_DATA_TC_ARB_MODE_ADR 0x00007100 +/* bitmask for bitfield data_tc_arb_mode */ +#define HW_ATL_TPS_DATA_TC_ARB_MODE_MSK 0x00000001 +/* inverted bitmask for bitfield data_tc_arb_mode */ +#define HW_ATL_TPS_DATA_TC_ARB_MODE_MSKN 0xfffffffe +/* lower bit position of bitfield data_tc_arb_mode */ +#define HW_ATL_TPS_DATA_TC_ARB_MODE_SHIFT 0 +/* width of bitfield data_tc_arb_mode */ +#define HW_ATL_TPS_DATA_TC_ARB_MODE_WIDTH 1 +/* default value of bitfield data_tc_arb_mode */ +#define HW_ATL_TPS_DATA_TC_ARB_MODE_DEFAULT 0x0 + +/* tx desc_rate_ta_rst bitfield definitions + * preprocessor definitions for the bitfield "desc_rate_ta_rst". + * port="pif_tps_desc_rate_ta_rst_i" + */ + +/* register address for bitfield desc_rate_ta_rst */ +#define HW_ATL_TPS_DESC_RATE_TA_RST_ADR 0x00007310 +/* bitmask for bitfield desc_rate_ta_rst */ +#define HW_ATL_TPS_DESC_RATE_TA_RST_MSK 0x80000000 +/* inverted bitmask for bitfield desc_rate_ta_rst */ +#define HW_ATL_TPS_DESC_RATE_TA_RST_MSKN 0x7fffffff +/* lower bit position of bitfield desc_rate_ta_rst */ +#define HW_ATL_TPS_DESC_RATE_TA_RST_SHIFT 31 +/* width of bitfield desc_rate_ta_rst */ +#define HW_ATL_TPS_DESC_RATE_TA_RST_WIDTH 1 +/* default value of bitfield desc_rate_ta_rst */ +#define HW_ATL_TPS_DESC_RATE_TA_RST_DEFAULT 0x0 + +/* tx desc_rate_limit[a:0] bitfield definitions + * preprocessor definitions for the bitfield "desc_rate_limit[a:0]". + * port="pif_tps_desc_rate_lim_i[10:0]" + */ + +/* register address for bitfield desc_rate_limit[a:0] */ +#define HW_ATL_TPS_DESC_RATE_LIM_ADR 0x00007310 +/* bitmask for bitfield desc_rate_limit[a:0] */ +#define HW_ATL_TPS_DESC_RATE_LIM_MSK 0x000007ff +/* inverted bitmask for bitfield desc_rate_limit[a:0] */ +#define HW_ATL_TPS_DESC_RATE_LIM_MSKN 0xfffff800 +/* lower bit position of bitfield desc_rate_limit[a:0] */ +#define HW_ATL_TPS_DESC_RATE_LIM_SHIFT 0 +/* width of bitfield desc_rate_limit[a:0] */ +#define HW_ATL_TPS_DESC_RATE_LIM_WIDTH 11 +/* default value of bitfield desc_rate_limit[a:0] */ +#define HW_ATL_TPS_DESC_RATE_LIM_DEFAULT 0x0 + +/* tx desc_tc_arb_mode[1:0] bitfield definitions + * preprocessor definitions for the bitfield "desc_tc_arb_mode[1:0]". + * port="pif_tps_desc_tc_arb_mode_i[1:0]" + */ + +/* register address for bitfield desc_tc_arb_mode[1:0] */ +#define HW_ATL_TPS_DESC_TC_ARB_MODE_ADR 0x00007200 +/* bitmask for bitfield desc_tc_arb_mode[1:0] */ +#define HW_ATL_TPS_DESC_TC_ARB_MODE_MSK 0x00000003 +/* inverted bitmask for bitfield desc_tc_arb_mode[1:0] */ +#define HW_ATL_TPS_DESC_TC_ARB_MODE_MSKN 0xfffffffc +/* lower bit position of bitfield desc_tc_arb_mode[1:0] */ +#define HW_ATL_TPS_DESC_TC_ARB_MODE_SHIFT 0 +/* width of bitfield desc_tc_arb_mode[1:0] */ +#define HW_ATL_TPS_DESC_TC_ARB_MODE_WIDTH 2 +/* default value of bitfield desc_tc_arb_mode[1:0] */ +#define HW_ATL_TPS_DESC_TC_ARB_MODE_DEFAULT 0x0 + +/* tx desc_tc{t}_credit_max[b:0] bitfield definitions + * preprocessor definitions for the bitfield "desc_tc{t}_credit_max[b:0]". + * parameter: tc {t} | stride size 0x4 | range [0, 7] + * port="pif_tps_desc_tc0_credit_max_i[11:0]" + */ + +/* register address for bitfield desc_tc{t}_credit_max[b:0] */ +#define HW_ATL_TPS_DESC_TCTCREDIT_MAX_ADR(tc) (0x00007210 + (tc) * 0x4) +/* bitmask for bitfield desc_tc{t}_credit_max[b:0] */ +#define HW_ATL_TPS_DESC_TCTCREDIT_MAX_MSK 0x0fff0000 +/* inverted bitmask for bitfield desc_tc{t}_credit_max[b:0] */ +#define HW_ATL_TPS_DESC_TCTCREDIT_MAX_MSKN 0xf000ffff +/* lower bit position of bitfield desc_tc{t}_credit_max[b:0] */ +#define HW_ATL_TPS_DESC_TCTCREDIT_MAX_SHIFT 16 +/* width of bitfield desc_tc{t}_credit_max[b:0] */ +#define HW_ATL_TPS_DESC_TCTCREDIT_MAX_WIDTH 12 +/* default value of bitfield desc_tc{t}_credit_max[b:0] */ +#define HW_ATL_TPS_DESC_TCTCREDIT_MAX_DEFAULT 0x0 + +/* tx desc_tc{t}_weight[8:0] bitfield definitions + * preprocessor definitions for the bitfield "desc_tc{t}_weight[8:0]". + * parameter: tc {t} | stride size 0x4 | range [0, 7] + * port="pif_tps_desc_tc0_weight_i[8:0]" + */ + +/* register address for bitfield desc_tc{t}_weight[8:0] */ +#define HW_ATL_TPS_DESC_TCTWEIGHT_ADR(tc) (0x00007210 + (tc) * 0x4) +/* bitmask for bitfield desc_tc{t}_weight[8:0] */ +#define HW_ATL_TPS_DESC_TCTWEIGHT_MSK 0x000001ff +/* inverted bitmask for bitfield desc_tc{t}_weight[8:0] */ +#define HW_ATL_TPS_DESC_TCTWEIGHT_MSKN 0xfffffe00 +/* lower bit position of bitfield desc_tc{t}_weight[8:0] */ +#define HW_ATL_TPS_DESC_TCTWEIGHT_SHIFT 0 +/* width of bitfield desc_tc{t}_weight[8:0] */ +#define HW_ATL_TPS_DESC_TCTWEIGHT_WIDTH 9 +/* default value of bitfield desc_tc{t}_weight[8:0] */ +#define HW_ATL_TPS_DESC_TCTWEIGHT_DEFAULT 0x0 + +/* tx desc_vm_arb_mode bitfield definitions + * preprocessor definitions for the bitfield "desc_vm_arb_mode". + * port="pif_tps_desc_vm_arb_mode_i" + */ + +/* register address for bitfield desc_vm_arb_mode */ +#define HW_ATL_TPS_DESC_VM_ARB_MODE_ADR 0x00007300 +/* bitmask for bitfield desc_vm_arb_mode */ +#define HW_ATL_TPS_DESC_VM_ARB_MODE_MSK 0x00000001 +/* inverted bitmask for bitfield desc_vm_arb_mode */ +#define HW_ATL_TPS_DESC_VM_ARB_MODE_MSKN 0xfffffffe +/* lower bit position of bitfield desc_vm_arb_mode */ +#define HW_ATL_TPS_DESC_VM_ARB_MODE_SHIFT 0 +/* width of bitfield desc_vm_arb_mode */ +#define HW_ATL_TPS_DESC_VM_ARB_MODE_WIDTH 1 +/* default value of bitfield desc_vm_arb_mode */ +#define HW_ATL_TPS_DESC_VM_ARB_MODE_DEFAULT 0x0 + +/* tx data_tc{t}_credit_max[b:0] bitfield definitions + * preprocessor definitions for the bitfield "data_tc{t}_credit_max[b:0]". + * parameter: tc {t} | stride size 0x4 | range [0, 7] + * port="pif_tps_data_tc0_credit_max_i[11:0]" + */ + +/* register address for bitfield data_tc{t}_credit_max[b:0] */ +#define HW_ATL_TPS_DATA_TCTCREDIT_MAX_ADR(tc) (0x00007110 + (tc) * 0x4) +/* bitmask for bitfield data_tc{t}_credit_max[b:0] */ +#define HW_ATL_TPS_DATA_TCTCREDIT_MAX_MSK 0x0fff0000 +/* inverted bitmask for bitfield data_tc{t}_credit_max[b:0] */ +#define HW_ATL_TPS_DATA_TCTCREDIT_MAX_MSKN 0xf000ffff +/* lower bit position of bitfield data_tc{t}_credit_max[b:0] */ +#define HW_ATL_TPS_DATA_TCTCREDIT_MAX_SHIFT 16 +/* width of bitfield data_tc{t}_credit_max[b:0] */ +#define HW_ATL_TPS_DATA_TCTCREDIT_MAX_WIDTH 12 +/* default value of bitfield data_tc{t}_credit_max[b:0] */ +#define HW_ATL_TPS_DATA_TCTCREDIT_MAX_DEFAULT 0x0 + +/* tx data_tc{t}_weight[8:0] bitfield definitions + * preprocessor definitions for the bitfield "data_tc{t}_weight[8:0]". + * parameter: tc {t} | stride size 0x4 | range [0, 7] + * port="pif_tps_data_tc0_weight_i[8:0]" + */ + +/* register address for bitfield data_tc{t}_weight[8:0] */ +#define HW_ATL_TPS_DATA_TCTWEIGHT_ADR(tc) (0x00007110 + (tc) * 0x4) +/* bitmask for bitfield data_tc{t}_weight[8:0] */ +#define HW_ATL_TPS_DATA_TCTWEIGHT_MSK 0x000001ff +/* inverted bitmask for bitfield data_tc{t}_weight[8:0] */ +#define HW_ATL_TPS_DATA_TCTWEIGHT_MSKN 0xfffffe00 +/* lower bit position of bitfield data_tc{t}_weight[8:0] */ +#define HW_ATL_TPS_DATA_TCTWEIGHT_SHIFT 0 +/* width of bitfield data_tc{t}_weight[8:0] */ +#define HW_ATL_TPS_DATA_TCTWEIGHT_WIDTH 9 +/* default value of bitfield data_tc{t}_weight[8:0] */ +#define HW_ATL_TPS_DATA_TCTWEIGHT_DEFAULT 0x0 + +/* tx reg_res_dsbl bitfield definitions + * preprocessor definitions for the bitfield "reg_res_dsbl". + * port="pif_tx_reg_res_dsbl_i" + */ + +/* register address for bitfield reg_res_dsbl */ +#define HW_ATL_TX_REG_RES_DSBL_ADR 0x00007000 +/* bitmask for bitfield reg_res_dsbl */ +#define HW_ATL_TX_REG_RES_DSBL_MSK 0x20000000 +/* inverted bitmask for bitfield reg_res_dsbl */ +#define HW_ATL_TX_REG_RES_DSBL_MSKN 0xdfffffff +/* lower bit position of bitfield reg_res_dsbl */ +#define HW_ATL_TX_REG_RES_DSBL_SHIFT 29 +/* width of bitfield reg_res_dsbl */ +#define HW_ATL_TX_REG_RES_DSBL_WIDTH 1 +/* default value of bitfield reg_res_dsbl */ +#define HW_ATL_TX_REG_RES_DSBL_DEFAULT 0x1 + +/* mac_phy register access busy bitfield definitions + * preprocessor definitions for the bitfield "register access busy". + * port="msm_pif_reg_busy_o" + */ + +/* register address for bitfield register access busy */ +#define HW_ATL_MSM_REG_ACCESS_BUSY_ADR 0x00004400 +/* bitmask for bitfield register access busy */ +#define HW_ATL_MSM_REG_ACCESS_BUSY_MSK 0x00001000 +/* inverted bitmask for bitfield register access busy */ +#define HW_ATL_MSM_REG_ACCESS_BUSY_MSKN 0xffffefff +/* lower bit position of bitfield register access busy */ +#define HW_ATL_MSM_REG_ACCESS_BUSY_SHIFT 12 +/* width of bitfield register access busy */ +#define HW_ATL_MSM_REG_ACCESS_BUSY_WIDTH 1 + +/* mac_phy msm register address[7:0] bitfield definitions + * preprocessor definitions for the bitfield "msm register address[7:0]". + * port="pif_msm_reg_addr_i[7:0]" + */ + +/* register address for bitfield msm register address[7:0] */ +#define HW_ATL_MSM_REG_ADDR_ADR 0x00004400 +/* bitmask for bitfield msm register address[7:0] */ +#define HW_ATL_MSM_REG_ADDR_MSK 0x000000ff +/* inverted bitmask for bitfield msm register address[7:0] */ +#define HW_ATL_MSM_REG_ADDR_MSKN 0xffffff00 +/* lower bit position of bitfield msm register address[7:0] */ +#define HW_ATL_MSM_REG_ADDR_SHIFT 0 +/* width of bitfield msm register address[7:0] */ +#define HW_ATL_MSM_REG_ADDR_WIDTH 8 +/* default value of bitfield msm register address[7:0] */ +#define HW_ATL_MSM_REG_ADDR_DEFAULT 0x0 + +/* mac_phy register read strobe bitfield definitions + * preprocessor definitions for the bitfield "register read strobe". + * port="pif_msm_reg_rden_i" + */ + +/* register address for bitfield register read strobe */ +#define HW_ATL_MSM_REG_RD_STROBE_ADR 0x00004400 +/* bitmask for bitfield register read strobe */ +#define HW_ATL_MSM_REG_RD_STROBE_MSK 0x00000200 +/* inverted bitmask for bitfield register read strobe */ +#define HW_ATL_MSM_REG_RD_STROBE_MSKN 0xfffffdff +/* lower bit position of bitfield register read strobe */ +#define HW_ATL_MSM_REG_RD_STROBE_SHIFT 9 +/* width of bitfield register read strobe */ +#define HW_ATL_MSM_REG_RD_STROBE_WIDTH 1 +/* default value of bitfield register read strobe */ +#define HW_ATL_MSM_REG_RD_STROBE_DEFAULT 0x0 + +/* mac_phy msm register read data[31:0] bitfield definitions + * preprocessor definitions for the bitfield "msm register read data[31:0]". + * port="msm_pif_reg_rd_data_o[31:0]" + */ + +/* register address for bitfield msm register read data[31:0] */ +#define HW_ATL_MSM_REG_RD_DATA_ADR 0x00004408 +/* bitmask for bitfield msm register read data[31:0] */ +#define HW_ATL_MSM_REG_RD_DATA_MSK 0xffffffff +/* inverted bitmask for bitfield msm register read data[31:0] */ +#define HW_ATL_MSM_REG_RD_DATA_MSKN 0x00000000 +/* lower bit position of bitfield msm register read data[31:0] */ +#define HW_ATL_MSM_REG_RD_DATA_SHIFT 0 +/* width of bitfield msm register read data[31:0] */ +#define HW_ATL_MSM_REG_RD_DATA_WIDTH 32 + +/* mac_phy msm register write data[31:0] bitfield definitions + * preprocessor definitions for the bitfield "msm register write data[31:0]". + * port="pif_msm_reg_wr_data_i[31:0]" + */ + +/* register address for bitfield msm register write data[31:0] */ +#define HW_ATL_MSM_REG_WR_DATA_ADR 0x00004404 +/* bitmask for bitfield msm register write data[31:0] */ +#define HW_ATL_MSM_REG_WR_DATA_MSK 0xffffffff +/* inverted bitmask for bitfield msm register write data[31:0] */ +#define HW_ATL_MSM_REG_WR_DATA_MSKN 0x00000000 +/* lower bit position of bitfield msm register write data[31:0] */ +#define HW_ATL_MSM_REG_WR_DATA_SHIFT 0 +/* width of bitfield msm register write data[31:0] */ +#define HW_ATL_MSM_REG_WR_DATA_WIDTH 32 +/* default value of bitfield msm register write data[31:0] */ +#define HW_ATL_MSM_REG_WR_DATA_DEFAULT 0x0 + +/* mac_phy register write strobe bitfield definitions + * preprocessor definitions for the bitfield "register write strobe". + * port="pif_msm_reg_wren_i" + */ + +/* register address for bitfield register write strobe */ +#define HW_ATL_MSM_REG_WR_STROBE_ADR 0x00004400 +/* bitmask for bitfield register write strobe */ +#define HW_ATL_MSM_REG_WR_STROBE_MSK 0x00000100 +/* inverted bitmask for bitfield register write strobe */ +#define HW_ATL_MSM_REG_WR_STROBE_MSKN 0xfffffeff +/* lower bit position of bitfield register write strobe */ +#define HW_ATL_MSM_REG_WR_STROBE_SHIFT 8 +/* width of bitfield register write strobe */ +#define HW_ATL_MSM_REG_WR_STROBE_WIDTH 1 +/* default value of bitfield register write strobe */ +#define HW_ATL_MSM_REG_WR_STROBE_DEFAULT 0x0 + +/* mif soft reset bitfield definitions + * preprocessor definitions for the bitfield "soft reset". + * port="pif_glb_res_i" + */ + +/* register address for bitfield soft reset */ +#define HW_ATL_GLB_SOFT_RES_ADR 0x00000000 +/* bitmask for bitfield soft reset */ +#define HW_ATL_GLB_SOFT_RES_MSK 0x00008000 +/* inverted bitmask for bitfield soft reset */ +#define HW_ATL_GLB_SOFT_RES_MSKN 0xffff7fff +/* lower bit position of bitfield soft reset */ +#define HW_ATL_GLB_SOFT_RES_SHIFT 15 +/* width of bitfield soft reset */ +#define HW_ATL_GLB_SOFT_RES_WIDTH 1 +/* default value of bitfield soft reset */ +#define HW_ATL_GLB_SOFT_RES_DEFAULT 0x0 + +/* mif register reset disable bitfield definitions + * preprocessor definitions for the bitfield "register reset disable". + * port="pif_glb_reg_res_dsbl_i" + */ + +/* register address for bitfield register reset disable */ +#define HW_ATL_GLB_REG_RES_DIS_ADR 0x00000000 +/* bitmask for bitfield register reset disable */ +#define HW_ATL_GLB_REG_RES_DIS_MSK 0x00004000 +/* inverted bitmask for bitfield register reset disable */ +#define HW_ATL_GLB_REG_RES_DIS_MSKN 0xffffbfff +/* lower bit position of bitfield register reset disable */ +#define HW_ATL_GLB_REG_RES_DIS_SHIFT 14 +/* width of bitfield register reset disable */ +#define HW_ATL_GLB_REG_RES_DIS_WIDTH 1 +/* default value of bitfield register reset disable */ +#define HW_ATL_GLB_REG_RES_DIS_DEFAULT 0x1 + +/* tx dma debug control definitions */ +#define HW_ATL_TX_DMA_DEBUG_CTL_ADR 0x00008920u + +/* tx dma descriptor base address msw definitions */ +#define HW_ATL_TX_DMA_DESC_BASE_ADDRMSW_ADR(descriptor) \ + (0x00007c04u + (descriptor) * 0x40) + +/* tx dma total request limit */ +#define HW_ATL_TX_DMA_TOTAL_REQ_LIMIT_ADR 0x00007b20u + +/* tx interrupt moderation control register definitions + * Preprocessor definitions for TX Interrupt Moderation Control Register + * Base Address: 0x00008980 + * Parameter: queue {Q} | stride size 0x4 | range [0, 31] + */ + +#define HW_ATL_TX_INTR_MODERATION_CTL_ADR(queue) (0x00008980u + (queue) * 0x4) + +/* pcie reg_res_dsbl bitfield definitions + * preprocessor definitions for the bitfield "reg_res_dsbl". + * port="pif_pci_reg_res_dsbl_i" + */ + +/* register address for bitfield reg_res_dsbl */ +#define HW_ATL_PCI_REG_RES_DSBL_ADR 0x00001000 +/* bitmask for bitfield reg_res_dsbl */ +#define HW_ATL_PCI_REG_RES_DSBL_MSK 0x20000000 +/* inverted bitmask for bitfield reg_res_dsbl */ +#define HW_ATL_PCI_REG_RES_DSBL_MSKN 0xdfffffff +/* lower bit position of bitfield reg_res_dsbl */ +#define HW_ATL_PCI_REG_RES_DSBL_SHIFT 29 +/* width of bitfield reg_res_dsbl */ +#define HW_ATL_PCI_REG_RES_DSBL_WIDTH 1 +/* default value of bitfield reg_res_dsbl */ +#define HW_ATL_PCI_REG_RES_DSBL_DEFAULT 0x1 + +/* PCI core control register */ +#define HW_ATL_PCI_REG_CONTROL6_ADR 0x1014u + +/* global microprocessor scratch pad definitions */ +#define HW_ATL_GLB_CPU_SCRATCH_SCP_ADR(scratch_scp) \ + (0x00000300u + (scratch_scp) * 0x4) + +/* register address for bitfield uP Force Interrupt */ +#define mcp_up_force_interrupt_adr 0x00000404 +/* bitmask for bitfield uP Force Interrupt */ +#define mcp_up_force_interrupt_msk 0x00000002 +/* inverted bitmask for bitfield uP Force Interrupt */ +#define mcp_up_force_interrupt_mskn 0xFFFFFFFD +/* lower bit position of bitfield uP Force Interrupt */ +#define mcp_up_force_interrupt_shift 1 +/* width of bitfield uP Force Interrupt */ +#define mcp_up_force_interrupt_width 1 +/* default value of bitfield uP Force Interrupt */ +#define mcp_up_force_interrupt_default 0x0 + +#endif /* HW_ATL_LLH_INTERNAL_H */ diff --git a/drivers/net/atlantic/meson.build b/drivers/net/atlantic/meson.build index 7fdde358ba21..f3193b75b650 100644 --- a/drivers/net/atlantic/meson.build +++ b/drivers/net/atlantic/meson.build @@ -1,9 +1,12 @@ # SPDX-License-Identifier: BSD-3-Clause # Copyright(c) 2018 Aquantia Corporation +#subdir('hw_atl') + sources = files( 'atl_ethdev.c', 'atl_hw_regs.c', + 'hw_atl/hw_atl_llh.c', ) deps += ['eal'] From patchwork Sat Sep 29 10:30:19 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Russkikh X-Patchwork-Id: 45669 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 73A731B174; Sat, 29 Sep 2018 12:31:33 +0200 (CEST) Received: from NAM05-DM3-obe.outbound.protection.outlook.com (mail-eopbgr730053.outbound.protection.outlook.com [40.107.73.53]) by dpdk.org (Postfix) with ESMTP id D9C061B174 for ; Sat, 29 Sep 2018 12:31:31 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=AQUANTIA1COM.onmicrosoft.com; s=selector1-aquantia-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=AIFKhUMaY/aiROwNGejy76Hqjjwr1XWCssBE+8FCI6g=; b=uBj1UQwQ6MMr0PzqEItzCyVJAMZbEj7nCCvEunAx9Sx2+99iKLOu14yAT7TrO0RaBYx+0FMXSP5mYKyPNp6Xa0Wn5Tz+0SOMBjgju8pWhPPF97t4BIBPAk60tlzmWStmeLcd7KXgqSggfpVSlY8YV4EJECCdASRWsdfq/PYrIFs= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Igor.Russkikh@aquantia.com; Received: from ubuntubox.rdc.aquantia.com (95.79.108.179) by BLUPR0701MB1650.namprd07.prod.outlook.com (2a01:111:e400:58c6::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1185.22; Sat, 29 Sep 2018 10:31:23 +0000 From: Igor Russkikh To: dev@dpdk.org Cc: pavel.belous@aquantia.com, igor.russkikh@aquantia.com, Pavel Belous Date: Sat, 29 Sep 2018 13:30:19 +0300 Message-Id: X-Mailer: git-send-email 2.7.4 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [95.79.108.179] X-ClientProxiedBy: VI1P193CA0009.EURP193.PROD.OUTLOOK.COM (2603:10a6:800:bd::19) To BLUPR0701MB1650.namprd07.prod.outlook.com (2a01:111:e400:58c6::20) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 2666d1c7-0046-4878-069c-08d625f6b7ca X-Microsoft-Antispam: BCL:0; PCL:0; RULEID:(7020095)(4652040)(8989299)(4534165)(4627221)(201703031133081)(201702281549075)(8990200)(5600074)(711020)(2017052603328)(7153060)(7193020); SRVR:BLUPR0701MB1650; X-Microsoft-Exchange-Diagnostics: 1; BLUPR0701MB1650; 3:Rz1sV/hbbDw6kyHFat2M9tv76oubenLhlmQhJwA4N6YEdIbvt3Q4w8zOK7K/ibaXocsrGhc5LhfyyAGZ3yVxifCNmi34Wpy+deQ6K5uTy+Jc0dMAGcndd6VZM5IwNpKbJ4zGo4rYZo6sEz09GiLLfbUIuWmw3AYq10/06n8Ojy2V4vbFLbJ1cis33+FItfzGe4Xd/3dk5JAdRanUkemJgxE+wI84wV11I0hGoF8UcEe8qiyibwxnHAMsav+fwU+e; 25:bMwKFBnA6UAPjqeIBURtQXRb0xeR/EUHvKLuHxP+c36jyW7gn9ZArg0XFqGDS1qOKjSzlhN/QzufkjQW0nam2KZfygLhHMni3itz55lhcVHpjydmx0Ha1OJEwVTNk2MdaAMyLof3YSw/c5sACW9nUS8aeC6NSBNeoAw13zPg2Epllpiu5gYScyP5TWGUDFxM4e4rP1lZx9dkK+OboW5+ir4a8uc5KyAupv6jmDPAf5eH3YNqy0RouZA3PQnczADooRaX9ZDAtdHDLTIdTrEyyeXWOC8mBqBHolKVvsYigHToPfAnceTw5hRMm78ZuXarIdNgLsx3PGNv9sO58K7WDSE3ftC7ohXvFq3wwS1AFsA=; 31:uHC1sgFndeGPMliEY4eltqsGwX1wS1gNxpzD9546+mNdJxwRJJdiWcGVmphm5Ana+3tMHmHYcOlnNT13UkQSKLGXr5UXy3brVIa2FdjzckMW4673NnOZjNUBl1hfA0qspXnQg+Cnr2f+I71ujuzDcMZamKlpsLdz749OmyF/eRr4r27b1p6mPLdPl7EWBt9+/HkQnAO5L+LgkmY9wMu8qtmr8ciO/FlgFykqABRWTg8= X-MS-TrafficTypeDiagnostic: BLUPR0701MB1650: X-Microsoft-Exchange-Diagnostics: 1; BLUPR0701MB1650; 20:o/NrJA9fzfIWzupYGTr3pR3cgCsZuBWyFBUZNKzUclLoFRlaaqetd3f2mQS8saQnSB8Fb/sxL9IVf6j/9WXeujpqqKNlRdU/KwrrsoA6bk6kidd2W8GGq8URT0/uoCDwzgfSfX/VuJs/yXuAg1jIq5vvNGoBVexa5rJVXq2gEwHcl5f8RP6xVI1HUQa+bGo5lSM/Zrvr4uO358sRI7aB6IrVOkHgJTcKlu/ow6WlHUvV2Osnrj0XPwJiCGvMFL3NAPdHjeCz0ff4UZn1v6ZTPX2wBMGGP1yOrErxeLbxOC6vyPrOaDRUvhB16Q9U7m97QkffdtLPxdWXpH9ks7UdLcbW0Op6RpDZyzMLof+NnXw/89zqpnNfKRkOAASa9r5Bc8QhWcn3a2fDamjIZKR2ee3Yjx85OPqQCWYsN+bB2Ly2DH6Tg9a/MwL9QSci1Nh8Y0mV27EEIAO72TFI6MP47MOUi8vJ9IaKHag5FQCFj1VNfHfhQPIMr+jvvoEk2nF/; 4:kLobn8CbSKuX0PrDFx9cSrmDtsC4YoDfpC5NDiYdAwJzXi6vrRjuGPtaUmyseFMcQYJE//dH0bMBsIWxIh172gLR3oTVfmmUyWXPOu60lN4eJgjBjh7IQaBrAbHL8f1az0A6g4MzYgHFsNlIZUgIvEj0zhyIbPqB5FsWcu3rhjgfUKlQONCGST2OIiaMbizwE3dsG8PHb+QYZnLZAdE7lOG/J1yubuMOc5Enziv29usTGuY7rgVRuLsBid0OGwdCwLrIP6hSGkrp8zSZoyIDKQ== X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-MS-Exchange-SenderADCheck: 1 X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(6040522)(2401047)(8121501046)(5005006)(10201501046)(3002001)(93006095)(93001095)(3231355)(944501410)(52105095)(149066)(150057)(6041310)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123558120)(20161123564045)(20161123562045)(20161123560045)(201708071742011)(7699051); SRVR:BLUPR0701MB1650; BCL:0; PCL:0; RULEID:; SRVR:BLUPR0701MB1650; X-Forefront-PRVS: 0810818DA0 X-Forefront-Antispam-Report: SFV:NSPM; SFS:(10009020)(346002)(136003)(396003)(376002)(39850400004)(366004)(189003)(199004)(16526019)(14444005)(446003)(76176011)(2906002)(6916009)(6666003)(97736004)(8676002)(81166006)(81156014)(36756003)(4326008)(316002)(8936002)(50226002)(34290500001)(575784001)(86362001)(5660300001)(68736007)(16586007)(118296001)(53946003)(72206003)(3846002)(6116002)(53936002)(386003)(105586002)(6486002)(47776003)(66066001)(486006)(25786009)(305945005)(50466002)(44832011)(956004)(2616005)(26005)(107886003)(52116002)(51416003)(7696005)(186003)(476003)(478600001)(2361001)(551934003)(7736002)(2351001)(48376002)(106356001)(11346002)(559001)(579004); DIR:OUT; SFP:1101; SCL:1; SRVR:BLUPR0701MB1650; H:ubuntubox.rdc.aquantia.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; Received-SPF: None (protection.outlook.com: aquantia.com does not designate permitted sender hosts) X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; BLUPR0701MB1650; 23:gEPqaV8dMoahjqqC+iDbQpZR1+xw50HRghmXMGs?= bmWOi8Uo5OcAqME1hBOI3ufW4aEIuthypdcwv/o8SDjc/eWkWBol0edqARjCf04Pu1dCORT8+2jMhcn8n5hNvmbVZVrfxLrKXUF/6o0OFWK78vClNNzKkX9x7OTXS8/TWbwC4RcDNwp6zwbobkC1D87Y6jE0smUPUIbgIPAUzoS07vRJh6vFtTCaymx5QFHSkaMYrioJ5wkKpHl56Y/Y9cZ7d8Xp3Uj2BzoYtcmvI7VK7cPg1nuZDIfFCSKmZhHT2u9p7i9yRwd6IaMn/i47nvQovYC6+Z7XhRkyB94mdcl0tfPkLzbY8wma86ha3wesG41jwBO5pYSDY2SGfI+C753i+skNVg1HE/Xwav71vtklT6dRqdPvApSfS6k4AvoyDyDiQf9T4cC5xowfu/eeItUARTu4xbpep9/lNJF3UsU2LnzPjLEjHxKYEl9Ofhz3Moe/PkY1KSLeikoxY9j8plfDbcs0LxTyd7K0tbpSh/hVACy8gttcjdbf5fVvi8r+I0BDgFQbxuJdXWJRzqIDjSnYEU4HSpuhUDdjf5UvfnHuB3YVEuixBGEFBswAky3nXdaQLnazuCs9z9cg1dxoNz+XwkWSEl5AtSmOg01JRo8SnwX1rtoBjwezPSU4PA8JnQxCilfpw2CgCEZS0wl07ij3qMpvy8kGqyxdmmHU5QB24HXSaPxVlRPjPKR+VO5v1AibQiQinq4W9AQqlXOfPjlVqxITKzfwhUxijhkZ1cty3KELDwUehiOlI8gFvADwdARokVjgDf/fzEpVMXiGdm9J7BEsnCireaoveWdbgBuIO2OkymOTp86RYuuiIt7C9VexMEvOJPHekCpFvWIASu00IRunX+dem/mYiRArxkq+CGTuUD1InW73RE1uFLPtB5PvSkkgEZJ9JC035mrFA7lxV2OhYQuD1SqOTLEAXC5atNiY+fD4cG3MKO+1bjrQ6Dmy6mAn3IQQPvz14gvr0Za6uq29ywJ5VhyaE6XVXH+x3zUp5iLQDZsIC0Sl9bMAN1XYspZpCzd5ATxGSDE9jf7c94K1ljVVuz1ZGVxGUDQUFd6yBMD7+3VbYtAx3UUabI89osD+tJ9rgdhM/znwk3oGNGv9EgjbN3OZPBJzRSnsD7oVrI3sgVmPxvzuRDBZeQghoIc6VacotzCrvV2XFS/qeFyOSe8DBN6iGE1FtmhldOM8akwp5pkVoMjWYlbbOisbf5sXZusFf4yqrAbuNF3Xxts4Hi5IQc9iwkinU3PyBYBaXAiJ/7xFwhjww69jwTkDNb7okHwIq26RsoCirVsZxXBsRpuMzUu9NhHcdCDNFX4+pItW9vfgujZAwfnFd4dq0pZtWrl46cDFlH2wILBGljShD9Q/GRl/o0BUkgUr1BQ== X-Microsoft-Antispam-Message-Info: 3ETST+Y2pMk11jzJtClFD6EMa0X9YAmQ1NFl70UvrFsOoUWBBJenaZRk1E34DBEHg5O2Sfp9O2N9u5BxaPJ8L8HkA7MAzRd5eBSPsx1D98o91y9hCH0a79l79QkPdQFk21baR36gs+tGpdTWSdarN14IxOUuTJsE/w38Vz0Nmwy8nzW99ljAXrCirL287rEN6HiHM8ZXCQyHpeZQjYMHL3VA3NHqBrwzU9SwwBLuWZuCISDUEC2AAI203/KSaNPOQCp06bQS9MiuuWQ8cm9JO7T7VAgbh49awDwHdDR47oB8KhYHlcmLdOw1kHLPK7uY8l9rc9bQtLhjdXYQ11blIuKaEcPiKZjeZwbqKi5hSSQ= X-Microsoft-Exchange-Diagnostics: 1; BLUPR0701MB1650; 6:RIHgTD0vqlsd99S/sAAyIBp0xKm2bd1muZrfxfuO4jdBvBPsaiTHa7G3y0mwvvGSGsxcA0gxDMISHRvmpOycctar61LcoU9AC9LI0GrNOrUVXfA60FiqkaQ/H3TGYhHBIxosybjkn1Fb1/cSINm8drIVAEVA0WFS5tQa7CBKChGrfyRORlLzgpH1ePqU3T8egz9UdM3FavY5bUAxe3XZoBIKdb7EAXOQQ9TsyzVAGZItrljgoeNlmQbnBCmaFv1sweOwMHySoE320eBsQS6QYAFnc68eOBfeCKD1HLHBlkU3uL6+q6Vl0lx+x6WIFPMhYzfbUu1UAv+RpvXGhcXa4BIfUrLjGNlqb6anKVYuyf5nlEP1SKUCJrlBRqqMP+xSFAb5tTcXB/1MJAEjCsMey56PuzE48r3UrRxkN7bTNVl+gPLDyva/fUZYiFoXKfJE/+vFGzxocvhv5QzM9Ij4KA==; 5:+bUbOE72NdelubIhZG8lmkRwpHPYFVxcOuv3VnL9hnMLsiSdJ9hREojnj3zVMTvkS2ACof7B6Iv42zQvIg5JyMfjNraNgkKrG8S5Q/9SPyyfmQXA3co46mDsQ/7I7BpG1tnLIFRxF04y8zpET02342DwJDbN5HGmerFJAv2oUn8=; 7:nVdziHdufypQ6nWquVBtmcShxqwMyG2TXYFFyKc1wfM8RHb4CduE+J4l7wZDjkweX01es0/qYS73mulXkVP8cPGg9dn3AN3Mymq/Z2h1Cox8kRtLu8ufBwxb5Rwc82Mcv6BPzOR+6Dlgk9aCAzSl5Kn4txR2w0T4YNaNKqdWhF6wsAas9xYh1JtZrXjKZalqx7MUVqc/srjKoZp8Qe2BZMIV5d7vf2ihQC9EpLMItRkI5+8LUffOLp9g60iq8IMi SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: aquantia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Sep 2018 10:31:23.4685 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2666d1c7-0046-4878-069c-08d625f6b7ca X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 83e2e134-991c-4ede-8ced-34d47e38e6b1 X-MS-Exchange-Transport-CrossTenantHeadersStamped: BLUPR0701MB1650 Subject: [dpdk-dev] [PATCH v3 05/22] net/atlantic: firmware operations layer X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" AQC NICs comes in fields with two major FW generations: 1x and 3x. This is part of linux atlantic driver shared code, responsible for internal NIC firmware interactions, including link management ops, FW initialization, various lifecycle features. Signed-off-by: Igor Russkikh Signed-off-by: Pavel Belous --- drivers/net/atlantic/Makefile | 2 + drivers/net/atlantic/atl_types.h | 95 +++ drivers/net/atlantic/hw_atl/hw_atl_utils.c | 942 ++++++++++++++++++++++++ drivers/net/atlantic/hw_atl/hw_atl_utils.h | 510 +++++++++++++ drivers/net/atlantic/hw_atl/hw_atl_utils_fw2x.c | 618 ++++++++++++++++ drivers/net/atlantic/meson.build | 2 + 6 files changed, 2169 insertions(+) create mode 100644 drivers/net/atlantic/hw_atl/hw_atl_utils.c create mode 100644 drivers/net/atlantic/hw_atl/hw_atl_utils.h create mode 100644 drivers/net/atlantic/hw_atl/hw_atl_utils_fw2x.c diff --git a/drivers/net/atlantic/Makefile b/drivers/net/atlantic/Makefile index cae317badc0c..a291053b5ab7 100644 --- a/drivers/net/atlantic/Makefile +++ b/drivers/net/atlantic/Makefile @@ -26,6 +26,8 @@ VPATH += $(SRCDIR)/hw_atl # SRCS-$(CONFIG_RTE_LIBRTE_ATLANTIC_PMD) += atl_ethdev.c SRCS-$(CONFIG_RTE_LIBRTE_ATLANTIC_PMD) += atl_hw_regs.c +SRCS-$(CONFIG_RTE_LIBRTE_ATLANTIC_PMD) += hw_atl_utils.c SRCS-$(CONFIG_RTE_LIBRTE_ATLANTIC_PMD) += hw_atl_llh.c +SRCS-$(CONFIG_RTE_LIBRTE_ATLANTIC_PMD) += hw_atl_utils_fw2x.c include $(RTE_SDK)/mk/rte.lib.mk diff --git a/drivers/net/atlantic/atl_types.h b/drivers/net/atlantic/atl_types.h index 83fb377add47..589088a82227 100644 --- a/drivers/net/atlantic/atl_types.h +++ b/drivers/net/atlantic/atl_types.h @@ -28,8 +28,103 @@ typedef int bool; #define min(a, b) RTE_MIN(a, b) #define max(a, b) RTE_MAX(a, b) +#include "hw_atl/hw_atl_utils.h" + +struct aq_hw_link_status_s { + unsigned int mbps; +}; + +struct aq_stats_s { + u64 uprc; + u64 mprc; + u64 bprc; + u64 erpt; + u64 uptc; + u64 mptc; + u64 bptc; + u64 erpr; + u64 mbtc; + u64 bbtc; + u64 mbrc; + u64 bbrc; + u64 ubrc; + u64 ubtc; + u64 dpc; + u64 dma_pkt_rc; + u64 dma_pkt_tc; + u64 dma_oct_rc; + u64 dma_oct_tc; +}; + +struct aq_hw_cfg_s { + bool is_lro; + int wol; + + int link_speed_msk; + int irq_type; + int irq_mask; + unsigned int vecs; + + uint32_t flow_control; +}; + struct aq_hw_s { + u8 rbl_enabled:1; + struct aq_hw_cfg_s *aq_nic_cfg; + const struct aq_fw_ops *aq_fw_ops; void *mmio; + + struct aq_hw_link_status_s aq_link_status; + + struct hw_aq_atl_utils_mbox mbox; + struct hw_atl_stats_s last_stats; + struct aq_stats_s curr_stats; + + unsigned int chip_features; + u32 fw_ver_actual; + u32 mbox_addr; + u32 rpc_addr; + u32 rpc_tid; + struct hw_aq_atl_utils_fw_rpc rpc; +}; + +struct aq_fw_ops { + int (*init)(struct aq_hw_s *self); + + int (*deinit)(struct aq_hw_s *self); + + int (*reset)(struct aq_hw_s *self); + + int (*get_mac_permanent)(struct aq_hw_s *self, u8 *mac); + + int (*set_link_speed)(struct aq_hw_s *self, u32 speed); + + int (*set_state)(struct aq_hw_s *self, + enum hal_atl_utils_fw_state_e state); + + int (*update_link_status)(struct aq_hw_s *self); + + int (*update_stats)(struct aq_hw_s *self); + + int (*set_power)(struct aq_hw_s *self, unsigned int power_state, + u8 *mac); + + int (*get_temp)(struct aq_hw_s *self, int *temp); + + int (*get_cable_len)(struct aq_hw_s *self, int *cable_len); + + int (*set_eee_rate)(struct aq_hw_s *self, u32 speed); + + int (*get_eee_rate)(struct aq_hw_s *self, u32 *rate, + u32 *supported_rates); + + int (*set_flow_control)(struct aq_hw_s *self); + + int (*led_control)(struct aq_hw_s *self, u32 mode); + + int (*get_eeprom)(struct aq_hw_s *self, u32 *data, u32 len); + + int (*set_eeprom)(struct aq_hw_s *self, u32 *data, u32 len); }; #endif diff --git a/drivers/net/atlantic/hw_atl/hw_atl_utils.c b/drivers/net/atlantic/hw_atl/hw_atl_utils.c new file mode 100644 index 000000000000..f18ce54762dc --- /dev/null +++ b/drivers/net/atlantic/hw_atl/hw_atl_utils.c @@ -0,0 +1,942 @@ +// SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) +/* Copyright (C) 2014-2017 aQuantia Corporation. */ + +/* File hw_atl_utils.c: Definition of common functions for Atlantic hardware + * abstraction layer. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "../atl_hw_regs.h" + +#include "hw_atl_llh.h" +#include "hw_atl_llh_internal.h" +#include "../atl_logs.h" + +#define HW_ATL_UCP_0X370_REG 0x0370U + +#define HW_ATL_MIF_CMD 0x0200U +#define HW_ATL_MIF_ADDR 0x0208U +#define HW_ATL_MIF_VAL 0x020CU + +#define HW_ATL_FW_SM_RAM 0x2U +#define HW_ATL_MPI_FW_VERSION 0x18 +#define HW_ATL_MPI_CONTROL_ADR 0x0368U +#define HW_ATL_MPI_STATE_ADR 0x036CU + +#define HW_ATL_MPI_STATE_MSK 0x00FFU +#define HW_ATL_MPI_STATE_SHIFT 0U +#define HW_ATL_MPI_SPEED_MSK 0x00FF0000U +#define HW_ATL_MPI_SPEED_SHIFT 16U +#define HW_ATL_MPI_DIRTY_WAKE_MSK 0x02000000U + +#define HW_ATL_MPI_DAISY_CHAIN_STATUS 0x704 +#define HW_ATL_MPI_BOOT_EXIT_CODE 0x388 + +#define HW_ATL_MAC_PHY_CONTROL 0x4000 +#define HW_ATL_MAC_PHY_MPI_RESET_BIT 0x1D + +#define HW_ATL_FW_VER_1X 0x01050006U +#define HW_ATL_FW_VER_2X 0x02000000U +#define HW_ATL_FW_VER_3X 0x03000000U + +#define FORCE_FLASHLESS 0 + +static int hw_atl_utils_ver_match(u32 ver_expected, u32 ver_actual); +static int hw_atl_utils_mpi_set_state(struct aq_hw_s *self, + enum hal_atl_utils_fw_state_e state); + + +int hw_atl_utils_initfw(struct aq_hw_s *self, const struct aq_fw_ops **fw_ops) +{ + int err = 0; + + err = hw_atl_utils_soft_reset(self); + if (err) + return err; + + hw_atl_utils_hw_chip_features_init(self, + &self->chip_features); + + hw_atl_utils_get_fw_version(self, &self->fw_ver_actual); + + if (hw_atl_utils_ver_match(HW_ATL_FW_VER_1X, + self->fw_ver_actual) == 0) { + *fw_ops = &aq_fw_1x_ops; + } else if (hw_atl_utils_ver_match(HW_ATL_FW_VER_2X, + self->fw_ver_actual) == 0) { + *fw_ops = &aq_fw_2x_ops; + } else if (hw_atl_utils_ver_match(HW_ATL_FW_VER_3X, + self->fw_ver_actual) == 0) { + *fw_ops = &aq_fw_2x_ops; + } else { + PMD_DRV_LOG(ERR, "Bad FW version detected: %x\n", + self->fw_ver_actual); + return -EOPNOTSUPP; + } + self->aq_fw_ops = *fw_ops; + err = self->aq_fw_ops->init(self); + return err; +} + +static int hw_atl_utils_soft_reset_flb(struct aq_hw_s *self) +{ + u32 gsr, val; + int k = 0; + + aq_hw_write_reg(self, 0x404, 0x40e1); + AQ_HW_SLEEP(50); + + /* Cleanup SPI */ + val = aq_hw_read_reg(self, 0x53C); + aq_hw_write_reg(self, 0x53C, val | 0x10); + + gsr = aq_hw_read_reg(self, HW_ATL_GLB_SOFT_RES_ADR); + aq_hw_write_reg(self, HW_ATL_GLB_SOFT_RES_ADR, (gsr & 0xBFFF) | 0x8000); + + /* Kickstart MAC */ + aq_hw_write_reg(self, 0x404, 0x80e0); + aq_hw_write_reg(self, 0x32a8, 0x0); + aq_hw_write_reg(self, 0x520, 0x1); + + /* Reset SPI again because of possible interrupted SPI burst */ + val = aq_hw_read_reg(self, 0x53C); + aq_hw_write_reg(self, 0x53C, val | 0x10); + AQ_HW_SLEEP(10); + /* Clear SPI reset state */ + aq_hw_write_reg(self, 0x53C, val & ~0x10); + + aq_hw_write_reg(self, 0x404, 0x180e0); + + for (k = 0; k < 1000; k++) { + u32 flb_status = aq_hw_read_reg(self, + HW_ATL_MPI_DAISY_CHAIN_STATUS); + + flb_status = flb_status & 0x10; + if (flb_status) + break; + AQ_HW_SLEEP(10); + } + if (k == 1000) { + PMD_DRV_LOG(ERR, "MAC kickstart failed\n"); + return -EIO; + } + + /* FW reset */ + aq_hw_write_reg(self, 0x404, 0x80e0); + AQ_HW_SLEEP(50); + aq_hw_write_reg(self, 0x3a0, 0x1); + + /* Kickstart PHY - skipped */ + + /* Global software reset*/ + hw_atl_rx_rx_reg_res_dis_set(self, 0U); + hw_atl_tx_tx_reg_res_dis_set(self, 0U); + aq_hw_write_reg_bit(self, HW_ATL_MAC_PHY_CONTROL, + BIT(HW_ATL_MAC_PHY_MPI_RESET_BIT), + HW_ATL_MAC_PHY_MPI_RESET_BIT, 0x0); + gsr = aq_hw_read_reg(self, HW_ATL_GLB_SOFT_RES_ADR); + aq_hw_write_reg(self, HW_ATL_GLB_SOFT_RES_ADR, (gsr & 0xBFFF) | 0x8000); + + for (k = 0; k < 1000; k++) { + u32 fw_state = aq_hw_read_reg(self, HW_ATL_MPI_FW_VERSION); + + if (fw_state) + break; + AQ_HW_SLEEP(10); + } + if (k == 1000) { + PMD_DRV_LOG(ERR, "FW kickstart failed\n"); + return -EIO; + } + /* Old FW requires fixed delay after init */ + AQ_HW_SLEEP(15); + + return 0; +} + +static int hw_atl_utils_soft_reset_rbl(struct aq_hw_s *self) +{ + u32 gsr, val, rbl_status; + int k; + + aq_hw_write_reg(self, 0x404, 0x40e1); + aq_hw_write_reg(self, 0x3a0, 0x1); + aq_hw_write_reg(self, 0x32a8, 0x0); + + /* Alter RBL status */ + aq_hw_write_reg(self, 0x388, 0xDEAD); + + /* Cleanup SPI */ + val = aq_hw_read_reg(self, 0x53C); + aq_hw_write_reg(self, 0x53C, val | 0x10); + + /* Global software reset*/ + hw_atl_rx_rx_reg_res_dis_set(self, 0U); + hw_atl_tx_tx_reg_res_dis_set(self, 0U); + aq_hw_write_reg_bit(self, HW_ATL_MAC_PHY_CONTROL, + BIT(HW_ATL_MAC_PHY_MPI_RESET_BIT), + HW_ATL_MAC_PHY_MPI_RESET_BIT, 0x0); + gsr = aq_hw_read_reg(self, HW_ATL_GLB_SOFT_RES_ADR); + aq_hw_write_reg(self, HW_ATL_GLB_SOFT_RES_ADR, + (gsr & 0xFFFFBFFF) | 0x8000); + + if (FORCE_FLASHLESS) + aq_hw_write_reg(self, 0x534, 0x0); + + aq_hw_write_reg(self, 0x404, 0x40e0); + + /* Wait for RBL boot */ + for (k = 0; k < 1000; k++) { + rbl_status = aq_hw_read_reg(self, 0x388) & 0xFFFF; + if (rbl_status && rbl_status != 0xDEAD) + break; + AQ_HW_SLEEP(10); + } + if (!rbl_status || rbl_status == 0xDEAD) { + PMD_DRV_LOG(ERR, "RBL Restart failed"); + return -EIO; + } + + /* Restore NVR */ + if (FORCE_FLASHLESS) + aq_hw_write_reg(self, 0x534, 0xA0); + + if (rbl_status == 0xF1A7) { + PMD_DRV_LOG(ERR, "No FW detected. Dynamic FW load not implemented\n"); + return -EOPNOTSUPP; + } + + for (k = 0; k < 1000; k++) { + u32 fw_state = aq_hw_read_reg(self, HW_ATL_MPI_FW_VERSION); + + if (fw_state) + break; + AQ_HW_SLEEP(10); + } + if (k == 1000) { + PMD_DRV_LOG(ERR, "FW kickstart failed\n"); + return -EIO; + } + /* Old FW requires fixed delay after init */ + AQ_HW_SLEEP(15); + + return 0; +} + +int hw_atl_utils_soft_reset(struct aq_hw_s *self) +{ + int err = 0; + int k; + u32 boot_exit_code = 0; + + for (k = 0; k < 1000; ++k) { + u32 flb_status = aq_hw_read_reg(self, + HW_ATL_MPI_DAISY_CHAIN_STATUS); + boot_exit_code = aq_hw_read_reg(self, + HW_ATL_MPI_BOOT_EXIT_CODE); + if (flb_status != 0x06000000 || boot_exit_code != 0) + break; + } + + if (k == 1000) { + PMD_DRV_LOG(ERR, "Neither RBL nor FLB firmware started\n"); + return -EOPNOTSUPP; + } + + self->rbl_enabled = (boot_exit_code != 0); + + /* FW 1.x may bootup in an invalid POWER state (WOL feature). + * We should work around this by forcing its state back to DEINIT + */ + if (!hw_atl_utils_ver_match(HW_ATL_FW_VER_1X, + aq_hw_read_reg(self, + HW_ATL_MPI_FW_VERSION))) { + hw_atl_utils_mpi_set_state(self, MPI_DEINIT); + AQ_HW_WAIT_FOR((aq_hw_read_reg(self, HW_ATL_MPI_STATE_ADR) & + HW_ATL_MPI_STATE_MSK) == MPI_DEINIT, + 10, 1000U); + } + + if (self->rbl_enabled) + err = hw_atl_utils_soft_reset_rbl(self); + else + err = hw_atl_utils_soft_reset_flb(self); + + return err; +} + +int hw_atl_utils_fw_downld_dwords(struct aq_hw_s *self, u32 a, + u32 *p, u32 cnt) +{ + int err = 0; + + AQ_HW_WAIT_FOR(hw_atl_reg_glb_cpu_sem_get(self, + HW_ATL_FW_SM_RAM) == 1U, + 1U, 10000U); + + if (err < 0) { + bool is_locked; + + hw_atl_reg_glb_cpu_sem_set(self, 1U, HW_ATL_FW_SM_RAM); + is_locked = hw_atl_reg_glb_cpu_sem_get(self, HW_ATL_FW_SM_RAM); + if (!is_locked) { + err = -ETIMEDOUT; + goto err_exit; + } + } + + aq_hw_write_reg(self, HW_ATL_MIF_ADDR, a); + + for (++cnt; --cnt && !err;) { + aq_hw_write_reg(self, HW_ATL_MIF_CMD, 0x00008000U); + + if (IS_CHIP_FEATURE(REVISION_B1)) + AQ_HW_WAIT_FOR(a != aq_hw_read_reg(self, + HW_ATL_MIF_ADDR), + 1, 1000U); + else + AQ_HW_WAIT_FOR(!(0x100 & aq_hw_read_reg(self, + HW_ATL_MIF_CMD)), + 1, 1000U); + + *(p++) = aq_hw_read_reg(self, HW_ATL_MIF_VAL); + a += 4; + } + + hw_atl_reg_glb_cpu_sem_set(self, 1U, HW_ATL_FW_SM_RAM); + +err_exit: + return err; +} + +int hw_atl_utils_fw_upload_dwords(struct aq_hw_s *self, u32 a, u32 *p, + u32 cnt) +{ + int err = 0; + bool is_locked; + + is_locked = hw_atl_reg_glb_cpu_sem_get(self, HW_ATL_FW_SM_RAM); + if (!is_locked) { + err = -ETIMEDOUT; + goto err_exit; + } + if (IS_CHIP_FEATURE(REVISION_B1)) { + u32 offset = 0; + + for (; offset < cnt; ++offset) { + aq_hw_write_reg(self, 0x328, p[offset]); + aq_hw_write_reg(self, 0x32C, + (0x80000000 | (0xFFFF & (offset * 4)))); + mcp_up_force_intr_set(self, 1); + /* 1000 times by 10us = 10ms */ + AQ_HW_WAIT_FOR((aq_hw_read_reg(self, + 0x32C) & 0xF0000000) != 0x80000000, + 10, 1000); + } + } else { + u32 offset = 0; + + aq_hw_write_reg(self, 0x208, a); + + for (; offset < cnt; ++offset) { + aq_hw_write_reg(self, 0x20C, p[offset]); + aq_hw_write_reg(self, 0x200, 0xC000); + + AQ_HW_WAIT_FOR((aq_hw_read_reg(self, 0x200U) + & 0x100) == 0, 10, 1000); + } + } + + hw_atl_reg_glb_cpu_sem_set(self, 1U, HW_ATL_FW_SM_RAM); + +err_exit: + return err; +} + +static int hw_atl_utils_ver_match(u32 ver_expected, u32 ver_actual) +{ + int err = 0; + const u32 dw_major_mask = 0xff000000U; + const u32 dw_minor_mask = 0x00ffffffU; + + err = (dw_major_mask & (ver_expected ^ ver_actual)) ? -EOPNOTSUPP : 0; + if (err < 0) + goto err_exit; + err = ((dw_minor_mask & ver_expected) > (dw_minor_mask & ver_actual)) ? + -EOPNOTSUPP : 0; +err_exit: + return err; +} + +static int hw_atl_utils_init_ucp(struct aq_hw_s *self) +{ + int err = 0; + + if (!aq_hw_read_reg(self, 0x370U)) { + unsigned int rnd = (uint32_t)rte_rand(); + unsigned int ucp_0x370 = 0U; + + ucp_0x370 = 0x02020202U | (0xFEFEFEFEU & rnd); + aq_hw_write_reg(self, HW_ATL_UCP_0X370_REG, ucp_0x370); + } + + hw_atl_reg_glb_cpu_scratch_scp_set(self, 0x00000000U, 25U); + + /* check 10 times by 1ms */ + AQ_HW_WAIT_FOR(0U != (self->mbox_addr = + aq_hw_read_reg(self, 0x360U)), 1000U, 10U); + AQ_HW_WAIT_FOR(0U != (self->rpc_addr = + aq_hw_read_reg(self, 0x334U)), 1000U, 100U); + + return err; +} + +#define HW_ATL_RPC_CONTROL_ADR 0x0338U +#define HW_ATL_RPC_STATE_ADR 0x033CU + +struct aq_hw_atl_utils_fw_rpc_tid_s { + union { + u32 val; + struct { + u16 tid; + u16 len; + }; + }; +}; + +#define hw_atl_utils_fw_rpc_init(_H_) hw_atl_utils_fw_rpc_wait(_H_, NULL) + +int hw_atl_utils_fw_rpc_call(struct aq_hw_s *self, unsigned int rpc_size) +{ + int err = 0; + struct aq_hw_atl_utils_fw_rpc_tid_s sw; + + if (!IS_CHIP_FEATURE(MIPS)) { + err = -1; + goto err_exit; + } + err = hw_atl_utils_fw_upload_dwords(self, self->rpc_addr, + (u32 *)(void *)&self->rpc, + (rpc_size + sizeof(u32) - + sizeof(u8)) / sizeof(u32)); + if (err < 0) + goto err_exit; + + sw.tid = 0xFFFFU & (++self->rpc_tid); + sw.len = (u16)rpc_size; + aq_hw_write_reg(self, HW_ATL_RPC_CONTROL_ADR, sw.val); + +err_exit: + return err; +} + +int hw_atl_utils_fw_rpc_wait(struct aq_hw_s *self, + struct hw_aq_atl_utils_fw_rpc **rpc) +{ + int err = 0; + struct aq_hw_atl_utils_fw_rpc_tid_s sw; + struct aq_hw_atl_utils_fw_rpc_tid_s fw; + + do { + sw.val = aq_hw_read_reg(self, HW_ATL_RPC_CONTROL_ADR); + + self->rpc_tid = sw.tid; + + AQ_HW_WAIT_FOR(sw.tid == + (fw.val = + aq_hw_read_reg(self, HW_ATL_RPC_STATE_ADR), + fw.tid), 1000U, 100U); + if (err < 0) + goto err_exit; + + if (fw.len == 0xFFFFU) { + err = hw_atl_utils_fw_rpc_call(self, sw.len); + if (err < 0) + goto err_exit; + } + } while (sw.tid != fw.tid || 0xFFFFU == fw.len); + if (err < 0) + goto err_exit; + + if (rpc) { + if (fw.len) { + err = + hw_atl_utils_fw_downld_dwords(self, + self->rpc_addr, + (u32 *)(void *) + &self->rpc, + (fw.len + sizeof(u32) - + sizeof(u8)) / + sizeof(u32)); + if (err < 0) + goto err_exit; + } + + *rpc = &self->rpc; + } + +err_exit: + return err; +} + +static int hw_atl_utils_mpi_create(struct aq_hw_s *self) +{ + int err = 0; + + err = hw_atl_utils_init_ucp(self); + if (err < 0) + goto err_exit; + + err = hw_atl_utils_fw_rpc_init(self); + if (err < 0) + goto err_exit; + +err_exit: + return err; +} + +int hw_atl_utils_mpi_read_mbox(struct aq_hw_s *self, + struct hw_aq_atl_utils_mbox_header *pmbox) +{ + return hw_atl_utils_fw_downld_dwords(self, + self->mbox_addr, + (u32 *)(void *)pmbox, + sizeof(*pmbox) / sizeof(u32)); +} + +void hw_atl_utils_mpi_read_stats(struct aq_hw_s *self, + struct hw_aq_atl_utils_mbox *pmbox) +{ + int err = 0; + + err = hw_atl_utils_fw_downld_dwords(self, + self->mbox_addr, + (u32 *)(void *)pmbox, + sizeof(*pmbox) / sizeof(u32)); + if (err < 0) + goto err_exit; + + if (IS_CHIP_FEATURE(REVISION_A0)) { + unsigned int mtu = 1514; + pmbox->stats.ubrc = pmbox->stats.uprc * mtu; + pmbox->stats.ubtc = pmbox->stats.uptc * mtu; + } else { + pmbox->stats.dpc = hw_atl_rpb_rx_dma_drop_pkt_cnt_get(self); + } + +err_exit:; +} + +static +int hw_atl_utils_mpi_set_speed(struct aq_hw_s *self, u32 speed) +{ + u32 val = aq_hw_read_reg(self, HW_ATL_MPI_CONTROL_ADR); + + val = val & ~HW_ATL_MPI_SPEED_MSK; + val |= speed << HW_ATL_MPI_SPEED_SHIFT; + aq_hw_write_reg(self, HW_ATL_MPI_CONTROL_ADR, val); + + return 0; +} + +int hw_atl_utils_mpi_set_state(struct aq_hw_s *self, + enum hal_atl_utils_fw_state_e state) +{ + int err = 0; + u32 transaction_id = 0; + struct hw_aq_atl_utils_mbox_header mbox; + u32 val = aq_hw_read_reg(self, HW_ATL_MPI_CONTROL_ADR); + + if (state == MPI_RESET) { + hw_atl_utils_mpi_read_mbox(self, &mbox); + + transaction_id = mbox.transaction_id; + + AQ_HW_WAIT_FOR(transaction_id != + (hw_atl_utils_mpi_read_mbox(self, &mbox), + mbox.transaction_id), + 1000U, 100U); + if (err < 0) + goto err_exit; + } + /* On interface DEINIT we disable DW (raise bit) + * Otherwise enable DW (clear bit) + */ + if (state == MPI_DEINIT || state == MPI_POWER) + val |= HW_ATL_MPI_DIRTY_WAKE_MSK; + else + val &= ~HW_ATL_MPI_DIRTY_WAKE_MSK; + + /* Set new state bits */ + val = val & ~HW_ATL_MPI_STATE_MSK; + val |= state & HW_ATL_MPI_STATE_MSK; + + aq_hw_write_reg(self, HW_ATL_MPI_CONTROL_ADR, val); +err_exit: + return err; +} + +int hw_atl_utils_mpi_get_link_status(struct aq_hw_s *self) +{ + u32 cp0x036C = aq_hw_read_reg(self, HW_ATL_MPI_STATE_ADR); + u32 link_speed_mask = cp0x036C >> HW_ATL_MPI_SPEED_SHIFT; + struct aq_hw_link_status_s *link_status = &self->aq_link_status; + + if (!link_speed_mask) { + link_status->mbps = 0U; + } else { + switch (link_speed_mask) { + case HAL_ATLANTIC_RATE_10G: + link_status->mbps = 10000U; + break; + + case HAL_ATLANTIC_RATE_5G: + case HAL_ATLANTIC_RATE_5GSR: + link_status->mbps = 5000U; + break; + + case HAL_ATLANTIC_RATE_2GS: + link_status->mbps = 2500U; + break; + + case HAL_ATLANTIC_RATE_1G: + link_status->mbps = 1000U; + break; + + case HAL_ATLANTIC_RATE_100M: + link_status->mbps = 100U; + break; + + default: + return -EBUSY; + } + } + + return 0; +} + +static int hw_atl_utils_get_mac_permanent(struct aq_hw_s *self, + u8 *mac) +{ + int err = 0; + u32 h = 0U; + u32 l = 0U; + u32 mac_addr[2]; + + if (!aq_hw_read_reg(self, HW_ATL_UCP_0X370_REG)) { + unsigned int rnd = (uint32_t)rte_rand(); + unsigned int ucp_0x370 = 0; + + //get_random_bytes(&rnd, sizeof(unsigned int)); + + ucp_0x370 = 0x02020202 | (0xFEFEFEFE & rnd); + aq_hw_write_reg(self, HW_ATL_UCP_0X370_REG, ucp_0x370); + } + + err = hw_atl_utils_fw_downld_dwords(self, + aq_hw_read_reg(self, 0x00000374U) + + (40U * 4U), + mac_addr, + ARRAY_SIZE(mac_addr)); + if (err < 0) { + mac_addr[0] = 0U; + mac_addr[1] = 0U; + err = 0; + } else { + mac_addr[0] = rte_constant_bswap32(mac_addr[0]); + mac_addr[1] = rte_constant_bswap32(mac_addr[1]); + } + + ether_addr_copy((struct ether_addr *)mac_addr, + (struct ether_addr *)mac); + + if ((mac[0] & 0x01U) || ((mac[0] | mac[1] | mac[2]) == 0x00U)) { + /* chip revision */ + l = 0xE3000000U + | (0xFFFFU & aq_hw_read_reg(self, HW_ATL_UCP_0X370_REG)) + | (0x00 << 16); + h = 0x8001300EU; + + mac[5] = (u8)(0xFFU & l); + l >>= 8; + mac[4] = (u8)(0xFFU & l); + l >>= 8; + mac[3] = (u8)(0xFFU & l); + l >>= 8; + mac[2] = (u8)(0xFFU & l); + mac[1] = (u8)(0xFFU & h); + h >>= 8; + mac[0] = (u8)(0xFFU & h); + } + + return err; +} + +unsigned int hw_atl_utils_mbps_2_speed_index(unsigned int mbps) +{ + unsigned int ret = 0U; + + switch (mbps) { + case 100U: + ret = 5U; + break; + + case 1000U: + ret = 4U; + break; + + case 2500U: + ret = 3U; + break; + + case 5000U: + ret = 1U; + break; + + case 10000U: + ret = 0U; + break; + + default: + break; + } + return ret; +} + +void hw_atl_utils_hw_chip_features_init(struct aq_hw_s *self, u32 *p) +{ + u32 chip_features = 0U; + u32 val = hw_atl_reg_glb_mif_id_get(self); + u32 mif_rev = val & 0xFFU; + + if ((0xFU & mif_rev) == 1U) { + chip_features |= HAL_ATLANTIC_UTILS_CHIP_REVISION_A0 | + HAL_ATLANTIC_UTILS_CHIP_MPI_AQ | + HAL_ATLANTIC_UTILS_CHIP_MIPS; + } else if ((0xFU & mif_rev) == 2U) { + chip_features |= HAL_ATLANTIC_UTILS_CHIP_REVISION_B0 | + HAL_ATLANTIC_UTILS_CHIP_MPI_AQ | + HAL_ATLANTIC_UTILS_CHIP_MIPS | + HAL_ATLANTIC_UTILS_CHIP_TPO2 | + HAL_ATLANTIC_UTILS_CHIP_RPF2; + } else if ((0xFU & mif_rev) == 0xAU) { + chip_features |= HAL_ATLANTIC_UTILS_CHIP_REVISION_B1 | + HAL_ATLANTIC_UTILS_CHIP_MPI_AQ | + HAL_ATLANTIC_UTILS_CHIP_MIPS | + HAL_ATLANTIC_UTILS_CHIP_TPO2 | + HAL_ATLANTIC_UTILS_CHIP_RPF2; + } + + *p = chip_features; +} + +static int hw_atl_fw1x_deinit(struct aq_hw_s *self) +{ + hw_atl_utils_mpi_set_speed(self, 0); + hw_atl_utils_mpi_set_state(self, MPI_DEINIT); + return 0; +} + +int hw_atl_utils_update_stats(struct aq_hw_s *self) +{ + struct hw_aq_atl_utils_mbox mbox; + + hw_atl_utils_mpi_read_stats(self, &mbox); + +#define AQ_SDELTA(_N_) (self->curr_stats._N_ += \ + mbox.stats._N_ - self->last_stats._N_) + + if (1) {//self->aq_link_status.mbps) { + AQ_SDELTA(uprc); + AQ_SDELTA(mprc); + AQ_SDELTA(bprc); + AQ_SDELTA(erpt); + + AQ_SDELTA(uptc); + AQ_SDELTA(mptc); + AQ_SDELTA(bptc); + AQ_SDELTA(erpr); + AQ_SDELTA(ubrc); + AQ_SDELTA(ubtc); + AQ_SDELTA(mbrc); + AQ_SDELTA(mbtc); + AQ_SDELTA(bbrc); + AQ_SDELTA(bbtc); + AQ_SDELTA(dpc); + } +#undef AQ_SDELTA + self->curr_stats.dma_pkt_rc = + hw_atl_stats_rx_dma_good_pkt_counterlsw_get(self) + + ((u64)hw_atl_stats_rx_dma_good_pkt_countermsw_get(self) << 32); + self->curr_stats.dma_pkt_tc = + hw_atl_stats_tx_dma_good_pkt_counterlsw_get(self) + + ((u64)hw_atl_stats_tx_dma_good_pkt_countermsw_get(self) << 32); + self->curr_stats.dma_oct_rc = + hw_atl_stats_rx_dma_good_octet_counterlsw_get(self) + + ((u64)hw_atl_stats_rx_dma_good_octet_countermsw_get(self) << 32); + self->curr_stats.dma_oct_tc = + hw_atl_stats_tx_dma_good_octet_counterlsw_get(self) + + ((u64)hw_atl_stats_tx_dma_good_octet_countermsw_get(self) << 32); + + self->curr_stats.dpc = hw_atl_rpb_rx_dma_drop_pkt_cnt_get(self); + + memcpy(&self->last_stats, &mbox.stats, sizeof(mbox.stats)); + + return 0; +} + +struct aq_stats_s *hw_atl_utils_get_hw_stats(struct aq_hw_s *self) +{ + return &self->curr_stats; +} + +static const u32 hw_atl_utils_hw_mac_regs[] = { + 0x00005580U, 0x00005590U, 0x000055B0U, 0x000055B4U, + 0x000055C0U, 0x00005B00U, 0x00005B04U, 0x00005B08U, + 0x00005B0CU, 0x00005B10U, 0x00005B14U, 0x00005B18U, + 0x00005B1CU, 0x00005B20U, 0x00005B24U, 0x00005B28U, + 0x00005B2CU, 0x00005B30U, 0x00005B34U, 0x00005B38U, + 0x00005B3CU, 0x00005B40U, 0x00005B44U, 0x00005B48U, + 0x00005B4CU, 0x00005B50U, 0x00005B54U, 0x00005B58U, + 0x00005B5CU, 0x00005B60U, 0x00005B64U, 0x00005B68U, + 0x00005B6CU, 0x00005B70U, 0x00005B74U, 0x00005B78U, + 0x00005B7CU, 0x00007C00U, 0x00007C04U, 0x00007C08U, + 0x00007C0CU, 0x00007C10U, 0x00007C14U, 0x00007C18U, + 0x00007C1CU, 0x00007C20U, 0x00007C40U, 0x00007C44U, + 0x00007C48U, 0x00007C4CU, 0x00007C50U, 0x00007C54U, + 0x00007C58U, 0x00007C5CU, 0x00007C60U, 0x00007C80U, + 0x00007C84U, 0x00007C88U, 0x00007C8CU, 0x00007C90U, + 0x00007C94U, 0x00007C98U, 0x00007C9CU, 0x00007CA0U, + 0x00007CC0U, 0x00007CC4U, 0x00007CC8U, 0x00007CCCU, + 0x00007CD0U, 0x00007CD4U, 0x00007CD8U, 0x00007CDCU, + 0x00007CE0U, 0x00000300U, 0x00000304U, 0x00000308U, + 0x0000030cU, 0x00000310U, 0x00000314U, 0x00000318U, + 0x0000031cU, 0x00000360U, 0x00000364U, 0x00000368U, + 0x0000036cU, 0x00000370U, 0x00000374U, 0x00006900U, +}; + +unsigned int hw_atl_utils_hw_get_reg_length(void) +{ + return ARRAY_SIZE(hw_atl_utils_hw_mac_regs); +} + +int hw_atl_utils_hw_get_regs(struct aq_hw_s *self, + u32 *regs_buff) +{ + unsigned int i = 0U; + unsigned int mac_regs_count = hw_atl_utils_hw_get_reg_length(); + + for (i = 0; i < mac_regs_count; i++) + regs_buff[i] = aq_hw_read_reg(self, + hw_atl_utils_hw_mac_regs[i]); + return 0; +} + +int hw_atl_utils_get_fw_version(struct aq_hw_s *self, u32 *fw_version) +{ + *fw_version = aq_hw_read_reg(self, 0x18U); + return 0; +} + +static int aq_fw1x_set_wol(struct aq_hw_s *self, bool wol_enabled, u8 *mac) +{ + struct hw_aq_atl_utils_fw_rpc *prpc = NULL; + unsigned int rpc_size = 0U; + int err = 0; + + err = hw_atl_utils_fw_rpc_wait(self, &prpc); + if (err < 0) + goto err_exit; + + memset(prpc, 0, sizeof(*prpc)); + + if (wol_enabled) { + rpc_size = sizeof(prpc->msg_id) + sizeof(prpc->msg_wol); + + prpc->msg_id = HAL_ATLANTIC_UTILS_FW_MSG_WOL_ADD; + prpc->msg_wol.priority = 0x10000000; /* normal priority */ + prpc->msg_wol.pattern_id = 1U; + prpc->msg_wol.wol_packet_type = 2U; /* Magic Packet */ + + ether_addr_copy((struct ether_addr *)mac, + (struct ether_addr *)&prpc->msg_wol.wol_pattern); + } else { + rpc_size = sizeof(prpc->msg_id) + sizeof(prpc->msg_del_id); + + prpc->msg_id = HAL_ATLANTIC_UTILS_FW_MSG_WOL_DEL; + prpc->msg_wol.pattern_id = 1U; + } + + err = hw_atl_utils_fw_rpc_call(self, rpc_size); + if (err < 0) + goto err_exit; +err_exit: + return err; +} + +static +int aq_fw1x_set_power(struct aq_hw_s *self, + unsigned int power_state __rte_unused, + u8 *mac) +{ + struct hw_aq_atl_utils_fw_rpc *prpc = NULL; + unsigned int rpc_size = 0U; + int err = 0; + if (self->aq_nic_cfg->wol & AQ_NIC_WOL_ENABLED) { + err = aq_fw1x_set_wol(self, 1, mac); + + if (err < 0) + goto err_exit; + + rpc_size = sizeof(prpc->msg_id) + + sizeof(prpc->msg_enable_wakeup); + + err = hw_atl_utils_fw_rpc_wait(self, &prpc); + + if (err < 0) + goto err_exit; + + memset(prpc, 0, rpc_size); + + prpc->msg_id = HAL_ATLANTIC_UTILS_FW_MSG_ENABLE_WAKEUP; + prpc->msg_enable_wakeup.pattern_mask = 0x00000002; + + err = hw_atl_utils_fw_rpc_call(self, rpc_size); + if (err < 0) + goto err_exit; + } + + hw_atl_utils_mpi_set_speed(self, 0); + hw_atl_utils_mpi_set_state(self, MPI_POWER); +err_exit: + return err; +} + + + +const struct aq_fw_ops aq_fw_1x_ops = { + .init = hw_atl_utils_mpi_create, + .deinit = hw_atl_fw1x_deinit, + .reset = NULL, + .get_mac_permanent = hw_atl_utils_get_mac_permanent, + .set_link_speed = hw_atl_utils_mpi_set_speed, + .set_state = hw_atl_utils_mpi_set_state, + .update_link_status = hw_atl_utils_mpi_get_link_status, + .update_stats = hw_atl_utils_update_stats, + .set_power = aq_fw1x_set_power, + .get_temp = NULL, + .get_cable_len = NULL, + .set_eee_rate = NULL, + .get_eee_rate = NULL, + .set_flow_control = NULL, + .led_control = NULL, + .get_eeprom = NULL, + .set_eeprom = NULL, +}; diff --git a/drivers/net/atlantic/hw_atl/hw_atl_utils.h b/drivers/net/atlantic/hw_atl/hw_atl_utils.h new file mode 100644 index 000000000000..8767459347fc --- /dev/null +++ b/drivers/net/atlantic/hw_atl/hw_atl_utils.h @@ -0,0 +1,510 @@ +/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) */ +/* Copyright (C) 2014-2017 aQuantia Corporation. */ + +/* File hw_atl_utils.h: Declaration of common functions for Atlantic hardware + * abstraction layer. + */ + +#ifndef HW_ATL_UTILS_H +#define HW_ATL_UTILS_H + +#define HW_ATL_FLUSH() { (void)aq_hw_read_reg(self, 0x10); } + +/* Hardware tx descriptor */ +struct hw_atl_txd_s { + u64 buf_addr; + + union { + struct { + u32 type:3; + u32:1; + u32 len:16; + u32 dd:1; + u32 eop:1; + u32 cmd:8; + u32:14; + u32 ct_idx:1; + u32 ct_en:1; + u32 pay_len:18; + } __attribute__((__packed__)); + u64 flags; + }; +} __attribute__((__packed__)); + +/* Hardware tx context descriptor */ +union hw_atl_txc_s { + struct { + u64 flags1; + u64 flags2; + }; + + struct { + u64:40; + u32 tun_len:8; + u32 out_len:16; + u32 type:3; + u32 idx:1; + u32 vlan_tag:16; + u32 cmd:4; + u32 l2_len:7; + u32 l3_len:9; + u32 l4_len:8; + u32 mss_len:16; + } __attribute__((__packed__)); +} __attribute__((__packed__)); + +enum aq_tx_desc_type { + tx_desc_type_desc = 1, + tx_desc_type_ctx = 2, +}; + +enum aq_tx_desc_cmd { + tx_desc_cmd_vlan = 1, + tx_desc_cmd_fcs = 2, + tx_desc_cmd_ipv4 = 4, + tx_desc_cmd_l4cs = 8, + tx_desc_cmd_lso = 0x10, + tx_desc_cmd_wb = 0x20, +}; + + +/* Hardware rx descriptor */ +struct hw_atl_rxd_s { + u64 buf_addr; + u64 hdr_addr; +} __attribute__((__packed__)); + +/* Hardware rx descriptor writeback */ +struct hw_atl_rxd_wb_s { + u32 rss_type:4; + u32 pkt_type:8; + u32 type:20; + u32 rss_hash; + u16 dd:1; + u16 eop:1; + u16 rx_stat:4; + u16 rx_estat:6; + u16 rsc_cnt:4; + u16 pkt_len; + u16 next_desc_ptr; + u16 vlan; +} __attribute__((__packed__)); + +struct hw_atl_stats_s { + u32 uprc; + u32 mprc; + u32 bprc; + u32 erpt; + u32 uptc; + u32 mptc; + u32 bptc; + u32 erpr; + u32 mbtc; + u32 bbtc; + u32 mbrc; + u32 bbrc; + u32 ubrc; + u32 ubtc; + u32 dpc; +} __attribute__((__packed__)); + +union ip_addr { + struct { + u8 addr[16]; + } v6; + struct { + u8 padding[12]; + u8 addr[4]; + } v4; +} __attribute__((__packed__)); + +struct hw_aq_atl_utils_fw_rpc { + u32 msg_id; + + union { + struct { + u32 pong; + } msg_ping; + + struct { + u8 mac_addr[6]; + u32 ip_addr_cnt; + + struct { + union ip_addr addr; + union ip_addr mask; + } ip[1]; + } msg_arp; + + struct { + u32 len; + u8 packet[1514U]; + } msg_inject; + + struct { + u32 priority; + u32 wol_packet_type; + u32 pattern_id; + u32 next_wol_pattern_offset; + union { + struct { + u32 flags; + u8 ipv4_source_address[4]; + u8 ipv4_dest_address[4]; + u16 tcp_source_port_number; + u16 tcp_dest_port_number; + } ipv4_tcp_syn_parameters; + + struct { + u32 flags; + u8 ipv6_source_address[16]; + u8 ipv6_dest_address[16]; + u16 tcp_source_port_number; + u16 tcp_dest_port_number; + } ipv6_tcp_syn_parameters; + + struct { + u32 flags; + } eapol_request_id_message_parameters; + + struct { + u32 flags; + u32 mask_offset; + u32 mask_size; + u32 pattern_offset; + u32 pattern_size; + } wol_bit_map_pattern; + struct { + u8 mac_addr[6]; + } wol_magic_packet_pattern; + + } wol_pattern; + } msg_wol; + + struct { + u16 tcQuanta[8]; + u16 tcThreshold[8]; + } msg_msm_pfc_quantas; + + struct { + union { + u32 pattern_mask; + struct { + u32 aq_pm_wol_reason_arp_v4_pkt : 1; + u32 aq_pm_wol_reason_ipv4_ping_pkt : 1; + u32 aq_pm_wol_reason_ipv6_ns_pkt : 1; + u32 aq_pm_wol_reason_ipv6_ping_pkt : 1; + u32 aq_pm_wol_reason_link_up : 1; + u32 aq_pm_wol_reason_link_down : 1; + u32 aq_pm_wol_reason_maximum : 1; + }; + }; + union { + u32 offload_mask; + }; + } msg_enable_wakeup; + + struct { + u32 priority; + u32 protocol_offload_type; + u32 protocol_offload_id; + u32 next_protocol_offload_offset; + + union { + struct { + u32 flags; + u8 remote_ipv4_addr[4]; + u8 host_ipv4_addr[4]; + u8 mac_addr[6]; + } ipv4_arp_params; + }; + } msg_offload; + + struct { + u32 id; + } msg_del_id; + + }; +} __attribute__((__packed__)); + +struct hw_aq_atl_utils_mbox_header { + u32 version; + u32 transaction_id; + u32 error; +} __attribute__((__packed__)); + +struct hw_aq_info { + u8 reserved[6]; + u16 phy_fault_code; + u16 phy_temperature; + u8 cable_len; + u8 reserved1; + u32 cable_diag_data[4]; + u8 reserved2[32]; + u32 caps_lo; + u32 caps_hi; +} __attribute__((__packed__)); + +struct hw_aq_atl_utils_mbox { + struct hw_aq_atl_utils_mbox_header header; + struct hw_atl_stats_s stats; + struct hw_aq_info info; +} __attribute__((__packed__)); + +/* fw2x */ +typedef u16 in_port_t; +typedef u32 ip4_addr_t; +typedef int int32_t; +typedef short int16_t; +typedef u32 fw_offset_t; + +struct ip6_addr { + u32 addr[4]; +} __attribute__((__packed__)); + +struct offload_ka_v4 { + u32 timeout; + in_port_t local_port; + in_port_t remote_port; + u8 remote_mac_addr[6]; + u16 win_size; + u32 seq_num; + u32 ack_num; + ip4_addr_t local_ip; + ip4_addr_t remote_ip; +} __attribute__((__packed__)); + +struct offload_ka_v6 { + u32 timeout; + in_port_t local_port; + in_port_t remote_port; + u8 remote_mac_addr[6]; + u16 win_size; + u32 seq_num; + u32 ack_num; + struct ip6_addr local_ip; + struct ip6_addr remote_ip; +} __attribute__((__packed__)); + +struct offload_ip_info { + u8 v4_local_addr_count; + u8 v4_addr_count; + u8 v6_local_addr_count; + u8 v6_addr_count; + fw_offset_t v4_addr; + fw_offset_t v4_prefix; + fw_offset_t v6_addr; + fw_offset_t v6_prefix; +} __attribute__((__packed__)); + +struct offload_port_info { + u16 udp_port_count; + u16 tcp_port_count; + fw_offset_t udp_port; + fw_offset_t tcp_port; +} __attribute__((__packed__)); + +struct offload_ka_info { + u16 v4_ka_count; + u16 v6_ka_count; + u32 retry_count; + u32 retry_interval; + fw_offset_t v4_ka; + fw_offset_t v6_ka; +} __attribute__((__packed__)); + +struct offload_rr_info { + u32 rr_count; + u32 rr_buf_len; + fw_offset_t rr_id_x; + fw_offset_t rr_buf; +} __attribute__((__packed__)); + +struct offload_info { + u32 version; // current version is 0x00000000 + u32 len; // The whole structure length + // including the variable-size buf + u8 mac_addr[6]; // 8 bytes to keep alignment. Only + // first 6 meaningful. + + u8 reserved[2]; + + struct offload_ip_info ips; + struct offload_port_info ports; + struct offload_ka_info kas; + struct offload_rr_info rrs; + u8 buf[0]; +} __attribute__((__packed__)); + +struct smbus_read_request { + u32 offset; /* not used */ + u32 device_id; + u32 address; + u32 length; +} __attribute__((__packed__)); + +struct smbus_write_request { + u32 offset; /* not used */ + u32 device_id; + u32 address; + u32 length; +} __attribute__((__packed__)); + +#define HAL_ATLANTIC_UTILS_CHIP_MIPS 0x00000001U +#define HAL_ATLANTIC_UTILS_CHIP_TPO2 0x00000002U +#define HAL_ATLANTIC_UTILS_CHIP_RPF2 0x00000004U +#define HAL_ATLANTIC_UTILS_CHIP_MPI_AQ 0x00000010U +#define HAL_ATLANTIC_UTILS_CHIP_REVISION_A0 0x01000000U +#define HAL_ATLANTIC_UTILS_CHIP_REVISION_B0 0x02000000U +#define HAL_ATLANTIC_UTILS_CHIP_REVISION_B1 0x04000000U + + +#define IS_CHIP_FEATURE(_F_) (HAL_ATLANTIC_UTILS_CHIP_##_F_ & \ + self->chip_features) + +enum hal_atl_utils_fw_state_e { + MPI_DEINIT = 0, + MPI_RESET = 1, + MPI_INIT = 2, + MPI_POWER = 4, +}; + +#define HAL_ATLANTIC_RATE_10G BIT(0) +#define HAL_ATLANTIC_RATE_5G BIT(1) +#define HAL_ATLANTIC_RATE_5GSR BIT(2) +#define HAL_ATLANTIC_RATE_2GS BIT(3) +#define HAL_ATLANTIC_RATE_1G BIT(4) +#define HAL_ATLANTIC_RATE_100M BIT(5) +#define HAL_ATLANTIC_RATE_INVALID BIT(6) + +#define HAL_ATLANTIC_UTILS_FW_MSG_PING 1U +#define HAL_ATLANTIC_UTILS_FW_MSG_ARP 2U +#define HAL_ATLANTIC_UTILS_FW_MSG_INJECT 3U +#define HAL_ATLANTIC_UTILS_FW_MSG_WOL_ADD 4U +#define HAL_ATLANTIC_UTILS_FW_MSG_WOL_DEL 5U +#define HAL_ATLANTIC_UTILS_FW_MSG_ENABLE_WAKEUP 6U +#define HAL_ATLANTIC_UTILS_FW_MSG_MSM_PFC 7U +#define HAL_ATLANTIC_UTILS_FW_MSG_PROVISIONING 8U +#define HAL_ATLANTIC_UTILS_FW_MSG_OFFLOAD_ADD 9U +#define HAL_ATLANTIC_UTILS_FW_MSG_OFFLOAD_DEL 10U +#define HAL_ATLANTIC_UTILS_FW_MSG_CABLE_DIAG 13U // 0xd + +#define SMBUS_READ_REQUEST BIT(13) +#define SMBUS_WRITE_REQUEST BIT(14) +#define SMBUS_DEVICE_ID 0x50 + +enum hw_atl_fw2x_rate { + FW2X_RATE_100M = 0x20, + FW2X_RATE_1G = 0x100, + FW2X_RATE_2G5 = 0x200, + FW2X_RATE_5G = 0x400, + FW2X_RATE_10G = 0x800, +}; + +enum hw_atl_fw2x_caps_lo { + CAPS_LO_10BASET_HD = 0x00, + CAPS_LO_10BASET_FD, + CAPS_LO_100BASETX_HD, + CAPS_LO_100BASET4_HD, + CAPS_LO_100BASET2_HD, + CAPS_LO_100BASETX_FD, + CAPS_LO_100BASET2_FD, + CAPS_LO_1000BASET_HD, + CAPS_LO_1000BASET_FD, + CAPS_LO_2P5GBASET_FD, + CAPS_LO_5GBASET_FD, + CAPS_LO_10GBASET_FD, +}; + +enum hw_atl_fw2x_caps_hi { + CAPS_HI_RESERVED1 = 0x00, + CAPS_HI_10BASET_EEE, + CAPS_HI_RESERVED2, + CAPS_HI_PAUSE, + CAPS_HI_ASYMMETRIC_PAUSE, + CAPS_HI_100BASETX_EEE, + CAPS_HI_RESERVED3, + CAPS_HI_RESERVED4, + CAPS_HI_1000BASET_FD_EEE, + CAPS_HI_2P5GBASET_FD_EEE, + CAPS_HI_5GBASET_FD_EEE, + CAPS_HI_10GBASET_FD_EEE, + CAPS_HI_RESERVED5, + CAPS_HI_RESERVED6, + CAPS_HI_RESERVED7, + CAPS_HI_RESERVED8, + CAPS_HI_RESERVED9, + CAPS_HI_CABLE_DIAG, + CAPS_HI_TEMPERATURE, + CAPS_HI_DOWNSHIFT, + CAPS_HI_PTP_AVB_EN, + CAPS_HI_MEDIA_DETECT, + CAPS_HI_LINK_DROP, + CAPS_HI_SLEEP_PROXY, + CAPS_HI_WOL, + CAPS_HI_MAC_STOP, + CAPS_HI_EXT_LOOPBACK, + CAPS_HI_INT_LOOPBACK, + CAPS_HI_EFUSE_AGENT, + CAPS_HI_WOL_TIMER, + CAPS_HI_STATISTICS, + CAPS_HI_TRANSACTION_ID, +}; + +struct aq_hw_s; +struct aq_fw_ops; +struct aq_hw_link_status_s; + +int hw_atl_utils_initfw(struct aq_hw_s *self, const struct aq_fw_ops **fw_ops); + +int hw_atl_utils_soft_reset(struct aq_hw_s *self); + +void hw_atl_utils_hw_chip_features_init(struct aq_hw_s *self, u32 *p); + +int hw_atl_utils_mpi_read_mbox(struct aq_hw_s *self, + struct hw_aq_atl_utils_mbox_header *pmbox); + +void hw_atl_utils_mpi_read_stats(struct aq_hw_s *self, + struct hw_aq_atl_utils_mbox *pmbox); + +void hw_atl_utils_mpi_set(struct aq_hw_s *self, + enum hal_atl_utils_fw_state_e state, + u32 speed); + +int hw_atl_utils_mpi_get_link_status(struct aq_hw_s *self); + +unsigned int hw_atl_utils_mbps_2_speed_index(unsigned int mbps); + +unsigned int hw_atl_utils_hw_get_reg_length(void); + +int hw_atl_utils_hw_get_regs(struct aq_hw_s *self, + u32 *regs_buff); + +int hw_atl_utils_hw_set_power(struct aq_hw_s *self, + unsigned int power_state); + +int hw_atl_utils_hw_deinit(struct aq_hw_s *self); + +int hw_atl_utils_get_fw_version(struct aq_hw_s *self, u32 *fw_version); + +int hw_atl_utils_update_stats(struct aq_hw_s *self); + +struct aq_stats_s *hw_atl_utils_get_hw_stats(struct aq_hw_s *self); + +int hw_atl_utils_fw_downld_dwords(struct aq_hw_s *self, u32 a, + u32 *p, u32 cnt); + +int hw_atl_utils_fw_upload_dwords(struct aq_hw_s *self, u32 a, u32 *p, + u32 cnt); + +int hw_atl_utils_fw_set_wol(struct aq_hw_s *self, bool wol_enabled, u8 *mac); + +int hw_atl_utils_fw_rpc_call(struct aq_hw_s *self, unsigned int rpc_size); + +int hw_atl_utils_fw_rpc_wait(struct aq_hw_s *self, + struct hw_aq_atl_utils_fw_rpc **rpc); + +extern const struct aq_fw_ops aq_fw_1x_ops; +extern const struct aq_fw_ops aq_fw_2x_ops; + +#endif /* HW_ATL_UTILS_H */ diff --git a/drivers/net/atlantic/hw_atl/hw_atl_utils_fw2x.c b/drivers/net/atlantic/hw_atl/hw_atl_utils_fw2x.c new file mode 100644 index 000000000000..6841d9bce39c --- /dev/null +++ b/drivers/net/atlantic/hw_atl/hw_atl_utils_fw2x.c @@ -0,0 +1,618 @@ +// SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) +/* Copyright (C) 2014-2017 aQuantia Corporation. */ + +/* File hw_atl_utils_fw2x.c: Definition of firmware 2.x functions for + * Atlantic hardware abstraction layer. + */ + +#include +#include "../atl_hw_regs.h" + +#include "../atl_types.h" +#include "hw_atl_utils.h" +#include "hw_atl_llh.h" + +#define HW_ATL_FW2X_MPI_EFUSE_ADDR 0x364 +#define HW_ATL_FW2X_MPI_MBOX_ADDR 0x360 +#define HW_ATL_FW2X_MPI_RPC_ADDR 0x334 + +#define HW_ATL_FW2X_MPI_CONTROL_ADDR 0x368 +#define HW_ATL_FW2X_MPI_CONTROL2_ADDR 0x36C +#define HW_ATL_FW2X_MPI_LED_ADDR 0x31c + +#define HW_ATL_FW2X_MPI_STATE_ADDR 0x370 +#define HW_ATL_FW2X_MPI_STATE2_ADDR 0x374 + +#define HW_ATL_FW2X_CAP_SLEEP_PROXY BIT(CAPS_HI_SLEEP_PROXY) +#define HW_ATL_FW2X_CAP_WOL BIT(CAPS_HI_WOL) + +#define HW_ATL_FW2X_CAP_EEE_1G_MASK BIT(CAPS_HI_1000BASET_FD_EEE) +#define HW_ATL_FW2X_CAP_EEE_2G5_MASK BIT(CAPS_HI_2P5GBASET_FD_EEE) +#define HW_ATL_FW2X_CAP_EEE_5G_MASK BIT(CAPS_HI_5GBASET_FD_EEE) +#define HW_ATL_FW2X_CAP_EEE_10G_MASK BIT(CAPS_HI_10GBASET_FD_EEE) + +#define HAL_ATLANTIC_WOL_FILTERS_COUNT 8 +#define HAL_ATLANTIC_UTILS_FW2X_MSG_WOL 0x0E + +#define HW_ATL_FW_FEATURE_EEPROM 0x03010025 +#define HW_ATL_FW_FEATURE_LED 0x03010026 + +struct fw2x_msg_wol_pattern { + u8 mask[16]; + u32 crc; +} __attribute__((__packed__)); + +struct fw2x_msg_wol { + u32 msg_id; + u8 hw_addr[6]; + u8 magic_packet_enabled; + u8 filter_count; + struct fw2x_msg_wol_pattern filter[HAL_ATLANTIC_WOL_FILTERS_COUNT]; + u8 link_up_enabled; + u8 link_down_enabled; + u16 reserved; + u32 link_up_timeout; + u32 link_down_timeout; +} __attribute__((__packed__)); + +static int aq_fw2x_set_link_speed(struct aq_hw_s *self, u32 speed); +static int aq_fw2x_set_state(struct aq_hw_s *self, + enum hal_atl_utils_fw_state_e state); + +static int aq_fw2x_init(struct aq_hw_s *self) +{ + int err = 0; + + /* check 10 times by 1ms */ + AQ_HW_WAIT_FOR(0U != (self->mbox_addr = + aq_hw_read_reg(self, HW_ATL_FW2X_MPI_MBOX_ADDR)), + 1000U, 10U); + AQ_HW_WAIT_FOR(0U != (self->rpc_addr = + aq_hw_read_reg(self, HW_ATL_FW2X_MPI_RPC_ADDR)), + 1000U, 100U); + return err; +} + +static int aq_fw2x_deinit(struct aq_hw_s *self) +{ + int err = aq_fw2x_set_link_speed(self, 0); + + if (!err) + err = aq_fw2x_set_state(self, MPI_DEINIT); + + return err; +} + +static enum hw_atl_fw2x_rate link_speed_mask_2fw2x_ratemask(u32 speed) +{ + enum hw_atl_fw2x_rate rate = 0; + + if (speed & AQ_NIC_RATE_10G) + rate |= FW2X_RATE_10G; + + if (speed & AQ_NIC_RATE_5G) + rate |= FW2X_RATE_5G; + + if (speed & AQ_NIC_RATE_5G5R) + rate |= FW2X_RATE_5G; + + if (speed & AQ_NIC_RATE_2G5) + rate |= FW2X_RATE_2G5; + + if (speed & AQ_NIC_RATE_1G) + rate |= FW2X_RATE_1G; + + if (speed & AQ_NIC_RATE_100M) + rate |= FW2X_RATE_100M; + + return rate; +} + +static u32 fw2x_to_eee_mask(u32 speed) +{ + u32 rate = 0; + + if (speed & HW_ATL_FW2X_CAP_EEE_10G_MASK) + rate |= AQ_NIC_RATE_EEE_10G; + + if (speed & HW_ATL_FW2X_CAP_EEE_5G_MASK) + rate |= AQ_NIC_RATE_EEE_5G; + + if (speed & HW_ATL_FW2X_CAP_EEE_2G5_MASK) + rate |= AQ_NIC_RATE_EEE_2G5; + + if (speed & HW_ATL_FW2X_CAP_EEE_1G_MASK) + rate |= AQ_NIC_RATE_EEE_1G; + + return rate; +} + +static int aq_fw2x_set_link_speed(struct aq_hw_s *self, u32 speed) +{ + u32 val = link_speed_mask_2fw2x_ratemask(speed); + + aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL_ADDR, val); + + return 0; +} + +static void aq_fw2x_set_mpi_flow_control(struct aq_hw_s *self, u32 *mpi_state) +{ + if (self->aq_nic_cfg->flow_control & AQ_NIC_FC_RX) + *mpi_state |= BIT(CAPS_HI_PAUSE); + else + *mpi_state &= ~BIT(CAPS_HI_PAUSE); + + if (self->aq_nic_cfg->flow_control & AQ_NIC_FC_TX) + *mpi_state |= BIT(CAPS_HI_ASYMMETRIC_PAUSE); + else + *mpi_state &= ~BIT(CAPS_HI_ASYMMETRIC_PAUSE); +} + +static int aq_fw2x_set_state(struct aq_hw_s *self, + enum hal_atl_utils_fw_state_e state) +{ + u32 mpi_state = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR); + + switch (state) { + case MPI_INIT: + mpi_state &= ~BIT(CAPS_HI_LINK_DROP); + aq_fw2x_set_mpi_flow_control(self, &mpi_state); + break; + case MPI_DEINIT: + mpi_state |= BIT(CAPS_HI_LINK_DROP); + break; + case MPI_RESET: + case MPI_POWER: + /* No actions */ + break; + } + aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_state); + return 0; +} + +static int aq_fw2x_update_link_status(struct aq_hw_s *self) +{ + u32 mpi_state = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE_ADDR); + u32 speed = mpi_state & (FW2X_RATE_100M | FW2X_RATE_1G | + FW2X_RATE_2G5 | FW2X_RATE_5G | FW2X_RATE_10G); + struct aq_hw_link_status_s *link_status = &self->aq_link_status; + + if (speed) { + if (speed & FW2X_RATE_10G) + link_status->mbps = 10000; + else if (speed & FW2X_RATE_5G) + link_status->mbps = 5000; + else if (speed & FW2X_RATE_2G5) + link_status->mbps = 2500; + else if (speed & FW2X_RATE_1G) + link_status->mbps = 1000; + else if (speed & FW2X_RATE_100M) + link_status->mbps = 100; + else + link_status->mbps = 10000; + } else { + link_status->mbps = 0; + } + + return 0; +} + +static +int aq_fw2x_get_mac_permanent(struct aq_hw_s *self, u8 *mac) +{ + int err = 0; + u32 h = 0U; + u32 l = 0U; + u32 mac_addr[2] = { 0 }; + u32 efuse_addr = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_EFUSE_ADDR); + + if (efuse_addr != 0) { + err = hw_atl_utils_fw_downld_dwords(self, + efuse_addr + (40U * 4U), + mac_addr, + ARRAY_SIZE(mac_addr)); + if (err) + return err; + mac_addr[0] = rte_constant_bswap32(mac_addr[0]); + mac_addr[1] = rte_constant_bswap32(mac_addr[1]); + } + + ether_addr_copy((struct ether_addr *)mac_addr, + (struct ether_addr *)mac); + + if ((mac[0] & 0x01U) || ((mac[0] | mac[1] | mac[2]) == 0x00U)) { + unsigned int rnd = (uint32_t)rte_rand(); + + //get_random_bytes(&rnd, sizeof(unsigned int)); + + l = 0xE3000000U + | (0xFFFFU & rnd) + | (0x00 << 16); + h = 0x8001300EU; + + mac[5] = (u8)(0xFFU & l); + l >>= 8; + mac[4] = (u8)(0xFFU & l); + l >>= 8; + mac[3] = (u8)(0xFFU & l); + l >>= 8; + mac[2] = (u8)(0xFFU & l); + mac[1] = (u8)(0xFFU & h); + h >>= 8; + mac[0] = (u8)(0xFFU & h); + } + return err; +} + +static int aq_fw2x_update_stats(struct aq_hw_s *self) +{ + int err = 0; + u32 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR); + u32 orig_stats_val = mpi_opts & BIT(CAPS_HI_STATISTICS); + + /* Toggle statistics bit for FW to update */ + mpi_opts = mpi_opts ^ BIT(CAPS_HI_STATISTICS); + aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts); + + /* Wait FW to report back */ + AQ_HW_WAIT_FOR(orig_stats_val != + (aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE2_ADDR) & + BIT(CAPS_HI_STATISTICS)), + 1U, 10000U); + if (err) + return err; + + return hw_atl_utils_update_stats(self); +} + +static int aq_fw2x_get_temp(struct aq_hw_s *self, int *temp) +{ + int err = 0; + u32 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR); + u32 temp_val = mpi_opts & BIT(CAPS_HI_TEMPERATURE); + u32 temp_res; + + /* Toggle statistics bit for FW to 0x36C.18 (CAPS_HI_TEMPERATURE) */ + mpi_opts = mpi_opts ^ BIT(CAPS_HI_TEMPERATURE); + aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts); + + /* Wait FW to report back */ + AQ_HW_WAIT_FOR(temp_val != + (aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE2_ADDR) & + BIT(CAPS_HI_TEMPERATURE)), 1U, 10000U); + err = hw_atl_utils_fw_downld_dwords(self, + self->mbox_addr + + offsetof(struct hw_aq_atl_utils_mbox, info) + + offsetof(struct hw_aq_info, phy_temperature), + &temp_res, + sizeof(temp_res) / sizeof(u32)); + + if (err) + return err; + + *temp = temp_res * 100 / 256; + return 0; +} + +static int aq_fw2x_get_cable_len(struct aq_hw_s *self, int *cable_len) +{ + int err = 0; + u32 cable_len_res; + + err = hw_atl_utils_fw_downld_dwords(self, + self->mbox_addr + + offsetof(struct hw_aq_atl_utils_mbox, info) + + offsetof(struct hw_aq_info, phy_temperature), + &cable_len_res, + sizeof(cable_len_res) / sizeof(u32)); + + if (err) + return err; + + *cable_len = (cable_len_res >> 16) & 0xFF; + return 0; +} + +#ifndef ETH_ALEN +#define ETH_ALEN 6 +#endif + +static int aq_fw2x_set_sleep_proxy(struct aq_hw_s *self, u8 *mac) +{ + int err = 0; + struct hw_aq_atl_utils_fw_rpc *rpc = NULL; + struct offload_info *cfg = NULL; + unsigned int rpc_size = 0U; + u32 mpi_opts; + + rpc_size = sizeof(rpc->msg_id) + sizeof(*cfg); + + err = hw_atl_utils_fw_rpc_wait(self, &rpc); + if (err < 0) + goto err_exit; + + memset(rpc, 0, rpc_size); + cfg = (struct offload_info *)(&rpc->msg_id + 1); + + memcpy(cfg->mac_addr, mac, ETH_ALEN); + cfg->len = sizeof(*cfg); + + /* Clear bit 0x36C.23 */ + mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR); + mpi_opts &= ~HW_ATL_FW2X_CAP_SLEEP_PROXY; + + aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts); + + err = hw_atl_utils_fw_rpc_call(self, rpc_size); + if (err < 0) + goto err_exit; + + /* Set bit 0x36C.23 */ + mpi_opts |= HW_ATL_FW2X_CAP_SLEEP_PROXY; + aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts); + + AQ_HW_WAIT_FOR((aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE2_ADDR) & + HW_ATL_FW2X_CAP_SLEEP_PROXY), 1U, 10000U); +err_exit: + return err; +} + +static int aq_fw2x_set_wol_params(struct aq_hw_s *self, u8 *mac) +{ + int err = 0; + struct fw2x_msg_wol *msg = NULL; + u32 mpi_opts; + + struct hw_aq_atl_utils_fw_rpc *rpc = NULL; + + err = hw_atl_utils_fw_rpc_wait(self, &rpc); + if (err < 0) + goto err_exit; + + msg = (struct fw2x_msg_wol *)rpc; + + msg->msg_id = HAL_ATLANTIC_UTILS_FW2X_MSG_WOL; + msg->magic_packet_enabled = true; + memcpy(msg->hw_addr, mac, ETH_ALEN); + + mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR); + mpi_opts &= ~(HW_ATL_FW2X_CAP_SLEEP_PROXY | HW_ATL_FW2X_CAP_WOL); + + aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts); + + err = hw_atl_utils_fw_rpc_call(self, sizeof(*msg)); + if (err < 0) + goto err_exit; + + /* Set bit 0x36C.24 */ + mpi_opts |= HW_ATL_FW2X_CAP_WOL; + aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts); + + AQ_HW_WAIT_FOR((aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE2_ADDR) & + HW_ATL_FW2X_CAP_WOL), 1U, 10000U); +err_exit: + return err; +} + +static int aq_fw2x_set_power(struct aq_hw_s *self, + unsigned int power_state __rte_unused, + u8 *mac) +{ + int err = 0; + + if (self->aq_nic_cfg->wol & AQ_NIC_WOL_ENABLED) { + err = aq_fw2x_set_sleep_proxy(self, mac); + if (err < 0) + goto err_exit; + err = aq_fw2x_set_wol_params(self, mac); + if (err < 0) + goto err_exit; + } +err_exit: + return err; +} + +static int aq_fw2x_set_eee_rate(struct aq_hw_s *self, u32 speed) +{ + u32 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR); + mpi_opts &= ~(HW_ATL_FW2X_CAP_EEE_1G_MASK | + HW_ATL_FW2X_CAP_EEE_2G5_MASK | HW_ATL_FW2X_CAP_EEE_5G_MASK | + HW_ATL_FW2X_CAP_EEE_10G_MASK); + + if (speed & AQ_NIC_RATE_EEE_10G) + mpi_opts |= HW_ATL_FW2X_CAP_EEE_10G_MASK; + + if (speed & AQ_NIC_RATE_EEE_5G) + mpi_opts |= HW_ATL_FW2X_CAP_EEE_5G_MASK; + + if (speed & AQ_NIC_RATE_EEE_2G5) + mpi_opts |= HW_ATL_FW2X_CAP_EEE_2G5_MASK; + + if (speed & AQ_NIC_RATE_EEE_1G) + mpi_opts |= HW_ATL_FW2X_CAP_EEE_1G_MASK; + + aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts); + + return 0; +} + +static int aq_fw2x_get_eee_rate(struct aq_hw_s *self, u32 *rate, + u32 *supported_rates) +{ + int err = 0; + u32 caps_hi; + u32 mpi_state; + + err = hw_atl_utils_fw_downld_dwords(self, + self->mbox_addr + + offsetof(struct hw_aq_atl_utils_mbox, info) + + offsetof(struct hw_aq_info, caps_hi), + &caps_hi, + sizeof(caps_hi) / sizeof(u32)); + + if (err) + return err; + + *supported_rates = fw2x_to_eee_mask(caps_hi); + + mpi_state = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE2_ADDR); + *rate = fw2x_to_eee_mask(mpi_state); + + return err; +} + + + +static int aq_fw2x_set_flow_control(struct aq_hw_s *self) +{ + u32 mpi_state = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR); + + aq_fw2x_set_mpi_flow_control(self, &mpi_state); + + aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_state); + + return 0; +} + +static int aq_fw2x_led_control(struct aq_hw_s *self, u32 mode) +{ + if (self->fw_ver_actual < HW_ATL_FW_FEATURE_LED) + return -EOPNOTSUPP; + + aq_hw_write_reg(self, HW_ATL_FW2X_MPI_LED_ADDR, mode); + return 0; +} + +static int aq_fw2x_get_eeprom(struct aq_hw_s *self, u32 *data, u32 len) +{ + int err = 0; + struct smbus_read_request request; + u32 mpi_opts; + u32 result = 0; + + if (self->fw_ver_actual < HW_ATL_FW_FEATURE_EEPROM) + return -EOPNOTSUPP; + + request.device_id = SMBUS_DEVICE_ID; + request.address = 0; + request.length = len; + + /* Write SMBUS request to cfg memory */ + err = hw_atl_utils_fw_upload_dwords(self, self->rpc_addr, + (u32 *)(void *)&request, + RTE_ALIGN(sizeof(request), sizeof(u32))); + + if (err < 0) + return err; + + /* Toggle 0x368.SMBUS_READ_REQUEST bit */ + mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL_ADDR); + mpi_opts ^= SMBUS_READ_REQUEST; + + aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL_ADDR, mpi_opts); + + /* Wait until REQUEST_BIT matched in 0x370 */ + + AQ_HW_WAIT_FOR((aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE_ADDR) & + SMBUS_READ_REQUEST) == (mpi_opts & SMBUS_READ_REQUEST), + 10U, 10000U); + + if (err < 0) + return err; + + err = hw_atl_utils_fw_downld_dwords(self, self->rpc_addr + sizeof(u32), + &result, + RTE_ALIGN(sizeof(result), sizeof(u32))); + + if (err < 0) + return err; + + if (result == 0) { + err = hw_atl_utils_fw_downld_dwords(self, + self->rpc_addr + sizeof(u32) * 2, + data, + RTE_ALIGN(len, sizeof(u32))); + + if (err < 0) + return err; + } + + return 0; +} + + +static int aq_fw2x_set_eeprom(struct aq_hw_s *self, u32 *data, u32 len) +{ + struct smbus_write_request request; + u32 mpi_opts, result = 0; + int err = 0; + + if (self->fw_ver_actual < HW_ATL_FW_FEATURE_EEPROM) + return -EOPNOTSUPP; + + request.device_id = SMBUS_DEVICE_ID; + request.address = 0; + request.length = len; + + /* Write SMBUS request to cfg memory */ + err = hw_atl_utils_fw_upload_dwords(self, self->rpc_addr, + (u32 *)(void *)&request, + RTE_ALIGN(sizeof(request), sizeof(u32))); + + if (err < 0) + return err; + + /* Write SMBUS data to cfg memory */ + err = hw_atl_utils_fw_upload_dwords(self, + self->rpc_addr + sizeof(request), + (u32 *)(void *)data, + RTE_ALIGN(len, sizeof(u32))); + + if (err < 0) + return err; + + /* Toggle 0x368.SMBUS_WRITE_REQUEST bit */ + mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL_ADDR); + mpi_opts ^= SMBUS_WRITE_REQUEST; + + aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL_ADDR, mpi_opts); + + /* Wait until REQUEST_BIT matched in 0x370 */ + AQ_HW_WAIT_FOR((aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE_ADDR) & + SMBUS_WRITE_REQUEST) == (mpi_opts & SMBUS_WRITE_REQUEST), + 10U, 10000U); + + if (err < 0) + return err; + + /* Read status of write operation */ + err = hw_atl_utils_fw_downld_dwords(self, self->rpc_addr + sizeof(u32), + &result, + RTE_ALIGN(sizeof(result), sizeof(u32))); + + if (err < 0) + return err; + + return 0; +} + +const struct aq_fw_ops aq_fw_2x_ops = { + .init = aq_fw2x_init, + .deinit = aq_fw2x_deinit, + .reset = NULL, + .get_mac_permanent = aq_fw2x_get_mac_permanent, + .set_link_speed = aq_fw2x_set_link_speed, + .set_state = aq_fw2x_set_state, + .update_link_status = aq_fw2x_update_link_status, + .update_stats = aq_fw2x_update_stats, + .set_power = aq_fw2x_set_power, + .get_temp = aq_fw2x_get_temp, + .get_cable_len = aq_fw2x_get_cable_len, + .set_eee_rate = aq_fw2x_set_eee_rate, + .get_eee_rate = aq_fw2x_get_eee_rate, + .set_flow_control = aq_fw2x_set_flow_control, + .led_control = aq_fw2x_led_control, + .get_eeprom = aq_fw2x_get_eeprom, + .set_eeprom = aq_fw2x_set_eeprom, +}; diff --git a/drivers/net/atlantic/meson.build b/drivers/net/atlantic/meson.build index f3193b75b650..919cf6e4f20a 100644 --- a/drivers/net/atlantic/meson.build +++ b/drivers/net/atlantic/meson.build @@ -7,6 +7,8 @@ sources = files( 'atl_ethdev.c', 'atl_hw_regs.c', 'hw_atl/hw_atl_llh.c', + 'hw_atl/hw_atl_utils_fw2x.c', + 'hw_atl/hw_atl_utils.c', ) deps += ['eal'] From patchwork Sat Sep 29 10:30:20 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Russkikh X-Patchwork-Id: 45670 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id B83D41B19A; Sat, 29 Sep 2018 12:31:39 +0200 (CEST) Received: from NAM05-DM3-obe.outbound.protection.outlook.com (mail-eopbgr730056.outbound.protection.outlook.com [40.107.73.56]) by dpdk.org (Postfix) with ESMTP id CA6381B184 for ; Sat, 29 Sep 2018 12:31:37 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=AQUANTIA1COM.onmicrosoft.com; s=selector1-aquantia-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=T3YOTB3FQDo/uhFN8DV8T56/x0YhCzyWuF/kCw2Jl10=; b=ZUzBJJrgithimEbHBINnuYgTGx/oaNMqCQisvD+EgontSFLnS96Rsu3euS1rNXIBV2YJBGurrUjUQAUWhVZ7SvaYoGEEr0WW7fnfpwsuLlrz8AzmjAfSLMPu0HoaytBYoJZUEzxclUGidmovXKR6rG78ceinXUgf9z1UOymvVAk= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Igor.Russkikh@aquantia.com; Received: from ubuntubox.rdc.aquantia.com (95.79.108.179) by BLUPR0701MB1650.namprd07.prod.outlook.com (2a01:111:e400:58c6::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1185.22; Sat, 29 Sep 2018 10:31:30 +0000 From: Igor Russkikh To: dev@dpdk.org Cc: pavel.belous@aquantia.com, igor.russkikh@aquantia.com, Pavel Belous Date: Sat, 29 Sep 2018 13:30:20 +0300 Message-Id: <82654080404ee4f32f0d0517495465e24d956b0f.1538215990.git.igor.russkikh@aquantia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [95.79.108.179] X-ClientProxiedBy: VI1P193CA0009.EURP193.PROD.OUTLOOK.COM (2603:10a6:800:bd::19) To BLUPR0701MB1650.namprd07.prod.outlook.com (2a01:111:e400:58c6::20) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 0123c1ec-46fa-4645-bdd2-08d625f6bbc1 X-Microsoft-Antispam: BCL:0; PCL:0; RULEID:(7020095)(4652040)(8989299)(4534165)(4627221)(201703031133081)(201702281549075)(8990200)(5600074)(711020)(2017052603328)(7153060)(7193020); SRVR:BLUPR0701MB1650; X-Microsoft-Exchange-Diagnostics: 1; BLUPR0701MB1650; 3:R07OxbT9ah9AtSERBLzyojNRXfiGnX7xh41GwJA+Rul+0HRr+XE6zCS1Mzhs1vgJDTJJHe1U47AW1yI2lLO21VBl++duqVfOtDymnl86nOMXJ4IawfoEgXEqrpkAeVgb8WAo5jS1Gonop1pTahjnUjxrxJF2ccrSUu3LP8ZdrlRGSiSo0enOkvM8+ArjqdlG4VSVBh5OOpSKCYV3S4/rXok+tHsRdkVX66Ys9lMq8kFJGanfPFj0MoOnhyPjneSm; 25:xbTktwvt9dGu6KXYatWPqMzPiaSNWpLz6pxU8GLe4DIpN1iId8EEirUdmjKD+ePADplfUGvS234TH7ZcLNNWIiJ0GxNAy2jgfxdiNeW0L8jyhljra/0WK5py0vy92RAoZj0AP0VpG8uCF7mO0RExSSrrZMOLDZYFiILjw4vUcwI0DA0554GUUDvDmOEWnXPXqfV3bNElFzVP6nk/dVJ2rah0XdRiwXWlEMC7QxBn7lJNaY5KsNKmmeCobHe/+hOZT+VDUjnivjl808d7LTxVH/ncSKLb/iDbBmhT2hkrju5FqcpwzTi0MUOvX+FAFtv+aPFEbL74yrO0msQ/MkLT+eXv9jabSonPCfnc5+nNHQs=; 31:ilikX6JYl4yOclyguyaqeUnij2B9uxgmw1sZjfDgm61PAzFVc5yofZfYr27hP39gd65p2lD8w0YWnDRbvonjtHPdLukf864Q1jZsYfhOS6dhh7Rrk4d7YkQV6RGzJHnuLKo67nlFRjNqLF40/dl7Y9/2t4m9Y7vaX4ild4iFPEwnZuQvWURUW0jWEK5+ayMQq97iabUP4w9v+NNOVss+OluOggO8/WBZiHW+Rnu8VMw= X-MS-TrafficTypeDiagnostic: BLUPR0701MB1650: X-Microsoft-Exchange-Diagnostics: 1; BLUPR0701MB1650; 20:P8jBupx1ntQkdBR5E7dUa4EHliqyRC9HvfkuNDOvhAoVSVvklyQDI/WBluRANC5fZYAc+0axTgnrJNmJvA3J5c0+j5iD/CRHf0C//poHfrWYQMfywoKwvOENIMEgAwn+LQ2VjKXkDppZrKqk+0HB75OFFgrrhQ93zhq9DjYi8WLaAFVvXoEBPzwg0De8chTjmuV9AbRzNmh8x5y6Dhevs0iNkRcZowZGXbjM8mj05f3KvE8oXzOrwGYCWogTROlFu1vqdnDCuUDNO8+cfZcuzR16nlcrj7IEl4yxa+YDdJ60JAEUKFvA22O9Wc2Ae4hQbeF+44iWWdwZmO+bOfIJExkdtZXcxvuToJuoCzpiWbFxhGaIO4qzaGcjEf7zY3kbWyBbey9DAdlx7sbOAx/0y1Jg71qIzOkrUF0mth0BYD6szJAxdLNmgCgo287kVll0u/bFgRLpQNBXLhmXDlbyLlk5/4jpTi4sk6u9RVJSVUAqsne6gWQ6dvFIxE/daVCV; 4:s7TJai+2ycr0zfLgs1BAv4JarNfIES+Ejh9VWRP1SCI5ZrzR2aL806xp1v6JD4ZLUHCsaWxw9wHhHFLR3rN1Llzt/pqKKKQBb0kbv6ZOAzJggkyXKNdO39gtEJfESg9IWsJ+UozJvxx6dYm2ccxSAcSm7fBCT53Gc6rD/BHVURkF8uBPvLQ1hYv84zAI4oekkpYP4MaOPrypgEhshE8Y78V6I2UJvVVtcXGvHLVGOGsCp7HQARDo3zHrxZmufWR6YR2GuWXeoLzZbVJlujnrFA== X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-MS-Exchange-SenderADCheck: 1 X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(6040522)(2401047)(8121501046)(5005006)(10201501046)(3002001)(93006095)(93001095)(3231355)(944501410)(52105095)(149066)(150057)(6041310)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123558120)(20161123564045)(20161123562045)(20161123560045)(201708071742011)(7699051); SRVR:BLUPR0701MB1650; BCL:0; PCL:0; RULEID:; SRVR:BLUPR0701MB1650; X-Forefront-PRVS: 0810818DA0 X-Forefront-Antispam-Report: SFV:NSPM; SFS:(10009020)(346002)(136003)(396003)(376002)(39850400004)(366004)(189003)(199004)(16526019)(14444005)(446003)(76176011)(2906002)(6916009)(6666003)(97736004)(8676002)(81166006)(81156014)(36756003)(4326008)(316002)(8936002)(50226002)(34290500001)(575784001)(86362001)(5660300001)(68736007)(16586007)(118296001)(72206003)(3846002)(6116002)(53936002)(386003)(105586002)(6486002)(47776003)(66066001)(486006)(25786009)(305945005)(50466002)(44832011)(956004)(2616005)(26005)(107886003)(52116002)(51416003)(7696005)(186003)(476003)(478600001)(2361001)(7736002)(2351001)(48376002)(106356001)(11346002); DIR:OUT; SFP:1101; SCL:1; SRVR:BLUPR0701MB1650; H:ubuntubox.rdc.aquantia.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; Received-SPF: None (protection.outlook.com: aquantia.com does not designate permitted sender hosts) X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; BLUPR0701MB1650; 23:qaAtOm8AbAfPw7wu+/BepDuqD+eNG9cDVySPQMI?= r542+RRYu/2wqIhSQuMgMU0SBzA01XxxiQ7CuQiGragqTA7DP/jk1jJbt7CIoZXb8OgJmCN/6QCQ8HEuqIi5dz4VDrZdpNjd9PLDoDU6RicandX/CsOZDc1i8sgvgC22afTHcstVPxD+cCwayFwT/GVMUlMliJ1PVm/akqVcrrgJIKQDq8xYc9TGm55V6tqqBzLKtbScLpaN/X29Zqi7maMPlb39ekRY7g/1dDEL50xU3bQR24qwIxn8urR4NIklkQTPtlybJrWQ+heiEVKnGMqAh9Lmj+eZBsXkQLceqYIMZSsLwXnqNAxtvDmRVmNjnOWcktAb/pYvbWfqj8p+gK2HUJi+sF2oPkRSV7+VoMw6EeXjJUXahonYZ/iQ5BIe92pmVDLdgwSDppYT7UdBSFrysQM5KDK3ahgQAN4Qd5ljSZ7nQrRjA092l48qLIDUUE7rU+Uh/8nbdGcG5N3L2WnXlsnCrbKk2PVJT3la7pxGzlnYGVDBhssUq7qqYxwCQ16N9XX3xA5OyYHUy45VO4YhsrxsFTjejDgsMO7ARxweUiBMjr2NfB3VAP2td0ItIEoERTTAoO76XIv/54hbpmga4Oj1N4XAFMtMLgAgnGKXHp/1yFM4oWs05QRvvRkJ8K8sFg7qxkkz31yAkYcu2dvIzf5krGb+58nMiHNaS8w6wuxdTFfQ9rjZjeWvtaASNKtng8GAB78PLGy6ORctRz2yTas3umsLoPChCad/h9EWNgJ8toSZU8/myQktgXt6vC4UF8s1sn7IdIDNgFtReh59IM/2TM+D4qC1YOpQNZZ73p78rPzbqOhlWaX31EZ7Mq3B9BcLmP+7L1nV+30DNOI1R/jhbJgKYlnZNQYeRyyIN1QIKDA7ZINae6vUlMQhOt4DnfHFu0FKDkWv2sYCtVr21ORDOwHD/nsiwGJAuYMdYZ79fogEx2eQStCag1yf5o7TIWEHfOxADbUWQ06CTCq5wd6kQaMlNpvg1f2gFmRnht0epECRggFavAtxFjIvOeXnYbIdSYMo0YEJrYPV0NsmX+jBPtau7CSXmWq0l0RIw8YoBgoIlggm4bzGKJ81MVynL0lQ6fDaDGnGZGVEWJMj1bAmj1VMHIC9U7i3akJn/0khn7HdZ1hekh+kE8DOXmb4elYHbsiQSf+M5MjzEtuZIY6yEAPpYuSQhprxPfNw5UDhzS9Iw26b7iqwCPVkPMC3GB8W4zzHw6HbhmAZKvWJ4DrW1fQr3X7UDcLDLo59ge4NLqRcLROOKThiUWsrYZofT7x3nQZGnagrEMVdH087x X-Microsoft-Antispam-Message-Info: F3AFFpFgTpIyiJBLnFxQunr4sm9Pdx2fQeHVb29mYCzkU7EE7P1nCxWNK0yVPO/DIJxBJX0kYdM3bd891+4ykoEJq3wiIapTxOh+VmCCxAkQajWXlWsG7e/r1S8qcNuZwjB7HaT2wX8xnL/j/+nqPJ8s7IGShuPcpaAJhV7NsKGbEqWQiDLzaufK4uFWIVTvmYH+OU7hyBHBx4d+Orksh/tx+RwFKGKhl17AFJrrICzCYqhg0j+OJG41fy0ZW8sicJQBHow2BV2uvE8llbljOUbXwKG9Sq7miSq1MNcHH9gGpn98cDW3sEMLthwUDDUcnwzoSjappqysuu1HOnDenSCA8Bz3POJcV5pa40Swa28= X-Microsoft-Exchange-Diagnostics: 1; BLUPR0701MB1650; 6:IAmDdIS8M5Aj5Y0AI7lc+00L8vPUIOZ/o5Esxqmhyy4gkr2VKlitfeYk7qGL0uwDKUOZEGc9fepn0iyPHrP/bEuAjVdlfu1ofmm2JVLaXId2OAbbLcFatV8V7w7nRMAKbvcFvMENhe6cl5a15DEsCZZmxZqRHTDIJ5VWpuUpcmnYg6jwlrcmSPxAYevSCYRehTAKlsfVYox+sT7FHwBPcMiV0Tsak9YNNxHhb49ukqGO6hPGeBZJV4qlNUBqNJlRs/IGz1BcoSDXVH51E68MqRfDdYQzT5kkCw0FKPPtM8SPV62ccyYtV+WTerGkjsPxK0R2ADFDbQQUqqRRqg5bodjzjvfOMmPY7dWLIA/gpjFc5Bow/QGWHEZBx4xNueh1wPzlA/SAnAcJz+c727ja9TCFeuZLUNRc1JxLqHGGGTs5nwx+IoQY4Efh0+tw/N6XfHp4YJow9oDYupUfEB9eXA==; 5:TR/EwTbMMyLsNCGVWQ+KUOAvewg9Y9oDg0pMJAkbMYc8BZTJFjV74Pu61L7wuygNvvm73u/7gevqRR4GTH7iDDRDqWDDGolGAjkZTD05hCjL0ElkSnjYcwohBGg7MU+mLLz7FiLO65gHyS1lDiQ7ry8wYyCx8jEDY9tQXWAIGjs=; 7:dysLOls7YS4jGonTSZ93+Divi/zFSwJT8UtJ7JBaRl6nmhsd0T74D8y85wrwshuQkLSzIQ+Ygz96tvGWGQCOp3eLgbrJufIsiC07or090x0tXtzG+Q8UfuHt0YF7Chsp7n0uz51u5SIqO0qfYh2vArXTsdumav4nVcW5ZaQk9SNuSIix8+VvHV6aY9riTNH37jnPlMccMc+ySEmHlAEJs9QauZoR2sa/SH02pr9gq0rgSrSen5viSKMF1d9q9oB0 SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: aquantia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Sep 2018 10:31:30.0938 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0123c1ec-46fa-4645-bdd2-08d625f6bbc1 X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 83e2e134-991c-4ede-8ced-34d47e38e6b1 X-MS-Exchange-Transport-CrossTenantHeadersStamped: BLUPR0701MB1650 Subject: [dpdk-dev] [PATCH v3 06/22] net/atlantic: b0 hardware layer main logic X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This is hw_atl logic layer derived from linux atlantic driver. It contains RX/TX hardware initialization sequences, various hw configuration. Signed-off-by: Igor Russkikh Signed-off-by: Pavel Belous --- drivers/net/atlantic/Makefile | 1 + drivers/net/atlantic/atl_types.h | 14 + drivers/net/atlantic/hw_atl/hw_atl_b0.c | 510 +++++++++++++++++++++++ drivers/net/atlantic/hw_atl/hw_atl_b0.h | 40 ++ drivers/net/atlantic/hw_atl/hw_atl_b0_internal.h | 145 +++++++ drivers/net/atlantic/meson.build | 1 + 6 files changed, 711 insertions(+) create mode 100644 drivers/net/atlantic/hw_atl/hw_atl_b0.c create mode 100644 drivers/net/atlantic/hw_atl/hw_atl_b0.h create mode 100644 drivers/net/atlantic/hw_atl/hw_atl_b0_internal.h diff --git a/drivers/net/atlantic/Makefile b/drivers/net/atlantic/Makefile index a291053b5ab7..91306d71ba97 100644 --- a/drivers/net/atlantic/Makefile +++ b/drivers/net/atlantic/Makefile @@ -29,5 +29,6 @@ SRCS-$(CONFIG_RTE_LIBRTE_ATLANTIC_PMD) += atl_hw_regs.c SRCS-$(CONFIG_RTE_LIBRTE_ATLANTIC_PMD) += hw_atl_utils.c SRCS-$(CONFIG_RTE_LIBRTE_ATLANTIC_PMD) += hw_atl_llh.c SRCS-$(CONFIG_RTE_LIBRTE_ATLANTIC_PMD) += hw_atl_utils_fw2x.c +SRCS-$(CONFIG_RTE_LIBRTE_ATLANTIC_PMD) += hw_atl_b0.c include $(RTE_SDK)/mk/rte.lib.mk diff --git a/drivers/net/atlantic/atl_types.h b/drivers/net/atlantic/atl_types.h index 589088a82227..8185a86e1733 100644 --- a/drivers/net/atlantic/atl_types.h +++ b/drivers/net/atlantic/atl_types.h @@ -8,6 +8,7 @@ #include #include #include +#include typedef uint8_t u8; typedef int8_t s8; @@ -28,6 +29,7 @@ typedef int bool; #define min(a, b) RTE_MIN(a, b) #define max(a, b) RTE_MAX(a, b) +#include "hw_atl/hw_atl_b0_internal.h" #include "hw_atl/hw_atl_utils.h" struct aq_hw_link_status_s { @@ -56,8 +58,18 @@ struct aq_stats_s { u64 dma_oct_tc; }; +struct aq_rss_parameters { + u16 base_cpu_number; + u16 indirection_table_size; + u16 hash_secret_key_size; + u32 hash_secret_key[HW_ATL_B0_RSS_HASHKEY_BITS / 8]; + u8 indirection_table[HW_ATL_B0_RSS_REDIRECTION_MAX]; +}; + struct aq_hw_cfg_s { bool is_lro; + bool is_rss; + unsigned int num_rss_queues; int wol; int link_speed_msk; @@ -66,6 +78,8 @@ struct aq_hw_cfg_s { unsigned int vecs; uint32_t flow_control; + + struct aq_rss_parameters aq_rss; }; struct aq_hw_s { diff --git a/drivers/net/atlantic/hw_atl/hw_atl_b0.c b/drivers/net/atlantic/hw_atl/hw_atl_b0.c new file mode 100644 index 000000000000..9400e0edb999 --- /dev/null +++ b/drivers/net/atlantic/hw_atl/hw_atl_b0.c @@ -0,0 +1,510 @@ +// SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) +/* Copyright (C) 2014-2017 aQuantia Corporation. */ + +/* File hw_atl_b0.c: Definition of Atlantic hardware specific functions. */ + +#include "../atl_types.h" +#include "hw_atl_b0.h" + +#include "../atl_hw_regs.h" +#include "hw_atl_utils.h" +#include "hw_atl_llh.h" +#include "hw_atl_b0_internal.h" +#include "hw_atl_llh_internal.h" +#include "../atl_logs.h" + +int hw_atl_b0_hw_reset(struct aq_hw_s *self) +{ + int err = 0; + + err = hw_atl_utils_soft_reset(self); + if (err) + return err; + + self->aq_fw_ops->set_state(self, MPI_RESET); + + return err; +} + +static int hw_atl_b0_hw_qos_set(struct aq_hw_s *self) +{ + u32 tc = 0U; + u32 buff_size = 0U; + unsigned int i_priority = 0U; + bool is_rx_flow_control = false; + + /* TPS Descriptor rate init */ + hw_atl_tps_tx_pkt_shed_desc_rate_curr_time_res_set(self, 0x0U); + hw_atl_tps_tx_pkt_shed_desc_rate_lim_set(self, 0xA); + + /* TPS VM init */ + hw_atl_tps_tx_pkt_shed_desc_vm_arb_mode_set(self, 0U); + + /* TPS TC credits init */ + hw_atl_tps_tx_pkt_shed_desc_tc_arb_mode_set(self, 0U); + hw_atl_tps_tx_pkt_shed_data_arb_mode_set(self, 0U); + + hw_atl_tps_tx_pkt_shed_tc_data_max_credit_set(self, 0xFFF, 0U); + hw_atl_tps_tx_pkt_shed_tc_data_weight_set(self, 0x64, 0U); + hw_atl_tps_tx_pkt_shed_desc_tc_max_credit_set(self, 0x50, 0U); + hw_atl_tps_tx_pkt_shed_desc_tc_weight_set(self, 0x1E, 0U); + + /* Tx buf size */ + buff_size = HW_ATL_B0_TXBUF_MAX; + + hw_atl_tpb_tx_pkt_buff_size_per_tc_set(self, buff_size, tc); + hw_atl_tpb_tx_buff_hi_threshold_per_tc_set(self, + (buff_size * + (1024 / 32U) * 66U) / + 100U, tc); + hw_atl_tpb_tx_buff_lo_threshold_per_tc_set(self, + (buff_size * + (1024 / 32U) * 50U) / + 100U, tc); + + /* QoS Rx buf size per TC */ + tc = 0; + is_rx_flow_control = 0; + buff_size = HW_ATL_B0_RXBUF_MAX; + + hw_atl_rpb_rx_pkt_buff_size_per_tc_set(self, buff_size, tc); + hw_atl_rpb_rx_buff_hi_threshold_per_tc_set(self, + (buff_size * + (1024U / 32U) * 66U) / + 100U, tc); + hw_atl_rpb_rx_buff_lo_threshold_per_tc_set(self, + (buff_size * + (1024U / 32U) * 50U) / + 100U, tc); + hw_atl_rpb_rx_xoff_en_per_tc_set(self, + is_rx_flow_control ? 1U : 0U, + tc); + + /* QoS 802.1p priority -> TC mapping */ + for (i_priority = 8U; i_priority--;) + hw_atl_rpf_rpb_user_priority_tc_map_set(self, i_priority, 0U); + + return aq_hw_err_from_flags(self); +} + +/* calc hash only in IPv4 header, regardless of presence of TCP */ +#define pif_rpf_rss_ipv4_hdr_only_i (1 << 4) +/* calc hash only if TCP header and IPv4 */ +#define pif_rpf_rss_ipv4_tcp_hdr_only_i (1 << 3) +/* calc hash only in IPv6 header, regardless of presence of TCP */ +#define pif_rpf_rss_ipv6_hdr_only_i (1 << 2) +/* calc hash only if TCP header and IPv4 */ +#define pif_rpf_rss_ipv6_tcp_hdr_only_i (1 << 1) +/* bug 5124 - rss hashing types - FIXME */ +#define pif_rpf_rss_dont_use_udp_i (1 << 0) + +static int hw_atl_b0_hw_rss_hash_type_set(struct aq_hw_s *self) +{ + /* misc */ + unsigned int control_reg_val = + IS_CHIP_FEATURE(RPF2) ? 0x000F0000U : 0x00000000U; + + /* RSS hash type set for IP/TCP */ + control_reg_val |= pif_rpf_rss_ipv4_hdr_only_i;//0x1EU; + + aq_hw_write_reg(self, 0x5040U, control_reg_val); + + return aq_hw_err_from_flags(self); +} + +int hw_atl_b0_hw_rss_hash_set(struct aq_hw_s *self, + struct aq_rss_parameters *rss_params) +{ + struct aq_hw_cfg_s *cfg = self->aq_nic_cfg; + int err = 0; + unsigned int i = 0U; + unsigned int addr = 0U; + + for (i = 10, addr = 0U; i--; ++addr) { + u32 key_data = cfg->is_rss ? + htonl(rss_params->hash_secret_key[i]) : 0U; + hw_atl_rpf_rss_key_wr_data_set(self, key_data); + hw_atl_rpf_rss_key_addr_set(self, addr); + hw_atl_rpf_rss_key_wr_en_set(self, 1U); + AQ_HW_WAIT_FOR(hw_atl_rpf_rss_key_wr_en_get(self) == 0, + 1000U, 10U); + if (err < 0) + goto err_exit; + } + + /* RSS Ring selection */ + hw_atl_reg_rx_flr_rss_control1set(self, + cfg->is_rss ? 0xB3333333U : 0x00000000U); + hw_atl_b0_hw_rss_hash_type_set(self); + + err = aq_hw_err_from_flags(self); + +err_exit: + return err; +} + + +int hw_atl_b0_hw_rss_set(struct aq_hw_s *self, + struct aq_rss_parameters *rss_params) +{ + u8 *indirection_table = rss_params->indirection_table; + u32 num_rss_queues = max(1U, self->aq_nic_cfg->num_rss_queues); + u32 i = 0; + u32 addr = 0; + u32 val = 0; + u32 shift = 0; + int err = 0; + + for (i = 0; i < HW_ATL_B0_RSS_REDIRECTION_MAX; i++) { + val |= (u32)(indirection_table[i] % num_rss_queues) << shift; + shift += 3; + + if (shift < 16) + continue; + + hw_atl_rpf_rss_redir_tbl_wr_data_set(self, val & 0xffff); + hw_atl_rpf_rss_redir_tbl_addr_set(self, addr); + + hw_atl_rpf_rss_redir_wr_en_set(self, 1U); + AQ_HW_WAIT_FOR(hw_atl_rpf_rss_redir_wr_en_get(self) == 0, + 1000U, 10U); + + if (err < 0) + goto err_exit; + + shift -= 16; + val >>= 16; + addr++; + } + +err_exit: + return err; +} + +static int hw_atl_b0_hw_offload_set(struct aq_hw_s *self) + /*struct aq_nic_cfg_s *aq_nic_cfg)*/ +{ + unsigned int i; + + /* TX checksums offloads*/ + hw_atl_tpo_ipv4header_crc_offload_en_set(self, 1); + hw_atl_tpo_tcp_udp_crc_offload_en_set(self, 1); + + /* RX checksums offloads*/ + hw_atl_rpo_ipv4header_crc_offload_en_set(self, 1); + hw_atl_rpo_tcp_udp_crc_offload_en_set(self, 1); + + /* LSO offloads*/ + hw_atl_tdm_large_send_offload_en_set(self, 0xFFFFFFFFU); + +/* LRO offloads */ + { + unsigned int val = (8U < HW_ATL_B0_LRO_RXD_MAX) ? 0x3U : + ((4U < HW_ATL_B0_LRO_RXD_MAX) ? 0x2U : + ((2U < HW_ATL_B0_LRO_RXD_MAX) ? 0x1U : 0x0)); + + for (i = 0; i < HW_ATL_B0_RINGS_MAX; i++) + hw_atl_rpo_lro_max_num_of_descriptors_set(self, val, i); + + hw_atl_rpo_lro_time_base_divider_set(self, 0x61AU); + hw_atl_rpo_lro_inactive_interval_set(self, 0); + hw_atl_rpo_lro_max_coalescing_interval_set(self, 2); + + hw_atl_rpo_lro_qsessions_lim_set(self, 1U); + + hw_atl_rpo_lro_total_desc_lim_set(self, 2U); + + hw_atl_rpo_lro_patch_optimization_en_set(self, 0U); + + hw_atl_rpo_lro_min_pay_of_first_pkt_set(self, 10U); + + hw_atl_rpo_lro_pkt_lim_set(self, 1U); + + hw_atl_rpo_lro_en_set(self, + self->aq_nic_cfg->is_lro ? 0xFFFFFFFFU : 0U); + } + return aq_hw_err_from_flags(self); +} + +static +int hw_atl_b0_hw_init_tx_path(struct aq_hw_s *self) +{ + /* Tx TC/RSS number config */ + hw_atl_rpb_tps_tx_tc_mode_set(self, 1U); + + hw_atl_thm_lso_tcp_flag_of_first_pkt_set(self, 0x0FF6U); + hw_atl_thm_lso_tcp_flag_of_middle_pkt_set(self, 0x0FF6U); + hw_atl_thm_lso_tcp_flag_of_last_pkt_set(self, 0x0F7FU); + + /* Tx interrupts */ + hw_atl_tdm_tx_desc_wr_wb_irq_en_set(self, 0U); + + /* misc */ + aq_hw_write_reg(self, 0x00007040U, IS_CHIP_FEATURE(TPO2) ? + 0x00010000U : 0x00000000U); + hw_atl_tdm_tx_dca_en_set(self, 0U); + hw_atl_tdm_tx_dca_mode_set(self, 0U); + + hw_atl_tpb_tx_path_scp_ins_en_set(self, 1U); + + return aq_hw_err_from_flags(self); +} + +static +int hw_atl_b0_hw_init_rx_path(struct aq_hw_s *self) +{ + struct aq_hw_cfg_s *cfg = self->aq_nic_cfg; + int i; + + /* Rx TC/RSS number config */ + hw_atl_rpb_rpf_rx_traf_class_mode_set(self, 1U); /* 1: 4TC/8Queues */ + + /* Rx flow control */ + hw_atl_rpb_rx_flow_ctl_mode_set(self, 1U); + + /* RSS Ring selection */ + hw_atl_reg_rx_flr_rss_control1set(self, cfg->is_rss ? + 0xB3333333U : 0x00000000U); + + /* Multicast filters */ + for (i = HW_ATL_B0_MAC_MAX; i--;) { + hw_atl_rpfl2_uc_flr_en_set(self, (i == 0U) ? 1U : 0U, i); + hw_atl_rpfl2unicast_flr_act_set(self, 1U, i); + } + + hw_atl_reg_rx_flr_mcst_flr_msk_set(self, 0x00000000U); + hw_atl_reg_rx_flr_mcst_flr_set(self, 0x00010FFFU, 0U); + + /* Vlan filters */ + hw_atl_rpf_vlan_outer_etht_set(self, 0x88A8U); + hw_atl_rpf_vlan_inner_etht_set(self, 0x8100U); + + /* VLAN proimisc bu defauld */ + hw_atl_rpf_vlan_prom_mode_en_set(self, 1); + + /* Rx Interrupts */ + hw_atl_rdm_rx_desc_wr_wb_irq_en_set(self, 0U); + + hw_atl_b0_hw_rss_hash_type_set(self); + + hw_atl_rpfl2broadcast_flr_act_set(self, 1U); + hw_atl_rpfl2broadcast_count_threshold_set(self, 0xFFFFU & (~0U / 256U)); + + hw_atl_rdm_rx_dca_en_set(self, 0U); + hw_atl_rdm_rx_dca_mode_set(self, 0U); + + return aq_hw_err_from_flags(self); +} + +static int hw_atl_b0_hw_mac_addr_set(struct aq_hw_s *self, u8 *mac_addr) +{ + int err = 0; + unsigned int h = 0U; + unsigned int l = 0U; + + if (!mac_addr) { + err = -EINVAL; + goto err_exit; + } + h = (mac_addr[0] << 8) | (mac_addr[1]); + l = (mac_addr[2] << 24) | (mac_addr[3] << 16) | + (mac_addr[4] << 8) | mac_addr[5]; + + hw_atl_rpfl2_uc_flr_en_set(self, 0U, HW_ATL_B0_MAC); + hw_atl_rpfl2unicast_dest_addresslsw_set(self, l, HW_ATL_B0_MAC); + hw_atl_rpfl2unicast_dest_addressmsw_set(self, h, HW_ATL_B0_MAC); + hw_atl_rpfl2_uc_flr_en_set(self, 1U, HW_ATL_B0_MAC); + + err = aq_hw_err_from_flags(self); + +err_exit: + return err; +} + +int hw_atl_b0_hw_init(struct aq_hw_s *self, u8 *mac_addr) +{ + static u32 aq_hw_atl_igcr_table_[4][2] = { + { 0x20000080U, 0x20000080U }, /* AQ_IRQ_INVALID */ + { 0x20000080U, 0x20000080U }, /* AQ_IRQ_LEGACY */ + { 0x20000021U, 0x20000025U }, /* AQ_IRQ_MSI */ + { 0x200000A2U, 0x200000A6U } /* AQ_IRQ_MSIX */ + }; + + int err = 0; + u32 val; + + struct aq_hw_cfg_s *aq_nic_cfg = self->aq_nic_cfg; + + hw_atl_b0_hw_init_tx_path(self); + hw_atl_b0_hw_init_rx_path(self); + + hw_atl_b0_hw_mac_addr_set(self, mac_addr); + + self->aq_fw_ops->set_link_speed(self, aq_nic_cfg->link_speed_msk); + self->aq_fw_ops->set_state(self, MPI_INIT); + + hw_atl_b0_hw_qos_set(self); + hw_atl_b0_hw_rss_set(self, &aq_nic_cfg->aq_rss); + hw_atl_b0_hw_rss_hash_set(self, &aq_nic_cfg->aq_rss); + + /* Force limit MRRS on RDM/TDM to 2K */ + val = aq_hw_read_reg(self, HW_ATL_PCI_REG_CONTROL6_ADR); + aq_hw_write_reg(self, HW_ATL_PCI_REG_CONTROL6_ADR, + (val & ~0x707) | 0x404); + + /* TX DMA total request limit. B0 hardware is not capable to + * handle more than (8K-MRRS) incoming DMA data. + * Value 24 in 256byte units + */ + aq_hw_write_reg(self, HW_ATL_TX_DMA_TOTAL_REQ_LIMIT_ADR, 24); + + /* Reset link status and read out initial hardware counters */ + self->aq_link_status.mbps = 0; + self->aq_fw_ops->update_stats(self); + + err = aq_hw_err_from_flags(self); + if (err < 0) + goto err_exit; + + /* Interrupts */ + hw_atl_reg_irq_glb_ctl_set(self, + aq_hw_atl_igcr_table_[aq_nic_cfg->irq_type] + [(aq_nic_cfg->vecs > 1U) ? + 1 : 0]); + + hw_atl_itr_irq_auto_masklsw_set(self, 0xffffffff); + + /* Interrupts */ + hw_atl_reg_gen_irq_map_set(self, 0, 0); + hw_atl_reg_gen_irq_map_set(self, 0x80 | ATL_IRQ_CAUSE_LINK, 3); + + hw_atl_b0_hw_offload_set(self); + +err_exit: + return err; +} + +int hw_atl_b0_hw_ring_tx_start(struct aq_hw_s *self, int index) +{ + hw_atl_tdm_tx_desc_en_set(self, 1, index); + return aq_hw_err_from_flags(self); +} + +int hw_atl_b0_hw_ring_rx_start(struct aq_hw_s *self, int index) +{ + hw_atl_rdm_rx_desc_en_set(self, 1, index); + return aq_hw_err_from_flags(self); +} + +int hw_atl_b0_hw_start(struct aq_hw_s *self) +{ + hw_atl_tpb_tx_buff_en_set(self, 1); + hw_atl_rpb_rx_buff_en_set(self, 1); + return aq_hw_err_from_flags(self); +} + +int hw_atl_b0_hw_tx_ring_tail_update(struct aq_hw_s *self, int tail, int index) +{ + hw_atl_reg_tx_dma_desc_tail_ptr_set(self, tail, index); + return 0; +} + +int hw_atl_b0_hw_ring_rx_init(struct aq_hw_s *self, uint64_t base_addr, + int index, int size, int buff_size, int cpu, int vec) +{ + u32 dma_desc_addr_lsw = (u32)base_addr; + u32 dma_desc_addr_msw = (u32)(base_addr >> 32); + + hw_atl_rdm_rx_desc_en_set(self, false, index); + + hw_atl_rdm_rx_desc_head_splitting_set(self, 0U, index); + + hw_atl_reg_rx_dma_desc_base_addresslswset(self, dma_desc_addr_lsw, + index); + + hw_atl_reg_rx_dma_desc_base_addressmswset(self, dma_desc_addr_msw, + index); + + hw_atl_rdm_rx_desc_len_set(self, size / 8U, index); + + hw_atl_rdm_rx_desc_data_buff_size_set(self, buff_size / 1024U, index); + + hw_atl_rdm_rx_desc_head_buff_size_set(self, 0U, index); + hw_atl_rdm_rx_desc_head_splitting_set(self, 0U, index); + hw_atl_rpo_rx_desc_vlan_stripping_set(self, 0U, index); + + /* Rx ring set mode */ + + /* Mapping interrupt vector */ + hw_atl_itr_irq_map_rx_set(self, vec, index); + hw_atl_itr_irq_map_en_rx_set(self, true, index); + + hw_atl_rdm_cpu_id_set(self, cpu, index); + hw_atl_rdm_rx_desc_dca_en_set(self, 0U, index); + hw_atl_rdm_rx_head_dca_en_set(self, 0U, index); + hw_atl_rdm_rx_pld_dca_en_set(self, 0U, index); + + return aq_hw_err_from_flags(self); +} + +int hw_atl_b0_hw_ring_tx_init(struct aq_hw_s *self, uint64_t base_addr, + int index, int size, int cpu, int vec) +{ + u32 dma_desc_lsw_addr = (u32)base_addr; + u32 dma_desc_msw_addr = (u32)(base_addr >> 32); + + hw_atl_reg_tx_dma_desc_base_addresslswset(self, dma_desc_lsw_addr, + index); + + hw_atl_reg_tx_dma_desc_base_addressmswset(self, dma_desc_msw_addr, + index); + + hw_atl_tdm_tx_desc_len_set(self, size / 8U, index); + + hw_atl_b0_hw_tx_ring_tail_update(self, 0, index); + + /* Set Tx threshold */ + hw_atl_tdm_tx_desc_wr_wb_threshold_set(self, 0U, index); + + /* Mapping interrupt vector */ + hw_atl_itr_irq_map_tx_set(self, vec, index); + hw_atl_itr_irq_map_en_tx_set(self, true, index); + + hw_atl_tdm_cpu_id_set(self, cpu, index); + hw_atl_tdm_tx_desc_dca_en_set(self, 0U, index); + + return aq_hw_err_from_flags(self); +} + +int hw_atl_b0_hw_irq_enable(struct aq_hw_s *self, u64 mask) +{ + hw_atl_itr_irq_msk_setlsw_set(self, LODWORD(mask)); + return aq_hw_err_from_flags(self); +} + +int hw_atl_b0_hw_irq_disable(struct aq_hw_s *self, u64 mask) +{ + hw_atl_itr_irq_msk_clearlsw_set(self, LODWORD(mask)); + hw_atl_itr_irq_status_clearlsw_set(self, LODWORD(mask)); + + return aq_hw_err_from_flags(self); +} + +int hw_atl_b0_hw_irq_read(struct aq_hw_s *self, u64 *mask) +{ + *mask = hw_atl_itr_irq_statuslsw_get(self); + return aq_hw_err_from_flags(self); +} + +int hw_atl_b0_hw_ring_tx_stop(struct aq_hw_s *self, int index) +{ + hw_atl_tdm_tx_desc_en_set(self, 0U, index); + return aq_hw_err_from_flags(self); +} + +int hw_atl_b0_hw_ring_rx_stop(struct aq_hw_s *self, int index) +{ + hw_atl_rdm_rx_desc_en_set(self, 0U, index); + return aq_hw_err_from_flags(self); +} + diff --git a/drivers/net/atlantic/hw_atl/hw_atl_b0.h b/drivers/net/atlantic/hw_atl/hw_atl_b0.h new file mode 100644 index 000000000000..06feb56c1620 --- /dev/null +++ b/drivers/net/atlantic/hw_atl/hw_atl_b0.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) */ +/* Copyright (C) 2014-2017 aQuantia Corporation. */ + +/* File hw_atl_b0.h: Declaration of abstract interface for Atlantic hardware + * specific functions. + */ + +#ifndef HW_ATL_B0_H +#define HW_ATL_B0_H + +int hw_atl_b0_hw_reset(struct aq_hw_s *self); +int hw_atl_b0_hw_init(struct aq_hw_s *self, u8 *mac_addr); + +int hw_atl_b0_hw_ring_tx_init(struct aq_hw_s *self, uint64_t base_addr, + int index, int size, int cpu, int vec); +int hw_atl_b0_hw_ring_rx_init(struct aq_hw_s *self, uint64_t base_addr, + int index, int size, int buff_size, int cpu, int vec); + +int hw_atl_b0_hw_start(struct aq_hw_s *self); + +int hw_atl_b0_hw_ring_rx_start(struct aq_hw_s *self, int index); +int hw_atl_b0_hw_ring_tx_start(struct aq_hw_s *self, int index); + + +int hw_atl_b0_hw_ring_tx_stop(struct aq_hw_s *self, int index); +int hw_atl_b0_hw_ring_rx_stop(struct aq_hw_s *self, int index); + + +int hw_atl_b0_hw_tx_ring_tail_update(struct aq_hw_s *self, int tail, int index); + +int hw_atl_b0_hw_rss_hash_set(struct aq_hw_s *self, + struct aq_rss_parameters *rss_params); +int hw_atl_b0_hw_rss_set(struct aq_hw_s *self, + struct aq_rss_parameters *rss_params); + +int hw_atl_b0_hw_irq_enable(struct aq_hw_s *self, u64 mask); +int hw_atl_b0_hw_irq_disable(struct aq_hw_s *self, u64 mask); +int hw_atl_b0_hw_irq_read(struct aq_hw_s *self, u64 *mask); + +#endif /* HW_ATL_B0_H */ diff --git a/drivers/net/atlantic/hw_atl/hw_atl_b0_internal.h b/drivers/net/atlantic/hw_atl/hw_atl_b0_internal.h new file mode 100644 index 000000000000..48152eada731 --- /dev/null +++ b/drivers/net/atlantic/hw_atl/hw_atl_b0_internal.h @@ -0,0 +1,145 @@ +/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) */ +/* Copyright (C) 2014-2017 aQuantia Corporation. */ + +/* File hw_atl_b0_internal.h: Definition of Atlantic B0 chip specific + * constants. + */ + +#ifndef HW_ATL_B0_INTERNAL_H +#define HW_ATL_B0_INTERNAL_H + + +#define HW_ATL_B0_MTU_JUMBO 16352U +#define HW_ATL_B0_MTU 1514U + +#define HW_ATL_B0_TX_RINGS 4U +#define HW_ATL_B0_RX_RINGS 4U + +#define HW_ATL_B0_RINGS_MAX 32U +#define HW_ATL_B0_TXD_SIZE (16U) +#define HW_ATL_B0_RXD_SIZE (16U) + +#define HW_ATL_B0_MAC 0U +#define HW_ATL_B0_MAC_MIN 1U +#define HW_ATL_B0_MAC_MAX 33U + +/* Maximum supported VLAN filters */ +#define HW_ATL_B0_MAX_VLAN_IDS 16 + +/* UCAST/MCAST filters */ +#define HW_ATL_B0_UCAST_FILTERS_MAX 38 +#define HW_ATL_B0_MCAST_FILTERS_MAX 8 + +/* interrupts */ +#define HW_ATL_B0_ERR_INT 8U +#define HW_ATL_B0_INT_MASK (0xFFFFFFFFU) + +#define HW_ATL_B0_TXD_CTL2_LEN (0xFFFFC000) +#define HW_ATL_B0_TXD_CTL2_CTX_EN (0x00002000) +#define HW_ATL_B0_TXD_CTL2_CTX_IDX (0x00001000) + +#define HW_ATL_B0_TXD_CTL_DESC_TYPE_TXD (0x00000001) +#define HW_ATL_B0_TXD_CTL_DESC_TYPE_TXC (0x00000002) +#define HW_ATL_B0_TXD_CTL_BLEN (0x000FFFF0) +#define HW_ATL_B0_TXD_CTL_DD (0x00100000) +#define HW_ATL_B0_TXD_CTL_EOP (0x00200000) + +#define HW_ATL_B0_TXD_CTL_CMD_X (0x3FC00000) + +#define HW_ATL_B0_TXD_CTL_CMD_VLAN BIT(22) +#define HW_ATL_B0_TXD_CTL_CMD_FCS BIT(23) +#define HW_ATL_B0_TXD_CTL_CMD_IPCSO BIT(24) +#define HW_ATL_B0_TXD_CTL_CMD_TUCSO BIT(25) +#define HW_ATL_B0_TXD_CTL_CMD_LSO BIT(26) +#define HW_ATL_B0_TXD_CTL_CMD_WB BIT(27) +#define HW_ATL_B0_TXD_CTL_CMD_VXLAN BIT(28) + +#define HW_ATL_B0_TXD_CTL_CMD_IPV6 BIT(21) +#define HW_ATL_B0_TXD_CTL_CMD_TCP BIT(22) + +#define HW_ATL_B0_MPI_CONTROL_ADR 0x0368U +#define HW_ATL_B0_MPI_STATE_ADR 0x036CU + +#define HW_ATL_B0_MPI_SPEED_MSK 0xFFFFU +#define HW_ATL_B0_MPI_SPEED_SHIFT 16U + +#define HW_ATL_B0_TXBUF_MAX 160U +#define HW_ATL_B0_RXBUF_MAX 320U + +#define HW_ATL_B0_RXD_BUF_SIZE_MAX (16 * 1024) + +#define HW_ATL_B0_RSS_REDIRECTION_MAX 64U +#define HW_ATL_B0_RSS_REDIRECTION_BITS 3U +#define HW_ATL_B0_RSS_HASHKEY_BITS 320U + +#define HW_ATL_B0_TCRSS_4_8 1 +#define HW_ATL_B0_TC_MAX 1U +#define HW_ATL_B0_RSS_MAX 8U + +#define HW_ATL_B0_LRO_RXD_MAX 2U +#define HW_ATL_B0_RS_SLIP_ENABLED 0U + +/* (256k -1(max pay_len) - 54(header)) */ +#define HAL_ATL_B0_LSO_MAX_SEGMENT_SIZE 262089U + +/* (256k -1(max pay_len) - 74(header)) */ +#define HAL_ATL_B0_LSO_IPV6_MAX_SEGMENT_SIZE 262069U + +#define HW_ATL_B0_CHIP_REVISION_B0 0xA0U +#define HW_ATL_B0_CHIP_REVISION_UNKNOWN 0xFFU + +#define HW_ATL_B0_FW_SEMA_RAM 0x2U + +#define HW_ATL_B0_TXC_LEN_TUNLEN (0x0000FF00) +#define HW_ATL_B0_TXC_LEN_OUTLEN (0xFFFF0000) + +#define HW_ATL_B0_TXC_CTL_DESC_TYPE (0x00000007) +#define HW_ATL_B0_TXC_CTL_CTX_ID (0x00000008) +#define HW_ATL_B0_TXC_CTL_VLAN (0x000FFFF0) +#define HW_ATL_B0_TXC_CTL_CMD (0x00F00000) +#define HW_ATL_B0_TXC_CTL_L2LEN (0x7F000000) + +#define HW_ATL_B0_TXC_CTL_L3LEN (0x80000000) /* L3LEN lsb */ +#define HW_ATL_B0_TXC_LEN2_L3LEN (0x000000FF) /* L3LE upper bits */ +#define HW_ATL_B0_TXC_LEN2_L4LEN (0x0000FF00) +#define HW_ATL_B0_TXC_LEN2_MSSLEN (0xFFFF0000) + +#define HW_ATL_B0_RXD_DD (0x1) +#define HW_ATL_B0_RXD_NCEA0 (0x1) + +#define HW_ATL_B0_RXD_WB_STAT_RSSTYPE (0x0000000F) +#define HW_ATL_B0_RXD_WB_STAT_PKTTYPE (0x00000FF0) +#define HW_ATL_B0_RXD_WB_STAT_RXCTRL (0x00180000) +#define HW_ATL_B0_RXD_WB_STAT_SPLHDR (0x00200000) +#define HW_ATL_B0_RXD_WB_STAT_HDRLEN (0xFFC00000) + +#define HW_ATL_B0_RXD_WB_STAT2_DD (0x0001) +#define HW_ATL_B0_RXD_WB_STAT2_EOP (0x0002) +#define HW_ATL_B0_RXD_WB_STAT2_RXSTAT (0x003C) +#define HW_ATL_B0_RXD_WB_STAT2_MACERR (0x0004) +#define HW_ATL_B0_RXD_WB_STAT2_IP4ERR (0x0008) +#define HW_ATL_B0_RXD_WB_STAT2_TCPUPDERR (0x0010) +#define HW_ATL_B0_RXD_WB_STAT2_RXESTAT (0x0FC0) +#define HW_ATL_B0_RXD_WB_STAT2_RSCCNT (0xF000) + +#define L2_FILTER_ACTION_DISCARD (0x0) +#define L2_FILTER_ACTION_HOST (0x1) + +#define HW_ATL_B0_UCP_0X370_REG (0x370) + +#define HW_ATL_B0_FLUSH() AQ_HW_READ_REG(self, 0x10) + +#define HW_ATL_INTR_MODER_MAX 0x1FF +#define HW_ATL_INTR_MODER_MIN 0xFF + +#define HW_ATL_B0_MIN_RXD \ + (ALIGN(AQ_CFG_SKB_FRAGS_MAX + 1U, AQ_HW_RXD_MULTIPLE)) +#define HW_ATL_B0_MIN_TXD \ + (ALIGN(AQ_CFG_SKB_FRAGS_MAX + 1U, AQ_HW_TXD_MULTIPLE)) + +#define HW_ATL_B0_MAX_RXD 8184U +#define HW_ATL_B0_MAX_TXD 8184U + +/* HW layer capabilities */ + +#endif /* HW_ATL_B0_INTERNAL_H */ diff --git a/drivers/net/atlantic/meson.build b/drivers/net/atlantic/meson.build index 919cf6e4f20a..e7b4e0cba574 100644 --- a/drivers/net/atlantic/meson.build +++ b/drivers/net/atlantic/meson.build @@ -6,6 +6,7 @@ sources = files( 'atl_ethdev.c', 'atl_hw_regs.c', + 'hw_atl/hw_atl_b0.c', 'hw_atl/hw_atl_llh.c', 'hw_atl/hw_atl_utils_fw2x.c', 'hw_atl/hw_atl_utils.c', From patchwork Sat Sep 29 10:30:21 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Russkikh X-Patchwork-Id: 45671 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 22E311B1E9; Sat, 29 Sep 2018 12:31:44 +0200 (CEST) Received: from NAM05-DM3-obe.outbound.protection.outlook.com (mail-eopbgr730065.outbound.protection.outlook.com [40.107.73.65]) by dpdk.org (Postfix) with ESMTP id 0DA031B160 for ; Sat, 29 Sep 2018 12:31:39 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=AQUANTIA1COM.onmicrosoft.com; s=selector1-aquantia-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=z57x+gJxhLAaKfpNCgkID8gIGB9YT11pq8MwL3oSnwg=; b=ZhPsR7rnGXOAAH8MglOdeaDKzoEtUHO3hpC+Hz5P93qQ9mUDV4DYGYwJUNBZ1pi5QUioNJclxDqTCf0Z9saHwxAp6Iy/EfAcaEwUWB44pQC3w3+LGKNS2qoeaiEwippPwPAVbyu5kpnEYzsRMTKLyg7bWCNLId0BlPIZlReuyPI= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Igor.Russkikh@aquantia.com; Received: from ubuntubox.rdc.aquantia.com (95.79.108.179) by BLUPR0701MB1650.namprd07.prod.outlook.com (2a01:111:e400:58c6::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1185.22; Sat, 29 Sep 2018 10:31:36 +0000 From: Igor Russkikh To: dev@dpdk.org Cc: pavel.belous@aquantia.com, igor.russkikh@aquantia.com Date: Sat, 29 Sep 2018 13:30:21 +0300 Message-Id: <6e5d1bfd1e27795ec7136121b62923b3b7da5180.1538215990.git.igor.russkikh@aquantia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [95.79.108.179] X-ClientProxiedBy: VI1P193CA0009.EURP193.PROD.OUTLOOK.COM (2603:10a6:800:bd::19) To BLUPR0701MB1650.namprd07.prod.outlook.com (2a01:111:e400:58c6::20) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 2d4cb348-aea4-4806-f1e2-08d625f6bc95 X-Microsoft-Antispam: BCL:0; PCL:0; RULEID:(7020095)(4652040)(8989299)(4534165)(4627221)(201703031133081)(201702281549075)(8990200)(5600074)(711020)(2017052603328)(7153060)(7193020); SRVR:BLUPR0701MB1650; X-Microsoft-Exchange-Diagnostics: 1; BLUPR0701MB1650; 3:C3Db38LdHwkitNQsZ6Q5YSWp7poPUg5QpT3UG+tod004zyZdyagyGoTuZq9wmQtOb0QQGP8CaMCpi0BoZfMf5f5LA9bHmdLOL7lV1eDE/SLstfPNUqSvRv4mT4+HzWQdZE0ZL43Pr2m78NtE1R/X4krp638z021ygmfuRADp9leuri/4nj7uCRXCLbPbi8k9zAA00tZLKT7h2sVAhuzxz1AjtvI2FsE8PlXO2NCy0fXXtFiiuuJfkEoeoh3klYBG; 25:YyVPZQJUfwt6j9rZtfSF3wk9ZfPeDTGaM4iXQhhQPnptUQhvQcYa7SvUrP4jaXmIDqSR4J5Ls96oeDp9+hMUoE7/8dH7Hvm8xjesJPJibDUmmciVSOcagcZZTWCNURld4Y+8hwD3OtG8Ga2CBYx2M9enabSWGVpPsI1hXP1L7UnKVKsyzJPBLmN1Bp8CkiGNyK3jQDAXnwcjYUJiJgZb17lHhPVnbHfLP7ijIbdOFCKO1PAgN6Z4QNPfHowwBf+YVfguSDiMY71sp6XPzaupabIZovIrii7dgR5h313F0mBYtfIY70OBFU/VxpvuaWJmZsf2Ls/keRjL5dNxwYrzDRrknWoqw+PDGejgv0jZxkc=; 31:idkteOgSL3osb4t231EFwSN2kF3U8k1Gp2G0Xxe5g/+GdWeVrzvWPjQ2001axK1pFwCXzyUQkUrywJbXkJdReC05mSkrbqu6CMw+y98yfqNMXFH7KYiYKLoqhPYtAUF0enSz144nwyaAHAyiXj9PR9eGOc9gLCTMqYWs34meX6OKrnV+A6Tkycz/IA2/SMvHQ/eOS0wSbUATipotuGCj44wmD2kaN1HPM70n1yjXI/E= X-MS-TrafficTypeDiagnostic: BLUPR0701MB1650: X-Microsoft-Exchange-Diagnostics: 1; BLUPR0701MB1650; 20:3ULR4XD6s1dagWwsLS0/ahqDm6raVgT7M+cETxBmz9LBpW9LTEkxDbTFhk2uVdxT19ZeZuhNJcCqKIVWXjKflUs6qSmncaUAzHegJloWjJ/QWzMxBfyiYnKj1K/YvFO4bYQHvJbBLCZo6KUOvSUPjcSMQipLX/khzdu1YJSAYXv+75ujrZ+drQCI95C5zIwKfnk7+DBkvQEyrtsULSlhh5YfZoMJffpCzWsNkRnrzRtpktIYJDobt7II89c2IjXUFCvN+sRHel3h/7SxInQ2IpKm6GpCyFR1hUm7Dd4mrG8HPLqcyPcgcBVpQ8tQBltMf4SfLHcj+n9Wbpps8NX/l0fsMWsOk3zX5PwzaIIiufS2WuuH2TKR9rVt94YO59vwfy50DdYYO0LqLlRMcZFPaxQ3zuNbOziV+TxF04H/pjer21cWWecthxQ+rt5UGoNQz/a6qwjSOMmNrpAU3pjYYUhv7TvOHPLco258FiNSbzJ7/am0iS0PmTr0WoBdwKPi; 4:zrnOVDQtcKum58VbMGoNwWPTNQI+FgHhRDlLyTJEK6ZyeEcWSjg7C9jqzo4lnj70XMXIv2y7pXmjI9mGYo4Ef+5GkucXVjCrVn2oBuhbaEHkQnd0ybSQwJxS4ZpnLN8y80Flz0L1HH/Gi7jWTzVTiMrM2fNeHPK2ZhtJxLNQWPcQ1v8KzNXMlTPzJFCF6L24RzdOcDM7mhZHhGFJW9/3dIT1Wpktuf7UO6UuKSIMnGhiTnkzsJ3iNoO7q5R53pIX5pr1myi3ImYCICNByP417JceHaEesZ3Ci1ix3yFTgjRAsEKu2L8hq9fl2RFCwwSy X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:(192374486261705); X-MS-Exchange-SenderADCheck: 1 X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(6040522)(2401047)(8121501046)(5005006)(10201501046)(3002001)(93006095)(93001095)(3231355)(944501410)(52105095)(149066)(150057)(6041310)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123558120)(20161123564045)(20161123562045)(20161123560045)(201708071742011)(7699051); SRVR:BLUPR0701MB1650; BCL:0; PCL:0; RULEID:; SRVR:BLUPR0701MB1650; X-Forefront-PRVS: 0810818DA0 X-Forefront-Antispam-Report: SFV:NSPM; SFS:(10009020)(346002)(136003)(396003)(376002)(39850400004)(366004)(189003)(199004)(16526019)(14444005)(446003)(76176011)(2906002)(6916009)(6666003)(97736004)(8676002)(81166006)(81156014)(36756003)(4326008)(316002)(8936002)(50226002)(34290500001)(86362001)(5660300001)(68736007)(16586007)(118296001)(72206003)(3846002)(6116002)(53936002)(386003)(105586002)(6486002)(47776003)(66066001)(486006)(25786009)(305945005)(50466002)(44832011)(956004)(2616005)(26005)(107886003)(52116002)(51416003)(7696005)(186003)(476003)(478600001)(2361001)(7736002)(2351001)(48376002)(106356001)(11346002); DIR:OUT; SFP:1101; SCL:1; SRVR:BLUPR0701MB1650; H:ubuntubox.rdc.aquantia.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; Received-SPF: None (protection.outlook.com: aquantia.com does not designate permitted sender hosts) X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; BLUPR0701MB1650; 23:dHErJuXxql36CZ3rmgAq1rgvG5a0ajhIWz8yoXB?= WV/yhXcpZ/2OyrXDKuqaOxFW2JxM59wSgyVwtaK6kuJQlFgoWIs/Aiyf4VU8fi/3fF/+n/McOeZRcK0gCpPONjMZ1MNbl3vbWbcKCqnYuTcD6HxbQdB0mVwLq4TZSXd5dmw4yL60+DOZSN7+razl7iKGFZapx28ZQhEjMI2qv4PTwU7TznWxb8Sor2PDFtnoC0UfczCM8EEsrmkZQGI4rG5y0tLSemcOCS2rxHAmNywqNPWq5h3Zyd46jBfOLTdONybhkIdxFIMj2Yasu9ZfHXKlN6KyoHNgO69Icy0pT7yCAEQ7Q64bGFM2FDb3Ew7FgBpqU0M5ovb9tr9SAHjG56QJ8RE79x7MoDUruJb1pcOun5YIHy2ZAT3WVZumKbfMA4eUa3eiNcM3sJLsGEBHntUCaaHUnDgfmuSP5UpFB9XkVBNS78ldxkz4McNantcMZgTAE28+J4YUKZYZNwGmNQH7DIJKbhmLB2bX7C/rP0MpqEAzBoaTyctae1m3mkq6Hkf4QKaUL+IObyFrOtWcf1pQTTyG8X4w9HWdR7l69q4OGZvPtuZDh7JESHv7aICvFllRs5MoDF2ltzJCHwWHXuMP3r0LKfcZTm5FgDl2QWcDbzfb/RfoC/qOnQqxJnnPROnrczpuuillcPz0WC1MWAaK5zTtF9cxlPCpUuMAjqZAzm6soQNf99RSPBlXk4C6FDaaNkILERi0X/X21KY1sPDf41f8szh/6LG3PL2D8BmPXkw0Gxkp7OqTtwRBgMqSa+sSQF9Zz72VFCkwYMTDAo7M9HuFProAhmPWcau5cCdat5f/EzYG+heVYrTCyJv0Z+lAh8A1i+HNLL4pa+btp8+FU044UI6ZvybwoC9JLtz8OlZby5AFTkclhCR/8Iw/nZBB29/BZi9qCYJA/9BpaHVtNLQQaXxzAq9yf3Mza7YpI8HQvsDnYKzomPsiSjGjLbzMR3qQEiV1o6GM5jX6Stmal6DAXbkV91JfwYAvfOLMfvNi3R95fsPnjpmcCTE2VFTHCTp48p4PrB9iEMuoVCPCP4KPs/+KyQ2z4kLNvwWs6coEtKR/bsqW2GC/QKBczJ7fPsaMoB8I5Np4AJeLDcSwGXMiiw13o8kSkWmXNM9rEOip79cE9H9/nAokoC0zel/tyEJQVKV8Qg7SVEj5UjtFn+MPjEiVNQM1eOi/OqlwfrXPV1LJ+l8ujAQYIAPmQ8Sn3zAE7+/zyhVR1/e1EgS0fU7CvXOsFWIveNj4g1V39ZmBaVmesRqft1exxV7xqNSI= X-Microsoft-Antispam-Message-Info: /gEzIvbn8+eFbe3EZhiTj8MX0SqhgIofHFeWjp8JEZKYyVgGjFsfYD1K0HCfxrsJgYYXmFkoWOBU8pah0NkXpDLWM/oftH8j4EbssjqriK7TWJlf1sP/Wocvw8lurwBPRQclyGcnQ26JAN/4gDketHtat/amX8/I+R8/1Blsf47uymYhyhjaZC2G7B0PRldbdv6pUYUC0fiyzjEDl9TcdyMBVN7xvulaTS0ShSjM8qP+5kDvuBLR9NVMIMm9SFtts8qqOYjsOHK/YAn9LEjiVvzrTccZnh0kFFUPJ5CH7rpW7jE59riNwiUN0AJnhEX4sXPKjMiTm7Ia6nFHB+vYJEvTF8RC7o2cCQLFvLqAIFM= X-Microsoft-Exchange-Diagnostics: 1; BLUPR0701MB1650; 6:L558Umj/UuRnIO9wpTzKrFO5N53F8QnCiz6m+5QlD1Nxgxx7RJNcvFJxKZKc2LOIzQiLaeGbJ8Tasg46SJMWOv855lUvmBa/tKnDqaMWLGpNfnxAzv0/BejE0DKYHnHkTP6D1pRCB8r2kqs9rE8mhkkiyXDvW7jcrqSyYM1ErEjIXfr2xmOFEdp7COY1aNjRFeJgb8nt/N1vf3F61s1q1nQ1s+5arJMe4fhj5BJ52yGpuIi2kCkh3/8eBDRop/GLIA8Cgpzjjzy4s6AR3M7zj0Nd8Mdg/80giNh3OHYH80o40i1as8lQvsBqSUZ7jsijqra5XeHCu6+8kLO2XsfeIZJ2i8q0VuTqMd1TCrShsYtcJQiIQUmG9NEeOvbCK+M20y1CnOCdm5b5gBE9dVvwU0zHwbs2fhYOWJY2PFcg9iWu5+HepEd6UhFg0dHWzsiI8uP8EeZfQtonj55xCdREgg==; 5:BhumE2/+VxlAvGwUpj/WS3tubE3m53rc5zrn3FIhBcA9B5+kgKdv5B4VUjRnU42fltPXGxZAIUARQzQS/j30xcO2ahbw4kdOL3YqZkvlBO60du0We4xHMH/6j6JqsmGpI6IOpkqxHOpzAspKdfOOCVRQiqnt5eisE4ViocNRmdg=; 7:vA6Gp7ZeMmEPOC4Temzc86Ng2WMEBctjis69paY07VSgQXEg6yZeZk43yO3lW1PrJyIOe94RBlfTvaUZMdCIrE7bBzBP6Ris/2g6Y8VHoVCPW/NuiCAhLDTpoBZh2IdfuDJ6YnWVGgJsHKZ6oEYR9ca01xYKJOGiHYo2577dwYsAlh/PmZYd9094nkjvOs66aSg2MKOI9jcHBuxRVXf3HSfsQJ3tFXcz96NauxB2IVobZCfMl42LqGoazelG8/IY SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: aquantia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Sep 2018 10:31:36.6723 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2d4cb348-aea4-4806-f1e2-08d625f6bc95 X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 83e2e134-991c-4ede-8ced-34d47e38e6b1 X-MS-Exchange-Transport-CrossTenantHeadersStamped: BLUPR0701MB1650 Subject: [dpdk-dev] [PATCH v3 07/22] net/atlantic: rte device start, stop, initial configuration X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavel Belous Start, stop and reset are all done via hw_atl layer. Link interrupt configuration is also done here. Signed-off-by: Igor Russkikh Signed-off-by: Pavel Belous --- drivers/net/atlantic/atl_ethdev.c | 196 ++++++++++++++++++++++++++++++++++++-- drivers/net/atlantic/atl_ethdev.h | 8 ++ drivers/net/atlantic/atl_types.h | 4 + 3 files changed, 201 insertions(+), 7 deletions(-) diff --git a/drivers/net/atlantic/atl_ethdev.c b/drivers/net/atlantic/atl_ethdev.c index 5728d9037d72..afb2972ffcc2 100644 --- a/drivers/net/atlantic/atl_ethdev.c +++ b/drivers/net/atlantic/atl_ethdev.c @@ -6,6 +6,11 @@ #include "atl_ethdev.h" #include "atl_common.h" +#include "atl_hw_regs.h" +#include "atl_logs.h" +#include "hw_atl/hw_atl_llh.h" +#include "hw_atl/hw_atl_b0.h" +#include "hw_atl/hw_atl_b0_internal.h" static int eth_atl_dev_init(struct rte_eth_dev *eth_dev); static int eth_atl_dev_uninit(struct rte_eth_dev *eth_dev); @@ -16,6 +21,13 @@ static void atl_dev_stop(struct rte_eth_dev *dev); static void atl_dev_close(struct rte_eth_dev *dev); static int atl_dev_reset(struct rte_eth_dev *dev); +static int atl_fw_version_get(struct rte_eth_dev *dev, char *fw_version, + size_t fw_size); + +static void atl_dev_info_get(struct rte_eth_dev *dev, + struct rte_eth_dev_info *dev_info); + + static int eth_atl_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, struct rte_pci_device *pci_dev); static int eth_atl_pci_remove(struct rte_pci_device *pci_dev); @@ -66,17 +78,103 @@ static const struct eth_dev_ops atl_eth_dev_ops = { .dev_stop = atl_dev_stop, .dev_close = atl_dev_close, .dev_reset = atl_dev_reset, + + .fw_version_get = atl_fw_version_get, + .dev_infos_get = atl_dev_info_get, }; +static inline int32_t +atl_reset_hw(struct aq_hw_s *hw) +{ + return hw_atl_b0_hw_reset(hw); +} + +static void +atl_print_adapter_info(struct aq_hw_s *hw __rte_unused) +{ + PMD_INIT_LOG(DEBUG, "FW version: %u.%u.%u", + hw->fw_ver_actual >> 24, + (hw->fw_ver_actual >> 16) & 0xFF, + hw->fw_ver_actual & 0xFFFF); + PMD_INIT_LOG(DEBUG, "Driver version: %s", ATL_PMD_DRIVER_VERSION); +} + static int -eth_atl_dev_init(struct rte_eth_dev *eth_dev __rte_unused) +eth_atl_dev_init(struct rte_eth_dev *eth_dev) { - return 0; + struct atl_adapter *adapter = + (struct atl_adapter *)eth_dev->data->dev_private; + struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); + struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); + int err = 0; + + PMD_INIT_FUNC_TRACE(); + + eth_dev->dev_ops = &atl_eth_dev_ops; + + /* For secondary processes, the primary process has done all the work */ + if (rte_eal_process_type() != RTE_PROC_PRIMARY) + return 0; + + rte_eth_copy_pci_info(eth_dev, pci_dev); + + /* Vendor and Device ID need to be set before init of shared code */ + hw->device_id = pci_dev->id.device_id; + hw->vendor_id = pci_dev->id.vendor_id; + hw->mmio = (void *)pci_dev->mem_resource[0].addr; + + /* Hardware configuration - hardcode */ + adapter->hw_cfg.is_lro = false; + adapter->hw_cfg.wol = false; + + hw->aq_nic_cfg = &adapter->hw_cfg; + + /* Allocate memory for storing MAC addresses */ + eth_dev->data->mac_addrs = rte_zmalloc("atlantic", ETHER_ADDR_LEN, 0); + if (eth_dev->data->mac_addrs == NULL) { + PMD_INIT_LOG(ERR, "MAC Malloc failed"); + return -ENOMEM; + } + + err = hw_atl_utils_initfw(hw, &hw->aq_fw_ops); + if (err) + return err; + + /* Copy the permanent MAC address */ + if (hw->aq_fw_ops->get_mac_permanent(hw, + (u8 *)ð_dev->data->mac_addrs[0]) != 0) + return -EINVAL; + + return err; } static int -eth_atl_dev_uninit(struct rte_eth_dev *eth_dev __rte_unused) +eth_atl_dev_uninit(struct rte_eth_dev *eth_dev) { + struct aq_hw_s *hw; + + PMD_INIT_FUNC_TRACE(); + + if (rte_eal_process_type() != RTE_PROC_PRIMARY) + return -EPERM; + + hw = ATL_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); + + if (hw->adapter_stopped == 0) + atl_dev_close(eth_dev); + + eth_dev->dev_ops = NULL; + + rte_free(eth_dev->data->mac_addrs); + eth_dev->data->mac_addrs = NULL; + + rte_free(eth_dev->data->hash_mac_addrs); + eth_dev->data->hash_mac_addrs = NULL; + +#ifdef RTE_LIBRTE_SECURITY + rte_free(eth_dev->security_ctx); +#endif + return 0; } @@ -105,25 +203,62 @@ atl_dev_configure(struct rte_eth_dev *dev __rte_unused) * It returns 0 on success. */ static int -atl_dev_start(struct rte_eth_dev *dev __rte_unused) +atl_dev_start(struct rte_eth_dev *dev) { - return 0; + struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private); + int status; + int err; + + PMD_INIT_FUNC_TRACE(); + + /* stop adapter */ + hw->adapter_stopped = 0; + + /* reinitialize adapter + * this calls reset and start + */ + status = atl_reset_hw(hw); + if (status != 0) + return -1; + + err = hw_atl_b0_hw_init(hw, (uint8_t *)dev->data->mac_addrs); + + hw_atl_b0_hw_start(hw); + + atl_print_adapter_info(hw); + + return err; } /* * Stop device: disable rx and tx functions to allow for reconfiguring. */ static void -atl_dev_stop(struct rte_eth_dev *dev __rte_unused) +atl_dev_stop(struct rte_eth_dev *dev) { + struct aq_hw_s *hw = + ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private); + + /* reset the NIC */ + atl_reset_hw(hw); + hw->adapter_stopped = 0; + } /* * Reset and stop device. */ static void -atl_dev_close(struct rte_eth_dev *dev __rte_unused) +atl_dev_close(struct rte_eth_dev *dev) { + struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private); + + PMD_INIT_FUNC_TRACE(); + + atl_reset_hw(hw); + + atl_dev_stop(dev); + hw->adapter_stopped = 1; } static int @@ -140,6 +275,53 @@ atl_dev_reset(struct rte_eth_dev *dev) return ret; } +static int +atl_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size) +{ + struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private); + uint32_t fw_ver = 0; + unsigned int ret = 0; + + ret = hw_atl_utils_get_fw_version(hw, &fw_ver); + if (ret) + return 0; + + ret = snprintf(fw_version, fw_size, "%u.%u.%u", fw_ver >> 24, + (fw_ver >> 16) & 0xFFU, fw_ver & 0xFFFFU); + + ret += 1; /* add string null-terminator */ + + if (fw_size < ret) + return ret; + + return 0; +} + +static void +atl_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) +{ + struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); + + dev_info->max_vfs = pci_dev->max_vfs; + + dev_info->max_hash_mac_addrs = 0; + dev_info->max_vmdq_pools = 0; + dev_info->vmdq_queue_num = 0; +} + RTE_PMD_REGISTER_PCI(net_atlantic, rte_atl_pmd); RTE_PMD_REGISTER_PCI_TABLE(net_atlantic, pci_id_atl_map); RTE_PMD_REGISTER_KMOD_DEP(net_atlantic, "* igb_uio | uio_pci_generic"); + +RTE_INIT(atl_init_log); +static void +atl_init_log(void) +{ + atl_logtype_init = rte_log_register("pmd.atlantic.init"); + if (atl_logtype_init >= 0) + rte_log_set_level(atl_logtype_init, RTE_LOG_DEBUG); + atl_logtype_driver = rte_log_register("pmd.atlantic.driver"); + if (atl_logtype_driver >= 0) + rte_log_set_level(atl_logtype_driver, RTE_LOG_DEBUG); +} + diff --git a/drivers/net/atlantic/atl_ethdev.h b/drivers/net/atlantic/atl_ethdev.h index ae87517560de..0b5db79e1c22 100644 --- a/drivers/net/atlantic/atl_ethdev.h +++ b/drivers/net/atlantic/atl_ethdev.h @@ -6,10 +6,18 @@ #define _ATLANTIC_ETHDEV_H_ #include +#include "atl_types.h" +#include "hw_atl/hw_atl_utils.h" + +#define ATL_DEV_PRIVATE_TO_HW(adapter) \ + (&((struct atl_adapter *)adapter)->hw) + /* * Structure to store private data for each driver instance (for each port). */ struct atl_adapter { + struct aq_hw_s hw; + struct aq_hw_cfg_s hw_cfg; }; #endif /* _ATLANTIC_ETHDEV_H_ */ diff --git a/drivers/net/atlantic/atl_types.h b/drivers/net/atlantic/atl_types.h index 8185a86e1733..85f768ce7d93 100644 --- a/drivers/net/atlantic/atl_types.h +++ b/drivers/net/atlantic/atl_types.h @@ -83,6 +83,10 @@ struct aq_hw_cfg_s { }; struct aq_hw_s { + u16 device_id; + u16 vendor_id; + bool adapter_stopped; + u8 rbl_enabled:1; struct aq_hw_cfg_s *aq_nic_cfg; const struct aq_fw_ops *aq_fw_ops; From patchwork Sat Sep 29 10:30:22 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Russkikh X-Patchwork-Id: 45672 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id C42D31B1F0; Sat, 29 Sep 2018 12:31:46 +0200 (CEST) Received: from NAM05-DM3-obe.outbound.protection.outlook.com (mail-eopbgr730061.outbound.protection.outlook.com [40.107.73.61]) by dpdk.org (Postfix) with ESMTP id 676AD1B1AB for ; Sat, 29 Sep 2018 12:31:40 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=AQUANTIA1COM.onmicrosoft.com; s=selector1-aquantia-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=XtJyIql02OHd9GRWhQ6MwDVzjo12OjDYAIWzlWT9HJI=; b=ouwBIdFxVfoqizOrHRM8XPAAulSJ1Uoel/g3yTX0d6YcPSrsls3xkDIuJpoDqusxG3SM+3uIFzcsDESeZ9sd5hDiGEGLtjUS5A8gC6Rj+HReIKBQbhZYUsjXuecQWddL+YAJpAj3b+odxYHf+Cwc6lVvB8LMyATjxmKerMN8NDY= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Igor.Russkikh@aquantia.com; Received: from ubuntubox.rdc.aquantia.com (95.79.108.179) by BLUPR0701MB1650.namprd07.prod.outlook.com (2a01:111:e400:58c6::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1185.22; Sat, 29 Sep 2018 10:31:38 +0000 From: Igor Russkikh To: dev@dpdk.org Cc: pavel.belous@aquantia.com, igor.russkikh@aquantia.com Date: Sat, 29 Sep 2018 13:30:22 +0300 Message-Id: X-Mailer: git-send-email 2.7.4 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [95.79.108.179] X-ClientProxiedBy: VI1P193CA0009.EURP193.PROD.OUTLOOK.COM (2603:10a6:800:bd::19) To BLUPR0701MB1650.namprd07.prod.outlook.com (2a01:111:e400:58c6::20) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: b69809be-22a0-4ca7-744d-08d625f6bd78 X-Microsoft-Antispam: BCL:0; PCL:0; RULEID:(7020095)(4652040)(8989299)(4534165)(4627221)(201703031133081)(201702281549075)(8990200)(5600074)(711020)(2017052603328)(7153060)(7193020); SRVR:BLUPR0701MB1650; X-Microsoft-Exchange-Diagnostics: 1; BLUPR0701MB1650; 3:qJl7lyUynCibV9Yhx6sGOHR2fowFTCUkFR4my4OgU0nKhwym7+4Kjual3Wj9eeCYMPoJZ3MXfnozoBEPql7mCupgcUu/O8gzkhrVXBzl/eMj6+NDJsMmZnB/F0DGQLsS4mXdTn4rb0i7eHELWBLa3rdQ1O2rYiXkPCB+F0vB953CcDNvX9Ra7lZKi4/a3yZeguGS2up/SwhhBFcgwnDj9UYG923hTnHSHciANt/4yyqnP4ShOpshygOkZHTQV+da; 25:jocY9PcIZHqYU5kDbJpCf8/oVGaqyybInyQ7q8hoQwk6QWBEQ40K4SOeba50NBdM/q6yJl7aHX2Bd/P7DhKEZ1CwdnAuvw4sBCR+VhDaF2EsSz2wa/Ep6keFZuCx1sxX9FuKMBRxyCUIHXlpFeRFjNRiRUWjKPPV3Lv/GG6pECv8G0lqSKqc4VW/bJ/GvW8tyvlk7ousvluwt9lgHcrsESdW4MJ7W/N+r2vadT7TSZm++UswzErgKgZPgSsRSq+G8h36npSJ3H3a2FaedzdGQd21qh38yVQOq9++L725yU0UN95NTOQL18DWE52wUmvwPRhzPNWIkTWcHV/5aPEKSXr8/gCmCm9lXMdZuZfG4RU=; 31:9NiugVS8ZBED4nuWHmKHFWEnagkXkogj4MtIohwUe92rud4GZlLljyA48BalhrJwGW73I9CIFnFD9T91zTve8iLMHrFKvxgXxqWxamWNlxjNFCz9x5WN3SdrlL7aMnJWtygAlehuhDnFodRQVNU57EEoX4L7xAzYBQYeSDEUmW0Q7i1SddD8EYT97cKDjQOQX8moroFmvpzxfBTl87QnVfwjSN6MnMwe5TzS6o2lWKc= X-MS-TrafficTypeDiagnostic: BLUPR0701MB1650: X-Microsoft-Exchange-Diagnostics: 1; BLUPR0701MB1650; 20:Yf5nkZpVsgVoeN8+fsKuP8ZzbnHAnQPciTUseKCe5PMbxjh6rY6rX4iKVuBMtI4ADYHRC3v+Ol+l3dxVKEQ9zYrPWdesAfpqGVW3DuIL6jyhVaCeyipK4khmGHjc5ZuarJ54u+WbiFNCz3VAIfsc+fXJ1iEXllxwOfJJ/jWzTmpj3UWAQ6PnWeMfwBdoGsO7Q9aak0sPkly2k8QT2e3ZubR2uYARg5JXNWpBSuzkoSDjd+ABAEhMJHTs3aDEd70Sdja1Jf77JzWZ34X3JVtkg+pu/1xtMgcCcbo0H0g01AQpXUizG3mZfxEXShegyznjX/bdn72Ew6QQ5C+fPGckMSLlEqydCrGgoYEM0KpHvDc2rIZQyouGrtaOmxkFbOem07cYkFDtHE3Xi/4i/rdO6r4qfxk95EG+OsC2HqF3l6wkPzFbhw7bnvAJkE5p3aEOIEe7vFxt7wnMXHC3Ztdc7gybCNYYryhnITSUbmUFevgTG1N5bYxsaorTeO4oovXb; 4:GDTSgRxPiqqa+Z1heLes49yRJQ67pt4+KawQA0OldnNhqpyiVJsvXcnT7gQReXTQvi+OVVQBNdJuaFTfkkxRLgUu9AV4/e2TswPIUHLZ7i+apxOGPOoim5vt8/XrljwG2+aU3e2RgosXCHjRqoZIzt2u5hph1FAMKvuI+AN0l6TFlTYu7fhiVnbVwJt83cJvsubZ1RVdrrTMTSb/RnorgnFnJwYr+15ujLsBji/eE6g2+/iXOnO1lrxu4k16t9kF/PY/Ga/ODX2ag6REghgcXg== X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-MS-Exchange-SenderADCheck: 1 X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(6040522)(2401047)(8121501046)(5005006)(10201501046)(3002001)(93006095)(93001095)(3231355)(944501410)(52105095)(149066)(150057)(6041310)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123558120)(20161123564045)(20161123562045)(20161123560045)(201708071742011)(7699051); SRVR:BLUPR0701MB1650; BCL:0; PCL:0; RULEID:; SRVR:BLUPR0701MB1650; X-Forefront-PRVS: 0810818DA0 X-Forefront-Antispam-Report: SFV:NSPM; SFS:(10009020)(346002)(136003)(396003)(376002)(39850400004)(366004)(189003)(199004)(16526019)(14444005)(446003)(76176011)(2906002)(6916009)(6666003)(97736004)(8676002)(81166006)(81156014)(36756003)(4326008)(316002)(8936002)(50226002)(34290500001)(575784001)(86362001)(5660300001)(68736007)(16586007)(118296001)(72206003)(3846002)(6116002)(53936002)(386003)(105586002)(6486002)(47776003)(66066001)(486006)(25786009)(305945005)(50466002)(44832011)(956004)(2616005)(26005)(107886003)(52116002)(51416003)(7696005)(186003)(476003)(478600001)(2361001)(7736002)(2351001)(48376002)(106356001)(11346002); DIR:OUT; SFP:1101; SCL:1; SRVR:BLUPR0701MB1650; H:ubuntubox.rdc.aquantia.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; Received-SPF: None (protection.outlook.com: aquantia.com does not designate permitted sender hosts) X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; BLUPR0701MB1650; 23:6DIrxSnln0hRm6qG04sn3ZcM6d5seaxc6DMtSS9?= kFaiItYDaT7SAsMq+49lyRx8z6OCLBGwr5TF1Y/AnQ/9TC7fH8v1PBXYJ0b3+Xgdgl93rpuRvMLaBbEgcS1YK7bu4VxOqMs/zWYYmGKgXxFt2tTJBIO91NuTkJog9IA5pW4IQ/MBUTeUv5QW+AHeQE7PKZQsepfN1tDHrvonRi8wiIPpGKNjXXYsBYUXqTuPO71j/7VpBP40gFy6UqTYO8x5s0vKiM73JgSF9pN8ogAFO93/e6JvB21KmwJq35qCxqNaoAQ5poAFMNkJ4T1hkAfnpo5y6/3itqaOVsb3MIhH6MvU/Rlg3YJT40pXpFhcfMkbSpNQUPMA2Qd1M8nUbp+IMSO5X2GSTUpHuXeCdEdHvMi7DsOkLpUy4elreMleL5X/sSpciZdBwQ+sFxrf9rPGwvdlDrCNGCQ4h+aBrs3q2gvvlp5uYLgo7ufCMzerSQ9MW2JqrtXltXjJoJP0hbgjlPED1cIIjxCusMVKWGsj29nC/Pjf1emg9o/PhTy5s6wmTstxKxEZiIfRkOmuRQdekPaNNvobw3yPDfPg+HxaBB/fXPUqQxrMfE95FIzxws4he76bZza/e6IftoxqWDNPzYH1KnHn60VgHZBIgxI9ImZkk4RGlMYm7dpSKq0flT8BRpOSaSGYyJw/nK7CmWdfIRnersWrEmVTdnCYEuOyTxMdO1gz8B5waGXHBQvj074Et0MPbLI3KMypEPikjQ/Ofq6GXneQMG5wyp9NCF8F7Z7r6WOsxSicKtEw5Mc/2+wGZS4Dyq5RhhTzkcTMK6HKP0AHTtNxy4hGS1ZGcH4zTODFjptuotD6WfEa/eIS05W44IIC2Td0E2NFfs9Ld8bJdASkbwhFxL/6RgERjmbxT3r24ytDwY/dPBnqyKz4HoS4LG943oi1hIfsxFJBWzQvl8y4Ec4wj/R19U3DO5BtpNEVQcpa0sPhiwH7sQVU3qexFq1OHTBjlHvv3xjtPQlNfgSQQd+/uCswvIt7Neefaidly73m114UV/ToHOoOjCz9K852MWJVoddf4DOcmvHBKK1+yOzCjy2Gs4tHbIGvqshZ38Et6e6Ai1jUwP1hGWmrDIqK7u/m9/Vpg4Iuien+AAsnsmRoaDeERpCKGL5+WbtCsvbMM+6W4U5LBqAGwNDR9oFG7trptdJ5tB1KHjR1EaLNrLG6vWi0nkLmDSUHSbarXW03Pb+0D1FRCsbS35RoxBkYKG2Oy7vAGb3RPqqh+fSPIetI24egwpH+1uRlSyvjA9vI1MbY426DmejlV2Xkzam5ocqlMYN6tQvPqFbRg X-Microsoft-Antispam-Message-Info: dcnzyxkEHPHULZuWC0cYnKwdA5aEmSMYgHOS1fWU3nAfmaeMGyvK2OPycYOPCKxg6GaqzLICYvg/hjTNDeFbfm2BmEPv511gHoRHrwiBQpudqonFaQojesprCrFKUR1is2c0qYLhopipu17h2g97LromXkMTeYHQvzHaZFR0KDZWwf9LZUoU2tbBwdxe5Qwdz6F8lYZP/z5H5j94X4MjI/OnBqJAv5+3upDPBYSGQP2p/04S+hZsD0Zwj3Im6MsPI/mPx9dEiqRqbUs2fnCrxneYa+r/zh7EMWJoJVays84UK87GZrk5GYg+D7R5c4YyOgTBEgfvalD2u5w618qc+A7FK2paATiVj5D1r+VWtH8= X-Microsoft-Exchange-Diagnostics: 1; BLUPR0701MB1650; 6:SIxBrdkt4FrGst1cCsssQ3W8Cfy8JFRJLI0Db7kAGJYLmKJ98kP+hW/2/QUxeU5WD/Vl7XTxypYf5NGUQNXCQ9qzFz0zFCH7vlbRYvaELMoOOV0oQ3bGLW6IVePaRKG8+mkMaIVFoQvjNSGWJdOHIGoXJMEgPaxcTbceH7TxqN2tAlYH6wDaEhg9X5K3rvXLJX+EBgGuYdpw3TiPX/QPnAjJq6lpS38byPK85DXb1goZhOKntC9f8STGmZUJjK/FUWAtZDViYg8F8Q8cBy/OqD5D1hKaHC+Geu8iXNsRucIqHj4L/A3PHF/eGq9oxgJn1whJ3rYiH9gnYyjFY3Nq6juZ0hYVNXjkhXWm0anwhfzxb87yYa5Hrsj5iQRp5bJQGVefhSb8fW09GKUjf+Cec0WX6EDxE72cHBVRWphh1BfjcRHS5rG3GM5nAAazPxGKG6aXI4hlyNRITvxNm1+BOw==; 5:UuE+SU9gGnnn9Q6BQyyKSSS8VtfY13UXipS9SBmvQauoDWAqteGC/g6C1Nzl+scRjq1NjpkO/jkQBfMGcgLsoL4qTCwogr9FvzIs/EJ5URKkeGjzLekHoLjH50Jq88PKGhFknarSz4MKoNl0CiRmlwj4sjptbcrr7cvYtBTPd4k=; 7:Z7bgIam4IxTmo3wmDJlaAmmq51e7xGFbFQMhR1lOAWeEJ/rpyD7J9Rlnesy8fbEnEf3IpM+KKmaloeReri1Y8gX5T+rA8FZpQ64V6kMvLTmbPFsvNiGotntQP6s3M/u2Rn8MU6Rl0kAEnK701yiF+OuPo4FaVh1VsEVHyRKHkM1UrZqJ2CEgkq4zmzryU4SWfs8gdxEtPZXCYNCtUa3PvPgTLTdCDGPiP295Jh3B8W0W6sUHsF5oVdzl2oAPaQ6x SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: aquantia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Sep 2018 10:31:38.1411 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b69809be-22a0-4ca7-744d-08d625f6bd78 X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 83e2e134-991c-4ede-8ced-34d47e38e6b1 X-MS-Exchange-Transport-CrossTenantHeadersStamped: BLUPR0701MB1650 Subject: [dpdk-dev] [PATCH v3 08/22] net/atlantic: TX/RX function prototypes X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavel Belous Signed-off-by: Igor Russkikh Signed-off-by: Pavel Belous --- drivers/net/atlantic/Makefile | 1 + drivers/net/atlantic/atl_ethdev.c | 20 ++++++++++++++++++- drivers/net/atlantic/atl_ethdev.h | 15 ++++++++++++++ drivers/net/atlantic/atl_rxtx.c | 42 +++++++++++++++++++++++++++++++++++++++ drivers/net/atlantic/meson.build | 1 + 5 files changed, 78 insertions(+), 1 deletion(-) create mode 100644 drivers/net/atlantic/atl_rxtx.c diff --git a/drivers/net/atlantic/Makefile b/drivers/net/atlantic/Makefile index 91306d71ba97..b88da362146d 100644 --- a/drivers/net/atlantic/Makefile +++ b/drivers/net/atlantic/Makefile @@ -24,6 +24,7 @@ VPATH += $(SRCDIR)/hw_atl # # all source are stored in SRCS-y # +SRCS-$(CONFIG_RTE_LIBRTE_ATLANTIC_PMD) += atl_rxtx.c SRCS-$(CONFIG_RTE_LIBRTE_ATLANTIC_PMD) += atl_ethdev.c SRCS-$(CONFIG_RTE_LIBRTE_ATLANTIC_PMD) += atl_hw_regs.c SRCS-$(CONFIG_RTE_LIBRTE_ATLANTIC_PMD) += hw_atl_utils.c diff --git a/drivers/net/atlantic/atl_ethdev.c b/drivers/net/atlantic/atl_ethdev.c index afb2972ffcc2..4347f9772358 100644 --- a/drivers/net/atlantic/atl_ethdev.c +++ b/drivers/net/atlantic/atl_ethdev.c @@ -111,6 +111,9 @@ eth_atl_dev_init(struct rte_eth_dev *eth_dev) PMD_INIT_FUNC_TRACE(); eth_dev->dev_ops = &atl_eth_dev_ops; + eth_dev->rx_pkt_burst = &atl_recv_pkts; + eth_dev->tx_pkt_burst = &atl_xmit_pkts; + eth_dev->tx_pkt_prepare = &atl_prep_pkts; /* For secondary processes, the primary process has done all the work */ if (rte_eal_process_type() != RTE_PROC_PRIMARY) @@ -164,6 +167,8 @@ eth_atl_dev_uninit(struct rte_eth_dev *eth_dev) atl_dev_close(eth_dev); eth_dev->dev_ops = NULL; + eth_dev->rx_pkt_burst = NULL; + eth_dev->tx_pkt_burst = NULL; rte_free(eth_dev->data->mac_addrs); eth_dev->data->mac_addrs = NULL; @@ -224,10 +229,23 @@ atl_dev_start(struct rte_eth_dev *dev) err = hw_atl_b0_hw_init(hw, (uint8_t *)dev->data->mac_addrs); hw_atl_b0_hw_start(hw); + /* initialize transmission unit */ + atl_tx_init(dev); + + /* This can fail when allocating mbufs for descriptor rings */ + err = atl_rx_init(dev); + if (err) { + PMD_INIT_LOG(ERR, "Unable to initialize RX hardware"); + goto error; + } atl_print_adapter_info(hw); - return err; + return 0; + +error: + PMD_INIT_LOG(ERR, "failure in atl_dev_start(): %d", err); + return -EIO; } /* diff --git a/drivers/net/atlantic/atl_ethdev.h b/drivers/net/atlantic/atl_ethdev.h index 0b5db79e1c22..53fbc0a17bd2 100644 --- a/drivers/net/atlantic/atl_ethdev.h +++ b/drivers/net/atlantic/atl_ethdev.h @@ -20,4 +20,19 @@ struct atl_adapter { struct aq_hw_cfg_s hw_cfg; }; +/* + * RX/TX function prototypes + */ +int atl_rx_init(struct rte_eth_dev *dev); +int atl_tx_init(struct rte_eth_dev *dev); + +uint16_t atl_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, + uint16_t nb_pkts); + +uint16_t atl_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, + uint16_t nb_pkts); + +uint16_t atl_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, + uint16_t nb_pkts); + #endif /* _ATLANTIC_ETHDEV_H_ */ diff --git a/drivers/net/atlantic/atl_rxtx.c b/drivers/net/atlantic/atl_rxtx.c new file mode 100644 index 000000000000..0fbd93038075 --- /dev/null +++ b/drivers/net/atlantic/atl_rxtx.c @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2018 Aquantia Corporation + */ + +#include "atl_ethdev.h" + +int +atl_tx_init(struct rte_eth_dev *eth_dev __rte_unused) +{ + return 0; +} + +int +atl_rx_init(struct rte_eth_dev *eth_dev __rte_unused) +{ + return 0; +} + +uint16_t +atl_prep_pkts(void *tx_queue __rte_unused, + struct rte_mbuf **tx_pkts __rte_unused, + uint16_t nb_pkts __rte_unused) +{ + return 0; +} + +uint16_t +atl_recv_pkts(void *rx_queue __rte_unused, + struct rte_mbuf **rx_pkts __rte_unused, + uint16_t nb_pkts __rte_unused) +{ + return 0; +} + +uint16_t +atl_xmit_pkts(void *tx_queue __rte_unused, + struct rte_mbuf **tx_pkts __rte_unused, + uint16_t nb_pkts __rte_unused) +{ + return 0; +} + diff --git a/drivers/net/atlantic/meson.build b/drivers/net/atlantic/meson.build index e7b4e0cba574..7575e471e306 100644 --- a/drivers/net/atlantic/meson.build +++ b/drivers/net/atlantic/meson.build @@ -4,6 +4,7 @@ #subdir('hw_atl') sources = files( + 'atl_rxtx.c', 'atl_ethdev.c', 'atl_hw_regs.c', 'hw_atl/hw_atl_b0.c', From patchwork Sat Sep 29 10:30:23 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Russkikh X-Patchwork-Id: 45673 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 5C4661B274; Sat, 29 Sep 2018 12:31:51 +0200 (CEST) Received: from NAM05-DM3-obe.outbound.protection.outlook.com (mail-eopbgr730078.outbound.protection.outlook.com [40.107.73.78]) by dpdk.org (Postfix) with ESMTP id 215461B1F9 for ; Sat, 29 Sep 2018 12:31:47 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=AQUANTIA1COM.onmicrosoft.com; s=selector1-aquantia-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=cx9uwiHeZNhvMq5hzaKJNuZYEpQJjzPV8Ufc9rpU44s=; b=pEsYhVMQBFVp+qMyvTqy6PJe0Cf5BVvqIi4y/Xkfghs0sd+AoLxcrblFIPNb1lPakmaz7xR7ntK3E6ynDi+T1pdxbstiMsQ0pFys5J5dLYr0f5GZTqfVwNbTimBmW2mQZh/iOIzB4qkicXiENZm4ej9GZ36wqbO8/WtaBzYXS5A= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Igor.Russkikh@aquantia.com; Received: from ubuntubox.rdc.aquantia.com (95.79.108.179) by BLUPR0701MB1650.namprd07.prod.outlook.com (2a01:111:e400:58c6::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1185.22; Sat, 29 Sep 2018 10:31:39 +0000 From: Igor Russkikh To: dev@dpdk.org Cc: pavel.belous@aquantia.com, igor.russkikh@aquantia.com, Pavel Belous Date: Sat, 29 Sep 2018 13:30:23 +0300 Message-Id: <97aec34cd0a29f1daea939f42da8b21f6d1393df.1538215990.git.igor.russkikh@aquantia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [95.79.108.179] X-ClientProxiedBy: VI1P193CA0009.EURP193.PROD.OUTLOOK.COM (2603:10a6:800:bd::19) To BLUPR0701MB1650.namprd07.prod.outlook.com (2a01:111:e400:58c6::20) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 26fc3576-c510-4c58-66c4-08d625f6c16b X-Microsoft-Antispam: BCL:0; PCL:0; RULEID:(7020095)(4652040)(8989299)(4534165)(4627221)(201703031133081)(201702281549075)(8990200)(5600074)(711020)(2017052603328)(7153060)(7193020); SRVR:BLUPR0701MB1650; X-Microsoft-Exchange-Diagnostics: 1; BLUPR0701MB1650; 3:fG2OJzUU+DoUZESfIaW4rGewU0xnDtw9+G1Ycur6UVEu0Wqdr72bFfycWshY2pzFW4NZxEFJOoK9QHuVI2aDs+P+Wj/p1vZAqCbvSnTQSCSsJ6NBLkQS3mhy3X/bkbHQVZbaNW1fjB/WZnYv1nMcsn1EmoEaFvJtnhDd+qJxq0ilOxKAQt4tg9xghky7qxkWUwmIUIN3XxIfnBtP4KC5vHI70P2zOrhBLtC8mYc3vzXmgGcFBmkrsdEOxAqYUI8F; 25:HEWXQbfCJm9/a5bAihDIOR3usVNerYRVRYy/PVsmzVwIBJHWDoPerxRWLEiTEYuy18TW1vIZOqamDzJK+h9gAc4oQplbT6kx77uD6IrxMPElIJo496tsqDsBzGDegbr7aSlsN0tN2Fq7tWrEVB+kH/sVVLZrK/0xfkv7/AEc3pq5BC8m8MlTXyRb/YNo0izLyeJPVRsIKcyOoDLBkgEvIjC5IkXZ5E8ovz8n/Z04I/MwLoWPrUjxKphXiRkhwzKWOYi7DnmngLZTnyKFYJNgDr218GBvRyN4LFT3SMckRf/GN0Z39j4nf87+Ig0yzxnE3hhxw6oZ7rKQDW6npRXtrJqJk2LUyPS6khig42SfJ1Y=; 31:qFt5JJohwaryzQyd8PGZIb4YYVAPKkXLhT4KbsAMuiIZCamaWfiobzAFjLgZt8W59Vt59E061b7PZXgZJXF3vyTTPeI2Gef2e0IqNfgue6iZUD7ldZw0DmzTjfeyGr9jPBXUMXS7kSyhSKq3k3fUiXAdsi6a3coybxwj9fOSRAQOMfJqFMlYCCrIgCot+FaVRhzsoN/ayFOGjNjwPtbCGoaVG62dRFm0F3ugDVgj8ko= X-MS-TrafficTypeDiagnostic: BLUPR0701MB1650: X-Microsoft-Exchange-Diagnostics: 1; BLUPR0701MB1650; 20:tnKAHGJKlhHBwegRHep1L0Ds3y/Hcy0dQNZv+1zTEcLk1KHiWHyPNfz0v8RYvkX50XD8Xa/ewcpz5FUWd38L2oFLrwfhpYImvYG2B4dAW+6NMluO/8OBB0R0n9cWoon9MgjxTW84nrPXe0eIt7wte105YGCYPvnOGRS/m87rAyFWS275jSvb+sSLq5olcvj9AXJd6dhagFAA9GhRjj6bhj+xUMXesLN/aNyHddPcl/tYhxZccmz9HFZx/Nu7sN/fhMhqG9T7hMC2m9A9bDfRkzg3bjrktdOGZzzsocAS7u8tjZu4S/IhC5/UeF+6eRqDrIAK2fV3h8igM3S0S6v175S2r54NT2XmO2Z+j3E5y9cn6655LDekOhuXRxVBU4M6f02WTAOorldH3IyhJwKj5aO5gPY+f432sthcZxZH57WmVloFNNevg1E8Gp9+vNW2utXXvOk4X/R1PkM/mGBNufi8ebzC6Zywf/P3iLFC1ckkH3zSGfUGy1IPnGznL1Pq; 4:ucwfTBqj3eQzLNscep79U+gmQ2FqdXIBLMOZd0xxPQIY0xuQXttraLZq13ux3Il8zach3aKE+/6nO37xtAXC9sl72/fvkHl/mc6KgT43630sXMZCu9esvCEeHgyz8+xPXA4L1WV03o0SWrkFz25NCrxDaD1JoP4j5xD39Z5v25DGAw7sRXM2aPWDTXDOtAbVhh/T5IttZAqVGbuH5H8nF9qYkXmC5QUuU7ql2hz3xqNnbCsfQeDNUOci+mpty4simXv7W1w+SATFHT6DS4qUmg== X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-MS-Exchange-SenderADCheck: 1 X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(6040522)(2401047)(8121501046)(5005006)(10201501046)(3002001)(93006095)(93001095)(3231355)(944501410)(52105095)(149066)(150057)(6041310)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123558120)(20161123564045)(20161123562045)(20161123560045)(201708071742011)(7699051); SRVR:BLUPR0701MB1650; BCL:0; PCL:0; RULEID:; SRVR:BLUPR0701MB1650; X-Forefront-PRVS: 0810818DA0 X-Forefront-Antispam-Report: SFV:NSPM; SFS:(10009020)(346002)(136003)(396003)(376002)(39850400004)(366004)(189003)(199004)(16526019)(14444005)(446003)(76176011)(2906002)(6916009)(6666003)(97736004)(8676002)(81166006)(81156014)(36756003)(4326008)(316002)(8936002)(50226002)(34290500001)(575784001)(86362001)(5660300001)(68736007)(16586007)(118296001)(72206003)(3846002)(6116002)(53936002)(386003)(105586002)(6486002)(47776003)(66066001)(486006)(25786009)(305945005)(50466002)(44832011)(956004)(2616005)(26005)(107886003)(52116002)(51416003)(7696005)(186003)(476003)(478600001)(2361001)(7736002)(2351001)(48376002)(106356001)(11346002); DIR:OUT; SFP:1101; SCL:1; SRVR:BLUPR0701MB1650; H:ubuntubox.rdc.aquantia.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; Received-SPF: None (protection.outlook.com: aquantia.com does not designate permitted sender hosts) X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; BLUPR0701MB1650; 23:Fyr4G7M9S+W4Ls0M0LP/JkLMAnsE0r51xdJmcAO?= 0QAl+vXdHIYSEYLeTF/lN553Gd2bNH+7FnqIQjS/NAsSqjlSD7v5rSozQyWpB09LAxA9suNcYgF2lGdnj4rAW2My9DlHn8dvlnLTzFNtzCBYvwqyN2tgZ3So1TMPKuvn9bDytbBHGVjclJ5FA+/MUo8ILNfAtDbEO1Dd0y0ZuT9e2bB00Ii02YyYjnRxaW7WsNygi9QJYU1jXSv7CTPOsp6S+rX/YPd752uutOASNjz7DNL8eWzNR7ArWAYhvo4TazgsAteL5R7mrEouKBOnoqVnpvoMvSau8fwc/AOVVlO2CU5h0Svy2iScrSvggr1CngLglUhZjX09X+RdzyOcLDXurvoI3V9A0c9UMLAXj50wO4g4yobaWlPH2g9AtwVq7sxbP9JbAoOd5o4tKhc9VSE6qJ+f4JXAhMVbt1xNuSwkkX05p7tIZZ6zcuhokOXGZhLgj0qcOdnlmHt5ZwgbirgGHmgapiVfi80FTqQIqo72++LmeV66CrclgibTIe3oW034bUh1hHXPJpw1i5FWCCNKFnqr1qAcKMtgWXit4mgglnW04XndyLT7/uYiGi9MWTo7cv1rLSAHeyScnvlTTmQ1APb0PCXRpW20cclmI88bRBx6lzZdmWj1V/G+yLkbc/uThMpRBCm6+0lptq+PnhpoI20q82ub16AWs5QR7jKKy9tFxc13JiImeHVEbL8TOFBKuKln+w5o3ZnF5a6tLoKddLrzKI76mfYlUSaYH5sWuqMnjDwcPWNSGqwKeuHgaEPsUlcTxlTqrpPQ46ioqNPzElHcsyu39v/OG9XiuZbqJw1XnXW2s82soa13oloDNsXnEnjUe7Fq0EZOjkwvDH2wKVaNKX/Z4N/vqpVCLUD9UDe0Ab9c2fVcQx/9lm4b9Y2EVafOx3QxJW+XI7BUi2LfvfBkeXWRKEWv/m3xxIMaCOGumdctJVCWBa1SIK0vSzF4xyINNfThY07vihrhv/LwR2VrtfSzyrkWYRK6slCPjGBKRKOSQbxIMMqThyzxg+QZQtlhVI4XCeLlKjJe2sWCkGFjzM5hfbaZuOukXMIjn9wfHAAtJ0mHtv+XLlzBTAVsqbRn37RGf8KNyw5hXx7crA+7/XzwmzQsh99q02JXKhieHF2dgQHuFkA5RNhKltiYHDIcl+NMC2e5t4zmjF3zer03ZcYiTqhV4UVqALEP7BG3AtkRi8jarhaWpYmKQyvPpl3dI01FLqo3nlDbQkPFD4tUN7AM/FmHOxYvqXPkfI/KYQvpPkWbXuq1kO3t75MeN1ujQSIaLu37pvbYvXx0u X-Microsoft-Antispam-Message-Info: 0OD52yvhulVUC+X4u+fGMdDOil4dI3eWc43AkJVNyzpIrr67jvdspZ6DrZ4R5ZiigxV2WxzUfCU6O+7PNRezcSUH/JRJZHZiTsNrhMReempGUXcL96S2qEu0FJjnublOkir1GOnPGWHuQTs15C1r0HE+4FpDc8rSuTaGLN3BV4NHec3vKZwzbGY2h5o7kXtsWX3X/Y2MR0bj9BPIMWUMlWBa/bCUFvDrYMbtOdhq3pp2ZZUP3kBsSU1ZiYKl6ndtk+5d6JBqjgwNPg7wu58ImK/VyfU4xHUyC/GpQLEIgK+StFG3DKJfoMGQi+XFQZN394gV4qrQfXEGHjN+kXljZbPdgo3s2KJrEcu1HUo09JY= X-Microsoft-Exchange-Diagnostics: 1; BLUPR0701MB1650; 6:2TUbWd2wIbNs6EctZPBPIPkud4nTj5/ijTIqaCpZWC6a7URdDJbOUQ946lY4Tkm5SLFKrOsSfAPxZuleKP5MY0VAboeKiCLFik1mZj3tJXhRPTP1+bRtg39mXfugxC/Ayj/9m57iZm62zpuORh9QDZhDsTb66JxUtcxZ5HT9NIsBoY5CRC/8N2Hsrvx4Rh9eG5cWYl5PMISNev8IncxmWG6nxA3XFGu3R+CY4cILbdeNxTuPtXNTQa7R9Ev2BqF99WySEYFNHUKK6Ge7fWZCU57G8b/mdnPM8gfKINNlbHI1DZeN1WRPyxEbNklZb3EBsojSZAkUnRhCH72s5AMTL8ydhB0+wD/NsqMmtplQk++HWey0+NCv87H9oBjEC6eGEWDCi5/QQNeGbgXQQP4ZbP8exqtk0c/D8NDoBfWRlZLkAs1AzqF5llt45dNcWg+8tT23kBK7KTEhBKcFfeOPSg==; 5:RKLXRmEEZk+X4d0Qd36LhwNjRL1indxVvC4jzjsT8KdGicccPBbXYHmzLYEi/iTgZ+iiPdWPH6ysixlO3OPzCg5LTsUaiGplh4xnl3Q57OGFS/w0bVWUznx2PPLXY0Lf0SXp6ypil0k4agFRHljsdszV4/WlLkUaeI2xLZ1atok=; 7:vEemLFrZqo9UuU1f0B/Jjn1aKuO4TG/ORqAOl4DKUqROC9Ul56+kjca9iFdjHqxK/ulCOtgET8AQGXcOLJgY/3Kc1ksU3iCKCRnhpQsIVVKzfUYKpBv8p4yPrKRJ0iJ6+jxBZCS5zeWm1Sh5spls/u7On7fdtub/ofXkzNqVuasI73yLrLb+DqN9NfTaS3gKrGEpFCchjXIe2oWNYW9CMroCl1jJVe0buf5X2SNTija5hR4hI2LctwMtgh+H07O3 SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: aquantia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Sep 2018 10:31:39.6099 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 26fc3576-c510-4c58-66c4-08d625f6c16b X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 83e2e134-991c-4ede-8ced-34d47e38e6b1 X-MS-Exchange-Transport-CrossTenantHeadersStamped: BLUPR0701MB1650 Subject: [dpdk-dev] [PATCH v3 09/22] net/atlantic: RX side structures and implementation X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Signed-off-by: Igor Russkikh Signed-off-by: Pavel Belous --- drivers/net/atlantic/Makefile | 2 +- drivers/net/atlantic/atl_ethdev.c | 71 +++++ drivers/net/atlantic/atl_ethdev.h | 19 ++ drivers/net/atlantic/atl_rxtx.c | 616 +++++++++++++++++++++++++++++++++++++- 4 files changed, 702 insertions(+), 6 deletions(-) diff --git a/drivers/net/atlantic/Makefile b/drivers/net/atlantic/Makefile index b88da362146d..62dcdbffa69c 100644 --- a/drivers/net/atlantic/Makefile +++ b/drivers/net/atlantic/Makefile @@ -15,7 +15,7 @@ EXPORT_MAP := rte_pmd_atlantic_version.map LIBABIVER := 1 -LDLIBS += -lrte_eal +LDLIBS += -lrte_eal -lrte_mbuf -lrte_mempool -lrte_ring LDLIBS += -lrte_ethdev -lrte_net LDLIBS += -lrte_bus_pci diff --git a/drivers/net/atlantic/atl_ethdev.c b/drivers/net/atlantic/atl_ethdev.c index 4347f9772358..cdcfc5ec02c2 100644 --- a/drivers/net/atlantic/atl_ethdev.c +++ b/drivers/net/atlantic/atl_ethdev.c @@ -27,6 +27,7 @@ static int atl_fw_version_get(struct rte_eth_dev *dev, char *fw_version, static void atl_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info); +static const uint32_t *atl_dev_supported_ptypes_get(struct rte_eth_dev *dev); static int eth_atl_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, struct rte_pci_device *pci_dev); @@ -72,6 +73,18 @@ static struct rte_pci_driver rte_atl_pmd = { .remove = eth_atl_pci_remove, }; +#define ATL_RX_OFFLOADS (DEV_RX_OFFLOAD_VLAN_STRIP \ + | DEV_RX_OFFLOAD_IPV4_CKSUM \ + | DEV_RX_OFFLOAD_UDP_CKSUM \ + | DEV_RX_OFFLOAD_TCP_CKSUM \ + | DEV_RX_OFFLOAD_JUMBO_FRAME) + +static const struct rte_eth_desc_lim rx_desc_lim = { + .nb_max = ATL_MAX_RING_DESC, + .nb_min = ATL_MIN_RING_DESC, + .nb_align = ATL_RXD_ALIGN, +}; + static const struct eth_dev_ops atl_eth_dev_ops = { .dev_configure = atl_dev_configure, .dev_start = atl_dev_start, @@ -81,6 +94,13 @@ static const struct eth_dev_ops atl_eth_dev_ops = { .fw_version_get = atl_fw_version_get, .dev_infos_get = atl_dev_info_get, + .dev_supported_ptypes_get = atl_dev_supported_ptypes_get, + + /* Queue Control */ + .rx_queue_start = atl_rx_queue_start, + .rx_queue_stop = atl_rx_queue_stop, + .rx_queue_setup = atl_rx_queue_setup, + .rx_queue_release = atl_rx_queue_release, }; static inline int32_t @@ -239,12 +259,19 @@ atl_dev_start(struct rte_eth_dev *dev) goto error; } + err = atl_start_queues(dev); + if (err < 0) { + PMD_INIT_LOG(ERR, "Unable to start rxtx queues"); + goto error; + } + atl_print_adapter_info(hw); return 0; error: PMD_INIT_LOG(ERR, "failure in atl_dev_start(): %d", err); + atl_stop_queues(dev); return -EIO; } @@ -261,6 +288,12 @@ atl_dev_stop(struct rte_eth_dev *dev) atl_reset_hw(hw); hw->adapter_stopped = 0; + atl_stop_queues(dev); + + /* Clear stored conf */ + dev->data->scattered_rx = 0; + dev->data->lro = 0; + } /* @@ -277,6 +310,8 @@ atl_dev_close(struct rte_eth_dev *dev) atl_dev_stop(dev); hw->adapter_stopped = 1; + + atl_free_queues(dev); } static int @@ -320,11 +355,47 @@ atl_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) { struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); + dev_info->max_rx_queues = AQ_HW_MAX_RX_QUEUES; + dev_info->max_tx_queues = AQ_HW_MAX_TX_QUEUES; + + dev_info->min_rx_bufsize = 1024; + dev_info->max_rx_pktlen = HW_ATL_B0_MTU_JUMBO; + dev_info->max_mac_addrs = HW_ATL_B0_MAC_MAX; dev_info->max_vfs = pci_dev->max_vfs; dev_info->max_hash_mac_addrs = 0; dev_info->max_vmdq_pools = 0; dev_info->vmdq_queue_num = 0; + + dev_info->rx_offload_capa = ATL_RX_OFFLOADS; + + dev_info->default_rxconf = (struct rte_eth_rxconf) { + .rx_free_thresh = ATL_DEFAULT_RX_FREE_THRESH, + }; + + dev_info->rx_desc_lim = rx_desc_lim; +} + +static const uint32_t * +atl_dev_supported_ptypes_get(struct rte_eth_dev *dev) +{ + static const uint32_t ptypes[] = { + RTE_PTYPE_L2_ETHER, + RTE_PTYPE_L2_ETHER_ARP, + RTE_PTYPE_L2_ETHER_VLAN, + RTE_PTYPE_L3_IPV4, + RTE_PTYPE_L3_IPV6, + RTE_PTYPE_L4_TCP, + RTE_PTYPE_L4_UDP, + RTE_PTYPE_L4_SCTP, + RTE_PTYPE_L4_ICMP, + RTE_PTYPE_UNKNOWN + }; + + if (dev->rx_pkt_burst == atl_recv_pkts) + return ptypes; + + return NULL; } RTE_PMD_REGISTER_PCI(net_atlantic, rte_atl_pmd); diff --git a/drivers/net/atlantic/atl_ethdev.h b/drivers/net/atlantic/atl_ethdev.h index 53fbc0a17bd2..acb3066c189f 100644 --- a/drivers/net/atlantic/atl_ethdev.h +++ b/drivers/net/atlantic/atl_ethdev.h @@ -12,6 +12,10 @@ #define ATL_DEV_PRIVATE_TO_HW(adapter) \ (&((struct atl_adapter *)adapter)->hw) +#define ATL_DEV_TO_ADAPTER(dev) \ + ((struct atl_adapter *)(dev)->data->dev_private) + + /* * Structure to store private data for each driver instance (for each port). */ @@ -23,9 +27,24 @@ struct atl_adapter { /* * RX/TX function prototypes */ +void atl_rx_queue_release(void *rxq); + +int atl_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id, + uint16_t nb_rx_desc, unsigned int socket_id, + const struct rte_eth_rxconf *rx_conf, + struct rte_mempool *mb_pool); + int atl_rx_init(struct rte_eth_dev *dev); int atl_tx_init(struct rte_eth_dev *dev); +int atl_start_queues(struct rte_eth_dev *dev); +int atl_stop_queues(struct rte_eth_dev *dev); +void atl_free_queues(struct rte_eth_dev *dev); + +int atl_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id); +int atl_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id); + + uint16_t atl_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts); diff --git a/drivers/net/atlantic/atl_rxtx.c b/drivers/net/atlantic/atl_rxtx.c index 0fbd93038075..0ce41aaf1780 100644 --- a/drivers/net/atlantic/atl_rxtx.c +++ b/drivers/net/atlantic/atl_rxtx.c @@ -2,7 +2,146 @@ * Copyright(c) 2018 Aquantia Corporation */ +#include +#include + #include "atl_ethdev.h" +#include "atl_hw_regs.h" + +#include "atl_logs.h" +#include "hw_atl/hw_atl_llh.h" +#include "hw_atl/hw_atl_b0.h" +#include "hw_atl/hw_atl_b0_internal.h" + +/** + * Structure associated with each descriptor of the RX ring of a RX queue. + */ +struct atl_rx_entry { + struct rte_mbuf *mbuf; +}; + +/** + * Structure associated with each RX queue. + */ +struct atl_rx_queue { + struct rte_mempool *mb_pool; + struct hw_atl_rxd_s *hw_ring; + uint64_t hw_ring_phys_addr; + struct atl_rx_entry *sw_ring; + uint16_t nb_rx_desc; + uint16_t rx_tail; + uint16_t nb_rx_hold; + uint16_t rx_free_thresh; + uint16_t queue_id; + uint16_t port_id; + uint16_t buff_size; + bool l3_csum_enabled; + bool l4_csum_enabled; +}; + +static inline void +atl_reset_rx_queue(struct atl_rx_queue *rxq) +{ + struct hw_atl_rxd_s *rxd = NULL; + int i; + + PMD_INIT_FUNC_TRACE(); + + for (i = 0; i < rxq->nb_rx_desc; i++) { + rxd = (struct hw_atl_rxd_s *)&rxq->hw_ring[i]; + rxd->buf_addr = 0; + rxd->hdr_addr = 0; + } + + rxq->rx_tail = 0; +} + +int +atl_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id, + uint16_t nb_rx_desc, unsigned int socket_id, + const struct rte_eth_rxconf *rx_conf, + struct rte_mempool *mb_pool) +{ + struct atl_rx_queue *rxq; + const struct rte_memzone *mz; + + PMD_INIT_FUNC_TRACE(); + + /* make sure a valid number of descriptors have been requested */ + if (nb_rx_desc < AQ_HW_MIN_RX_RING_SIZE || + nb_rx_desc > AQ_HW_MAX_RX_RING_SIZE) { + PMD_INIT_LOG(ERR, "Number of Rx descriptors must be " + "less than or equal to %d, " + "greater than or equal to %d", AQ_HW_MAX_RX_RING_SIZE, + AQ_HW_MIN_RX_RING_SIZE); + return -EINVAL; + } + + /* + * if this queue existed already, free the associated memory. The + * queue cannot be reused in case we need to allocate memory on + * different socket than was previously used. + */ + if (dev->data->rx_queues[rx_queue_id] != NULL) { + atl_rx_queue_release(dev->data->rx_queues[rx_queue_id]); + dev->data->rx_queues[rx_queue_id] = NULL; + } + + /* allocate memory for the queue structure */ + rxq = rte_zmalloc_socket("atlantic Rx queue", sizeof(*rxq), + RTE_CACHE_LINE_SIZE, socket_id); + if (rxq == NULL) { + PMD_INIT_LOG(ERR, "Cannot allocate queue structure"); + return -ENOMEM; + } + + /* setup queue */ + rxq->mb_pool = mb_pool; + rxq->nb_rx_desc = nb_rx_desc; + rxq->port_id = dev->data->port_id; + rxq->queue_id = rx_queue_id; + rxq->rx_free_thresh = rx_conf->rx_free_thresh; + + rxq->l3_csum_enabled = dev->data->dev_conf.rxmode.offloads & + DEV_RX_OFFLOAD_IPV4_CKSUM; + rxq->l4_csum_enabled = dev->data->dev_conf.rxmode.offloads & + (DEV_RX_OFFLOAD_UDP_CKSUM | DEV_RX_OFFLOAD_TCP_CKSUM); + if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) + PMD_DRV_LOG(ERR, "PMD does not support KEEP_CRC offload"); + + /* allocate memory for the software ring */ + rxq->sw_ring = rte_zmalloc_socket("atlantic sw rx ring", + nb_rx_desc * sizeof(struct atl_rx_entry), + RTE_CACHE_LINE_SIZE, socket_id); + if (rxq->sw_ring == NULL) { + PMD_INIT_LOG(ERR, "Cannot allocate software ring"); + rte_free(rxq); + return -ENOMEM; + } + + /* + * allocate memory for the hardware descriptor ring. A memzone large + * enough to hold the maximum ring size is requested to allow for + * resizing in later calls to the queue setup function. + */ + mz = rte_eth_dma_zone_reserve(dev, "rx hw_ring", rx_queue_id, + HW_ATL_B0_MAX_RXD * + sizeof(struct hw_atl_rxd_s), + 128, socket_id); + if (mz == NULL) { + PMD_INIT_LOG(ERR, "Cannot allocate hardware ring"); + rte_free(rxq->sw_ring); + rte_free(rxq); + return -ENOMEM; + } + rxq->hw_ring = mz->addr; + rxq->hw_ring_phys_addr = mz->iova; + + atl_reset_rx_queue(rxq); + + dev->data->rx_queues[rx_queue_id] = rxq; + return 0; +} int atl_tx_init(struct rte_eth_dev *eth_dev __rte_unused) @@ -11,11 +150,169 @@ atl_tx_init(struct rte_eth_dev *eth_dev __rte_unused) } int -atl_rx_init(struct rte_eth_dev *eth_dev __rte_unused) +atl_rx_init(struct rte_eth_dev *eth_dev) +{ + struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); + struct atl_rx_queue *rxq; + uint64_t base_addr = 0; + int i = 0; + int err = 0; + + PMD_INIT_FUNC_TRACE(); + + for (i = 0; i < eth_dev->data->nb_rx_queues; i++) { + rxq = eth_dev->data->rx_queues[i]; + base_addr = rxq->hw_ring_phys_addr; + + /* Take requested pool mbuf size and adapt + * descriptor buffer to best fit + */ + int buff_size = rte_pktmbuf_data_room_size(rxq->mb_pool) - + RTE_PKTMBUF_HEADROOM; + + buff_size = RTE_ALIGN_FLOOR(buff_size, 1024); + if (buff_size > HW_ATL_B0_RXD_BUF_SIZE_MAX) { + PMD_INIT_LOG(WARNING, + "queue %d: mem pool buff size is too big\n", + rxq->queue_id); + buff_size = HW_ATL_B0_RXD_BUF_SIZE_MAX; + } + if (buff_size < 1024) { + PMD_INIT_LOG(ERR, + "queue %d: mem pool buff size is too small\n", + rxq->queue_id); + return -EINVAL; + } + rxq->buff_size = buff_size; + + err = hw_atl_b0_hw_ring_rx_init(hw, base_addr, rxq->queue_id, + rxq->nb_rx_desc, buff_size, 0, + rxq->port_id); + } + + return err; +} + +static int +atl_alloc_rx_queue_mbufs(struct atl_rx_queue *rxq) +{ + struct atl_rx_entry *rx_entry = rxq->sw_ring; + struct hw_atl_rxd_s *rxd; + uint64_t dma_addr = 0; + uint32_t i = 0; + + PMD_INIT_FUNC_TRACE(); + + /* fill Rx ring */ + for (i = 0; i < rxq->nb_rx_desc; i++) { + struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mb_pool); + + if (mbuf == NULL) { + PMD_INIT_LOG(ERR, "mbuf alloca failed for rx queue %u", + (unsigned int)rxq->queue_id); + return -ENOMEM; + } + + mbuf->data_off = RTE_PKTMBUF_HEADROOM; + mbuf->port = rxq->port_id; + + dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf)); + rxd = (struct hw_atl_rxd_s *)&rxq->hw_ring[i]; + rxd->buf_addr = dma_addr; + rxd->hdr_addr = 0; + rx_entry[i].mbuf = mbuf; + } + + return 0; +} + +static void +atl_rx_queue_release_mbufs(struct atl_rx_queue *rxq) +{ + int i; + + PMD_INIT_FUNC_TRACE(); + + if (rxq->sw_ring != NULL) { + for (i = 0; i < rxq->nb_rx_desc; i++) { + if (rxq->sw_ring[i].mbuf != NULL) { + rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf); + rxq->sw_ring[i].mbuf = NULL; + } + } + } +} + +int +atl_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id) { + struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct atl_rx_queue *rxq = NULL; + + PMD_INIT_FUNC_TRACE(); + + if (rx_queue_id < dev->data->nb_rx_queues) { + rxq = dev->data->rx_queues[rx_queue_id]; + + if (atl_alloc_rx_queue_mbufs(rxq) != 0) { + PMD_INIT_LOG(ERR, "Allocate mbufs for queue %d failed", + rx_queue_id); + return -1; + } + + hw_atl_b0_hw_ring_rx_start(hw, rx_queue_id); + + rte_wmb(); + hw_atl_reg_rx_dma_desc_tail_ptr_set(hw, rxq->nb_rx_desc - 1, + rx_queue_id); + dev->data->rx_queue_state[rx_queue_id] = + RTE_ETH_QUEUE_STATE_STARTED; + } else { + return -1; + } + return 0; } +int +atl_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id) +{ + struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct atl_rx_queue *rxq = NULL; + + PMD_INIT_FUNC_TRACE(); + + if (rx_queue_id < dev->data->nb_rx_queues) { + rxq = dev->data->rx_queues[rx_queue_id]; + + hw_atl_b0_hw_ring_rx_stop(hw, rx_queue_id); + + atl_rx_queue_release_mbufs(rxq); + atl_reset_rx_queue(rxq); + + dev->data->rx_queue_state[rx_queue_id] = + RTE_ETH_QUEUE_STATE_STOPPED; + } else { + return -1; + } + + return 0; +} + +void +atl_rx_queue_release(void *rx_queue) +{ + PMD_INIT_FUNC_TRACE(); + + if (rx_queue != NULL) { + struct atl_rx_queue *rxq = (struct atl_rx_queue *)rx_queue; + + atl_rx_queue_release_mbufs(rxq); + rte_free(rxq->sw_ring); + rte_free(rxq); + } +} + uint16_t atl_prep_pkts(void *tx_queue __rte_unused, struct rte_mbuf **tx_pkts __rte_unused, @@ -24,14 +321,323 @@ atl_prep_pkts(void *tx_queue __rte_unused, return 0; } -uint16_t -atl_recv_pkts(void *rx_queue __rte_unused, - struct rte_mbuf **rx_pkts __rte_unused, - uint16_t nb_pkts __rte_unused) +void +atl_free_queues(struct rte_eth_dev *dev) +{ + unsigned int i; + + PMD_INIT_FUNC_TRACE(); + + for (i = 0; i < dev->data->nb_rx_queues; i++) { + atl_rx_queue_release(dev->data->rx_queues[i]); + dev->data->rx_queues[i] = 0; + } + dev->data->nb_rx_queues = 0; +} + +int +atl_start_queues(struct rte_eth_dev *dev) { + int i; + + PMD_INIT_FUNC_TRACE(); + + for (i = 0; i < dev->data->nb_rx_queues; i++) { + if (atl_rx_queue_start(dev, i) != 0) { + PMD_DRV_LOG(ERR, "Start Rx queue %d failed", i); + return -1; + } + } + return 0; } +int +atl_stop_queues(struct rte_eth_dev *dev) +{ + int i; + + PMD_INIT_FUNC_TRACE(); + + for (i = 0; i < dev->data->nb_rx_queues; i++) { + if (atl_rx_queue_stop(dev, i) != 0) { + PMD_DRV_LOG(ERR, "Stop Rx queue %d failed", i); + return -1; + } + } + + return 0; +} + +static uint64_t +atl_desc_to_offload_flags(struct atl_rx_queue *rxq, + struct hw_atl_rxd_wb_s *rxd_wb) +{ + uint64_t mbuf_flags = 0; + + PMD_INIT_FUNC_TRACE(); + + /* IPv4 ? */ + if (rxq->l3_csum_enabled && ((rxd_wb->pkt_type & 0x3) == 0)) { + /* IPv4 csum error ? */ + if (rxd_wb->rx_stat & BIT(1)) + mbuf_flags |= PKT_RX_IP_CKSUM_BAD; + else + mbuf_flags |= PKT_RX_IP_CKSUM_GOOD; + } else { + mbuf_flags |= PKT_RX_IP_CKSUM_UNKNOWN; + } + + /* CSUM calculated ? */ + if (rxq->l4_csum_enabled && (rxd_wb->rx_stat & BIT(3))) { + if (rxd_wb->rx_stat & BIT(2)) + mbuf_flags |= PKT_RX_L4_CKSUM_BAD; + else + mbuf_flags |= PKT_RX_L4_CKSUM_GOOD; + } else { + mbuf_flags |= PKT_RX_L4_CKSUM_UNKNOWN; + } + + return mbuf_flags; +} + +static uint32_t +atl_desc_to_pkt_type(struct hw_atl_rxd_wb_s *rxd_wb) +{ + uint32_t type = RTE_PTYPE_UNKNOWN; + uint16_t l2_l3_type = rxd_wb->pkt_type & 0x3; + uint16_t l4_type = (rxd_wb->pkt_type & 0x1C) >> 2; + + switch (l2_l3_type) { + case 0: + type = RTE_PTYPE_L3_IPV4; + break; + case 1: + type = RTE_PTYPE_L3_IPV6; + break; + case 2: + type = RTE_PTYPE_L2_ETHER; + break; + case 3: + type = RTE_PTYPE_L2_ETHER_ARP; + break; + } + + switch (l4_type) { + case 0: + type |= RTE_PTYPE_L4_TCP; + break; + case 1: + type |= RTE_PTYPE_L4_UDP; + break; + case 2: + type |= RTE_PTYPE_L4_SCTP; + break; + case 3: + type |= RTE_PTYPE_L4_ICMP; + break; + } + + if (rxd_wb->pkt_type & BIT(5)) + type |= RTE_PTYPE_L2_ETHER_VLAN; + + return type; +} + +uint16_t +atl_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts) +{ + struct atl_rx_queue *rxq = (struct atl_rx_queue *)rx_queue; + struct rte_eth_dev *dev = &rte_eth_devices[rxq->port_id]; + struct atl_adapter *adapter = + ATL_DEV_TO_ADAPTER(&rte_eth_devices[rxq->port_id]); + struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(adapter); + struct atl_rx_entry *sw_ring = rxq->sw_ring; + + struct rte_mbuf *new_mbuf; + struct rte_mbuf *rx_mbuf, *rx_mbuf_prev, *rx_mbuf_first; + struct atl_rx_entry *rx_entry; + uint16_t nb_rx = 0; + uint16_t nb_hold = 0; + struct hw_atl_rxd_wb_s rxd_wb; + struct hw_atl_rxd_s *rxd = NULL; + uint16_t tail = rxq->rx_tail; + uint64_t dma_addr; + uint16_t pkt_len = 0; + + while (nb_rx < nb_pkts) { + uint16_t eop_tail = tail; + + rxd = (struct hw_atl_rxd_s *)&rxq->hw_ring[tail]; + rxd_wb = *(struct hw_atl_rxd_wb_s *)rxd; + + if (!rxd_wb.dd) { /* RxD is not done */ + break; + } + + PMD_RX_LOG(ERR, "port_id=%u queue_id=%u tail=%u " + "eop=0x%x pkt_len=%u hash=0x%x hash_type=0x%x", + (unsigned int)rxq->port_id, + (unsigned int)rxq->queue_id, + (unsigned int)tail, (unsigned int)rxd_wb.eop, + (unsigned int)rte_le_to_cpu_16(rxd_wb.pkt_len), + rxd_wb.rss_hash, rxd_wb.rss_type); + + /* RxD is not done */ + if (!rxd_wb.eop) { + while (true) { + struct hw_atl_rxd_wb_s *eop_rxwbd; + + eop_tail = (eop_tail + 1) % rxq->nb_rx_desc; + eop_rxwbd = (struct hw_atl_rxd_wb_s *) + &rxq->hw_ring[eop_tail]; + if (!eop_rxwbd->dd) { + /* no EOP received yet */ + eop_tail = tail; + break; + } + if (eop_rxwbd->dd && eop_rxwbd->eop) + break; + } + /* No EOP in ring */ + if (eop_tail == tail) + break; + } + rx_mbuf_prev = NULL; + rx_mbuf_first = NULL; + + /* Run through packet segments */ + while (true) { + new_mbuf = rte_mbuf_raw_alloc(rxq->mb_pool); + if (new_mbuf == NULL) { + PMD_RX_LOG(ERR, + "RX mbuf alloc failed port_id=%u " + "queue_id=%u", (unsigned int)rxq->port_id, + (unsigned int)rxq->queue_id); + dev->data->rx_mbuf_alloc_failed++; + goto err_stop; + } + + nb_hold++; + rx_entry = &sw_ring[tail]; + + rx_mbuf = rx_entry->mbuf; + rx_entry->mbuf = new_mbuf; + dma_addr = rte_cpu_to_le_64( + rte_mbuf_data_iova_default(new_mbuf)); + + /* setup RX descriptor */ + rxd->hdr_addr = 0; + rxd->buf_addr = dma_addr; + + /* + * Initialize the returned mbuf. + * 1) setup generic mbuf fields: + * - number of segments, + * - next segment, + * - packet length, + * - RX port identifier. + * 2) integrate hardware offload data, if any: + * < - RSS flag & hash, + * - IP checksum flag, + * - VLAN TCI, if any, + * - error flags. + */ + pkt_len = (uint16_t)rte_le_to_cpu_16(rxd_wb.pkt_len); + rx_mbuf->data_off = RTE_PKTMBUF_HEADROOM; + rte_prefetch1((char *)rx_mbuf->buf_addr + + rx_mbuf->data_off); + rx_mbuf->nb_segs = 0; + rx_mbuf->next = NULL; + rx_mbuf->pkt_len = pkt_len; + rx_mbuf->data_len = pkt_len; + if (rxd_wb.eop) { + u16 remainder_len = pkt_len % rxq->buff_size; + if (!remainder_len) + remainder_len = rxq->buff_size; + rx_mbuf->data_len = remainder_len; + } else { + rx_mbuf->data_len = pkt_len > rxq->buff_size ? + rxq->buff_size : pkt_len; + } + rx_mbuf->port = rxq->port_id; + + rx_mbuf->hash.rss = rxd_wb.rss_hash; + + rx_mbuf->vlan_tci = rxd_wb.vlan; + + rx_mbuf->ol_flags = + atl_desc_to_offload_flags(rxq, &rxd_wb); + rx_mbuf->packet_type = atl_desc_to_pkt_type(&rxd_wb); + + if (!rx_mbuf_first) + rx_mbuf_first = rx_mbuf; + rx_mbuf_first->nb_segs++; + + if (rx_mbuf_prev) + rx_mbuf_prev->next = rx_mbuf; + rx_mbuf_prev = rx_mbuf; + + tail = (tail + 1) % rxq->nb_rx_desc; + /* Prefetch next mbufs */ + rte_prefetch0(sw_ring[tail].mbuf); + if ((tail & 0x3) == 0) { + rte_prefetch0(&sw_ring[tail]); + rte_prefetch0(&sw_ring[tail]); + } + + /* filled mbuf_first */ + if (rxd_wb.eop) + break; + rxd = (struct hw_atl_rxd_s *)&rxq->hw_ring[tail]; + rxd_wb = *(struct hw_atl_rxd_wb_s *)rxd; + }; + + /* + * Store the mbuf address into the next entry of the array + * of returned packets. + */ + rx_pkts[nb_rx++] = rx_mbuf_first; + + PMD_RX_LOG(ERR, "add mbuf segs=%d pkt_len=%d", + rx_mbuf_first->nb_segs, + rx_mbuf_first->pkt_len); + } + +err_stop: + + rxq->rx_tail = tail; + + /* + * If the number of free RX descriptors is greater than the RX free + * threshold of the queue, advance the Receive Descriptor Tail (RDT) + * register. + * Update the RDT with the value of the last processed RX descriptor + * minus 1, to guarantee that the RDT register is never equal to the + * RDH register, which creates a "full" ring situtation from the + * hardware point of view... + */ + nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold); + if (nb_hold > rxq->rx_free_thresh) { + PMD_RX_LOG(ERR, "port_id=%u queue_id=%u rx_tail=%u " + "nb_hold=%u nb_rx=%u", + (unsigned int)rxq->port_id, (unsigned int)rxq->queue_id, + (unsigned int)tail, (unsigned int)nb_hold, + (unsigned int)nb_rx); + tail = (uint16_t)((tail == 0) ? + (rxq->nb_rx_desc - 1) : (tail - 1)); + + hw_atl_reg_rx_dma_desc_tail_ptr_set(hw, tail, rxq->queue_id); + + nb_hold = 0; + } + + rxq->nb_rx_hold = nb_hold; + + return nb_rx; +} + + uint16_t atl_xmit_pkts(void *tx_queue __rte_unused, struct rte_mbuf **tx_pkts __rte_unused, From patchwork Sat Sep 29 10:30:24 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Russkikh X-Patchwork-Id: 45674 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 57F441B205; Sat, 29 Sep 2018 12:32:01 +0200 (CEST) Received: from NAM05-DM3-obe.outbound.protection.outlook.com (mail-eopbgr730046.outbound.protection.outlook.com [40.107.73.46]) by dpdk.org (Postfix) with ESMTP id CE1291B1D3 for ; Sat, 29 Sep 2018 12:31:53 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=AQUANTIA1COM.onmicrosoft.com; s=selector1-aquantia-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=+WFaZP/A4N5LIhjUjciyIiZPGZ5/MNISr4LF1bxgPpE=; b=g5YN12WgqZxGNvo1ByN/xZi287X4jstMBwNfESk0xbZBibH/ZiRoS519p/wSPEy8+/7iHtG2UQyT74Nt4OIqpwjSqk8azZzB0wwbiep/TUmQHdYkEVWbyrKuyDLxjQaKkp/rGF0Q18HKkpx7NVCA5Lj0O4npuVZofZNq5imfJRE= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Igor.Russkikh@aquantia.com; Received: from ubuntubox.rdc.aquantia.com (95.79.108.179) by BLUPR0701MB1650.namprd07.prod.outlook.com (2a01:111:e400:58c6::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1185.22; Sat, 29 Sep 2018 10:31:46 +0000 From: Igor Russkikh To: dev@dpdk.org Cc: pavel.belous@aquantia.com, igor.russkikh@aquantia.com, Pavel Belous Date: Sat, 29 Sep 2018 13:30:24 +0300 Message-Id: <88d51a926b48f55695fab80c120913ee88bd6122.1538215990.git.igor.russkikh@aquantia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [95.79.108.179] X-ClientProxiedBy: VI1P193CA0009.EURP193.PROD.OUTLOOK.COM (2603:10a6:800:bd::19) To BLUPR0701MB1650.namprd07.prod.outlook.com (2a01:111:e400:58c6::20) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 18e177b1-43cb-4fa1-1df6-08d625f6c563 X-Microsoft-Antispam: BCL:0; PCL:0; RULEID:(7020095)(4652040)(8989299)(4534165)(4627221)(201703031133081)(201702281549075)(8990200)(5600074)(711020)(2017052603328)(7153060)(7193020); SRVR:BLUPR0701MB1650; X-Microsoft-Exchange-Diagnostics: 1; BLUPR0701MB1650; 3:epc27eaxoOF69xNWo+3aYEziMkDLesxCuW96O4bAfIUU89vSBuupkHhhfDBV7/Q3AuGLLhEgIBSXcHUyjGGzdPpD4knLv8mIGrhl5bZvdqh90Erw+/neixKB2QyxlxXRj0q9J0yi3dlRqmSsbfO6w5q0x3XDNkd5xQ3ewxiRTISQDiYcEj59YwCiGnK2fPqNMskBkENTdu9YmMf0oBkCiHZwI4/TixWO5++9vC4KOtljgLGyyi4ZN36c8khCE3Qd; 25:jGxmGj/gXNDQMOjKvY8yfc6DPWC2R3QNgsHedzJgllCcOajSI+waZTrx8lRD74qfFPQrJHfKg4cgl+CwFgpltJXn5j4h19epIWnt+xJrdLWuddE0k0BxQlBLnsjFwisRzoB12G3+WUtE/dqq0nAPJ5vHRnEOIhHwXqP2E3F21uvFyJsNS4mRj0UQMU3dGMqkXU9yo8H0nUQlJMzdYKPWGkHydsX5j4y40a8AwUoSX1vVfwpEb8TLO89WNvpeM14dspTCHDM6E3I+4k05FkRg3TDhYE2yxmzKOKhBU8kKMh1AVJCgwrPGqYKprC4mzsRYCKmb0+UWgP0XeLkYWfibKA==; 31:ztZ/Gz2ThgUkI4/BL/jXJimy3PidX6Uq3rPNHbxQAMz/un6wrgl0lWwrrGiKjznQhL2OFhNndJy4lFepNerEEhfBaLNVEY0uNGZblFzW178ePYh7UdhH84B/WTDBJH4lN3k2WnKKTtgk+8muYZT6eQl6tkRDIzUQfugEKHPJZDlURxlLZRqFaLmQ2Gx7iZDYjuZ3mO4prYSSkhMG/2x0isfn1PxEF7zCloLoaJI4mn0= X-MS-TrafficTypeDiagnostic: BLUPR0701MB1650: X-Microsoft-Exchange-Diagnostics: 1; BLUPR0701MB1650; 20:eDp4D7M691F0GADr7hU/uWwD2kX2EfDsqQduQwvnlfYRKGY7HeaUf3Ax/2lXuxs4gbBDfmTNcduKYUnhFU6BEsAHezROS3GsM4Enw5pCa7ovspZVvJrSeoPA2BM14JfcKRdSSUsy+op9+3dfI+iaDH80v1D9GeCwSrVjwUuqjj+p8DBe5GJb/aLtHSD3MRz1fVEu2IJOw2bYu6zPv6w70AJYOv1cfxWFSm9e4PCQIhHr60RnPwpDGAQrxKCjkIG33sM5WcDGL8sQOLSE+uIROsC7UpNbO+FSYYIFV2aOGtg/PFBPg4OGpdWdlu9jtYMwsOGBIrMxUKWBHT8jhaJEi0H0nsFikvYP//Qchr1rAYyIJgHB68LWEFADDZrMX7qvniAqMcj9bLZH9U0A7+S+/MmzvI1lliITNFBLTvNBTZutFzBimzde/LGx3AAoSa1HwyL7hfoT7m03CvbECOLU1brgL3TsTvmLLN1d7yLbFU51MXKyhYyRFyz4q+qGABDV; 4:yx3ujsunvMbos8Bm/zG88cXtlLqHNxBUCz0YLgR8V5R8WvHtKHLB25fy/H0K/trf6qAiQsW4WMENsImsS+TAI7ho5DYcMoUR6OTEceaTozGPKJGK/SKe3t5mKkBoW61H2fTAgfDBeDRPA15SKeKm3qcA0p2cnx6W28cL+FJtLEjF0G/hAuZChCphCX4xdnwKOZgNrXHsBz+t+e1f/2C6qZC1FkqZ4a3yG5B7kL1bIwTdqa10wLrOMHUxWupFmtxrOfiwtnlLJPbHjL8LU7O5+w== X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-MS-Exchange-SenderADCheck: 1 X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(6040522)(2401047)(8121501046)(5005006)(10201501046)(3002001)(93006095)(93001095)(3231355)(944501410)(52105095)(149066)(150057)(6041310)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123558120)(20161123564045)(20161123562045)(20161123560045)(201708071742011)(7699051); SRVR:BLUPR0701MB1650; BCL:0; PCL:0; RULEID:; SRVR:BLUPR0701MB1650; X-Forefront-PRVS: 0810818DA0 X-Forefront-Antispam-Report: SFV:NSPM; SFS:(10009020)(346002)(136003)(396003)(376002)(39850400004)(366004)(189003)(199004)(16526019)(14444005)(446003)(76176011)(2906002)(6916009)(6666003)(97736004)(8676002)(81166006)(81156014)(36756003)(4326008)(316002)(8936002)(50226002)(34290500001)(86362001)(5660300001)(68736007)(16586007)(118296001)(72206003)(3846002)(6116002)(53936002)(386003)(105586002)(6486002)(47776003)(66066001)(486006)(25786009)(305945005)(50466002)(44832011)(956004)(2616005)(26005)(107886003)(52116002)(51416003)(7696005)(186003)(476003)(478600001)(2361001)(7736002)(2351001)(48376002)(106356001)(11346002)(309714004); DIR:OUT; SFP:1101; SCL:1; SRVR:BLUPR0701MB1650; H:ubuntubox.rdc.aquantia.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; Received-SPF: None (protection.outlook.com: aquantia.com does not designate permitted sender hosts) X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; BLUPR0701MB1650; 23:J08d+tSdiJwTd+hpQJ/19D7Lf/bxkVpPkmVaix6?= 43EpI2s4jHy4dBkGPrIUW6T0cMEUwrKVr5h1i08Il9TCmT816KdUdqW+y7p72NUJcVmzDuLQMNlXtLTE8fhnE+WSKW9rwAZekQxV2T43v0wRLh4O52h//MEF1x8NPlbpn6KeFfecXZghU2B8hQhQ+ub899TuzWbAYSY/Iy/x+anSy1G73Y8k/SK3TygFlAs5bobsEWNsyDpjGYVDZ7vj08fYbCB3MM+brta0ruuldwvV9tHhykAa+mMcdGA/G/7pEWizFU4gLaZyiREZsAuhAtlojm1g0aPGnVPVXFfKqmJOAFiR6CooIqtdb8+Bpo2KHryLzu6RbCZfmYGL8NME8U/XOeo3YsikNaZ11WWLKtWr9yYu/UYtuh5Td3qMjfgXI/31bd6slidySmO4JssG/oNNgczRVMktnPLEhfdMXYUs5BW1S77BBI8Nfv6HkvBdm2Zg67vRrhhnnuywD+r3fTn0GIkQ8zqETq+gA4GYloDe6tFtYXD8ut4SJZNAUTfoDvwM+AeZ+NWB3PXnnlyCNxDX7abDCxkP7l7R+m86VVRRP+WASNpkfBg0SfMHlkmE5BfykR36h69i60pUWlkNLQZX9Q+iP9mbEi3XvLJWmSIMuHYEsAxdpKHv/SdP/RbksDebCQ/q/TsoQwDpjvHfItmM5tvqHhGSW54sU93oAiJ9TtWgvO555pI8NxJwz5uL0kBkcgt/L4FAKvyfJyMpyK42I1+XfX3XrLduFR65ljRRdu81DK/9ojtWVKOlBNysOMOYUSej7mVm8rp3j8J106KvOrtotvDllnnALjufax5Ko+nAhD/2w2meLz9daW2ItUdV0iOKivJXvz0ah0Iejus/B9o0qrQo2tF/8+kSVDD7PH1t+MHE7Vsv8jkwQ0easHNwfH9hm9PIhnyncYJwPNWNpg58dd8o2yS+F/KMwEerE7Q817kwyOEulJgylvgLZgeg1DwYU2soU7cLVmOGMfGLMzPf+OrYtXvpNMIheKGjJqEX+MiddCgjF8Hizh4OqsijSYBfHJ1FT+XhBRGHk4CwpwdbmXiy8VqJj/q82JxAR+rVynw21tJj19Ri9UkVg4Uc+OjxZL7N6jThosPzRw8WoaGhroRSEJbld1T87GLZGVU/Y2vgM5u/4/DFdURFeU8zq+x1yUCuDVFxC/gYnTAli7pRubuxrmRmYfY5jBuEB6qSanYVbp/MKoME2ceiyQ/2r/y5Fu8lGgIFRXhvHJhfg3ubEwdU0+Vr9W5kstL0MBHsa+IJqKPdmRdCy7wiV6EPwfX6H9Ub0n3wSC4cHTHel X-Microsoft-Antispam-Message-Info: RUSnC8F9p/Wc1YWGPrs01nh+rhJsXZ1DDASrbE+Y8TKR+R0bZDw1iGDcrIL2NDeNG/7cs0V8dJ6Axu1z5KjKAbyzC0l6X2LkKkMqziLAbVWY318dn6OSAUYPkAFvkGLPhnboSznqZKNCu0IJYkbUv75jQn0aF9GeT+J73RL2qb4lX4YS3qTH0w2MC0osDwWIvYmPNgALxobNPn113uH9Sll/5N+QGw/AS8CoiEnPMknHSYzeESdCelanaAXgtJ4Yx4OAUks+O0CaWcyeZKSBAO9HRq5CdRLmVmUC42yQUsPLqyaKqwI/eG04IoM5nAO3oZ8LBJPEPljKWnMqRLkS1ICNVH5gjVdTNEHaN1YDfVQ= X-Microsoft-Exchange-Diagnostics: 1; BLUPR0701MB1650; 6:I42WE1SW+rdwwtgBadqgjYEIJ7UyOrA0hf4tKRjhIkQRBrK+HDJzwCHxhB+GkyyFSXvh3lt3TqUrFa4gVtUErvjxo2Grya42mxjneHL37+EA/9tr8YPTxHi8xFECIFjKAaT4Cb4RY8wdQzifCwJQsdzkEt4zGnsaHFR8LILVObxj2KpkebFmETBpo5cr7NCRrnPYrlVr3I4m12uM4hRTkyuiqT9aykdLRHfHl+1jW4ISZOSqK/+4QDzt7TnyM/mTSgH/XIAwHYbWtooDZ+9Zluvr2Q54mhfG4+1/OKQfIQOa4YBhXCSsdrgkYeyjwKL74buh6xsKAqKOHfbasvzRGrr9gR5SyOuCXGnZeAoaKmVlsH7+/6g6TvwjZ6A7Zhph75s0uXy1LnKGWXheQUXes7Q7ZktWLqqLA4Nb3yQqq5IRIFmSVHF1oJ1Vv+4imuGVh/OiNpA0rhk4y0U41dOaMw==; 5:0kDyNzxyXaxsJTFYR57SiKs4Iuqy2oDSV8UwPXlhF2Iiq7vtvpYC5cK+a42AzU+3T4Wtk6DaHAKF83YZTWeKRTIofwyT2Ri/YlXJgtMwCfVv+U75szc9tG7unbZQSLs0sCWasOJjnsIk5QWYCL3WOUEe6FLluBCBEKScdZa6W7E=; 7:Gs7z2uD7deyjBanEQjMHXse61ml3KWFiRNcHtNLrqRUHB+hYN6FQrfeSOhSf/8vEtjjuwZtrA9HXLmpOG2kDX3mEaRXIov26133lOXEeKCwdcGO5cYKPKsl/f5YA22+qeNnB96Qz3kzdRVaq0HDMU62qsZF0XFnj4VZ94gzQQPnJ7kBR361SwNfDXa3sDSQTMZl8H38anDjvjOxcZVP1XmwVr6ma8bEQj8K/5ONYUGj644knSMcu1laRP60sXxnO SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: aquantia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Sep 2018 10:31:46.2509 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 18e177b1-43cb-4fa1-1df6-08d625f6c563 X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 83e2e134-991c-4ede-8ced-34d47e38e6b1 X-MS-Exchange-Transport-CrossTenantHeadersStamped: BLUPR0701MB1650 Subject: [dpdk-dev] [PATCH v3 10/22] net/atlantic: TX side structures and implementation X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavel Belous Signed-off-by: Igor Russkikh Signed-off-by: Pavel Belous --- drivers/net/atlantic/atl_ethdev.c | 28 ++ drivers/net/atlantic/atl_ethdev.h | 7 + drivers/net/atlantic/atl_rxtx.c | 530 +++++++++++++++++++++++++++++++++++++- 3 files changed, 556 insertions(+), 9 deletions(-) diff --git a/drivers/net/atlantic/atl_ethdev.c b/drivers/net/atlantic/atl_ethdev.c index cdcfc5ec02c2..6a00277c3c8e 100644 --- a/drivers/net/atlantic/atl_ethdev.c +++ b/drivers/net/atlantic/atl_ethdev.c @@ -79,12 +79,27 @@ static struct rte_pci_driver rte_atl_pmd = { | DEV_RX_OFFLOAD_TCP_CKSUM \ | DEV_RX_OFFLOAD_JUMBO_FRAME) +#define ATL_TX_OFFLOADS (DEV_TX_OFFLOAD_VLAN_INSERT \ + | DEV_TX_OFFLOAD_IPV4_CKSUM \ + | DEV_TX_OFFLOAD_UDP_CKSUM \ + | DEV_TX_OFFLOAD_TCP_CKSUM \ + | DEV_TX_OFFLOAD_TCP_TSO \ + | DEV_TX_OFFLOAD_MULTI_SEGS) + static const struct rte_eth_desc_lim rx_desc_lim = { .nb_max = ATL_MAX_RING_DESC, .nb_min = ATL_MIN_RING_DESC, .nb_align = ATL_RXD_ALIGN, }; +static const struct rte_eth_desc_lim tx_desc_lim = { + .nb_max = ATL_MAX_RING_DESC, + .nb_min = ATL_MIN_RING_DESC, + .nb_align = ATL_TXD_ALIGN, + .nb_seg_max = ATL_TX_MAX_SEG, + .nb_mtu_seg_max = ATL_TX_MAX_SEG, +}; + static const struct eth_dev_ops atl_eth_dev_ops = { .dev_configure = atl_dev_configure, .dev_start = atl_dev_start, @@ -101,6 +116,11 @@ static const struct eth_dev_ops atl_eth_dev_ops = { .rx_queue_stop = atl_rx_queue_stop, .rx_queue_setup = atl_rx_queue_setup, .rx_queue_release = atl_rx_queue_release, + + .tx_queue_start = atl_tx_queue_start, + .tx_queue_stop = atl_tx_queue_stop, + .tx_queue_setup = atl_tx_queue_setup, + .tx_queue_release = atl_tx_queue_release, }; static inline int32_t @@ -369,11 +389,19 @@ atl_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) dev_info->rx_offload_capa = ATL_RX_OFFLOADS; + dev_info->tx_offload_capa = ATL_TX_OFFLOADS; + + dev_info->default_rxconf = (struct rte_eth_rxconf) { .rx_free_thresh = ATL_DEFAULT_RX_FREE_THRESH, }; + dev_info->default_txconf = (struct rte_eth_txconf) { + .tx_free_thresh = ATL_DEFAULT_TX_FREE_THRESH, + }; + dev_info->rx_desc_lim = rx_desc_lim; + dev_info->tx_desc_lim = tx_desc_lim; } static const uint32_t * diff --git a/drivers/net/atlantic/atl_ethdev.h b/drivers/net/atlantic/atl_ethdev.h index acb3066c189f..cafe37cdf963 100644 --- a/drivers/net/atlantic/atl_ethdev.h +++ b/drivers/net/atlantic/atl_ethdev.h @@ -28,12 +28,17 @@ struct atl_adapter { * RX/TX function prototypes */ void atl_rx_queue_release(void *rxq); +void atl_tx_queue_release(void *txq); int atl_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id, uint16_t nb_rx_desc, unsigned int socket_id, const struct rte_eth_rxconf *rx_conf, struct rte_mempool *mb_pool); +int atl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id, + uint16_t nb_tx_desc, unsigned int socket_id, + const struct rte_eth_txconf *tx_conf); + int atl_rx_init(struct rte_eth_dev *dev); int atl_tx_init(struct rte_eth_dev *dev); @@ -44,6 +49,8 @@ void atl_free_queues(struct rte_eth_dev *dev); int atl_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id); int atl_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id); +int atl_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id); +int atl_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id); uint16_t atl_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts); diff --git a/drivers/net/atlantic/atl_rxtx.c b/drivers/net/atlantic/atl_rxtx.c index 0ce41aaf1780..172d5fb232f2 100644 --- a/drivers/net/atlantic/atl_rxtx.c +++ b/drivers/net/atlantic/atl_rxtx.c @@ -4,6 +4,7 @@ #include #include +#include #include "atl_ethdev.h" #include "atl_hw_regs.h" @@ -13,6 +14,20 @@ #include "hw_atl/hw_atl_b0.h" #include "hw_atl/hw_atl_b0_internal.h" +#define ATL_TX_CKSUM_OFFLOAD_MASK ( \ + PKT_TX_IP_CKSUM | \ + PKT_TX_L4_MASK | \ + PKT_TX_TCP_SEG) + +#define ATL_TX_OFFLOAD_MASK ( \ + PKT_TX_VLAN_PKT | \ + PKT_TX_IP_CKSUM | \ + PKT_TX_L4_MASK | \ + PKT_TX_TCP_SEG) + +#define ATL_TX_OFFLOAD_NOTSUP_MASK \ + (PKT_TX_OFFLOAD_MASK ^ ATL_TX_OFFLOAD_MASK) + /** * Structure associated with each descriptor of the RX ring of a RX queue. */ @@ -21,6 +36,15 @@ struct atl_rx_entry { }; /** + * Structure associated with each descriptor of the TX ring of a TX queue. + */ +struct atl_tx_entry { + struct rte_mbuf *mbuf; + uint16_t next_id; + uint16_t last_id; +}; + +/** * Structure associated with each RX queue. */ struct atl_rx_queue { @@ -39,6 +63,22 @@ struct atl_rx_queue { bool l4_csum_enabled; }; +/** + * Structure associated with each TX queue. + */ +struct atl_tx_queue { + struct hw_atl_txd_s *hw_ring; + uint64_t hw_ring_phys_addr; + struct atl_tx_entry *sw_ring; + uint16_t nb_tx_desc; + uint16_t tx_tail; + uint16_t tx_head; + uint16_t queue_id; + uint16_t port_id; + uint16_t tx_free_thresh; + uint16_t tx_free; +}; + static inline void atl_reset_rx_queue(struct atl_rx_queue *rxq) { @@ -143,13 +183,141 @@ atl_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id, return 0; } +static inline void +atl_reset_tx_queue(struct atl_tx_queue *txq) +{ + struct atl_tx_entry *tx_entry; + union hw_atl_txc_s *txc; + uint16_t i; + + PMD_INIT_FUNC_TRACE(); + + if (!txq) { + PMD_DRV_LOG(ERR, "Pointer to txq is NULL"); + return; + } + + tx_entry = txq->sw_ring; + + for (i = 0; i < txq->nb_tx_desc; i++) { + txc = (union hw_atl_txc_s *)&txq->hw_ring[i]; + txc->flags1 = 0; + txc->flags2 = 2; + } + + for (i = 0; i < txq->nb_tx_desc; i++) { + txq->hw_ring[i].dd = 1; + tx_entry[i].mbuf = NULL; + } + + txq->tx_tail = 0; + txq->tx_head = 0; + txq->tx_free = txq->nb_tx_desc - 1; +} + int -atl_tx_init(struct rte_eth_dev *eth_dev __rte_unused) +atl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id, + uint16_t nb_tx_desc, unsigned int socket_id, + const struct rte_eth_txconf *tx_conf) { + struct atl_tx_queue *txq; + const struct rte_memzone *mz; + + PMD_INIT_FUNC_TRACE(); + + /* make sure a valid number of descriptors have been requested */ + if (nb_tx_desc < AQ_HW_MIN_TX_RING_SIZE || + nb_tx_desc > AQ_HW_MAX_TX_RING_SIZE) { + PMD_INIT_LOG(ERR, "Number of Tx descriptors must be " + "less than or equal to %d, " + "greater than or equal to %d", AQ_HW_MAX_TX_RING_SIZE, + AQ_HW_MIN_TX_RING_SIZE); + return -EINVAL; + } + + /* + * if this queue existed already, free the associated memory. The + * queue cannot be reused in case we need to allocate memory on + * different socket than was previously used. + */ + if (dev->data->tx_queues[tx_queue_id] != NULL) { + atl_tx_queue_release(dev->data->tx_queues[tx_queue_id]); + dev->data->tx_queues[tx_queue_id] = NULL; + } + + /* allocate memory for the queue structure */ + txq = rte_zmalloc_socket("atlantic Tx queue", sizeof(*txq), + RTE_CACHE_LINE_SIZE, socket_id); + if (txq == NULL) { + PMD_INIT_LOG(ERR, "Cannot allocate queue structure"); + return -ENOMEM; + } + + /* setup queue */ + txq->nb_tx_desc = nb_tx_desc; + txq->port_id = dev->data->port_id; + txq->queue_id = tx_queue_id; + txq->tx_free_thresh = tx_conf->tx_free_thresh; + + + /* allocate memory for the software ring */ + txq->sw_ring = rte_zmalloc_socket("atlantic sw tx ring", + nb_tx_desc * sizeof(struct atl_tx_entry), + RTE_CACHE_LINE_SIZE, socket_id); + if (txq->sw_ring == NULL) { + PMD_INIT_LOG(ERR, "Cannot allocate software ring"); + rte_free(txq); + return -ENOMEM; + } + + /* + * allocate memory for the hardware descriptor ring. A memzone large + * enough to hold the maximum ring size is requested to allow for + * resizing in later calls to the queue setup function. + */ + mz = rte_eth_dma_zone_reserve(dev, "tx hw_ring", tx_queue_id, + HW_ATL_B0_MAX_TXD * sizeof(struct hw_atl_txd_s), + 128, socket_id); + if (mz == NULL) { + PMD_INIT_LOG(ERR, "Cannot allocate hardware ring"); + rte_free(txq->sw_ring); + rte_free(txq); + return -ENOMEM; + } + txq->hw_ring = mz->addr; + txq->hw_ring_phys_addr = mz->iova; + + atl_reset_tx_queue(txq); + + dev->data->tx_queues[tx_queue_id] = txq; return 0; } int +atl_tx_init(struct rte_eth_dev *eth_dev) +{ + struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); + struct atl_tx_queue *txq; + uint64_t base_addr = 0; + int i = 0; + int err = 0; + + PMD_INIT_FUNC_TRACE(); + + for (i = 0; i < eth_dev->data->nb_tx_queues; i++) { + txq = eth_dev->data->tx_queues[i]; + base_addr = txq->hw_ring_phys_addr; + + err = hw_atl_b0_hw_ring_tx_init(hw, base_addr, + txq->queue_id, + txq->nb_tx_desc, 0, + txq->port_id); + } + + return err; +} + +int atl_rx_init(struct rte_eth_dev *eth_dev) { struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); @@ -313,15 +481,78 @@ atl_rx_queue_release(void *rx_queue) } } -uint16_t -atl_prep_pkts(void *tx_queue __rte_unused, - struct rte_mbuf **tx_pkts __rte_unused, - uint16_t nb_pkts __rte_unused) +static void +atl_tx_queue_release_mbufs(struct atl_tx_queue *txq) { + int i; + + PMD_INIT_FUNC_TRACE(); + + if (txq->sw_ring != NULL) { + for (i = 0; i < txq->nb_tx_desc; i++) { + if (txq->sw_ring[i].mbuf != NULL) { + rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf); + txq->sw_ring[i].mbuf = NULL; + } + } + } +} + +int +atl_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id) +{ + struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private); + + PMD_INIT_FUNC_TRACE(); + + if (tx_queue_id < dev->data->nb_tx_queues) { + hw_atl_b0_hw_ring_tx_start(hw, tx_queue_id); + + rte_wmb(); + hw_atl_b0_hw_tx_ring_tail_update(hw, 0, tx_queue_id); + dev->data->tx_queue_state[tx_queue_id] = + RTE_ETH_QUEUE_STATE_STARTED; + } else { + return -1; + } + + return 0; +} + +int +atl_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id) +{ + struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct atl_tx_queue *txq; + + PMD_INIT_FUNC_TRACE(); + + txq = dev->data->tx_queues[tx_queue_id]; + + hw_atl_b0_hw_ring_tx_stop(hw, tx_queue_id); + + atl_tx_queue_release_mbufs(txq); + atl_reset_tx_queue(txq); + dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED; + return 0; } void +atl_tx_queue_release(void *tx_queue) +{ + PMD_INIT_FUNC_TRACE(); + + if (tx_queue != NULL) { + struct atl_tx_queue *txq = (struct atl_tx_queue *)tx_queue; + + atl_tx_queue_release_mbufs(txq); + rte_free(txq->sw_ring); + rte_free(txq); + } +} + +void atl_free_queues(struct rte_eth_dev *dev) { unsigned int i; @@ -333,6 +564,12 @@ atl_free_queues(struct rte_eth_dev *dev) dev->data->rx_queues[i] = 0; } dev->data->nb_rx_queues = 0; + + for (i = 0; i < dev->data->nb_tx_queues; i++) { + atl_tx_queue_release(dev->data->tx_queues[i]); + dev->data->tx_queues[i] = 0; + } + dev->data->nb_tx_queues = 0; } int @@ -342,6 +579,13 @@ atl_start_queues(struct rte_eth_dev *dev) PMD_INIT_FUNC_TRACE(); + for (i = 0; i < dev->data->nb_tx_queues; i++) { + if (atl_tx_queue_start(dev, i) != 0) { + PMD_DRV_LOG(ERR, "Start Tx queue %d failed", i); + return -1; + } + } + for (i = 0; i < dev->data->nb_rx_queues; i++) { if (atl_rx_queue_start(dev, i) != 0) { PMD_DRV_LOG(ERR, "Start Rx queue %d failed", i); @@ -359,6 +603,13 @@ atl_stop_queues(struct rte_eth_dev *dev) PMD_INIT_FUNC_TRACE(); + for (i = 0; i < dev->data->nb_tx_queues; i++) { + if (atl_tx_queue_stop(dev, i) != 0) { + PMD_DRV_LOG(ERR, "Stop Tx queue %d failed", i); + return -1; + } + } + for (i = 0; i < dev->data->nb_rx_queues; i++) { if (atl_rx_queue_stop(dev, i) != 0) { PMD_DRV_LOG(ERR, "Stop Rx queue %d failed", i); @@ -369,6 +620,47 @@ atl_stop_queues(struct rte_eth_dev *dev) return 0; } +uint16_t +atl_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts, + uint16_t nb_pkts) +{ + int i, ret; + uint64_t ol_flags; + struct rte_mbuf *m; + + PMD_INIT_FUNC_TRACE(); + + for (i = 0; i < nb_pkts; i++) { + m = tx_pkts[i]; + ol_flags = m->ol_flags; + + if (m->nb_segs > AQ_HW_MAX_SEGS_SIZE) { + rte_errno = -EINVAL; + return i; + } + + if (ol_flags & ATL_TX_OFFLOAD_NOTSUP_MASK) { + rte_errno = -ENOTSUP; + return i; + } + +#ifdef RTE_LIBRTE_ETHDEV_DEBUG + ret = rte_validate_tx_offload(m); + if (ret != 0) { + rte_errno = ret; + return i; + } +#endif + ret = rte_net_intel_cksum_prepare(m); + if (ret != 0) { + rte_errno = ret; + return i; + } + } + + return i; +} + static uint64_t atl_desc_to_offload_flags(struct atl_rx_queue *rxq, struct hw_atl_rxd_wb_s *rxd_wb) @@ -637,12 +929,232 @@ atl_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts) return nb_rx; } +static void +atl_xmit_cleanup(struct atl_tx_queue *txq) +{ + struct atl_tx_entry *sw_ring; + struct hw_atl_txd_s *txd; + int to_clean = 0; + + PMD_INIT_FUNC_TRACE(); + + if (txq != NULL) { + sw_ring = txq->sw_ring; + int head = txq->tx_head; + int cnt; + int i; + + for (i = 0, cnt = head; ; i++) { + txd = &txq->hw_ring[cnt]; + + if (txd->dd) + to_clean++; + + cnt = (cnt + 1) % txq->nb_tx_desc; + if (cnt == txq->tx_tail) + break; + } + + if (to_clean == 0) + return; + + while (to_clean) { + txd = &txq->hw_ring[head]; + + struct atl_tx_entry *rx_entry = &sw_ring[head]; + + if (rx_entry->mbuf) { + rte_pktmbuf_free_seg(rx_entry->mbuf); + rx_entry->mbuf = NULL; + } + + if (txd->dd) + to_clean--; + + txd->buf_addr = 0; + txd->flags = 0; + + head = (head + 1) % txq->nb_tx_desc; + txq->tx_free++; + } + + txq->tx_head = head; + } +} + +static int +atl_tso_setup(struct rte_mbuf *tx_pkt, union hw_atl_txc_s *txc) +{ + uint32_t tx_cmd = 0; + uint64_t ol_flags = tx_pkt->ol_flags; + + PMD_INIT_FUNC_TRACE(); + + if (ol_flags & PKT_TX_TCP_SEG) { + PMD_DRV_LOG(DEBUG, "xmit TSO pkt"); + + tx_cmd |= tx_desc_cmd_lso | tx_desc_cmd_l4cs; + + txc->cmd = 0x4; + + if (ol_flags & PKT_TX_IPV6) + txc->cmd |= 0x2; + + txc->l2_len = tx_pkt->l2_len; + txc->l3_len = tx_pkt->l3_len; + txc->l4_len = tx_pkt->l4_len; + + txc->mss_len = tx_pkt->tso_segsz; + } + + if (ol_flags & PKT_TX_VLAN_PKT) { + tx_cmd |= tx_desc_cmd_vlan; + txc->vlan_tag = tx_pkt->vlan_tci; + } + + if (tx_cmd) { + txc->type = tx_desc_type_ctx; + txc->idx = 0; + } + + return tx_cmd; +} + +static inline void +atl_setup_csum_offload(struct rte_mbuf *mbuf, struct hw_atl_txd_s *txd, + uint32_t tx_cmd) +{ + txd->cmd |= tx_desc_cmd_fcs; + txd->cmd |= (mbuf->ol_flags & PKT_TX_IP_CKSUM) ? tx_desc_cmd_ipv4 : 0; + /* L4 csum requested */ + txd->cmd |= (mbuf->ol_flags & PKT_TX_L4_MASK) ? tx_desc_cmd_l4cs : 0; + txd->cmd |= tx_cmd; +} + +static inline void +atl_xmit_pkt(struct aq_hw_s *hw, struct atl_tx_queue *txq, + struct rte_mbuf *tx_pkt) +{ + uint32_t pay_len = 0; + int tail = 0; + struct atl_tx_entry *tx_entry; + uint64_t buf_dma_addr; + struct rte_mbuf *m_seg; + union hw_atl_txc_s *txc = NULL; + struct hw_atl_txd_s *txd = NULL; + u32 tx_cmd = 0U; + int desc_count = 0; + + PMD_INIT_FUNC_TRACE(); + + tail = txq->tx_tail; + + txc = (union hw_atl_txc_s *)&txq->hw_ring[tail]; + + txc->flags1 = 0U; + txc->flags2 = 0U; + + tx_cmd = atl_tso_setup(tx_pkt, txc); + + if (tx_cmd) { + /* We've consumed the first desc, adjust counters */ + tail = (tail + 1) % txq->nb_tx_desc; + txq->tx_tail = tail; + txq->tx_free -= 1; + + txd = &txq->hw_ring[tail]; + txd->flags = 0U; + } else { + txd = (struct hw_atl_txd_s *)txc; + } + + txd->ct_en = !!tx_cmd; + + txd->type = tx_desc_type_desc; + + atl_setup_csum_offload(tx_pkt, txd, tx_cmd); + + if (tx_cmd) + txd->ct_idx = 0; + + pay_len = tx_pkt->pkt_len; + + txd->pay_len = pay_len; + + for (m_seg = tx_pkt; m_seg; m_seg = m_seg->next) { + if (desc_count > 0) { + txd = &txq->hw_ring[tail]; + txd->flags = 0U; + } + + buf_dma_addr = rte_mbuf_data_iova(m_seg); + txd->buf_addr = rte_cpu_to_le_64(buf_dma_addr); + + txd->type = tx_desc_type_desc; + txd->len = m_seg->data_len; + txd->pay_len = pay_len; + + /* Store mbuf for freeing later */ + tx_entry = &txq->sw_ring[tail]; + + if (tx_entry->mbuf) + rte_pktmbuf_free_seg(tx_entry->mbuf); + tx_entry->mbuf = m_seg; + + tail = (tail + 1) % txq->nb_tx_desc; + + desc_count++; + } + + // Last descriptor requires EOP and WB + txd->eop = 1U; + txd->cmd |= tx_desc_cmd_wb; + + hw_atl_b0_hw_tx_ring_tail_update(hw, tail, txq->queue_id); + + txq->tx_tail = tail; + + txq->tx_free -= desc_count; +} uint16_t -atl_xmit_pkts(void *tx_queue __rte_unused, - struct rte_mbuf **tx_pkts __rte_unused, - uint16_t nb_pkts __rte_unused) +atl_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts) { - return 0; + struct rte_eth_dev *dev = NULL; + struct aq_hw_s *hw = NULL; + struct atl_tx_queue *txq = tx_queue; + struct rte_mbuf *tx_pkt; + uint16_t nb_tx; + + dev = &rte_eth_devices[txq->port_id]; + hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private); + + PMD_TX_LOG(DEBUG, "txq%d pkts: %d tx_free=%d tx_tail=%d tx_head=%d", + txq->queue_id, nb_pkts, txq->tx_free, + txq->tx_tail, txq->tx_head); + + for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) { + tx_pkt = *tx_pkts++; + + /* Clean Tx queue if needed */ + if (txq->tx_free < txq->tx_free_thresh) + atl_xmit_cleanup(txq); + + /* Check if we have enough free descriptors */ + if (txq->tx_free < tx_pkt->nb_segs) + break; + + /* check mbuf is valid */ + if ((tx_pkt->nb_segs == 0) || + ((tx_pkt->nb_segs > 1) && (tx_pkt->next == NULL))) + break; + + /* Send the packet */ + atl_xmit_pkt(hw, txq, tx_pkt); + } + + PMD_TX_LOG(DEBUG, "atl_xmit_pkts %d transmitted", nb_tx); + + return nb_tx; } From patchwork Sat Sep 29 10:30:25 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Russkikh X-Patchwork-Id: 45675 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 106DB1B3B5; Sat, 29 Sep 2018 12:32:05 +0200 (CEST) Received: from NAM05-DM3-obe.outbound.protection.outlook.com (mail-eopbgr730081.outbound.protection.outlook.com [40.107.73.81]) by dpdk.org (Postfix) with ESMTP id C456D1B176 for ; Sat, 29 Sep 2018 12:32:00 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=AQUANTIA1COM.onmicrosoft.com; s=selector1-aquantia-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=m4VtXGSDDVFdHRfkWwehVCOBfmLuCDO98m0/LNhg9kU=; b=MYVveJsbYx0XVUemeVohPPAYboaT7+dcBRCHrjtZm7RNKxIepfVUld60vkEMc5BNs+qvPfldSMmOmjT1vW7QUYsF9nREHMcqL24ItH08u7AeSwcmn8uHBrDBX8JXTVl0Efk4pzAjDcOJ/51dWTNoupUraMMgJWEXArIdiky6xGo= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Igor.Russkikh@aquantia.com; Received: from ubuntubox.rdc.aquantia.com (95.79.108.179) by BLUPR0701MB1650.namprd07.prod.outlook.com (2a01:111:e400:58c6::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1185.22; Sat, 29 Sep 2018 10:31:52 +0000 From: Igor Russkikh To: dev@dpdk.org Cc: pavel.belous@aquantia.com, igor.russkikh@aquantia.com, Pavel Belous Date: Sat, 29 Sep 2018 13:30:25 +0300 Message-Id: <1691fabf67f002c8ad6a85fd5a23a3b854a8daf3.1538215990.git.igor.russkikh@aquantia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [95.79.108.179] X-ClientProxiedBy: VI1P193CA0009.EURP193.PROD.OUTLOOK.COM (2603:10a6:800:bd::19) To BLUPR0701MB1650.namprd07.prod.outlook.com (2a01:111:e400:58c6::20) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 8d33b3ca-d164-4341-ad0a-08d625f6c972 X-Microsoft-Antispam: BCL:0; PCL:0; RULEID:(7020095)(4652040)(8989299)(4534165)(4627221)(201703031133081)(201702281549075)(8990200)(5600074)(711020)(2017052603328)(7153060)(7193020); SRVR:BLUPR0701MB1650; X-Microsoft-Exchange-Diagnostics: 1; BLUPR0701MB1650; 3:h/ES+3ArumZQS3CbDkulJNTWLnclDAhOuaOGobfJ13mrrSg9w8TlzT5j3tU+bT6JcPboPjfro5O66fwTcVR6KwPa/MUQ5ZCi6ypLBNA82h4aDphMRgSuG6aPfY9kQQqQkPt59nOEgG/ar8xzjovnH4udrRtZRSVtpJYuA9wmtN+nAk7XU15Nd3qmokFk0bTO0g3b4kDn+a+KrlyP92b9Yw0ZNjWjZLci7vKTJB/4nebraUKXixnr5xkouMUSAWLg; 25:t3SHEquNxF2w2USNMaWBcUfmtHvilsRuD5axyYWEBlt1XUU8XHQGq244EupwSg7HDV3J/CwRgGojLUtGiFxk6rC5buf6OsbKUtOllgKeFNHyv3C9+GkutVjyrniz4EA7NAjhjrMZ9XXbbMK1mq6JZZIZMMYB6B6sC2kDgZIpHU9W1gGg6hDK4iQd3RsfwCC0J1xfDrxvP/oL3LGEpqWj0MadDytUUrRpvTL9iM+0CYBVmtw1eQ7bGpAl31wYd2nxlYd0UY/AQWugySWxNRRPvZwyE3vu2WvH2iLYtxQjWOLFgRVbGpjHFXSWvEiePdSMiS4nqUsSW/3V0tEIbfETlTQL2WOPLSnElXa7EDBrpFE=; 31:D/8gLdVTPEA9So6VL6ZX83ruFp4RK5Jpwl5bGTnSqXgcccgNpxQnE2BAFGy2GCJIUj1zfyEnTe8izXWqMTSXOzMplQYyapHhuCir1jZ0wc3BWFuZQmtJkkgUstIstTMaRrmudOrROufuP3FYQnpFpPBOGZ/XlrzyxFc/PGb+ajHX3js391+fXD8DrAZWE9eJIAlXrUKCK+aGGLxUL3go4zte7UH9UzaPnVdgPy5lU9I= X-MS-TrafficTypeDiagnostic: BLUPR0701MB1650: X-Microsoft-Exchange-Diagnostics: 1; BLUPR0701MB1650; 20:G72f9cQ3/3mdlAmcabzIn9nfV2wUyzAeqjnBKyGEUdGYtD0oXsbIyqettfK/B6C7TYICrRCdbVHPwsYKSIYXDswk4c76KGLyCzhL8EJFLMamDWrM1XspI2KwHmKxjI58vCy4zFpPF8Omj0CPxSqTaPwYQKERGXvlQWovBBPvXRiLKqWnHdvVavupztZzeNRmqt9QC57uSP1WGi4SGc772utz7FeiFmgN8JBh755kTnlDnPMn61Mh+wnyPbZ5Jxqyl2Q4PFFNKRoxBzV2exBoCAkARjP2Jh33iOk4nXQZRlK1aIsx2LEy+Rl7jEaludBbIsC9ilZBsE6BuS+OZMSKyfoSg1d/QpUELRi6+Y0LpABuc/oGME9z706QZVABS/iTFdhBS+/vu+w+HIBrup7Gm9PYrhUFmRBl2nuk7joMuFDkpC5sZkkUUq4lb0uS0rkILBvf0lJHcQxyEgj/NzImY6TBtKXfioPfgqeQgs8p3J24X2lvRefcX6kDTYC17xZA; 4:Riy/MnERKc8KXzPtQTbbCVHg/B+wxKlpIRATASoH/agEfUazNi2YlKQrPPr1G0T3SeR0xS1+yYBc04KolWaKgNXceGSXkbJhDJLB0NFvTgHH6fba9PuSNfnwT9hUJMn7+Xar+/ZXvvRl02g0fBxLItUcNQcdb3FwnC5gXap0KKwY9ZkyxUq33UgLrXzPcxQa4josYOGhrspN1YhNvTk5GjzUOZCZyI3akLzKX1tTi24y3S4PHHpGhqx51RKXNs9I9/kCK2LGoy5+pgf9ESaQoKeF+d1AVj95Qj6FRs9Rk3QXY0iC33ta0JNKd9KGljWX X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:(269456686620040); X-MS-Exchange-SenderADCheck: 1 X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(6040522)(2401047)(8121501046)(5005006)(10201501046)(3002001)(93006095)(93001095)(3231355)(944501410)(52105095)(149066)(150057)(6041310)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123558120)(20161123564045)(20161123562045)(20161123560045)(201708071742011)(7699051); SRVR:BLUPR0701MB1650; BCL:0; PCL:0; RULEID:; SRVR:BLUPR0701MB1650; X-Forefront-PRVS: 0810818DA0 X-Forefront-Antispam-Report: SFV:NSPM; SFS:(10009020)(346002)(136003)(396003)(376002)(39850400004)(366004)(189003)(199004)(16526019)(14444005)(446003)(76176011)(2906002)(6916009)(6666003)(97736004)(8676002)(81166006)(81156014)(36756003)(4326008)(316002)(8936002)(50226002)(34290500001)(575784001)(86362001)(5660300001)(68736007)(16586007)(118296001)(72206003)(3846002)(6116002)(53936002)(386003)(105586002)(6486002)(47776003)(66066001)(486006)(25786009)(305945005)(50466002)(44832011)(956004)(2616005)(26005)(107886003)(52116002)(51416003)(7696005)(186003)(476003)(478600001)(2361001)(7736002)(2351001)(48376002)(106356001)(11346002); DIR:OUT; SFP:1101; SCL:1; SRVR:BLUPR0701MB1650; H:ubuntubox.rdc.aquantia.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; Received-SPF: None (protection.outlook.com: aquantia.com does not designate permitted sender hosts) X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; BLUPR0701MB1650; 23:G5uG2XmNHTeKhyM25FimIK+oYl2FG91AHNP/4yn?= +S6tXLnCGHBKYe8ukYxIpsQ2/nuC4lqvf3LZLKFA70oZ48el0lLw4DZlPqqn5u+7jsBeGFoCHv8FdrrE/zPrDWxv8uUWCxLpwvLMSphTVxlkcTDytC/6lf3tzuQ6q0XazTw3mBT1UsLeGzvLSG4I67VxuWjawNsFZuLaolmBJAtP6a13vLG2WejunhFvY8qOKy+9MsHz6IbKZbBEOaInG7uwoOCos2KctZUt1kbJrH9wWYP9yMRauEoqdE0jU0ha1FMXTbRR5C4wN4UsQPibWUy8DQbh6XfGt59nzhw1l/dB2wQFBIRRxs7kSaHKOHn1BpupzD7YK6AqB1r20uoPPzmJLZFluuDJLXFkSQdP39hTZxD9QJePv/p3QTfVwg0gXzA0DtydLSirsA0O5ozxLK0pPN8kn1sxhRju5rdPf+TPi6PwYdx9DX0+ib2G+Im2FCsIAyqcY6b6RT7HYixlhwpiNvQ70GdNDiBPIGzcieyz9cTikGz7c4+i5jgmeUPLPrKiANXc4t5Z367IVB4IBNt5g4ySAICIPMPO6kFGZ/WXiXaOISSvA5GS4WYILPLpv7UbU+NHI69O2x49Ql1kTwul0rcwcl3qjLWA/SrvzOvqzQsdkV12ne6kGuY9v+Bz/TlJyFgtmhH67rztJEZbpH9S7J+hfG+6E+nDcCZSuIrXkfxY/lPW73pjGQ1DUiIRtDmkWovCV0VExXuwl/3gLR5I46tWtDQdAGBrmksfpr7TkhNAHfiv8W6tvQnLIYEfLT/DV5sSMonkCWpkSDzxw9Tgiz3/rH4TQOtQ67Goc+A7pTxJR0xQhnqBVlDY+jeu/FE8G3ju07a11miEOPCHsot1MHn7P/IyoDHroQrEeq1jsvny1IxBN2B44tMmaKDvNto+5mSzwrnMX3HZb1Gfe6bPFNWRN997oNBtGZOLP5J02rS3SHO6zmplurahEe+C/W4YjHvzo6kd277DrkAAIUIrgfl62D9DhKgHEthTVIUr5gKukr5GAYys50FsIjgykATXsVC1+p2TaPWWMEmZ+9Q/oaMIh5A8dj2v9KGMd389YHI/mPKMwXkHL8voNk1DLKA0eVyuhBSZtl9FUjZloJAw+9cLQuu2QvvhYYPGV5cF4gVfGh3gNUgWLqXqnkBzXv9x7vHDvr79AcSoWZ1zolAry0Sl0frPsSJ6t1h0qn2m0aKgTmYOD33NdJIIuf24NvbuLt6IXWDpenSby7UuFaHysnoJ8j5MkoX8FZYGLOd4cHmxCMYTo8UwNwlJ4+k9sg9edMzN7sWPLyJ2WPlm89sDN X-Microsoft-Antispam-Message-Info: mSgorJ6hxoTOmYKxXoLBtFT0GSxzJei6KG/rtLxq3UWDqkRcyDEzhiLP4ysPdExNruGkKOsPlzZqgd9mHkE/LBXX1sUSrph2eXJHLaEV4FYpTB3OrIGxs+DUIPTy7gdu3xtf6EqezciY2VviFAFADfldE5WBPQ5sI0wFwca0s04GQRCeOxMPtCcHdVxql/rXc5jmKpC79z9+CzGbbeP8kmRiq+3t2Nj01qe/Dxh3aCW7sxQPIxM4KO5gIteKfra3qIbk0dsziz0zq93A9jmmSew+qnXE3hSpLoatfVr+7PSIqBYPBu3AzITMkT6bvqmYvH7i415wTrcia11z/6FQWQ+39Mr8jNwvbJcfVHjcORM= X-Microsoft-Exchange-Diagnostics: 1; BLUPR0701MB1650; 6:encTneyeTGHcbaCbwK19wqLyMAjBJ621PqO6W1+B8878tzhFMgm8UbABxUZUKHS2MKJxpNaCvFF31Q7TwmwI9xvZuS8OFVbVNfqZGNKJbhtRWaZGd5gvOLWsD+KZVUn78dQh+B9LVYX9pH0z3kDdbxmIAl/XbFIOrOhOUiwXqhdtdzk4tHTQgSsHv/tnJpupBllycsnLSKpNzuPSDrC7RTDuSz/2VhBz0ErmVY1l58MGr8Ql62u6mpDt79ofADQ7Ree9vrwON1w/IGs/CE+QrtE2Sbk5taUlFqq7MP6IQZFO6IcFPW//qB/LRJ0JhO/ty+vcCfSow25O1PMMKb0F88ygi8OmKrRpnugRiNaXnKWT77kcPkt8Lw2PV4s7GxBU9OV9CObFQxiPwtV2x/9RkjviVZI2CJp7vAyq/I97kAkpKpWiYHxQFePJA05AE3RKpkwUruXERf/IHYXWrIFptw==; 5:3hPqFcqWKxuHd113KLPkTYv7drdE7aRd1wxp8gb5ENEVfFO4hx5ZdG/DuCjyARsFR/+Spqii7LvXBIey+oSc2yscbBVys/bc48+FA2sURkZdjZeRTjYVFOUOBnWI3zk02IyxJXx8NvkCzNbe/oaVk8C0cU7miKsMSm3JMRkua98=; 7:VXwlqVHCZwttIom/aDvN1LIZcAPJttNiTwK51eGMyya+N20EKJ/eShJWl7RKsyXIcNhgPcrrdjR79j8lI7dPBcxFz5BoVHto8C/om0bkvSjfID2QdUIlFu91h4KnG/RPvYO7r/1ecyivxQRvKffjvVxjCGA4pELv8YSQgLfIlfUhQGs4BvxTZX1jQzs6WCigpLvktCXSxCCooEy7ITQRSb1l41YOc99KEpSfRLOMGSNM1hqzMRpepxuWzAwzmjzf SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: aquantia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Sep 2018 10:31:52.8762 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8d33b3ca-d164-4341-ad0a-08d625f6c972 X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 83e2e134-991c-4ede-8ced-34d47e38e6b1 X-MS-Exchange-Transport-CrossTenantHeadersStamped: BLUPR0701MB1650 Subject: [dpdk-dev] [PATCH v3 11/22] net/atlantic: link status and interrupt management X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavel Belous Implement link interrupt, link info, link polling. Signed-off-by: Igor Russkikh Signed-off-by: Pavel Belous --- drivers/net/atlantic/atl_ethdev.c | 461 +++++++++++++++++++++++++++++++++++++- drivers/net/atlantic/atl_ethdev.h | 16 ++ drivers/net/atlantic/atl_rxtx.c | 36 +++ drivers/net/atlantic/atl_types.h | 2 + 4 files changed, 514 insertions(+), 1 deletion(-) diff --git a/drivers/net/atlantic/atl_ethdev.c b/drivers/net/atlantic/atl_ethdev.c index 6a00277c3c8e..75c9fa169925 100644 --- a/drivers/net/atlantic/atl_ethdev.c +++ b/drivers/net/atlantic/atl_ethdev.c @@ -18,8 +18,11 @@ static int eth_atl_dev_uninit(struct rte_eth_dev *eth_dev); static int atl_dev_configure(struct rte_eth_dev *dev); static int atl_dev_start(struct rte_eth_dev *dev); static void atl_dev_stop(struct rte_eth_dev *dev); +static int atl_dev_set_link_up(struct rte_eth_dev *dev); +static int atl_dev_set_link_down(struct rte_eth_dev *dev); static void atl_dev_close(struct rte_eth_dev *dev); static int atl_dev_reset(struct rte_eth_dev *dev); +static int atl_dev_link_update(struct rte_eth_dev *dev, int wait); static int atl_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size); @@ -29,6 +32,16 @@ static void atl_dev_info_get(struct rte_eth_dev *dev, static const uint32_t *atl_dev_supported_ptypes_get(struct rte_eth_dev *dev); +static void atl_dev_link_status_print(struct rte_eth_dev *dev); + +/* Interrupts */ +static int atl_dev_rxq_interrupt_setup(struct rte_eth_dev *dev); +static int atl_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on); +static int atl_dev_interrupt_get_status(struct rte_eth_dev *dev); +static int atl_dev_interrupt_action(struct rte_eth_dev *dev, + struct rte_intr_handle *handle); +static void atl_dev_interrupt_handler(void *param); + static int eth_atl_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, struct rte_pci_device *pci_dev); static int eth_atl_pci_remove(struct rte_pci_device *pci_dev); @@ -104,9 +117,14 @@ static const struct eth_dev_ops atl_eth_dev_ops = { .dev_configure = atl_dev_configure, .dev_start = atl_dev_start, .dev_stop = atl_dev_stop, + .dev_set_link_up = atl_dev_set_link_up, + .dev_set_link_down = atl_dev_set_link_down, .dev_close = atl_dev_close, .dev_reset = atl_dev_reset, + /* Link */ + .link_update = atl_dev_link_update, + .fw_version_get = atl_fw_version_get, .dev_infos_get = atl_dev_info_get, .dev_supported_ptypes_get = atl_dev_supported_ptypes_get, @@ -121,14 +139,85 @@ static const struct eth_dev_ops atl_eth_dev_ops = { .tx_queue_stop = atl_tx_queue_stop, .tx_queue_setup = atl_tx_queue_setup, .tx_queue_release = atl_tx_queue_release, + + .rx_queue_intr_enable = atl_dev_rx_queue_intr_enable, + .rx_queue_intr_disable = atl_dev_rx_queue_intr_disable, }; + +/** + * Atomically reads the link status information from global + * structure rte_eth_dev. + * + * @param dev + * - Pointer to the structure rte_eth_dev to read from. + * - Pointer to the buffer to be saved with the link status. + * + * @return + * - On success, zero. + * - On failure, negative value. + */ +static inline int +rte_atl_dev_atomic_read_link_status(struct rte_eth_dev *dev, + struct rte_eth_link *link) +{ + struct rte_eth_link *dst = link; + struct rte_eth_link *src = &dev->data->dev_link; + + if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst, + *(uint64_t *)src) == 0) + return -1; + + return 0; +} + +/** + * Atomically writes the link status information into global + * structure rte_eth_dev. + * + * @param dev + * - Pointer to the structure rte_eth_dev to read from. + * - Pointer to the buffer to be saved with the link status. + * + * @return + * - On success, zero. + * - On failure, negative value. + */ +static inline int +rte_atl_dev_atomic_write_link_status(struct rte_eth_dev *dev, + struct rte_eth_link *link) +{ + struct rte_eth_link *dst = &dev->data->dev_link; + struct rte_eth_link *src = link; + + if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst, + *(uint64_t *)src) == 0) + return -1; + + return 0; +} + static inline int32_t atl_reset_hw(struct aq_hw_s *hw) { return hw_atl_b0_hw_reset(hw); } +static inline void +atl_enable_intr(struct rte_eth_dev *dev) +{ + struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private); + + hw_atl_itr_irq_msk_setlsw_set(hw, 0xffffffff); +} + +static void +atl_disable_intr(struct aq_hw_s *hw) +{ + PMD_INIT_FUNC_TRACE(); + hw_atl_itr_irq_msk_clearlsw_set(hw, 0xffffffff); +} + static void atl_print_adapter_info(struct aq_hw_s *hw __rte_unused) { @@ -145,6 +234,7 @@ eth_atl_dev_init(struct rte_eth_dev *eth_dev) struct atl_adapter *adapter = (struct atl_adapter *)eth_dev->data->dev_private; struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); + struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); int err = 0; @@ -169,9 +259,17 @@ eth_atl_dev_init(struct rte_eth_dev *eth_dev) /* Hardware configuration - hardcode */ adapter->hw_cfg.is_lro = false; adapter->hw_cfg.wol = false; + adapter->hw_cfg.link_speed_msk = AQ_NIC_RATE_10G | + AQ_NIC_RATE_5G | + AQ_NIC_RATE_2G5 | + AQ_NIC_RATE_1G | + AQ_NIC_RATE_100M; hw->aq_nic_cfg = &adapter->hw_cfg; + /* disable interrupt */ + atl_disable_intr(hw); + /* Allocate memory for storing MAC addresses */ eth_dev->data->mac_addrs = rte_zmalloc("atlantic", ETHER_ADDR_LEN, 0); if (eth_dev->data->mac_addrs == NULL) { @@ -188,12 +286,23 @@ eth_atl_dev_init(struct rte_eth_dev *eth_dev) (u8 *)ð_dev->data->mac_addrs[0]) != 0) return -EINVAL; + rte_intr_callback_register(intr_handle, + atl_dev_interrupt_handler, eth_dev); + + /* enable uio/vfio intr/eventfd mapping */ + rte_intr_enable(intr_handle); + + /* enable support intr */ + atl_enable_intr(eth_dev); + return err; } static int eth_atl_dev_uninit(struct rte_eth_dev *eth_dev) { + struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); + struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; struct aq_hw_s *hw; PMD_INIT_FUNC_TRACE(); @@ -210,6 +319,11 @@ eth_atl_dev_uninit(struct rte_eth_dev *eth_dev) eth_dev->rx_pkt_burst = NULL; eth_dev->tx_pkt_burst = NULL; + /* disable uio intr before callback unregister */ + rte_intr_disable(intr_handle); + rte_intr_callback_unregister(intr_handle, + atl_dev_interrupt_handler, eth_dev); + rte_free(eth_dev->data->mac_addrs); eth_dev->data->mac_addrs = NULL; @@ -238,8 +352,16 @@ eth_atl_pci_remove(struct rte_pci_device *pci_dev) } static int -atl_dev_configure(struct rte_eth_dev *dev __rte_unused) +atl_dev_configure(struct rte_eth_dev *dev) { + struct atl_interrupt *intr = + ATL_DEV_PRIVATE_TO_INTR(dev->data->dev_private); + + PMD_INIT_FUNC_TRACE(); + + /* set flag to update link status after init */ + intr->flags |= ATL_FLAG_NEED_LINK_UPDATE; + return 0; } @@ -251,11 +373,26 @@ static int atl_dev_start(struct rte_eth_dev *dev) { struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); + struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; + uint32_t intr_vector = 0; + uint32_t *link_speeds; + uint32_t speed = 0; int status; int err; PMD_INIT_FUNC_TRACE(); + if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) { + PMD_INIT_LOG(ERR, + "Invalid link_speeds for port %u, fix speed not supported", + dev->data->port_id); + return -EINVAL; + } + + /* disable uio/vfio intr/eventfd mapping */ + rte_intr_disable(intr_handle); + /* stop adapter */ hw->adapter_stopped = 0; @@ -269,6 +406,32 @@ atl_dev_start(struct rte_eth_dev *dev) err = hw_atl_b0_hw_init(hw, (uint8_t *)dev->data->mac_addrs); hw_atl_b0_hw_start(hw); + /* check and configure queue intr-vector mapping */ + if ((rte_intr_cap_multiple(intr_handle) || + !RTE_ETH_DEV_SRIOV(dev).active) && + dev->data->dev_conf.intr_conf.rxq != 0) { + intr_vector = dev->data->nb_rx_queues; + if (intr_vector > ATL_MAX_INTR_QUEUE_NUM) { + PMD_INIT_LOG(ERR, "At most %d intr queues supported", + ATL_MAX_INTR_QUEUE_NUM); + return -ENOTSUP; + } + if (rte_intr_efd_enable(intr_handle, intr_vector)) { + PMD_INIT_LOG(ERR, "rte_intr_efd_enable failed"); + return -1; + } + } + + if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) { + intr_handle->intr_vec = rte_zmalloc("intr_vec", + dev->data->nb_rx_queues * sizeof(int), 0); + if (intr_handle->intr_vec == NULL) { + PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues" + " intr_vec", dev->data->nb_rx_queues); + return -ENOMEM; + } + } + /* initialize transmission unit */ atl_tx_init(dev); @@ -285,6 +448,61 @@ atl_dev_start(struct rte_eth_dev *dev) goto error; } + err = hw->aq_fw_ops->update_link_status(hw); + + if (err) + goto error; + + dev->data->dev_link.link_status = hw->aq_link_status.mbps != 0; + + link_speeds = &dev->data->dev_conf.link_speeds; + + speed = 0x0; + + if (*link_speeds == ETH_LINK_SPEED_AUTONEG) { + speed = hw->aq_nic_cfg->link_speed_msk; + } else { + if (*link_speeds & ETH_LINK_SPEED_10G) + speed |= AQ_NIC_RATE_10G; + if (*link_speeds & ETH_LINK_SPEED_5G) + speed |= AQ_NIC_RATE_5G; + if (*link_speeds & ETH_LINK_SPEED_1G) + speed |= AQ_NIC_RATE_1G; + if (*link_speeds & ETH_LINK_SPEED_2_5G) + speed |= AQ_NIC_RATE_2G5; + if (*link_speeds & ETH_LINK_SPEED_100M) + speed |= AQ_NIC_RATE_100M; + } + + err = hw->aq_fw_ops->set_link_speed(hw, speed); + if (err) + goto error; + + if (rte_intr_allow_others(intr_handle)) { + /* check if lsc interrupt is enabled */ + if (dev->data->dev_conf.intr_conf.lsc != 0) + atl_dev_lsc_interrupt_setup(dev, TRUE); + else + atl_dev_lsc_interrupt_setup(dev, FALSE); + } else { + rte_intr_callback_unregister(intr_handle, + atl_dev_interrupt_handler, dev); + if (dev->data->dev_conf.intr_conf.lsc != 0) + PMD_INIT_LOG(INFO, "lsc won't enable because of" + " no intr multiplex"); + } + + /* check if rxq interrupt is enabled */ + if (dev->data->dev_conf.intr_conf.rxq != 0 && + rte_intr_dp_is_en(intr_handle)) + atl_dev_rxq_interrupt_setup(dev); + + /* enable uio/vfio intr/eventfd mapping */ + rte_intr_enable(intr_handle); + + /* resume enabled intr since hw reset */ + atl_enable_intr(dev); + atl_print_adapter_info(hw); return 0; @@ -301,8 +519,16 @@ atl_dev_start(struct rte_eth_dev *dev) static void atl_dev_stop(struct rte_eth_dev *dev) { + struct rte_eth_link link; struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); + struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; + + PMD_INIT_FUNC_TRACE(); + + /* disable interrupts */ + atl_disable_intr(hw); /* reset the NIC */ atl_reset_hw(hw); @@ -314,6 +540,45 @@ atl_dev_stop(struct rte_eth_dev *dev) dev->data->scattered_rx = 0; dev->data->lro = 0; + /* Clear recorded link status */ + memset(&link, 0, sizeof(link)); + rte_atl_dev_atomic_write_link_status(dev, &link); + + if (!rte_intr_allow_others(intr_handle)) + /* resume to the default handler */ + rte_intr_callback_register(intr_handle, + atl_dev_interrupt_handler, + (void *)dev); + + /* Clean datapath event and queue/vec mapping */ + rte_intr_efd_disable(intr_handle); + if (intr_handle->intr_vec != NULL) { + rte_free(intr_handle->intr_vec); + intr_handle->intr_vec = NULL; + } +} + +/* + * Set device link up: enable tx. + */ +static int +atl_dev_set_link_up(struct rte_eth_dev *dev) +{ + struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private); + + return hw->aq_fw_ops->set_link_speed(hw, + hw->aq_nic_cfg->link_speed_msk); +} + +/* + * Set device link down: disable tx. + */ +static int +atl_dev_set_link_down(struct rte_eth_dev *dev) +{ + struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private); + + return hw->aq_fw_ops->set_link_speed(hw, 0); } /* @@ -402,6 +667,11 @@ atl_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) dev_info->rx_desc_lim = rx_desc_lim; dev_info->tx_desc_lim = tx_desc_lim; + + dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G; + dev_info->speed_capa |= ETH_LINK_SPEED_100M; + dev_info->speed_capa |= ETH_LINK_SPEED_2_5G; + dev_info->speed_capa |= ETH_LINK_SPEED_5G; } static const uint32_t * @@ -426,6 +696,195 @@ atl_dev_supported_ptypes_get(struct rte_eth_dev *dev) return NULL; } +/* return 0 means link status changed, -1 means not changed */ +static int +atl_dev_link_update(struct rte_eth_dev *dev, int wait __rte_unused) +{ + struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct atl_interrupt *intr = + ATL_DEV_PRIVATE_TO_INTR(dev->data->dev_private); + struct rte_eth_link link, old; + int err = 0; + + link.link_status = ETH_LINK_DOWN; + link.link_speed = 0; + link.link_duplex = ETH_LINK_FULL_DUPLEX; + link.link_autoneg = hw->is_autoneg ? ETH_LINK_AUTONEG : ETH_LINK_FIXED; + memset(&old, 0, sizeof(old)); + + /* load old link status */ + rte_atl_dev_atomic_read_link_status(dev, &old); + + /* read current link status */ + err = hw->aq_fw_ops->update_link_status(hw); + + if (err) + return 0; + + if (hw->aq_link_status.mbps == 0) { + /* write default (down) link status */ + rte_atl_dev_atomic_write_link_status(dev, &link); + if (link.link_status == old.link_status) + return -1; + return 0; + } + + intr->flags &= ~ATL_FLAG_NEED_LINK_CONFIG; + + link.link_status = ETH_LINK_UP; + link.link_duplex = ETH_LINK_FULL_DUPLEX; + link.link_speed = hw->aq_link_status.mbps; + + rte_atl_dev_atomic_write_link_status(dev, &link); + + if (link.link_status == old.link_status) + return -1; + + return 0; +} + + +/** + * It clears the interrupt causes and enables the interrupt. + * It will be called once only during nic initialized. + * + * @param dev + * Pointer to struct rte_eth_dev. + * @param on + * Enable or Disable. + * + * @return + * - On success, zero. + * - On failure, a negative value. + */ + +static int +atl_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on __rte_unused) +{ + atl_dev_link_status_print(dev); + return 0; +} + +static int +atl_dev_rxq_interrupt_setup(struct rte_eth_dev *dev __rte_unused) +{ + return 0; +} + + +static int +atl_dev_interrupt_get_status(struct rte_eth_dev *dev) +{ + struct atl_interrupt *intr = + ATL_DEV_PRIVATE_TO_INTR(dev->data->dev_private); + struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private); + u64 cause = 0; + + hw_atl_b0_hw_irq_read(hw, &cause); + + atl_disable_intr(hw); + intr->flags = cause & BIT(ATL_IRQ_CAUSE_LINK) ? + ATL_FLAG_NEED_LINK_UPDATE : 0; + + return 0; +} + +/** + * It gets and then prints the link status. + * + * @param dev + * Pointer to struct rte_eth_dev. + * + * @return + * - On success, zero. + * - On failure, a negative value. + */ +static void +atl_dev_link_status_print(struct rte_eth_dev *dev) +{ + struct rte_eth_link link; + + memset(&link, 0, sizeof(link)); + rte_atl_dev_atomic_read_link_status(dev, &link); + if (link.link_status) { + PMD_DRV_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s", + (int)(dev->data->port_id), + (unsigned int)link.link_speed, + link.link_duplex == ETH_LINK_FULL_DUPLEX ? + "full-duplex" : "half-duplex"); + } else { + PMD_DRV_LOG(INFO, " Port %d: Link Down", + (int)(dev->data->port_id)); + } + + +#ifdef DEBUG +{ + struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); + + PMD_DRV_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT, + pci_dev->addr.domain, + pci_dev->addr.bus, + pci_dev->addr.devid, + pci_dev->addr.function); +} +#endif + + PMD_DRV_LOG(INFO, "Link speed:%d", link.link_speed); +} + +/* + * It executes link_update after knowing an interrupt occurred. + * + * @param dev + * Pointer to struct rte_eth_dev. + * + * @return + * - On success, zero. + * - On failure, a negative value. + */ +static int +atl_dev_interrupt_action(struct rte_eth_dev *dev, + struct rte_intr_handle *intr_handle) +{ + struct atl_interrupt *intr = + ATL_DEV_PRIVATE_TO_INTR(dev->data->dev_private); + + if (intr->flags & ATL_FLAG_NEED_LINK_UPDATE) { + atl_dev_link_update(dev, 0); + intr->flags &= ~ATL_FLAG_NEED_LINK_UPDATE; + atl_dev_link_status_print(dev); + _rte_eth_dev_callback_process(dev, + RTE_ETH_EVENT_INTR_LSC, NULL); + } + + atl_enable_intr(dev); + rte_intr_enable(intr_handle); + + return 0; +} + +/** + * Interrupt handler triggered by NIC for handling + * specific interrupt. + * + * @param handle + * Pointer to interrupt handle. + * @param param + * The address of parameter (struct rte_eth_dev *) regsitered before. + * + * @return + * void + */ +static void +atl_dev_interrupt_handler(void *param) +{ + struct rte_eth_dev *dev = (struct rte_eth_dev *)param; + + atl_dev_interrupt_get_status(dev); + atl_dev_interrupt_action(dev, dev->intr_handle); +} + RTE_PMD_REGISTER_PCI(net_atlantic, rte_atl_pmd); RTE_PMD_REGISTER_PCI_TABLE(net_atlantic, pci_id_atl_map); RTE_PMD_REGISTER_KMOD_DEP(net_atlantic, "* igb_uio | uio_pci_generic"); diff --git a/drivers/net/atlantic/atl_ethdev.h b/drivers/net/atlantic/atl_ethdev.h index cafe37cdf963..f75ed0fd1127 100644 --- a/drivers/net/atlantic/atl_ethdev.h +++ b/drivers/net/atlantic/atl_ethdev.h @@ -15,6 +15,16 @@ #define ATL_DEV_TO_ADAPTER(dev) \ ((struct atl_adapter *)(dev)->data->dev_private) +#define ATL_DEV_PRIVATE_TO_INTR(adapter) \ + (&((struct atl_adapter *)adapter)->intr) + +#define ATL_FLAG_NEED_LINK_UPDATE (uint32_t)(1 << 0) +#define ATL_FLAG_NEED_LINK_CONFIG (uint32_t)(4 << 0) + +struct atl_interrupt { + uint32_t flags; + uint32_t mask; +}; /* * Structure to store private data for each driver instance (for each port). @@ -22,6 +32,7 @@ struct atl_adapter { struct aq_hw_s hw; struct aq_hw_cfg_s hw_cfg; + struct atl_interrupt intr; }; /* @@ -39,6 +50,11 @@ int atl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id, uint16_t nb_tx_desc, unsigned int socket_id, const struct rte_eth_txconf *tx_conf); +int atl_dev_rx_queue_intr_enable(struct rte_eth_dev *eth_dev, + uint16_t queue_id); +int atl_dev_rx_queue_intr_disable(struct rte_eth_dev *eth_dev, + uint16_t queue_id); + int atl_rx_init(struct rte_eth_dev *dev); int atl_tx_init(struct rte_eth_dev *dev); diff --git a/drivers/net/atlantic/atl_rxtx.c b/drivers/net/atlantic/atl_rxtx.c index 172d5fb232f2..9d82a0d74f22 100644 --- a/drivers/net/atlantic/atl_rxtx.c +++ b/drivers/net/atlantic/atl_rxtx.c @@ -620,6 +620,42 @@ atl_stop_queues(struct rte_eth_dev *dev) return 0; } +static int +atl_rx_enable_intr(struct rte_eth_dev *dev, uint16_t queue_id, bool enable) +{ + struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct atl_rx_queue *rxq; + + PMD_INIT_FUNC_TRACE(); + + if (queue_id >= dev->data->nb_rx_queues) { + PMD_DRV_LOG(ERR, "Invalid RX queue id=%d", queue_id); + return -EINVAL; + } + + rxq = dev->data->rx_queues[queue_id]; + + if (rxq == NULL) + return 0; + + /* Mapping interrupt vector */ + hw_atl_itr_irq_map_en_rx_set(hw, enable, queue_id); + + return 0; +} + +int +atl_dev_rx_queue_intr_enable(struct rte_eth_dev *eth_dev, uint16_t queue_id) +{ + return atl_rx_enable_intr(eth_dev, queue_id, true); +} + +int +atl_dev_rx_queue_intr_disable(struct rte_eth_dev *eth_dev, uint16_t queue_id) +{ + return atl_rx_enable_intr(eth_dev, queue_id, false); +} + uint16_t atl_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts) diff --git a/drivers/net/atlantic/atl_types.h b/drivers/net/atlantic/atl_types.h index 85f768ce7d93..5f840cc8d63d 100644 --- a/drivers/net/atlantic/atl_types.h +++ b/drivers/net/atlantic/atl_types.h @@ -93,11 +93,13 @@ struct aq_hw_s { void *mmio; struct aq_hw_link_status_s aq_link_status; + bool is_autoneg; struct hw_aq_atl_utils_mbox mbox; struct hw_atl_stats_s last_stats; struct aq_stats_s curr_stats; + u64 speed; unsigned int chip_features; u32 fw_ver_actual; u32 mbox_addr; From patchwork Sat Sep 29 10:30:26 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Russkikh X-Patchwork-Id: 45676 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id ABBFD1B209; Sat, 29 Sep 2018 12:32:09 +0200 (CEST) Received: from NAM05-DM3-obe.outbound.protection.outlook.com (mail-eopbgr730041.outbound.protection.outlook.com [40.107.73.41]) by dpdk.org (Postfix) with ESMTP id 4E0881B3C0 for ; Sat, 29 Sep 2018 12:32:07 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=AQUANTIA1COM.onmicrosoft.com; s=selector1-aquantia-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=5kVY6OTULqZTdVizQ/zftkjo/+GKw5Rt/ISAMXXDKB4=; b=C+x8HYkLPVFY+502RJD5tHaHXPftaOFosV0EWFS9Y4d7ea7WRA/Dk3KluD+tZNeDB5pcMKxqQc3jBBkmY3DV8bmS1sgrnLpf0eSXzMEOlSnf7TRML4n2fP8kyP6Fc2F8iGn/wxxUgyoVJKFc9HrL323YN5I+Jyhh5PRDGe1h6YY= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Igor.Russkikh@aquantia.com; Received: from ubuntubox.rdc.aquantia.com (95.79.108.179) by BLUPR0701MB1650.namprd07.prod.outlook.com (2a01:111:e400:58c6::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1185.22; Sat, 29 Sep 2018 10:31:59 +0000 From: Igor Russkikh To: dev@dpdk.org Cc: pavel.belous@aquantia.com, igor.russkikh@aquantia.com, Pavel Belous Date: Sat, 29 Sep 2018 13:30:26 +0300 Message-Id: <30f6460dc35d9d8e87e714f53c8a93d4353e2468.1538215990.git.igor.russkikh@aquantia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [95.79.108.179] X-ClientProxiedBy: VI1P193CA0009.EURP193.PROD.OUTLOOK.COM (2603:10a6:800:bd::19) To BLUPR0701MB1650.namprd07.prod.outlook.com (2a01:111:e400:58c6::20) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: db8f7c32-24e1-4bcb-b289-08d625f6cd78 X-Microsoft-Antispam: BCL:0; PCL:0; RULEID:(7020095)(4652040)(8989299)(4534165)(4627221)(201703031133081)(201702281549075)(8990200)(5600074)(711020)(2017052603328)(7153060)(7193020); SRVR:BLUPR0701MB1650; X-Microsoft-Exchange-Diagnostics: 1; BLUPR0701MB1650; 3:cYBwmhQOmS4nUpI/biB5PfH2+my3mycahSCV1TF5oviU+aWBGW1zAn5vp/C0Ck5HjIC3QgNvQRRQsbZ3wPRNxzOUwhx5ZipZCPXa5DCxSjb/7N43GmeXzSDeitFaHN3VzmJD+ampUixRx2GLrWR1tM11PMvCZtVoGMwO/z2TCnTE9b2IDWglz83UL5IQ7JOJFxyb+e51Q1uJn+o/XDPyEhegaMwMO3zUmp0qtxsqXTYFHo1NfYjmrIzksNLxMykc; 25:OWY3wtXNYk0tKwwkRJJ4ZrZZxj5ir78vx0nyh6txXwC7SID8ox1H0cSHX13+DpTqrz7ITCDWDcG+bX6Z3T2SF5JQC0/rrksaILN6kGRU9O9SKvtijNEgGNlpsHDsDuKYvqAxz3mYjSsadUUr1DvdO6BgHwmWfSRvE/r7Zn50wq1urfP5biyDqQetEeGB6XgzoqCy1+dzv7aTGbMl74omXPB+dGmhRIn8+DOEp9C0Thu/6eVdIVwgEo4+zxzRuvrP1FcRq6qCCZPRpDWIhyJiB+2QfDoC/IiJkFh4Eyt13ytcE24TX726PQduWvASLjsN70teAaPNW/+Jk9ZCXtPWeE/dGHoo7UYVePL+BKKJtPA=; 31:8oxnKPyG8DM6d2jkVw5+x3xnbbHZ/intgp3ab0hSATRezh+QC3ElIVnYEL7YRnVF+tFfmiTPlCto4fQBsnBD6pJWSFHsWI0K1thEqM/Ig5Q3l1cZvBL+PK7FlLfUcJcsKdl6aDh2aJLqeB6A5R3EGNMU+BNQ7fU3QU2E8HQLkxi1JMA9R53YdVmDUmwTwhKTM6B7ldSWjeuTVAx2CIGuP815SGmdpYp2bQUM2ZRq2W0= X-MS-TrafficTypeDiagnostic: BLUPR0701MB1650: X-Microsoft-Exchange-Diagnostics: 1; BLUPR0701MB1650; 20:tbmXg7sathjsI1ySGn2Byo8Cd/4EgX7RH5OnPoI1QsPbJB2IHA1WAOzzlht2Q8U4wkVCux4GDFbxkFYIWl/PJQH9vh8yhL+7580TBeJl/QBCH4dX1skKTq4moawkEk5tkPKkyLQa/RG6UUqiTEDDG7/4bu0xpk8dUWi7tzYlohwb/A/G740aGeHLkFjwnePRBK59s8Vt8BKao9fDFvrKmfBYyEILZHdj/ygb5jpYMpvno76gADQizasZ33Ydm1yoPnKowwIE/yliNDGF8A9z9ii2fBSkp1JYBc2RJvzqU5bWS2XxINzi7HmQwPAEJRCOa4bcWSquhwfDKwZB10LpsnEjBa1xAZJv9SXeyy8IbhG/Nm8RNU0suxT/tq9nWAbvM/IbsQzPAesX4Z8O7UBHqZ7zWGc/nAQwIQhu1zHC1GqJH4XEfFC3QGJwb32wEV4lO9uXKG1LBo83yA55OQUF47SGqnkTR76HtMO4m21Xva01KDZqzLqYN/rYKHmNEYJm; 4:0Xt4YEbyeQwMakvkKEki31iM95w9+JoT1w1A+xfQYCkU976n7NBlWGEM4F6CoRDv1E8MaC3fBpMhtEp+aV09tUvVnM9/QTCoZ4L2/yuDqI61t/I0VtA64XyQTxXWgfmTyTLJhaSS6soMImqTZpBSeNYzJ8m9bgu+SoVWHfI9m3lnRRScGD0eAKrKq61PjB/MvwvBW4/LMpnZSqTgpSDRiThrTmSmHpkTaAKmuC1WlGJBGFXEjpnsD6SxlPXRabyB9ff43H7MShEgct+NkDDuPw== X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-MS-Exchange-SenderADCheck: 1 X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(6040522)(2401047)(8121501046)(5005006)(10201501046)(3002001)(93006095)(93001095)(3231355)(944501410)(52105095)(149066)(150057)(6041310)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123558120)(20161123564045)(20161123562045)(20161123560045)(201708071742011)(7699051); SRVR:BLUPR0701MB1650; BCL:0; PCL:0; RULEID:; SRVR:BLUPR0701MB1650; X-Forefront-PRVS: 0810818DA0 X-Forefront-Antispam-Report: SFV:NSPM; SFS:(10009020)(346002)(136003)(396003)(376002)(39850400004)(366004)(189003)(199004)(16526019)(14444005)(446003)(76176011)(2906002)(6916009)(6666003)(97736004)(8676002)(81166006)(81156014)(36756003)(4326008)(316002)(8936002)(50226002)(34290500001)(575784001)(86362001)(5660300001)(68736007)(16586007)(118296001)(72206003)(3846002)(6116002)(53936002)(386003)(105586002)(6486002)(47776003)(66066001)(486006)(25786009)(305945005)(50466002)(44832011)(956004)(2616005)(26005)(107886003)(52116002)(51416003)(7696005)(186003)(476003)(478600001)(2361001)(7736002)(2351001)(48376002)(106356001)(11346002); DIR:OUT; SFP:1101; SCL:1; SRVR:BLUPR0701MB1650; H:ubuntubox.rdc.aquantia.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; Received-SPF: None (protection.outlook.com: aquantia.com does not designate permitted sender hosts) X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; BLUPR0701MB1650; 23:R6hbtkxHr9MX2CQwlOi6RvTLKMo9yqlrQa9RB4P?= Na8CMCv0l8PZ1W9xMLS5UHf1j+YFtHW0YKm+XW+TKqGsaAqwD4MOUZFSwfN+XtqWsOPXx+OP3nUVpOC8DYlRH6QbRWceYMJWEEXCV7EP8y4i3yT6sHGBOb27IIl4JWWRHTj9NU/n4rUhwFLuHSAN38/2yYUKVmTkhoMH8MnDM1UIxcAC3c5NW2aZzEhac7ZS0BKqsksf6voHcdCM3evIpOhXZynSL00jcTL9cEgyHv+5stCAqU4SIcC0ZcJb8ZvLCywvC7fzc5SqAdExS+wS7PLCsXEZBKz8VZB3c6j5gjVOqvtRpKbF/Snm6NM1ny2EYrabAy7bQnRUepx3prgZIM+PQN8RwaGph046HQ/fBI3GUtuvYYbsTsOl0+mMv/9gS0HGRT1zWiMZXdJGuNElaEpR5JdanzEm2b2I1WTdac+3muro3nPm93M2IKwguS10Tjq7CBg4/Kzqp7AS0l5ABMtaeMo6BDKgvF226Rd1j3NKqm1NlHcuxaYbCa9gQIMy44v0obVwgaaF0AiGPtyLeQwCcmHL4dBtAi+xV6Cp7Mjw3+rd8yImMFMISKWQKbpYPGR9XH3w47Th2A4zJZIFLHMvl4p572NnE15Ghp/S+UHyvFFVsv5qI2/sAjLAOBBepfZDzh882M9/NWt5WJ6gao5xx245mZCtgXWwgIGg3uG0u+WMJnVmHcCvmqrI7Ln5KFocfKHfvNtafIxYW5diJ3GzqXabnVH4KDhzD97TIXyr5fSmkQ5amdgZEfO4ZooZbqPFLERdMaCJ9E89POqXYQPEhpiKZkpOFb5s8c97Xb6B2rwD7tsWvGueCvN77MShbn60Cbn/Rhrr9xj7f7+R25sHQPfqIBIcOodlVnmoVoKkr9y9eWugYPcASC8ACMWXYIH+BG9r0kJDn1+iJCuY+8FBxEfMTv/q8R4J9li4P2m5g3yN/n+IXgZuFkq39C6kraCXSAuf9Q1lXM+jEwJVxGmcTri/9VxA3SSe+NcpbPz7r3RCX46DK0Rnnq9pb9oaCx+mh+t372O846PMXM6i/rHQNbXh7GaijCUC4LiHbdkQSA6QwoIg4hYBqcBLmRzgnP7olc2CuGPyLZQgu/Uy9YhUNjRDO/KfGJb5anWcnfBhcvsCEw5lyLJ4KcImzTnmbmONUmQrj6i5du62FYgWwnUGv3yObfG1mthjbKWUKSYnqN16beahjwts9dbYKdZIuFetQoKPf4nRtoeVa7nVl9P2b1IsOYx5NyLYHqczLuOwyFsF9PyXPlaK3Hv1FujCQBPNQzc4NH95JsEntX79UXkDM X-Microsoft-Antispam-Message-Info: XEilpNhh76x8xAYkeJfdM6r1YIBYcBy4y1erPHX4z7C75UFcOn4Rvor8Lep+6cbPble5V2XCVGmSbk/QWSPl08lhSWvnkSOQGPo0bRreG/bYJXVeSSMshyBcy2TtZK1Lwiga1aqQNo0yeLE4A6z1041DblHEeWni9BRxbNYFjJd1CRevJGzVMT0tSZLPoHaBRoOw1ZKaI1Mc2z8AwJ11f/QC2gMSbWux6j0niX7kZfLNisoPgEUgiQ8vxXXU7sWxQ9gGMJORYV69v5h4+ISkr2n7tW768MbrDoztCrHFxlkeYVu+HcmIPdBWRb+Z50LwYzVSN5622pXlogLYi3wFVhFaJcxUeXVUv0RELhBN9W0= X-Microsoft-Exchange-Diagnostics: 1; BLUPR0701MB1650; 6:otfNUyr7T0HEACJeKd730AjDY7H32AglSI4ahnN/q3dg1caCnvfdhEp0KbRr+wBmJ2IZ5q5/5h2EtqUlJxJXlCs/MTb01oT5vkajtzAjIQj+XS7F2giWUTPm9QOCeLpGJBuYvWG2X0dP/iLy0ckikUjd7sCvJRlfnJlcZU4/9CJL7EDyjwNMlevRL7KvxkFHT1P4Nv+MQjMVPtEmbet2/5+JijFUGlCXUt4uwbLOcZEmJQmJG9LGvON5E0wykkBhx4cttC+8TvmUWUV5kVWcaB1ATvZEGyplSd/+xkCVnyAwsSi6a0mfgwaZmNCakGtnLetc6eV0a0iETgaVwwraPSbRoR6wBSYobQAiKEl/gZeX0wd0vTTI51jXrmU7RC98iD/h3b2K2bGQ1jx9tC12oyP5Kow8U1vMSbA6RDpZkxpj23EPz3veG72nykODbgCAeSCTJgVPOEWyAZOambE06A==; 5:Hj7h2lvmdThrAUWZKFnI5Gsthh92ude+OgNvo2nh8MypnAFq3Od6EdGkG/l/mPC7TzwSPSTi72S22fWagVQm12f74BXo8LerAl48pzS5Pr2jeHnoxyoEKDx5O3wRdt2fXUjWv2+SdQTyyGoyUPqK/4NA7oYqypQcPG/z/j8EozE=; 7:oN995kqWiBY6OH+zLYBpeqZ+wZBmHoXlazDK/KorPx4Nnx7caUxHhi3fw850xMW26KzvwxPZTNYxURaTRai87BNs+oAC+pqtZUZYXAF4TX8Shk+5DYYUAFb5TEcuARTfvH9ec3c8ZpFJJwLXCHjL40Hs7116uiKto7oC10LKGHPQ234sg/HZRXRxgVKLElscSg8LRnrEr8iYvPXtDL36iwQAYyv43IRE1hFVtWTLCghy41Ruqw/4jm6e3yHeAB3f SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: aquantia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Sep 2018 10:31:59.8297 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: db8f7c32-24e1-4bcb-b289-08d625f6cd78 X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 83e2e134-991c-4ede-8ced-34d47e38e6b1 X-MS-Exchange-Transport-CrossTenantHeadersStamped: BLUPR0701MB1650 Subject: [dpdk-dev] [PATCH v3 12/22] net/atlantic: device statistics, xstats X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavel Belous Signed-off-by: Igor Russkikh Signed-off-by: Pavel Belous --- drivers/net/atlantic/atl_ethdev.c | 154 ++++++++++++++++++++++++++++++++++++++ drivers/net/atlantic/atl_ethdev.h | 1 + drivers/net/atlantic/atl_rxtx.c | 11 ++- drivers/net/atlantic/atl_types.h | 41 ++++++++++ 4 files changed, 206 insertions(+), 1 deletion(-) diff --git a/drivers/net/atlantic/atl_ethdev.c b/drivers/net/atlantic/atl_ethdev.c index 75c9fa169925..fc1d862042d2 100644 --- a/drivers/net/atlantic/atl_ethdev.c +++ b/drivers/net/atlantic/atl_ethdev.c @@ -24,6 +24,24 @@ static void atl_dev_close(struct rte_eth_dev *dev); static int atl_dev_reset(struct rte_eth_dev *dev); static int atl_dev_link_update(struct rte_eth_dev *dev, int wait); +static int atl_dev_xstats_get_names(struct rte_eth_dev *dev __rte_unused, + struct rte_eth_xstat_name *xstats_names, + unsigned int size); + +static int atl_dev_stats_get(struct rte_eth_dev *dev, + struct rte_eth_stats *stats); + +static int atl_dev_xstats_get(struct rte_eth_dev *dev, + struct rte_eth_xstat *stats, unsigned int n); + +static void atl_dev_stats_reset(struct rte_eth_dev *dev); +static void atl_dev_xstats_reset(struct rte_eth_dev *dev); + +static int atl_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev, + uint16_t queue_id, + uint8_t stat_idx, + uint8_t is_rx); + static int atl_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size); @@ -113,6 +131,33 @@ static const struct rte_eth_desc_lim tx_desc_lim = { .nb_mtu_seg_max = ATL_TX_MAX_SEG, }; +#define ATL_XSTATS_FIELD(name) { \ + #name, \ + offsetof(struct aq_stats_s, name) \ +} + +struct atl_xstats_tbl_s { + const char *name; + unsigned int offset; +}; + +static struct atl_xstats_tbl_s atl_xstats_tbl[] = { + ATL_XSTATS_FIELD(uprc), + ATL_XSTATS_FIELD(mprc), + ATL_XSTATS_FIELD(bprc), + ATL_XSTATS_FIELD(erpt), + ATL_XSTATS_FIELD(uptc), + ATL_XSTATS_FIELD(mptc), + ATL_XSTATS_FIELD(bptc), + ATL_XSTATS_FIELD(erpr), + ATL_XSTATS_FIELD(ubrc), + ATL_XSTATS_FIELD(ubtc), + ATL_XSTATS_FIELD(mbrc), + ATL_XSTATS_FIELD(mbtc), + ATL_XSTATS_FIELD(bbrc), + ATL_XSTATS_FIELD(bbtc), +}; + static const struct eth_dev_ops atl_eth_dev_ops = { .dev_configure = atl_dev_configure, .dev_start = atl_dev_start, @@ -125,6 +170,14 @@ static const struct eth_dev_ops atl_eth_dev_ops = { /* Link */ .link_update = atl_dev_link_update, + /* Stats */ + .stats_get = atl_dev_stats_get, + .xstats_get = atl_dev_xstats_get, + .xstats_get_names = atl_dev_xstats_get_names, + .stats_reset = atl_dev_stats_reset, + .xstats_reset = atl_dev_xstats_reset, + .queue_stats_mapping_set = atl_dev_queue_stats_mapping_set, + .fw_version_get = atl_fw_version_get, .dev_infos_get = atl_dev_info_get, .dev_supported_ptypes_get = atl_dev_supported_ptypes_get, @@ -286,6 +339,9 @@ eth_atl_dev_init(struct rte_eth_dev *eth_dev) (u8 *)ð_dev->data->mac_addrs[0]) != 0) return -EINVAL; + /* Reset the hw statistics */ + atl_dev_stats_reset(eth_dev); + rte_intr_callback_register(intr_handle, atl_dev_interrupt_handler, eth_dev); @@ -613,6 +669,104 @@ atl_dev_reset(struct rte_eth_dev *dev) return ret; } + +static int +atl_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) +{ + struct atl_adapter *adapter = + (struct atl_adapter *)dev->data->dev_private; + struct aq_hw_s *hw = &adapter->hw; + struct atl_sw_stats *swstats = &adapter->sw_stats; + unsigned int i; + + hw->aq_fw_ops->update_stats(hw); + + /* Fill out the rte_eth_stats statistics structure */ + stats->ipackets = hw->curr_stats.dma_pkt_rc; + stats->ibytes = hw->curr_stats.dma_oct_rc; + stats->imissed = hw->curr_stats.dpc; + stats->ierrors = hw->curr_stats.erpt; + + stats->opackets = hw->curr_stats.dma_pkt_tc; + stats->obytes = hw->curr_stats.dma_oct_tc; + stats->oerrors = 0; + + stats->rx_nombuf = swstats->rx_nombuf; + + for (i = 0; i < RTE_ETHDEV_QUEUE_STAT_CNTRS; i++) { + stats->q_ipackets[i] = swstats->q_ipackets[i]; + stats->q_opackets[i] = swstats->q_opackets[i]; + stats->q_ibytes[i] = swstats->q_ibytes[i]; + stats->q_obytes[i] = swstats->q_obytes[i]; + stats->q_errors[i] = swstats->q_errors[i]; + } + return 0; +} + +static void +atl_dev_stats_reset(struct rte_eth_dev *dev) +{ + struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private); + + hw->aq_fw_ops->update_stats(hw); + + /* Reset software totals */ + memset(&hw->curr_stats, 0, sizeof(hw->curr_stats)); +} + +static int +atl_dev_xstats_get_names(struct rte_eth_dev *dev __rte_unused, + struct rte_eth_xstat_name *xstats_names, + unsigned int size) +{ + unsigned int i; + + if (!xstats_names) + return RTE_DIM(atl_xstats_tbl); + + for (i = 0; i < size && i < RTE_DIM(atl_xstats_tbl); i++) + snprintf(xstats_names[i].name, RTE_ETH_XSTATS_NAME_SIZE, "%s", + atl_xstats_tbl[i].name); + + return size; +} + +static int +atl_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *stats, + unsigned int n) +{ + struct atl_adapter *adapter = + (struct atl_adapter *)dev->data->dev_private; + struct aq_hw_s *hw = &adapter->hw; + unsigned int i; + + if (!stats) + return 0; + + for (i = 0; i < n && i < RTE_DIM(atl_xstats_tbl); i++) { + stats[i].id = i; + stats[i].value = *(u64 *)((uint8_t *)&hw->curr_stats + + atl_xstats_tbl[i].offset); + } + + return n; +} + +static void +atl_dev_xstats_reset(struct rte_eth_dev *dev __rte_unused) +{ +} + +static int +atl_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev __rte_unused, + uint16_t queue_id __rte_unused, + uint8_t stat_idx __rte_unused, + uint8_t is_rx __rte_unused) +{ + /* The mapping is hardcoded: queue 0 -> stat 0, etc */ + return 0; +} + static int atl_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size) { diff --git a/drivers/net/atlantic/atl_ethdev.h b/drivers/net/atlantic/atl_ethdev.h index f75ed0fd1127..90d63797b2c6 100644 --- a/drivers/net/atlantic/atl_ethdev.h +++ b/drivers/net/atlantic/atl_ethdev.h @@ -32,6 +32,7 @@ struct atl_interrupt { struct atl_adapter { struct aq_hw_s hw; struct aq_hw_cfg_s hw_cfg; + struct atl_sw_stats sw_stats; struct atl_interrupt intr; }; diff --git a/drivers/net/atlantic/atl_rxtx.c b/drivers/net/atlantic/atl_rxtx.c index 9d82a0d74f22..94054ca5c9fa 100644 --- a/drivers/net/atlantic/atl_rxtx.c +++ b/drivers/net/atlantic/atl_rxtx.c @@ -843,7 +843,8 @@ atl_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts) "queue_id=%u", (unsigned int)rxq->port_id, (unsigned int)rxq->queue_id); dev->data->rx_mbuf_alloc_failed++; - goto err_stop; + adapter->sw_stats.rx_nombuf++; + goto err_stop; } nb_hold++; @@ -926,6 +927,9 @@ atl_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts) * of returned packets. */ rx_pkts[nb_rx++] = rx_mbuf_first; + adapter->sw_stats.q_ipackets[rxq->queue_id]++; + adapter->sw_stats.q_ibytes[rxq->queue_id] += + rx_mbuf_first->pkt_len; PMD_RX_LOG(ERR, "add mbuf segs=%d pkt_len=%d", rx_mbuf_first->nb_segs, @@ -1071,6 +1075,8 @@ static inline void atl_xmit_pkt(struct aq_hw_s *hw, struct atl_tx_queue *txq, struct rte_mbuf *tx_pkt) { + struct atl_adapter *adapter = + ATL_DEV_TO_ADAPTER(&rte_eth_devices[txq->port_id]); uint32_t pay_len = 0; int tail = 0; struct atl_tx_entry *tx_entry; @@ -1151,6 +1157,9 @@ atl_xmit_pkt(struct aq_hw_s *hw, struct atl_tx_queue *txq, txq->tx_tail = tail; txq->tx_free -= desc_count; + + adapter->sw_stats.q_opackets[txq->queue_id]++; + adapter->sw_stats.q_obytes[txq->queue_id] += pay_len; } uint16_t diff --git a/drivers/net/atlantic/atl_types.h b/drivers/net/atlantic/atl_types.h index 5f840cc8d63d..99e920315014 100644 --- a/drivers/net/atlantic/atl_types.h +++ b/drivers/net/atlantic/atl_types.h @@ -147,4 +147,45 @@ struct aq_fw_ops { int (*set_eeprom)(struct aq_hw_s *self, u32 *data, u32 len); }; +struct atl_sw_stats { + u64 crcerrs; + u64 errbc; + u64 mspdc; + u64 mpctotal; + u64 mpc[8]; + u64 mlfc; + u64 mrfc; + u64 rlec; + u64 lxontxc; + u64 lxonrxc; + u64 lxofftxc; + u64 lxoffrxc; + u64 pxontxc[8]; + u64 pxonrxc[8]; + u64 pxofftxc[8]; + u64 pxoffrxc[8]; + u64 gprc; + u64 bprc; + u64 mprc; + u64 gptc; + u64 gorc; + u64 gotc; + u64 tor; + u64 tpr; + u64 tpt; + u64 mptc; + u64 bptc; + u64 xec; + u64 fccrc; + u64 ldpcec; + u64 pcrc8ec; + + u64 rx_nombuf; + u64 q_ipackets[RTE_ETHDEV_QUEUE_STAT_CNTRS]; + u64 q_opackets[RTE_ETHDEV_QUEUE_STAT_CNTRS]; + u64 q_ibytes[RTE_ETHDEV_QUEUE_STAT_CNTRS]; + u64 q_obytes[RTE_ETHDEV_QUEUE_STAT_CNTRS]; + u64 q_errors[RTE_ETHDEV_QUEUE_STAT_CNTRS]; +}; + #endif From patchwork Sat Sep 29 10:30:27 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Russkikh X-Patchwork-Id: 45677 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 813DD1B3DD; Sat, 29 Sep 2018 12:32:11 +0200 (CEST) Received: from NAM05-DM3-obe.outbound.protection.outlook.com (mail-eopbgr730041.outbound.protection.outlook.com [40.107.73.41]) by dpdk.org (Postfix) with ESMTP id A4EC31B1E8 for ; Sat, 29 Sep 2018 12:32:08 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=AQUANTIA1COM.onmicrosoft.com; s=selector1-aquantia-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=DrvGurQBsp8dKRGPmlT+WwBiohO7swqhIT6PEbBpriQ=; b=JHRbjksyZZMOYfIB3dmGP7GrhzyB3G8g2MJyioUdWcQLowBi49/v7Fxfcdy8JQutMiyYVF7OAC9WxkrlC3/dkPN+UBQPRksR22GdKQPCDrDFrXvUL01h0Qdsyb6nk1FAAh4rEzJVZjVIOwT5nThWxWyCVakV/8sn0NzYfZEtdQY= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Igor.Russkikh@aquantia.com; Received: from ubuntubox.rdc.aquantia.com (95.79.108.179) by BLUPR0701MB1650.namprd07.prod.outlook.com (2a01:111:e400:58c6::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1185.22; Sat, 29 Sep 2018 10:32:06 +0000 From: Igor Russkikh To: dev@dpdk.org Cc: pavel.belous@aquantia.com, igor.russkikh@aquantia.com Date: Sat, 29 Sep 2018 13:30:27 +0300 Message-Id: <64e175c35ae42681d7dc5cc7b3cbc38871873524.1538215990.git.igor.russkikh@aquantia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [95.79.108.179] X-ClientProxiedBy: VI1P193CA0009.EURP193.PROD.OUTLOOK.COM (2603:10a6:800:bd::19) To BLUPR0701MB1650.namprd07.prod.outlook.com (2a01:111:e400:58c6::20) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 57453221-237c-447d-d28c-08d625f6ce58 X-Microsoft-Antispam: BCL:0; PCL:0; RULEID:(7020095)(4652040)(8989299)(4534165)(4627221)(201703031133081)(201702281549075)(8990200)(5600074)(711020)(2017052603328)(7153060)(7193020); SRVR:BLUPR0701MB1650; X-Microsoft-Exchange-Diagnostics: 1; BLUPR0701MB1650; 3:HLK9nFlXU7i+vNCJxJGoVNhtyU5LygrYCZdIuJY2zEbpZUmUY9X6YNGoUSV/drLgU/rrBI77Zjy8ZxPjj9kHvrfv7TgSDY+MkG/Uvz8+6YtHNlaszfpZ+RBSFbS7Xz3KPPIqHuyA1kazmxAYyjld+G4Ly73P6P2i8Lu2fnI7OoNIGBA3dhqeSEi/SXpV9FiXqSaRMMWxRXUksuz+6uWw0KfwRELeSzNUPxhpsVlSRZL3ePPAlGOm7Ym7mtJ1swFB; 25:4HKHVTKnG5QM6uyhcC75+PeT9MKxyf/ptnJsOTsBqN3OGwuoWmUKeaaHSCvir9dG+7WV2hx//sq32C2aYXKIcquA1SycW/C238GnF4t+9wHtuOVZWba5FNX4JwtRRBD4Ltb92Ft4Pb9igaqpwXzueaWehCzGz591gLWepOVTvnhCZGD3y65+XTTUBuWiXEM8pd5n7XZsu9bZxDQLwI1lqd1DmWG6mLoP4wYAIN6Dm1hwRd5BqtFIX9uMslpWnm83tAkK7CakC5Gy/Qu8mSvZEiG2EwMlHXs8m5ty5h0jZ5OJyyij8wH0XYZ4/gT+LMjzZi5Legph3fW12FbZm8cbqw==; 31:CKV61jsVhASQs4FHvDPngxjc353a6KzifEb/uIiuzbISDbWu5V/yjMhqQJq+tRCYf5/xvdloR9OXhYn+i8hhQVlnwzpTO1rXiZb9fVEHwQWwnXqxNilMnZF48hjiYyKz5dcsbZp3sQyURR9+wh+ZcV2pRBkdFc6rrkiu8Mli+mXQXGBVtA7g6AOI5mYUTR0kvXbJyLuez1mGaKUnMe0AIiRrxagWFaslYw3XOuQh6Kc= X-MS-TrafficTypeDiagnostic: BLUPR0701MB1650: X-Microsoft-Exchange-Diagnostics: 1; BLUPR0701MB1650; 20:IhFzOjq4+a5eWN1Jlbvusky297lMItAAbYID/QT5AnN/Duj+gdxZBe3s+XeVahMHpZbeKEnd8jPbp9qG88sleNXt/mR407Bg92y7xgZeO4rQVRLC8txyRkcI3Zq/s6yFGDH5SQUFp593eY+QTrPODeN5XNPnqRP/bLDm5OQUsmEJk6v1IOTQh2KAVeuYYfcsZ+CqvIyeankKAzqOpjrxOfnWyVDlbYldsbohs1az6ODfHrDRENUQ3vP+Gk2lK64EgSV91iDLCxr/zLnsfiNV5Diqm8PrsASoE6dvpLuL411m4V9oiJhHWHeET0L3aHp5Q8oHw85umAX21adObBsi1DCD0StJieaxECc0ZSuUFSOh7gpetyeJ5BLOjvmkyVy4cr43cf1PIncVo+NJVGzq4aKQ1x6HfVsbV33nowL41JkuANGo8nXRtekqowA0193nL+S4dchHG+TdHd7NHSlUffFH6pP0Mo5H18viTEUZvCUfIu97ScKsQE131EXzVAll; 4:dVG+O8atn5c39MfU/EMZ0uCHTrU1BY0xbSx3AxFrlyq/2g72W2xEEL3Ug77ioITe32gL+HUPpvKn7HplHcpiO0s9e8GuPStNdLwbLqCk21t6Z4QIXeDUU61N1MXnu5Nov2KjemB4dPOl2C5Jsn4kgNC7k2Kr21WTrko1d0aP6jW0rRp7b7kKIucskwQLxkcrRolj7DXbG/U6km6QL/PRbbY8LyXTTvbYnch0bOSeTPRB+pXTnh/U94zNKdjG99H4Afz+Oa30EKwlA77PhqbAMA== X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-MS-Exchange-SenderADCheck: 1 X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(6040522)(2401047)(8121501046)(5005006)(10201501046)(3002001)(93006095)(93001095)(3231355)(944501410)(52105095)(149066)(150057)(6041310)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123558120)(20161123564045)(20161123562045)(20161123560045)(201708071742011)(7699051); SRVR:BLUPR0701MB1650; BCL:0; PCL:0; RULEID:; SRVR:BLUPR0701MB1650; X-Forefront-PRVS: 0810818DA0 X-Forefront-Antispam-Report: SFV:NSPM; SFS:(10009020)(346002)(136003)(396003)(376002)(39850400004)(366004)(189003)(199004)(16526019)(446003)(76176011)(2906002)(6916009)(6666003)(97736004)(8676002)(81166006)(81156014)(36756003)(4326008)(316002)(8936002)(50226002)(34290500001)(575784001)(86362001)(5660300001)(68736007)(16586007)(118296001)(72206003)(3846002)(6116002)(53936002)(386003)(105586002)(6486002)(47776003)(66066001)(486006)(25786009)(305945005)(50466002)(44832011)(956004)(2616005)(26005)(107886003)(52116002)(51416003)(7696005)(186003)(476003)(478600001)(2361001)(7736002)(2351001)(48376002)(106356001)(11346002); DIR:OUT; SFP:1101; SCL:1; SRVR:BLUPR0701MB1650; H:ubuntubox.rdc.aquantia.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; Received-SPF: None (protection.outlook.com: aquantia.com does not designate permitted sender hosts) X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; BLUPR0701MB1650; 23:FjumuGsgkLDJdB/WHvRJmuT70D6wpZU+8iCqNdB?= i4XP9rW0Qa5w20ODINrVjFJx6Qqtl849joREAWIQG41gJiCsHyOzsXv+UmiUCeAJHB/vv+kp52V7TWuh9zA61WztwcP/DAG1rRyJn25pGFDT2l8pX4pg+qrhOvWYul7uF8z+J45ZaEJdnXO1upIGCzq3r7OZhsWthh+tNWpO1op4k01m3aCKpgqpvKpDFYUsEJC/0SMwPdeqKuvppOxojMfkJ1UF3f3rqDRZHCRC2TyEhCl3wFrod8S42KNn+3owryhBiamcBt019QUL9z8xUa4G/lgdTgMcyKmLlSjfhOC212Um5jsvBT0z+R7GwUg+tiezM2Et9TN49w3ZJeaOO4e3PenBM21W4tv9l2jlUlE7oOjQt5EnV2De3LkoV7j8PjC3jT92p+NyJoOE2j2R2n82GVPJMTOiNyPNdlu6CfoYQlnm3K972RMEbZdpqKh6Lf/ACNpxWP+xv/na1gjRhe6GGLLM8yoyRqKsn4if4gfdFbrzYg+Hr7Nwyxm5yGAjVO3yc31gf1ONt7vRw4rOAOrkvCG/VpMjUb0A4mCZKpjkR+zgun8Q3vpXIsmSQd4iFL0nDw9YYE16il/tTTmyTLnKPNM014LlZUIBuuF++jw3h9E3VrccZGTHUGNtYF1OgXkTPfzBEoHZkpUYItlwt4pfCvTQLjr4eRrykggFQZ7Gl8SSMJHoRn7xw3Ic5EMw3rI4nOwfOzMvJTK+EdJ2+hudXbkgn/8eJ9conedKEEYSDZTBfXubxd7TBFoTq7ipngyrl0s0oIbUqbZVjkiz/8xgsCKP2miOKanf3JVrjvUlSykf4RCiCb97PzULv5oo0cb5Dt1sksWdaL+Sue+fSqfBAi/Ra3g8/E738RfETuUCyMcG3oouirhhiC5V/bhyd69/FtzSFpHfoXXTk7VYVL1NngRme1QiY7JYlPPJU6KZKVUB9yKiAQYmGvAhhkjZeFsPTNXXyhAgybdzWE3qtZkmIii+pyzaY8R0/yjYo8q7A3o5+TTjvGYFJbl+mT2Z6a5gOD1HYNLelhvSwI7XquZKPnxNe74m/LGfShJb/6Zukv3xAALrQDoCS1aAXjAh6MNoaM/cNsnli4QpUjNsIYTjsmyikb/kqxPxioFva4yLM/4H70hk1MIKpowy8cwAuNOvA8DaiJgzZP27npjMfKie3lofc7qpLifxQA+MNAN20mz9GVpR07sjAbMOX+Ks63vDZMgOubEIw83LGUj0peobsxg/vKv90HOudvl6Ebt2wzTbCEY8fVDGlZEDE/eiTQqE= X-Microsoft-Antispam-Message-Info: /rkEi8Xk2TOWFVYYUcMst/tfTGRmEQdgXgVhc3c4BuksgoRTyqMrO8H39g+w/vJESEHUKnHQqFpjTUR037r8/pNGci26/AnxJ1ktQKVwWEIuTHiKYAfxSaJBemD6ZS9W2u1wqGeB3qgIE2k3NgFHSftXnaLoUjx4NSCJRrdeU6gq7szhu3aPPYGJWsSb6Gdbf8pB1Yct4XWuYoU1BtAgEsBa5dhgkyeqPKe9Xq0G4hBZ8NhRuR9TCVttz4O2oPcS++Z1eziyryLNPPYl5+WSsWpFRRu1uhyF3dh6ZSd3+xYOFTl4F74hLtYTddGPXvtDJvcvQuPSSb/4GdDlByqCP6rtlFWbDtgGtoSAuRz+3Ls= X-Microsoft-Exchange-Diagnostics: 1; BLUPR0701MB1650; 6:+pK8WNXvXkxN82BdekSiFj9mTzl9u8Wk5cZVcOCtuVpnQn4GjbNBV7UN7pQA3ZAskj8hF3lvePTu0qS6wb8hgvbvM51+2sH8KXMagZ9ET6zB3JvFj0TbqVft32Ot02oDyFi1f16CrN697X9By8OrXH/1h6fb1K4vzXgZTtTndpTGfbEiXWhjXNsdaRz7Xl9+jFGq2O7Hy5uuXT5ZSRX1+TJ5fLHLyN7JGapuvhO0BQ5DfJBPI+v3D3CghQZkKufzm1Z/bQ+uJVACtgcgslZpmEAclNUWY08qDmGB/K2+X98LUJvjjHJQGORfAK6q1wRAtffVE1pKIjeUHcGTNFNS2Ybbp6uu863gtbz8aM6hQaUUligLwMtS2QLP4TjmvkUyAT3Hxd26jn1cdPo29fMtW1WmyG+zinOp2FkmF+IAxMGnTHlohxR0JUHawQfF51Rs2gFBK3qI8eVavVJ+uVFwqg==; 5:PcnNHQ1Zv9tmzQWMEBfmiL+hycbT0bsNXczC0BB4iq15WYIC+Kfrdooin3rEfKd54EhCWKfP9adebo4ZPfLsxzMDuTo6uQE3oJ6DJXogEAOC2P/l7R9yZNECN6Gsj2oHMCjhdR7zi3qCUWt8g4ezG2hjEBKBVH4dTAg+XRtMJWc=; 7:UA78QpLKlHj8lDJKGOA40oEG7qSdLgpkMiPndEn5bi4ZgGcDmZCei4a/43L4xbVaRVhMRo14ecJCQ9X70b9rTlg5VEFLHM4FRs08k9RzEtrORfJYR5e9VQYp0PB2drd5MlmKKrHFWqg0/v3j7+TghLVQBDovvlfwBKqhsxQHzrYy1SQuZPTbziT76RHpyqOO3uu2gX1WimA8TNVHmlGlDpdr31whQV/FVtpECxtKKmFz0cnUdGePk73KoF5G6pCW SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: aquantia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Sep 2018 10:32:06.4707 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 57453221-237c-447d-d28c-08d625f6ce58 X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 83e2e134-991c-4ede-8ced-34d47e38e6b1 X-MS-Exchange-Transport-CrossTenantHeadersStamped: BLUPR0701MB1650 Subject: [dpdk-dev] [PATCH v3 13/22] net/atlantic: support for RX/TX descriptors information X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavel Belous Signed-off-by: Igor Russkikh Signed-off-by: Pavel Belous --- drivers/net/atlantic/atl_ethdev.c | 8 +++ drivers/net/atlantic/atl_ethdev.h | 12 ++++ drivers/net/atlantic/atl_rxtx.c | 125 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 145 insertions(+) diff --git a/drivers/net/atlantic/atl_ethdev.c b/drivers/net/atlantic/atl_ethdev.c index fc1d862042d2..bc0cb3da1f66 100644 --- a/drivers/net/atlantic/atl_ethdev.c +++ b/drivers/net/atlantic/atl_ethdev.c @@ -195,6 +195,14 @@ static const struct eth_dev_ops atl_eth_dev_ops = { .rx_queue_intr_enable = atl_dev_rx_queue_intr_enable, .rx_queue_intr_disable = atl_dev_rx_queue_intr_disable, + + .rx_queue_count = atl_rx_queue_count, + .rx_descriptor_done = atl_dev_rx_descriptor_done, + .rx_descriptor_status = atl_dev_rx_descriptor_status, + .tx_descriptor_status = atl_dev_tx_descriptor_status, + + .rxq_info_get = atl_rxq_info_get, + .txq_info_get = atl_txq_info_get, }; diff --git a/drivers/net/atlantic/atl_ethdev.h b/drivers/net/atlantic/atl_ethdev.h index 90d63797b2c6..17c8505e4707 100644 --- a/drivers/net/atlantic/atl_ethdev.h +++ b/drivers/net/atlantic/atl_ethdev.h @@ -51,6 +51,12 @@ int atl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id, uint16_t nb_tx_desc, unsigned int socket_id, const struct rte_eth_txconf *tx_conf); +uint32_t atl_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id); + +int atl_dev_rx_descriptor_done(void *rx_queue, uint16_t offset); +int atl_dev_rx_descriptor_status(void *rx_queue, uint16_t offset); +int atl_dev_tx_descriptor_status(void *tx_queue, uint16_t offset); + int atl_dev_rx_queue_intr_enable(struct rte_eth_dev *eth_dev, uint16_t queue_id); int atl_dev_rx_queue_intr_disable(struct rte_eth_dev *eth_dev, @@ -69,6 +75,12 @@ int atl_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id); int atl_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id); int atl_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id); +void atl_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, + struct rte_eth_rxq_info *qinfo); + +void atl_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, + struct rte_eth_txq_info *qinfo); + uint16_t atl_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts); diff --git a/drivers/net/atlantic/atl_rxtx.c b/drivers/net/atlantic/atl_rxtx.c index 94054ca5c9fa..ebb606fbcd7c 100644 --- a/drivers/net/atlantic/atl_rxtx.c +++ b/drivers/net/atlantic/atl_rxtx.c @@ -620,6 +620,131 @@ atl_stop_queues(struct rte_eth_dev *dev) return 0; } +void +atl_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, + struct rte_eth_rxq_info *qinfo) +{ + struct atl_rx_queue *rxq; + + PMD_INIT_FUNC_TRACE(); + + rxq = dev->data->rx_queues[queue_id]; + + qinfo->mp = rxq->mb_pool; + qinfo->scattered_rx = dev->data->scattered_rx; + qinfo->nb_desc = rxq->nb_rx_desc; +} + +void +atl_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, + struct rte_eth_txq_info *qinfo) +{ + struct atl_tx_queue *txq; + + PMD_INIT_FUNC_TRACE(); + + txq = dev->data->tx_queues[queue_id]; + + qinfo->nb_desc = txq->nb_tx_desc; +} + +/* Return Rx queue avail count */ + +uint32_t +atl_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id) +{ + struct atl_rx_queue *rxq; + + PMD_INIT_FUNC_TRACE(); + + if (rx_queue_id >= dev->data->nb_rx_queues) { + PMD_DRV_LOG(ERR, "Invalid RX queue id=%d", rx_queue_id); + return 0; + } + + rxq = dev->data->rx_queues[rx_queue_id]; + + if (rxq == NULL) + return 0; + + return rxq->nb_rx_desc - rxq->nb_rx_hold; +} + +int +atl_dev_rx_descriptor_done(void *rx_queue, uint16_t offset) +{ + struct atl_rx_queue *rxq = rx_queue; + struct hw_atl_rxd_wb_s *rxd; + uint32_t idx; + + PMD_INIT_FUNC_TRACE(); + + if (unlikely(offset >= rxq->nb_rx_desc)) + return 0; + + idx = rxq->rx_tail + offset; + + if (idx >= rxq->nb_rx_desc) + idx -= rxq->nb_rx_desc; + + rxd = (struct hw_atl_rxd_wb_s *)&rxq->hw_ring[idx]; + + return rxd->dd; +} + +int +atl_dev_rx_descriptor_status(void *rx_queue, uint16_t offset) +{ + struct atl_rx_queue *rxq = rx_queue; + struct hw_atl_rxd_wb_s *rxd; + uint32_t idx; + + PMD_INIT_FUNC_TRACE(); + + if (unlikely(offset >= rxq->nb_rx_desc)) + return -EINVAL; + + if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold) + return RTE_ETH_RX_DESC_UNAVAIL; + + idx = rxq->rx_tail + offset; + + if (idx >= rxq->nb_rx_desc) + idx -= rxq->nb_rx_desc; + + rxd = (struct hw_atl_rxd_wb_s *)&rxq->hw_ring[idx]; + + if (rxd->dd) + return RTE_ETH_RX_DESC_DONE; + + return RTE_ETH_RX_DESC_AVAIL; +} + +int +atl_dev_tx_descriptor_status(void *tx_queue, uint16_t offset) +{ + struct atl_tx_queue *txq = tx_queue; + struct hw_atl_txd_s *txd; + uint32_t idx; + + PMD_INIT_FUNC_TRACE(); + + if (unlikely(offset >= txq->nb_tx_desc)) + return -EINVAL; + + idx = txq->tx_tail + offset; + + if (idx >= txq->nb_tx_desc) + idx -= txq->nb_tx_desc; + + txd = &txq->hw_ring[idx]; + + if (txd->dd) + return RTE_ETH_TX_DESC_DONE; + + return RTE_ETH_TX_DESC_FULL; +} + static int atl_rx_enable_intr(struct rte_eth_dev *dev, uint16_t queue_id, bool enable) { From patchwork Sat Sep 29 10:30:28 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Russkikh X-Patchwork-Id: 45678 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 854101B3A8; Sat, 29 Sep 2018 12:32:19 +0200 (CEST) Received: from NAM05-DM3-obe.outbound.protection.outlook.com (mail-eopbgr730063.outbound.protection.outlook.com [40.107.73.63]) by dpdk.org (Postfix) with ESMTP id 600001B396 for ; Sat, 29 Sep 2018 12:32:15 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=AQUANTIA1COM.onmicrosoft.com; s=selector1-aquantia-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=gpP22dAcqGla3WsDhiAkJ9oMBdIG+OuzgXouCn+C0ug=; b=gdhkSzStEW6J9ctTLL0+VrlRW+3kQGkWiCGbS23fKI79HZnaDtUX//6kAufymvdYFPXLSmV0yRdePvkhxDNPLIP36wSFFyFMPEOc/rMkH70W86nZ7FxlfwcO9AZKGjWxrtE52yRt+Oy3VlbP3CrLSqFiuSy3MmAfQQAmJa9ZVEE= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Igor.Russkikh@aquantia.com; Received: from ubuntubox.rdc.aquantia.com (95.79.108.179) by BLUPR0701MB1650.namprd07.prod.outlook.com (2a01:111:e400:58c6::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1185.22; Sat, 29 Sep 2018 10:32:07 +0000 From: Igor Russkikh To: dev@dpdk.org Cc: pavel.belous@aquantia.com, igor.russkikh@aquantia.com, Pavel Belous Date: Sat, 29 Sep 2018 13:30:28 +0300 Message-Id: <5788ce2f2879cdf3117356987b3f8d84e8f28ef6.1538215990.git.igor.russkikh@aquantia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [95.79.108.179] X-ClientProxiedBy: VI1P193CA0009.EURP193.PROD.OUTLOOK.COM (2603:10a6:800:bd::19) To BLUPR0701MB1650.namprd07.prod.outlook.com (2a01:111:e400:58c6::20) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: e680d7f6-2619-43f0-4e83-08d625f6d255 X-Microsoft-Antispam: BCL:0; PCL:0; RULEID:(7020095)(4652040)(8989299)(4534165)(4627221)(201703031133081)(201702281549075)(8990200)(5600074)(711020)(2017052603328)(7153060)(7193020); SRVR:BLUPR0701MB1650; X-Microsoft-Exchange-Diagnostics: 1; BLUPR0701MB1650; 3:OY5dzgOiz1BzOOcyWdjyKUg6jR8wwO/EM9xbTVofhfQoo+Ye6c6PObWvQXEGfBi0vKBKb40zNuI74CckBSCJzgW8X4to31DMUMt/enApRQEMgnNxOnCHLj6X5US5JR/0YLoY30FoIcNSsPUmNkMRsYuvWLbOr18RD6dtEoVfiXZA9xUTrkBAnKljp+fVcTA0+qicX2vf/AjoIgWV0PuFNAPA50OOG4wTkrmusqMfLY3vBIUQxbI4WOHuHlTsZIYs; 25:IWPB+kIQsl2z6WKsbRSdW5g7FoFO8rBvfPIn2sM8zHffT+pKeEXbOBvYrrYVXyfQTXnuPosMur7KvUkaPop3nP53f4vOlD/+oIWx5tnH6VDI6E9MPXVhH7yTAYOEA3F4f0AmIPrZ1tYHvvc6D498tzqWMwxXWiDr3PKF0SDg+GtUdbs+QgoLM69jltQeYollrELq6w4CHxp7mpsrhDB8+BHsnMVzSmChmul43hN0bPCdLopnGWT8ztHEV1rHOIqHUmG70FyFOsI9UArZGppYOEymyph/kmcrv4vYrnKe7qoD+TuazqA1hHxqOl5BHjHZ+f7hWtN4UW9gitCLe2pPd+A7Mpv1EYEGTydhJvkP4aw=; 31:6muv3xHHjFEwJyQbh1GNZDChkhdGEAtyR3xf3CsqyxONeWgOZMjkFjD/VPRDjHsGxfeT51NreoNomPToYAid7jXk94DN/tMqoXDTxAHEV3h22UYmHExsuX0i44UKJvGA+hKw95YhwgvH4XBzLxfjZdzjhB7thAQuxA2li0n/TWhrFCb/zQawwgKxrBKZ3pGIgxZALGRB7/q/Xoc0mqzn05KWDLxWhvYxY9vMjNFBcuQ= X-MS-TrafficTypeDiagnostic: BLUPR0701MB1650: X-Microsoft-Exchange-Diagnostics: 1; BLUPR0701MB1650; 20:ZnlVBRPwW6S6DFb2mgrWvPlZuYLMGhWjDI136vio3qLtujSn7IuNMznnIxPp+/1j77QnUjZzrK8pXKhRSRSuSfIx46S+YJsPWqll6p5X0xsZRksrg13S0jAZj4NiGJRJnZO5OCVuxzZJAyd+uacRhzX3yMhEhaXindXAs7A2GVHZ+6rVRH7tWOFv90bhpfSIWuQvVZFTRynDSeFR7zWKl6v6lOKf+zFehPlRuLjHtI+8gBk3nU0XRPMDf/Uhi+w0+eoti10624odWG1FXpdxQLaiTd93PlCogWezhx2X5vpmcWDC5WnsCd4JFi8+cDCm6qMiLgzJolNzBp2w1utP5Bn24LHBL+g+0hk9N1VPvnJ+DmY/dOOdFCPRVoy0V9PS7iUpPaOj6hIKqEuvKU1OW0xmlFALJABe1+WuGmSj9SI1cnYdz6FywM0D8/gpKFDcL6b5BbWGKXvlarIRdrkT4SJX6MMSnsJLbctPna1cTTys2W07e+oQsW9pXfEJCQce; 4:eMkHEQHnpq499Xqf5wCSxOsuNUcN2+p1nTjVv+iARN7Ib2GUycMAQSlr6zUa+2+qBFM5Bl3eF2PhfcZXoDz0rcm5PtE65pgfbMEoYMcelWkGJWnG/P8chgYxUZIBYMagkF9Pw5si3IdRziViAU+EaTTIU1pHhYN0jGzbsGFyEExVxOeg/cJX3QfwamLrBRxpKqtJCljcdbM3iN/XRFZQrGZqH4yjfeval7Fjxwz+22GAmgiEgvvtAq7v47sRxIF+brpn7GfE/oZ3nn8NUISU3A== X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-MS-Exchange-SenderADCheck: 1 X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(6040522)(2401047)(8121501046)(5005006)(10201501046)(3002001)(93006095)(93001095)(3231355)(944501410)(52105095)(149066)(150057)(6041310)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123558120)(20161123564045)(20161123562045)(20161123560045)(201708071742011)(7699051); SRVR:BLUPR0701MB1650; BCL:0; PCL:0; RULEID:; SRVR:BLUPR0701MB1650; X-Forefront-PRVS: 0810818DA0 X-Forefront-Antispam-Report: SFV:NSPM; SFS:(10009020)(346002)(136003)(396003)(376002)(39850400004)(366004)(189003)(199004)(16526019)(14444005)(446003)(76176011)(2906002)(6916009)(6666003)(97736004)(8676002)(81166006)(81156014)(36756003)(4326008)(316002)(8936002)(50226002)(34290500001)(575784001)(86362001)(5660300001)(68736007)(16586007)(118296001)(72206003)(3846002)(6116002)(53936002)(386003)(105586002)(6486002)(47776003)(66066001)(486006)(25786009)(305945005)(50466002)(44832011)(956004)(2616005)(26005)(107886003)(52116002)(51416003)(7696005)(186003)(476003)(478600001)(2361001)(7736002)(2351001)(48376002)(106356001)(11346002); DIR:OUT; SFP:1101; SCL:1; SRVR:BLUPR0701MB1650; H:ubuntubox.rdc.aquantia.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; Received-SPF: None (protection.outlook.com: aquantia.com does not designate permitted sender hosts) X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; BLUPR0701MB1650; 23:/gS76uuvsSKqXTUZTwmUzmKLmSANfoNJgrMzJvC?= GHA57jSC0cIHsNkV2I5ZWoUGzKi0B5t2lBFTDpI8fVYE5PUn66u9lfjo01mNWvPC6/uKXMuXmY2gHHprMzNWJv3nFYs6H/BoWUO3IABEUiNl6fiVAUe9PTLmf1UDs8/B7wgbXLw+/ZaYX0REDy29RKWJJ59PGf+57bMRsCwB4L/e3dt9I2r0bHhsmaw53y+rM8FbP6QM3DHylM2Le2nfuuRgt5lr+3LCPXPfdFcBbFjwGmvKaL3eA0VS0loullUN++EOkmTQ8TVNyjuznxb+8FhstWdtmhYfjU/Ed7VmNKDk03IvXZuuNc0XH2orajs7C+0O9Ccr5D0lGzW6NtusnXoMUuW/o7a2s6yVXoz9jKW/Asn8VzAhjmY8Vp6lezYm4gZ4oEcCbO/6QWBUVW94AE4UOwMh+XDeccDFCTp+wcD9bdGwskt/gzO6lnLpoPG8Zz22EPtZTazFeStXjaziQ8CMKBgEw3wY2E+twkkQp0wnDtqS5Ds471MJ51Gaa1ZxtblI+cUblEg6tmmlhL1fXbObj9ZSOuCST33/D+OX/hX5AKpb2IAUR/F1q5lU9eMq9DlBS6D1nsR4e0MZUGlEBv99WRuK8WjqL2mU3GX/fl7fZhp+OxZc/8WzgCwHobMe7i/xIaNqPIoNYDXiRmIDzSQr/dIn1WQrgMiipetDGe0GBo5XLR8SXnv78WJKHYkl7q27JWhKCMrfIVYvNzOFUbddIn0IeXJqNEZXkpF6raD8BVC0M2qyEF/4eYFesmcK92SwakveQgTDHt9TwDQqooY/5Cu7TEm/fDPwXfM3CD3jrOKdyRQVpQt5fKvsZDgfabLNgDSWc4pIsrHpG+kfNyln9xu43g6Rz5m6adhC5VuAC2KHdjEu6WBL5SFmmT5lsZGWXe1dysZgyb0GG4Pa8nMKCKYWmNY0W1XZQNqfuc+RZfqgYz5N8rZsxnDRuEr840hyF/gw90OtXWNFp+obe8Cu8Eqd2EZI//QO2UhcTxKypw/XXYx6aWUJyboXHattCBPyN/fmsYoOw2Tt2+rhGSQNfganR+1ld7eLPSl6OOHB5E8NCOCGtTIO/eKxOwOVc0NpDcR0U759DKxOWeanO9zfqLh/QPRJq08a4/CK8Xq9WYmCgHf8fV0vI29OVFAVyZkggERffVYh2EWYWINFEncs/oiPyFH4BrUX0axStoBhdaGaxAlEsjaXbNDWggSovWRwr+TVtAUu/UfwTxG5Y0vKH6FKOWJEi1Uwsh8HRTj1cvf+44NAXTFee10lY/EMu/SGZIEnJTpCkNLbBifFHqw72 X-Microsoft-Antispam-Message-Info: F66vEQMhtsB4nacJxuAvwQY+ca4axuPBvXbL4INRoL5pTSL765KPsh/tzkLCquvIDR4MNhQykF/rDXMR3GQ2q3ZmMGqiQs1w0E5FK4ck4ZkdRWAF5XGk6cPsSnrYnl8IdMVqBUTK6q0pyUqB4qVGAsYJRmY4BAFYIyCvZewhzbEpxvVXbPnrN8uIUVI3CQtQ61UgFDFZ8quUX49JvWL1JD7jSqBhF+LCUYDHicub+a9il1W6sabEfd5kZm0Ku8DU+3BuedFFsWEVekzx8sZQdgolBnugGTifTParCN6MSSxhDiSz2AFloaRD7LT0eVRpGVhoOmRUgYMC91JI+Qh2PDt2YjYdL9gi/Wyq3Z7khjQ= X-Microsoft-Exchange-Diagnostics: 1; BLUPR0701MB1650; 6:0R2LJaOrX2lLV26JwIZpn1WS/sGzhwTyimEa6keM2HiCk7xw00K85LFiSxfTAGdqGhp1gFAFdn7GKPar1whl6U43dkrFP1ibxGsUqLMW0FdMm5Ag8Q74BUmO7TsqovdNqCB1Yurmwr2U1h1QXDZkW1uaDjnBvFqUhv9XgxRnEhQGxMNed5dV+bDtOWSNXmQAjnbfCuJCi9A0uSbYoZW+E3QF/fXahUz2YEixoIuSf2YDMVLKDb2G2UeEOyeZhCTz38GI5IH+L3LftNbgNeDVHoVmoKWaHYnhTx164i8s0HawqvlhqdQY6orBIjTIGkeWXygp6NRRlgn3UwjxumMimAJhqGqGK6ymmJLB/f0afetZn9LnoACJC3b2DRYT10EPEE8UDTPF0HIaugSu5NNlYmz6u5MLphzQrPoafBxbGoYX1FLTRMrqsSiTFE/uzQ8PWjPXic4FmrMyV+p+AJAxEw==; 5:JCTiYY5j8xX3Q9QFNQWr5qhERTFDSjjJzUw9qm8D6cePE9YbjPRhXiBSicn/XIHF0y4aPR1qtehlv7EsR27f3ptYMAAsWpM3fSH2IsJHUAjAV0RHNJMCVs3X62k8SASY5nA649mwa87cKZVyIERa8+8612WxFVrt7sapF6Xgp4M=; 7:4WqHoyIC1daE3uswtffFWagIjDp+xK/tgO22oqhFynCpW/hrHoKHaDpPr/vNXJ9wmMUWtQYwOUZ7zmokuoWQvtWO9y8PyIytccCJffuOijpWaip3eSoeDAcjGbB270bBzh1sFy5cAbkudi1ljkTacciXZvhX3ZgN3fPtJFulTj1HP+xc4Mt/cqY5JhdJBJu3hMlSFSdFJpiDsCBIwqUouj57E2gkR8psBMC/87OuTfaq3HFlIZahfVvqV/3zDLdK SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: aquantia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Sep 2018 10:32:07.9551 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e680d7f6-2619-43f0-4e83-08d625f6d255 X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 83e2e134-991c-4ede-8ced-34d47e38e6b1 X-MS-Exchange-Transport-CrossTenantHeadersStamped: BLUPR0701MB1650 Subject: [dpdk-dev] [PATCH v3 14/22] net/atlantic: promisc and allmulti configuration X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavel Belous Signed-off-by: Igor Russkikh Signed-off-by: Pavel Belous --- drivers/net/atlantic/atl_ethdev.c | 44 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/drivers/net/atlantic/atl_ethdev.c b/drivers/net/atlantic/atl_ethdev.c index bc0cb3da1f66..e71be3e14ca5 100644 --- a/drivers/net/atlantic/atl_ethdev.c +++ b/drivers/net/atlantic/atl_ethdev.c @@ -22,6 +22,10 @@ static int atl_dev_set_link_up(struct rte_eth_dev *dev); static int atl_dev_set_link_down(struct rte_eth_dev *dev); static void atl_dev_close(struct rte_eth_dev *dev); static int atl_dev_reset(struct rte_eth_dev *dev); +static void atl_dev_promiscuous_enable(struct rte_eth_dev *dev); +static void atl_dev_promiscuous_disable(struct rte_eth_dev *dev); +static void atl_dev_allmulticast_enable(struct rte_eth_dev *dev); +static void atl_dev_allmulticast_disable(struct rte_eth_dev *dev); static int atl_dev_link_update(struct rte_eth_dev *dev, int wait); static int atl_dev_xstats_get_names(struct rte_eth_dev *dev __rte_unused, @@ -167,6 +171,12 @@ static const struct eth_dev_ops atl_eth_dev_ops = { .dev_close = atl_dev_close, .dev_reset = atl_dev_reset, + /* PROMISC */ + .promiscuous_enable = atl_dev_promiscuous_enable, + .promiscuous_disable = atl_dev_promiscuous_disable, + .allmulticast_enable = atl_dev_allmulticast_enable, + .allmulticast_disable = atl_dev_allmulticast_disable, + /* Link */ .link_update = atl_dev_link_update, @@ -905,6 +915,40 @@ atl_dev_link_update(struct rte_eth_dev *dev, int wait __rte_unused) return 0; } +static void +atl_dev_promiscuous_enable(struct rte_eth_dev *dev) +{ + struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private); + + hw_atl_rpfl2promiscuous_mode_en_set(hw, true); +} + +static void +atl_dev_promiscuous_disable(struct rte_eth_dev *dev) +{ + struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private); + + hw_atl_rpfl2promiscuous_mode_en_set(hw, false); +} + +static void +atl_dev_allmulticast_enable(struct rte_eth_dev *dev) +{ + struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private); + + hw_atl_rpfl2_accept_all_mc_packets_set(hw, true); +} + +static void +atl_dev_allmulticast_disable(struct rte_eth_dev *dev) +{ + struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private); + + if (dev->data->promiscuous == 1) + return; /* must remain in all_multicast mode */ + + hw_atl_rpfl2_accept_all_mc_packets_set(hw, false); +} /** * It clears the interrupt causes and enables the interrupt. From patchwork Sat Sep 29 10:30:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Russkikh X-Patchwork-Id: 45679 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 2DB721B13E; Sat, 29 Sep 2018 12:32:24 +0200 (CEST) Received: from NAM05-DM3-obe.outbound.protection.outlook.com (mail-eopbgr730047.outbound.protection.outlook.com [40.107.73.47]) by dpdk.org (Postfix) with ESMTP id E775B1B1FE for ; Sat, 29 Sep 2018 12:32:21 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=AQUANTIA1COM.onmicrosoft.com; s=selector1-aquantia-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=pA/IRKT/sU1SN1C1hSpUO0/ZUp9/KCEaaYgrynl/N+g=; b=T/5gHGlOz9ISbvlNmgZJ6mcB7MOVzavsoLcL7o90oNwHIddKG0MJ+UiHpr8YJWeJqLof3ZObXvg7NWCVuySD9bhnzvzPvnwnnT+5JoBvL1fWFbKhLYX5Knhy5Ra3oDLXwSOiLSxCD4jQzsY/i1EcS4NZQvcgYQQl4KTfn1AnCXk= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Igor.Russkikh@aquantia.com; Received: from ubuntubox.rdc.aquantia.com (95.79.108.179) by BLUPR0701MB1650.namprd07.prod.outlook.com (2a01:111:e400:58c6::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1185.22; Sat, 29 Sep 2018 10:32:14 +0000 From: Igor Russkikh To: dev@dpdk.org Cc: pavel.belous@aquantia.com, igor.russkikh@aquantia.com, Pavel Belous Date: Sat, 29 Sep 2018 13:30:29 +0300 Message-Id: <56a8740410d840ac5c83b984dcacb4d70b72d7ed.1538215990.git.igor.russkikh@aquantia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [95.79.108.179] X-ClientProxiedBy: VI1P193CA0009.EURP193.PROD.OUTLOOK.COM (2603:10a6:800:bd::19) To BLUPR0701MB1650.namprd07.prod.outlook.com (2a01:111:e400:58c6::20) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: d9a57a98-2400-42f3-de9a-08d625f6d645 X-Microsoft-Antispam: BCL:0; PCL:0; RULEID:(7020095)(4652040)(8989299)(4534165)(4627221)(201703031133081)(201702281549075)(8990200)(5600074)(711020)(2017052603328)(7153060)(7193020); SRVR:BLUPR0701MB1650; X-Microsoft-Exchange-Diagnostics: 1; BLUPR0701MB1650; 3:3yvbe3p4d4mIw5xcdoYUIqyaXYUm3bhiWP+Pgz4MrYDbrnwWngwZD9D62x0u+dutNb9uHIcsWM2fo1O0Iw1jldyYb2NzlqJhNa9Hsdyu9iYu+dYc5iHEeOYhAGHuPCtmimIonwHS3YpIxYVi+bkgRMY57kZll3ry42FLJYC4Uq7DgI5wkQoJNRneGc+QUmzWgFALGLjiaxOHp9Ujv4HTltK0fiIWYW5RfQVI30VRCE6txE73+N6reXbEr+pBhaKQ; 25:wwYvw5+ej+8iILof5BzBvdHAvVxxss6P0RDuF67VUJSvw2+zJaridu0fPgCuSQu0OfOMWYizypsW62fnjpXryNMCLKnEGe2e5LAmDhCziGYVTR1OquzUUbLrYbIO87fJ8wOzXhG94wYXJZi/NuoIVdvbKBkF7d2BgSarlCtfvOUcXP3aDM3JvvQH353FOBDJs+FzFNFMEBQipJ1ORJai3PRuV/GFFYZGiHn9zE9h5ey+hkSAymqyPvTs6iKzXZ7kOAP+WN/OgpgV0oblvIcWLWuiZR5AmkZSyZdO+B5VHE/7LysaiuaclipUtOQlK89lS4xvZ22diYwRKIjuPJBIeXJg4eM1PUxT9sZ7tdhc+q0=; 31:lNZAaGhfUgJD0uLxZpddJj1vsRdfNqaIQt9piL4Q2qM2MGU+APWXew2AJu+Gd7edaYifckENquApBeyKezrf85UyOp9ar21V66+KnYxqZosFuUa/dlN6LhMUSvR2N2xwm2lIORnm3RtykpgugYLEOcP+nvLv1YlZE+kcfAOQEaMnJ129jkO8FLfIHYLEqal6B03sIHCbPVe6xUJwVJnp3a+1394SNtYw8mVs8QCNG30= X-MS-TrafficTypeDiagnostic: BLUPR0701MB1650: X-Microsoft-Exchange-Diagnostics: 1; BLUPR0701MB1650; 20:rTaFTOAKyQDRH9C92UGWtw84zMcPDKu1bytSvfoJw3GJUZkceG1i7Zal96s/NUllhEwxIJlTK5llNvgeIb9u6PffnwDgGwV/c26uPA46lW5TrDTD2PBgoTBCgPv/GDb6G2aY9qrQVUMoJ56vMQPp4fY5Rfqhq3MMcgDJL83azSdgfF1P9EWeL582P82QlThrPZyeWqeZJBSF2dFIn67HVZWa0F1c2MhAO4gFiIfg8fyvM8w/4TUV8qT/r+cIsZ+vs51NB/TIsKObsgLPuCJEQzewCa0pIp5bsbVQK+O7jsv9zn3eRDqxWabxDCGOnkqqWZfoU0JH0JyMKYjDiMVSxwgaVwBAzUEOeinJ07sUa4tMGqTgS2WViFMGwDySNyiAwV0kyt1DCQ7wM9n+tloIpYgGN7cbMQ7M9+RkQXjzBk9FxcLXhhOix2WJsWi6a2R1Nq2bKl9VWLgvcDUILTJCgJt4liu4G2rpdmXRO5ssBVPCZkCJdU4NNOXuBuRDFPas; 4:Fd4l0DLKi+EfInr2BkszOSMYHUUHvnbs/hHHhbzaUQOM0uT5vbq1Y7PrewZBTpzfr9vCN29+17rT5rP5Qcs103BSR9Htx9cWMYygwlq0x2K7/6SEbAFE3C/ljr8V2BRrvvuM+mMgALBl4PpD7GNViUu8yBMbXwGHcEob75nc8mJFiVF2G1M1Zvk4Mo53cgcasMw3z5DR1F9A/JckAbDqF0ETLWbaxxTl99omm9SW0Tnbhd+lBUVHU/Lsl+Y5I+3wszBJJsG821gImcuOYtteuA== X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-MS-Exchange-SenderADCheck: 1 X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(6040522)(2401047)(8121501046)(5005006)(10201501046)(3002001)(93006095)(93001095)(3231355)(944501410)(52105095)(149066)(150057)(6041310)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123558120)(20161123564045)(20161123562045)(20161123560045)(201708071742011)(7699051); SRVR:BLUPR0701MB1650; BCL:0; PCL:0; RULEID:; SRVR:BLUPR0701MB1650; X-Forefront-PRVS: 0810818DA0 X-Forefront-Antispam-Report: SFV:NSPM; SFS:(10009020)(346002)(136003)(396003)(376002)(39850400004)(366004)(189003)(199004)(16526019)(14444005)(446003)(76176011)(2906002)(6916009)(6666003)(97736004)(8676002)(81166006)(81156014)(36756003)(4326008)(316002)(8936002)(50226002)(34290500001)(575784001)(86362001)(5660300001)(68736007)(16586007)(118296001)(72206003)(3846002)(6116002)(53936002)(386003)(105586002)(6486002)(47776003)(66066001)(486006)(25786009)(305945005)(50466002)(44832011)(956004)(2616005)(26005)(107886003)(52116002)(51416003)(7696005)(186003)(476003)(478600001)(2361001)(7736002)(2351001)(48376002)(106356001)(11346002)(309714004); DIR:OUT; SFP:1101; SCL:1; SRVR:BLUPR0701MB1650; H:ubuntubox.rdc.aquantia.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; Received-SPF: None (protection.outlook.com: aquantia.com does not designate permitted sender hosts) X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; BLUPR0701MB1650; 23:Kn66gzI7ULbGbVUiSiVm/ZXlIQWUZU7c0z11Ucx?= USB3zLRJT9XDNUK+vhP3r27twzhZWcy6aXIoyAG5tw6FpYxhiS/gYZYep70AiY0UlcHD2xoWuA9JsAR3AQ3FsHdD7Is5HUWfHFQ+AiovbIJXz+scQ59yI4evMpbADp9YwhnHoZh9/vMwdN8fodKLLJ6YsQNDxHySX8Dqy9Bi2wUN9qbjHPtMIOfd0yVj4PKg/W+P9bgfLCmxgUi65WjpFuJcmSf2Vun4Jp3mSyzmcoLRsDpBMkGui7xsWq5wgGQf0r20CRYEAXmZwG5C3Ev13wjvKoCco5udCO11aqldnCAW5/xTwSb9ERXWPkDgP0Q0lvvxQEr6EyBc11HTvSY91ev45fxKBUyUiuvYyNzX5smgN1zj4rv6h1vZUGtZbFQC+zqjMD9nSgB2uUx2exU5VHKVazLs7uAItz7dUdTcqbXw0BUMxmCjoFpe9N3XpTUbnEqVKgvDAmSfbusmhZwiS7/VsjMiMmffLLMZ1CCuH+5Zhs/Ee3+od+Dbg8b+NLHjnLg+DV9fcxqngirC7Xq5JUwtuRkjMCxkyIISniw1+rR6jsofgHjZXsm+ZDm/RwC/iOr0+P85WxF6xm3F1h854ZheTWJgAW7EkOYURiEsGojDSnhz6/wKsyc14OKYhDpaNxK5ENTT/AAu4SkzXW/inBFB5+vz0i1aq+V+mRKbLnm6Dwl1Se/AC4uOT8sOFxDT1cDZy2PxuWi3ewZn6Wx/JeAdKRkDEn3I2M+BnJw/UweIdCF88X4cBc9GHLL2C135fXO+cVS6NK1FFa4CJZydh5Rb9fO7dsyeodgKPqpCRDiXZ1cJDeoHxAE+8u/lZDJ0PhO6vbA7Rw4qsekiMN66Mg98Zutls6EOV+6O9aQY1QvPDIV/LHzGg4FJRWtld5IP5m3PRJSK0If9i9GGeJzljrU63oEAzs5MiOLwm3wp+XJoQaIrDksvMkeUXTvzohi1zhNrLFpFF+tgA8Gr6khXKsPd1qkvUj3f3OGgl+gICmSyx2+I0kLJbfLDiEA0azqa2Dbu2YzptTQewgT0BtXiuqbBFzeJLkQ6C+m3LswNtnbjqGLYJ3mAMt2dwM4mhOAV5Lgjf8L41qZKn01bmnV8e0HRM394isA+u8EaUj3E0//Nd9YSutlInxRCrOFrBd+w8NA7FMy+3bIy7zDoT4l+PgUDTo4TAaQQvm7mBJK2ibj+NcgjYaK6VmaGuKw5G03FL8BgyzPjEhcn+n+weN58V73lHPOaBqHlk6uMiJD0pj6XJYIMntlqfag526KVxFfh9QG4BXteICEK+5kQDI1tq5Jy8gzL0I4ImPhOYkxKGkmxyLg== X-Microsoft-Antispam-Message-Info: MSlAycQfCt9B+1uoB6doWaCpy2wIlIQuaARYliJP9ahIN2MVbgll2fwaL7W3wDLpOV7Tn5HWjoGXrNa7ZC6oRlYSCHiyMgkV4y3T+yjchuzyPjOM/E3aznAWt8fa1w0hA/ZCQ2m5KFeT6Bst8wtJCcODwqWaYd6+O9KeSqkeiEskRhMPAsyYcGEFy8vI35Lsm4rTR9JYiSPpxBZF9FA1OswuXWh3lzyE2bjgIQQSXpN1ff5Q7SulaFnGwmL0M1frI/dRL7u3FaVSNyZWh/eRThG8srcxO5h1Oes7eFhfnwOa7NQD2wuGmjn3nnm9oeCn+pN4ml8h+TknQpcGojp50Rv7I0giBqwy4nNLZ3OcYO4= X-Microsoft-Exchange-Diagnostics: 1; BLUPR0701MB1650; 6:xvZQoP0+52ihFcdXK4BWsChJvsBUW77NjvzL1+MaO2LBRr6AEXTkCyH8BkQMfiVG7qEzgKsgJbUikuUH/ymvkYjJbF8eXQrjmUCGT7koHBOJKJB97VsJlfu64Cw08bcUfzEJMdXb99PDwV+SizPygMAHWrTIiri1ogRAJMTa+8Yo2a91x5pAQMN6TPBXh8KKpxAcr2bsaKdBjLuq+VwG3oZbAZQCUa612X5VhPJj9QJbnHOJwdkMkGRsC5Wjdk/cIr9Xbvj1jDMvnxc6ZkgVnAzYTz1HUNd5ne8kTCoVioGMwfcbDqOVduAFya8Xe3VXyaD5TxBVlu/DwZDbkOkEYenUAajW2yh8YIeHW7spF9Fas9Z6LeQdK9gJDBIpMk1jJbpcYg2ifQPCnr9G8C9HklUPIIeYZEqTlr3+xuas1MP+svRWkAOTSNhxR09Wn19IGl/+KSfFqytqsd/a1UkPsg==; 5:FrL3VpBOBZX5dwQT70kFYVUv1jvokQH30g5xXlOa8EIN3+EPkJwT47DIUAH6gjNmI/cHBlqEwM0j+L/aqm/EFqF5uKhXQNkYVQuRTpDduWtmOv7I3pEG4kLgqeoKPlKx3s5P0CjdT7D2zs+nlbrC8xTN8Z/Ufw2wFocTDBAuxlo=; 7:8rcdoIlb2n9HEgyyXMQG9bSsCCM0LQsszTqZIJnkyTi+i6igrOiMwNi5eQwT98r6vZo2iED4PReEG6VWsGMiyHKR1Y4FnxPbOGYwZ6hhu5dxvfZTxe9vO3apBsgfTbk1m0Py/eLJCHyowkiImCI/FaOR9a8KPmUOAGPVYYlqNskoYhtMv4L6cAyyGNezBML95Z0vArfJapWVzAUjlldXKMmcZ+ctV6yPSngZHSpK69PqDgCkP3tXotV/bCr6wbri SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: aquantia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Sep 2018 10:32:14.5961 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d9a57a98-2400-42f3-de9a-08d625f6d645 X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 83e2e134-991c-4ede-8ced-34d47e38e6b1 X-MS-Exchange-Transport-CrossTenantHeadersStamped: BLUPR0701MB1650 Subject: [dpdk-dev] [PATCH v3 15/22] net/atlantic: RSS and RETA manipulation API X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Signed-off-by: Igor Russkikh Signed-off-by: Pavel Belous --- drivers/net/atlantic/atl_ethdev.c | 107 ++++++++++++++++++++++++++++++++++++++ drivers/net/atlantic/atl_ethdev.h | 14 +++++ drivers/net/atlantic/atl_rxtx.c | 5 ++ 3 files changed, 126 insertions(+) diff --git a/drivers/net/atlantic/atl_ethdev.c b/drivers/net/atlantic/atl_ethdev.c index e71be3e14ca5..51e933a3559a 100644 --- a/drivers/net/atlantic/atl_ethdev.c +++ b/drivers/net/atlantic/atl_ethdev.c @@ -64,6 +64,19 @@ static int atl_dev_interrupt_action(struct rte_eth_dev *dev, struct rte_intr_handle *handle); static void atl_dev_interrupt_handler(void *param); +/* RSS */ +static int atl_reta_update(struct rte_eth_dev *dev, + struct rte_eth_rss_reta_entry64 *reta_conf, + uint16_t reta_size); +static int atl_reta_query(struct rte_eth_dev *dev, + struct rte_eth_rss_reta_entry64 *reta_conf, + uint16_t reta_size); +static int atl_rss_hash_update(struct rte_eth_dev *dev, + struct rte_eth_rss_conf *rss_conf); +static int atl_rss_hash_conf_get(struct rte_eth_dev *dev, + struct rte_eth_rss_conf *rss_conf); + + static int eth_atl_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, struct rte_pci_device *pci_dev); static int eth_atl_pci_remove(struct rte_pci_device *pci_dev); @@ -213,6 +226,11 @@ static const struct eth_dev_ops atl_eth_dev_ops = { .rxq_info_get = atl_rxq_info_get, .txq_info_get = atl_txq_info_get, + + .reta_update = atl_reta_update, + .reta_query = atl_reta_query, + .rss_hash_update = atl_rss_hash_update, + .rss_hash_conf_get = atl_rss_hash_conf_get, }; @@ -330,12 +348,18 @@ eth_atl_dev_init(struct rte_eth_dev *eth_dev) /* Hardware configuration - hardcode */ adapter->hw_cfg.is_lro = false; adapter->hw_cfg.wol = false; + adapter->hw_cfg.is_rss = false; + adapter->hw_cfg.num_rss_queues = HW_ATL_B0_RSS_MAX; + adapter->hw_cfg.link_speed_msk = AQ_NIC_RATE_10G | AQ_NIC_RATE_5G | AQ_NIC_RATE_2G5 | AQ_NIC_RATE_1G | AQ_NIC_RATE_100M; + adapter->hw_cfg.aq_rss.indirection_table_size = + HW_ATL_B0_RSS_REDIRECTION_MAX; + hw->aq_nic_cfg = &adapter->hw_cfg; /* disable interrupt */ @@ -840,6 +864,10 @@ atl_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) dev_info->rx_desc_lim = rx_desc_lim; dev_info->tx_desc_lim = tx_desc_lim; + dev_info->hash_key_size = HW_ATL_B0_RSS_HASHKEY_BITS / 8; + dev_info->reta_size = HW_ATL_B0_RSS_REDIRECTION_MAX; + dev_info->flow_type_rss_offloads = ATL_RSS_OFFLOAD_ALL; + dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G; dev_info->speed_capa |= ETH_LINK_SPEED_100M; dev_info->speed_capa |= ETH_LINK_SPEED_2_5G; @@ -1091,6 +1119,85 @@ atl_dev_interrupt_handler(void *param) atl_dev_interrupt_action(dev, dev->intr_handle); } +static int +atl_reta_update(struct rte_eth_dev *dev, + struct rte_eth_rss_reta_entry64 *reta_conf, + uint16_t reta_size) +{ + int i; + struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct aq_hw_cfg_s *cf = ATL_DEV_PRIVATE_TO_CFG(dev->data->dev_private); + + for (i = 0; i < reta_size && i < cf->aq_rss.indirection_table_size; i++) + cf->aq_rss.indirection_table[i] = min(reta_conf->reta[i], + dev->data->nb_rx_queues - 1); + + hw_atl_b0_hw_rss_set(hw, &cf->aq_rss); + return 0; +} + +static int +atl_reta_query(struct rte_eth_dev *dev, + struct rte_eth_rss_reta_entry64 *reta_conf, + uint16_t reta_size) +{ + int i; + struct aq_hw_cfg_s *cf = ATL_DEV_PRIVATE_TO_CFG(dev->data->dev_private); + + for (i = 0; i < reta_size && i < cf->aq_rss.indirection_table_size; i++) + reta_conf->reta[i] = cf->aq_rss.indirection_table[i]; + reta_conf->mask = ~0U; + return 0; +} + +static int +atl_rss_hash_update(struct rte_eth_dev *dev, + struct rte_eth_rss_conf *rss_conf) +{ + struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct aq_hw_cfg_s *cfg = + ATL_DEV_PRIVATE_TO_CFG(dev->data->dev_private); + static u8 def_rss_key[40] = { + 0x1e, 0xad, 0x71, 0x87, 0x65, 0xfc, 0x26, 0x7d, + 0x0d, 0x45, 0x67, 0x74, 0xcd, 0x06, 0x1a, 0x18, + 0xb6, 0xc1, 0xf0, 0xc7, 0xbb, 0x18, 0xbe, 0xf8, + 0x19, 0x13, 0x4b, 0xa9, 0xd0, 0x3e, 0xfe, 0x70, + 0x25, 0x03, 0xab, 0x50, 0x6a, 0x8b, 0x82, 0x0c + }; + + cfg->is_rss = !!rss_conf->rss_hf; + if (rss_conf->rss_key) { + memcpy(cfg->aq_rss.hash_secret_key, rss_conf->rss_key, + rss_conf->rss_key_len); + cfg->aq_rss.hash_secret_key_size = rss_conf->rss_key_len; + } else { + memcpy(cfg->aq_rss.hash_secret_key, def_rss_key, + sizeof(def_rss_key)); + cfg->aq_rss.hash_secret_key_size = sizeof(def_rss_key); + } + + hw_atl_b0_hw_rss_set(hw, &cfg->aq_rss); + hw_atl_b0_hw_rss_hash_set(hw, &cfg->aq_rss); + return 0; +} + +static int +atl_rss_hash_conf_get(struct rte_eth_dev *dev, + struct rte_eth_rss_conf *rss_conf) +{ + struct aq_hw_cfg_s *cfg = + ATL_DEV_PRIVATE_TO_CFG(dev->data->dev_private); + + rss_conf->rss_hf = cfg->is_rss ? ATL_RSS_OFFLOAD_ALL : 0; + if (rss_conf->rss_key) { + rss_conf->rss_key_len = cfg->aq_rss.hash_secret_key_size; + memcpy(rss_conf->rss_key, cfg->aq_rss.hash_secret_key, + rss_conf->rss_key_len); + } + + return 0; +} + RTE_PMD_REGISTER_PCI(net_atlantic, rte_atl_pmd); RTE_PMD_REGISTER_PCI_TABLE(net_atlantic, pci_id_atl_map); RTE_PMD_REGISTER_KMOD_DEP(net_atlantic, "* igb_uio | uio_pci_generic"); diff --git a/drivers/net/atlantic/atl_ethdev.h b/drivers/net/atlantic/atl_ethdev.h index 17c8505e4707..69612a016089 100644 --- a/drivers/net/atlantic/atl_ethdev.h +++ b/drivers/net/atlantic/atl_ethdev.h @@ -9,6 +9,17 @@ #include "atl_types.h" #include "hw_atl/hw_atl_utils.h" +#define ATL_RSS_OFFLOAD_ALL ( \ + ETH_RSS_IPV4 | \ + ETH_RSS_NONFRAG_IPV4_TCP | \ + ETH_RSS_NONFRAG_IPV4_UDP | \ + ETH_RSS_IPV6 | \ + ETH_RSS_NONFRAG_IPV6_TCP | \ + ETH_RSS_NONFRAG_IPV6_UDP | \ + ETH_RSS_IPV6_EX | \ + ETH_RSS_IPV6_TCP_EX | \ + ETH_RSS_IPV6_UDP_EX) + #define ATL_DEV_PRIVATE_TO_HW(adapter) \ (&((struct atl_adapter *)adapter)->hw) @@ -18,6 +29,9 @@ #define ATL_DEV_PRIVATE_TO_INTR(adapter) \ (&((struct atl_adapter *)adapter)->intr) +#define ATL_DEV_PRIVATE_TO_CFG(adapter) \ + (&((struct atl_adapter *)adapter)->hw_cfg) + #define ATL_FLAG_NEED_LINK_UPDATE (uint32_t)(1 << 0) #define ATL_FLAG_NEED_LINK_CONFIG (uint32_t)(4 << 0) diff --git a/drivers/net/atlantic/atl_rxtx.c b/drivers/net/atlantic/atl_rxtx.c index ebb606fbcd7c..cac518c1a780 100644 --- a/drivers/net/atlantic/atl_rxtx.c +++ b/drivers/net/atlantic/atl_rxtx.c @@ -321,6 +321,7 @@ int atl_rx_init(struct rte_eth_dev *eth_dev) { struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); + struct aq_rss_parameters *rss_params = &hw->aq_nic_cfg->aq_rss; struct atl_rx_queue *rxq; uint64_t base_addr = 0; int i = 0; @@ -358,6 +359,10 @@ atl_rx_init(struct rte_eth_dev *eth_dev) rxq->port_id); } + for (i = rss_params->indirection_table_size; i--;) + rss_params->indirection_table[i] = i & + (eth_dev->data->nb_rx_queues - 1); + hw_atl_b0_hw_rss_set(hw, rss_params); return err; } From patchwork Sat Sep 29 10:30:30 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Russkikh X-Patchwork-Id: 45680 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id EDF3A1B125; Sat, 29 Sep 2018 12:32:29 +0200 (CEST) Received: from NAM05-DM3-obe.outbound.protection.outlook.com (mail-eopbgr730076.outbound.protection.outlook.com [40.107.73.76]) by dpdk.org (Postfix) with ESMTP id 726D21B125 for ; Sat, 29 Sep 2018 12:32:28 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=AQUANTIA1COM.onmicrosoft.com; s=selector1-aquantia-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=GOjsrWluW/fNOTk8Mnkj7005/UI+HbBjLXKrkK2XACE=; b=MG7/Yxw2MSU7mav8pVpSYQjHgcFF67ybRtY1sYjVkVsB6ZV54UVbPHtrbYDnxpVgAWclY/mDbqnpTB8oAl8GELNFn+52fQdK3lsdMWbNl9TsuuoTLNSurwmQzqJzWei7Z5JBCwJHaRo9Ss3yDAADYpJttTAG/x1mDpbMU2CUudM= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Igor.Russkikh@aquantia.com; Received: from ubuntubox.rdc.aquantia.com (95.79.108.179) by BLUPR0701MB1650.namprd07.prod.outlook.com (2a01:111:e400:58c6::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1185.22; Sat, 29 Sep 2018 10:32:21 +0000 From: Igor Russkikh To: dev@dpdk.org Cc: pavel.belous@aquantia.com, igor.russkikh@aquantia.com, Pavel Belous Date: Sat, 29 Sep 2018 13:30:30 +0300 Message-Id: <78cfcb87a404faa319b558820d6a0f80294c8464.1538215990.git.igor.russkikh@aquantia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [95.79.108.179] X-ClientProxiedBy: VI1P193CA0009.EURP193.PROD.OUTLOOK.COM (2603:10a6:800:bd::19) To BLUPR0701MB1650.namprd07.prod.outlook.com (2a01:111:e400:58c6::20) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: d0d5cf48-fd69-4a35-3374-08d625f6da3b X-Microsoft-Antispam: BCL:0; PCL:0; RULEID:(7020095)(4652040)(8989299)(4534165)(4627221)(201703031133081)(201702281549075)(8990200)(5600074)(711020)(2017052603328)(7153060)(7193020); SRVR:BLUPR0701MB1650; X-Microsoft-Exchange-Diagnostics: 1; BLUPR0701MB1650; 3:IjkX3vz0T2Je+3abW2TJG3QxvwmTwc5C4eOnZcma8Yh0Xoq5k0+a5bIbAAJWQV4OqstRv/Z7XpvKloPSTNQTnmbrWXcO9bxGQZXiSpWuJL8zURmd2l2kkY88col9dDoRu7ab4VX9XffF9Hw2pfAbwCaluceW+0ipzLDLutu+OaN7X1IzYY+Eu3ElR9F5irO8kcK+mTR/u4mk4v133MB6OG/y4+ko/wYpETPHkhGz7n2hfkXumQA1VPjrEZUsMQAA; 25:E+ezU4wDmqmTbNeHNDxe9oD+k3cREKt/TrQK2Cj2zWeKWqdqtuXkYkfTy09X3YAY+1h/h8yz+jwcTMpQAFInEE4bExc2YLjGv/Q/877v8wSIZm4AIdW4CG1/qKaRM2++Csdw/x3qgI3/fGE5Dt6QiFX4jyhKQ/czxITHfOUtS9T8N7XoEUB5Vf5jg2zUgAYeQHXW2uVT6bo+/n8Qv/4YbWEPfvet64UD5Wu0mpgMUYjl9BiWpJx2DevhBSiX/j8M74ed/NZDVtS8bJZcS8cK50YrR7D24VmIOnUQrSfunmeBPUMZgMAXw3ibgcH9dLcu/xvDHpkGgL57hm4B4QC//g4s/kL7OWnJaCKaOjJf+c4=; 31:bwp+VaeeO/rvAsOQqUHJF+aUKppFn4ZRpGRt1pQIDllzAp6pi6I8WpqZNwj2gMLe6vPSTeJVudfv1f/XAPtsUlBOhb7OO+FFJ7kSzaS+EhtKMnLV4fp25EMMBIR96UimdygWk+Tlm/AWPc06QEDtLPBlG88vPzhPN+QMcsrnguU/GmLiMGSkb2DBFm7KZwIZCd3Q0YpkWNwmErFF3GDVvxi7EBrpoK3zb03E9xePl7Y= X-MS-TrafficTypeDiagnostic: BLUPR0701MB1650: X-Microsoft-Exchange-Diagnostics: 1; BLUPR0701MB1650; 20:dkzGbu1bb0hsYezEB3rc359xBzTTaIKKxlX06iu1WNn0kwyVJVoXBGE6mGjnIJ3dDfyHB6FqlxVvOKvVTD49t5IgfKsU8bHVwfRXfMT/yrO5j8DiU/k8E+6UgQy62dbe6rAS9k2/F6X4gGpH07dpo+6T+kHuinxBdLO6A7vTdBBnPDRLHMtUh8qex5g5YsTGABDevsLgH1qc7973LjpM/BbAZenwuK7QkH8O39JNkBjXaPWlc81OMrpQwTbtqS6RQ3i3q/XJouHt70l/nhke90RSwm/U+VJruKL7PlYr7YSXBdKFvPrvb2GBEHl9CDyy6EN5mzFrdTbxQdYaC5jF+ckyF3xgkvEkssFKe4Jki9jjFznN6BlDL0xf1hXNpjslfB4qSpcP7UJEG9vViTChu9ztjGcbr3I6lSByhVZDjar7gnNBXUaILQN2LAHyyaN959X1AwlV7hrBzwPWPIFfbQ8XNzs/fkUeClWvKt6HUsUF+iQJmoCBF4EZBDi/HCIs; 4:0+a8Kp6F4UPuBDQFcyMLuQLccJNK/Mqk+rziZKJ1qgcev0UyMAll2+bHdandDWVU19mNzX1q0Mwt6FJsYNviVcrFNpgn6IYQlTNYYE+PiK+CdbMfyE2pVKR4C/LdzXe5gT9hosox2Z6KUOBJdgNLDb/sFA9cXrwjxqo87Kl1tlwhTMUTUmbLRGuzypX0UVPUve9W4enY2sWNc1V/rq5QPnk7YsL0uUgzxRfzpPEJfitfCC/LPgm5VGETIovnmIpguugdrndFoQAl25SoHUIYNA== X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-MS-Exchange-SenderADCheck: 1 X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(6040522)(2401047)(8121501046)(5005006)(10201501046)(3002001)(93006095)(93001095)(3231355)(944501410)(52105095)(149066)(150057)(6041310)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123558120)(20161123564045)(20161123562045)(20161123560045)(201708071742011)(7699051); SRVR:BLUPR0701MB1650; BCL:0; PCL:0; RULEID:; SRVR:BLUPR0701MB1650; X-Forefront-PRVS: 0810818DA0 X-Forefront-Antispam-Report: SFV:NSPM; SFS:(10009020)(346002)(136003)(396003)(376002)(39850400004)(366004)(189003)(199004)(16526019)(14444005)(446003)(76176011)(2906002)(6916009)(6666003)(97736004)(8676002)(81166006)(81156014)(36756003)(4326008)(316002)(8936002)(50226002)(34290500001)(86362001)(5660300001)(68736007)(16586007)(118296001)(72206003)(3846002)(6116002)(53936002)(386003)(105586002)(6486002)(47776003)(66066001)(486006)(25786009)(305945005)(50466002)(44832011)(956004)(2616005)(26005)(107886003)(52116002)(51416003)(7696005)(186003)(476003)(478600001)(2361001)(7736002)(2351001)(48376002)(106356001)(11346002); DIR:OUT; SFP:1101; SCL:1; SRVR:BLUPR0701MB1650; H:ubuntubox.rdc.aquantia.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; Received-SPF: None (protection.outlook.com: aquantia.com does not designate permitted sender hosts) X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; BLUPR0701MB1650; 23:c0vgQvNfbgRRPQ9vs2qIfTDRTL4HyiwyhEDYOFi?= 1W16Wge2D0kR345iHSYJNREnMUtxG/scmYGp1h2aoMrvhzSNhDstOSg07B5hyxSuvjvW9BCCMR/+rBHAQu/7Zyo6GqmNHruCutDbaEzRyPl6PpPdvo7V325jsndY/ua7ZVjmV4iJisSfFviu89OhvflldQxNYS8xfuOJIhwBXWfvLOOJkEwreHk5LsM+a9TcOgP+F6nOmcAabbMGNHo5GSFoAkKzHpBOsEEwT1tn8+u4O2ORspn1b2BZSHcMwqfkFJZREnoQ9DabfSVEqCGUKY5OdirYUvtQ2I7ymgSoKzb2X8rSZCVSrTzPBPkkIyKLWFHvdqKReqjT4Oy+9UVw0c8MHAUxcSg+Dk7Qwplu2+wbVd9DuSmpavpc1vhCtjxqkV7UBIBvI6QSdYdTSOtrla8QE05n+DIYWMjDJnyy+GxDz0MSQ42+askIbckOuXQxJWh0WxfhrMVkSTkJN/3DqF7TVYcR9HifewQY0279vxOJO/dkElsaVj4SkMpkPWx+nxL1ckjHLQs/dPW+f+AOTOh8AalXfCUjOhc7b7k1tFXQG2ZtxlCA4M6Ts7WHyBbplbD86iTjAmB2OvcgSUADogpdfS7JRQTfd6voautGvaONzOdxyvhUuAzRK4l2T2W6XdAePy53t64eHrWc6ZZl/iulD2D3DP+ukFaRr86Q/CXudDSNJXC1ZmweH+CZwCz7r6QD8zeaiASSjh9Q3ijsFKn3691f0aqmstDcX2LZf1LhmXa+E41fWujW3EkErfGRgTFjWwWGZ5Gai6jJNE79VTIIMDY0f0EbOLXRGOVdhLLxj2i+L60bg0IIOSUoD5O5mcP6LA2F/jbkrEqlMQjVnAfWJ8YlJpyvGjBxqecT3NBCEaBBx3QlPNKc4knyHq8iIxLxvO0rj0fuHhUD5Ibukg7/pJPid+yDCRHds8ATJx6vMzYnI4QWTE6EMq0lpU82190R2w7cPlewwHZGgo5GJkx0xty1RgN2c1jY8VS8B3cvRJHnFaeO9C03i8cNbPBWjFKXMV8YclMU9UL4wpf+uU1Wc0Dk8/jK3hivPIEQahNuTV7cLkUKJSDjMawvaZ4Mk26ajBmIAq61YH3YbB4k4t0eAV5IeLGh6W6wUx7EhJt6oFSC9VtTJp9dSzS7Rh+th92zJaGCU0i/0j5h3nZeFw7ZIFqWOfb/J8MK9Z3mMZtq9XzeO2WuRLZDGhceJBy2YhVC5JKrrKRLSgTutlrnaQ9+LNlrAF54kcbwL4E2xVLyRxkeE9wL8AR5KaX61l6MlKC8= X-Microsoft-Antispam-Message-Info: 0g0Fuvskz2z0mRAPr1cEIp4CxAuJ1WDKLV4vw3AYwyvNpbIczQOgXo5LEuALlhe62T/xyiAJczXPaXpOYctX+SzvN7KZdZwWsCLU2wZN9NHyIFtfWjCoXDLvjT8tf+EE2Jn0+KtTOz3xYhdgSkO/NVLjyiFC1mT0z5ljB8fcJ1uSRA8nGKDvnM3gONPRw6DmTJqGG8eqRtrqD5ou48Q3gK1OGqGRPQIB5Ooju0WLr7Sk1hEawXz27W3HcGD6fvbOM0YhOz+8frmAvYJ0mkIdIhKH4kiKUO9KSaCwUoH844OCF93AM//JzBrQX0rWCtYPnIwzx1SuQxeB5dRAtxiou3h0ChvT7SaZTPnttLivTK4= X-Microsoft-Exchange-Diagnostics: 1; BLUPR0701MB1650; 6:U35ND3mrIJhA2KEcK/wEQPHQvnczGdFsJUTeWllw+9QnVjhtkDMUD9eNnzGYrzFyIc6vooE3gOXnj6HCnIH+wc5jY9jTMf6NYNGfB0/73Cd+piGKaKG+OxQNgyqTpt26N97eIKJiK0JGK3JZoX82wKBKjIJV4os08EMbEoW33wL26fNh4AVLt30Y+wFYf+Rxr/Mm/vqAxAp263eZJ3crewQNlItu8sB2YadqJRRn3uZkC3oFVSghPS4xs543i/RIkkG575vg/tbuLK1ulFfnRRF2kk3n1ngkcWBafJuSmVjyWPkbzARCg9UhRNX7x0yLWB7YQqhYlxhciFWG/RFXa6ICEF7WY2/AAKaFnuDezX0p11kqL6GhjbUtqRM0ZcIdpMpibxJ4jO0eY60KXNSQHxiGkIBLJV8p426BDjhhrTwetSChQzkhwMRH7IAJpKq5J9JAPHnV/NTBfCUZu2iggw==; 5:AjbogMdX6TjwQJC2c9ydHbENhe0U+nuqPqgxfxJr7wYbzrzp78AXTZMC9SQDC2S2JpGajVzCqYNolv8yWaaTEvIvRvM4D6zv8YrOrRL8YKnT734sSC+MlbObANM0HQ8rmW02SGONuoveG/0v39mDQTcwsZ8kIdmLT8QF5snlDjM=; 7:8mKynijT5fmobgztybR6uf3MERPrJ6DdT5tHuDR7JTW9tydhbyBCZIRdJFrPPQT1x+ZPaZ+Wa1jpaPG86EFV4VqFihPCFNd5p2KEA7AAZ+3XzZagXMPAUdph7OWhzZrcc7cJJpL+iJZOWuG7K/ZmebjWqlSGbwIQ+mTDgFHP6aar26bMc4W7TuqSjBPM9J4IeqAnEyBcqAmvNT2ubn5zMl0Fcs1tmt4XuPk6j6311xY+La95tXBnzH2CUP6iIa94 SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: aquantia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Sep 2018 10:32:21.2058 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d0d5cf48-fd69-4a35-3374-08d625f6da3b X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 83e2e134-991c-4ede-8ced-34d47e38e6b1 X-MS-Exchange-Transport-CrossTenantHeadersStamped: BLUPR0701MB1650 Subject: [dpdk-dev] [PATCH v3 16/22] net/atlantic: flow control configuration X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavel Belous Signed-off-by: Igor Russkikh Signed-off-by: Pavel Belous --- drivers/net/atlantic/atl_ethdev.c | 54 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/drivers/net/atlantic/atl_ethdev.c b/drivers/net/atlantic/atl_ethdev.c index 51e933a3559a..243020dc00a9 100644 --- a/drivers/net/atlantic/atl_ethdev.c +++ b/drivers/net/atlantic/atl_ethdev.c @@ -54,6 +54,12 @@ static void atl_dev_info_get(struct rte_eth_dev *dev, static const uint32_t *atl_dev_supported_ptypes_get(struct rte_eth_dev *dev); +/* Flow control */ +static int atl_flow_ctrl_get(struct rte_eth_dev *dev, + struct rte_eth_fc_conf *fc_conf); +static int atl_flow_ctrl_set(struct rte_eth_dev *dev, + struct rte_eth_fc_conf *fc_conf); + static void atl_dev_link_status_print(struct rte_eth_dev *dev); /* Interrupts */ @@ -224,6 +230,10 @@ static const struct eth_dev_ops atl_eth_dev_ops = { .rx_descriptor_status = atl_dev_rx_descriptor_status, .tx_descriptor_status = atl_dev_tx_descriptor_status, + /* Flow Control */ + .flow_ctrl_get = atl_flow_ctrl_get, + .flow_ctrl_set = atl_flow_ctrl_set, + .rxq_info_get = atl_rxq_info_get, .txq_info_get = atl_txq_info_get, @@ -357,6 +367,7 @@ eth_atl_dev_init(struct rte_eth_dev *eth_dev) AQ_NIC_RATE_1G | AQ_NIC_RATE_100M; + adapter->hw_cfg.flow_control = (AQ_NIC_FC_RX | AQ_NIC_FC_TX); adapter->hw_cfg.aq_rss.indirection_table_size = HW_ATL_B0_RSS_REDIRECTION_MAX; @@ -1119,6 +1130,49 @@ atl_dev_interrupt_handler(void *param) atl_dev_interrupt_action(dev, dev->intr_handle); } + +static int +atl_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) +{ + struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private); + + if (hw->aq_nic_cfg->flow_control == AQ_NIC_FC_OFF) + fc_conf->mode = RTE_FC_NONE; + else if (hw->aq_nic_cfg->flow_control & (AQ_NIC_FC_RX | AQ_NIC_FC_TX)) + fc_conf->mode = RTE_FC_FULL; + else if (hw->aq_nic_cfg->flow_control & AQ_NIC_FC_RX) + fc_conf->mode = RTE_FC_RX_PAUSE; + else if (hw->aq_nic_cfg->flow_control & AQ_NIC_FC_RX) + fc_conf->mode = RTE_FC_TX_PAUSE; + + return 0; +} + +static int +atl_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) +{ + struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private); + uint32_t old_flow_control = hw->aq_nic_cfg->flow_control; + + + if (hw->aq_fw_ops->set_flow_control == NULL) + return -ENOTSUP; + + if (fc_conf->mode == RTE_FC_NONE) + hw->aq_nic_cfg->flow_control = AQ_NIC_FC_OFF; + else if (fc_conf->mode == RTE_FC_RX_PAUSE) + hw->aq_nic_cfg->flow_control = AQ_NIC_FC_RX; + else if (fc_conf->mode == RTE_FC_TX_PAUSE) + hw->aq_nic_cfg->flow_control = AQ_NIC_FC_TX; + else if (fc_conf->mode == RTE_FC_FULL) + hw->aq_nic_cfg->flow_control = (AQ_NIC_FC_RX | AQ_NIC_FC_TX); + + if (old_flow_control != hw->aq_nic_cfg->flow_control) + return hw->aq_fw_ops->set_flow_control(hw); + + return 0; +} + static int atl_reta_update(struct rte_eth_dev *dev, struct rte_eth_rss_reta_entry64 *reta_conf, From patchwork Sat Sep 29 10:30:31 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Russkikh X-Patchwork-Id: 45681 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id BD34E1B1F9; Sat, 29 Sep 2018 12:32:36 +0200 (CEST) Received: from NAM05-DM3-obe.outbound.protection.outlook.com (mail-eopbgr730046.outbound.protection.outlook.com [40.107.73.46]) by dpdk.org (Postfix) with ESMTP id 2A1EF1B1F9 for ; Sat, 29 Sep 2018 12:32:35 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=AQUANTIA1COM.onmicrosoft.com; s=selector1-aquantia-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=cSOhXwExijCam0sm7Wl8W1Mgd1ok7Fxa/T8TE9RikEs=; b=CeMXuc4PxQ7ci9qbcgjRbD0RrtlC0xVVcp88PfMlE2nrdJHF839Co8MmZSvqJTBSBlpaNcS4WligSI6y9yv6dhko6riOze6GKudOXU0TtwXR9g6tlru3gt7QZDAA2vRDRzauhUKmay5D/znOfwcB/kEczUvCfKVQiKLycLng01o= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Igor.Russkikh@aquantia.com; Received: from ubuntubox.rdc.aquantia.com (95.79.108.179) by BLUPR0701MB1650.namprd07.prod.outlook.com (2a01:111:e400:58c6::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1185.22; Sat, 29 Sep 2018 10:32:27 +0000 From: Igor Russkikh To: dev@dpdk.org Cc: pavel.belous@aquantia.com, igor.russkikh@aquantia.com, Pavel Belous Date: Sat, 29 Sep 2018 13:30:31 +0300 Message-Id: X-Mailer: git-send-email 2.7.4 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [95.79.108.179] X-ClientProxiedBy: VI1P193CA0009.EURP193.PROD.OUTLOOK.COM (2603:10a6:800:bd::19) To BLUPR0701MB1650.namprd07.prod.outlook.com (2a01:111:e400:58c6::20) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 78a79145-0fc9-464f-6112-08d625f6de29 X-Microsoft-Antispam: BCL:0; PCL:0; RULEID:(7020095)(4652040)(8989299)(4534165)(4627221)(201703031133081)(201702281549075)(8990200)(5600074)(711020)(2017052603328)(7153060)(7193020); SRVR:BLUPR0701MB1650; X-Microsoft-Exchange-Diagnostics: 1; BLUPR0701MB1650; 3:d8Boz7QSORHudwN5n+aTntwmKFQB2rDDu8hRS1ym8olc3wNCdDgPBCwp+Pll2b3/hom+R33NFLiHVxWxiQQ3hq/mCJ2tJwUrqktakmIhPRWEgKPfHHUrKVBl+9WUTYq0XKap8ME9v1D392/qBawkPJ9zyMv9ku0ojFpha4Khvjnzm133Gwi5E+2hSP68Z67FRghcs+zDthgYFHFPWnbWK5h8LlyfjP5RWb+q27pcc187sHwjP/2ScffeORQwkJ2h; 25:cHPBzVfaCqioGixDt2fS1WhgUvqKWrouV/b3+ttjCOA7Pk8ePtCfPkfctkIqbXlCkMCR6xvTJWsESa1iq0oHqzqiDVSeqfJxyjrkJGMHiPtsu6Q5W3FulrjW1+Pa0m6j/FxcyYo7NgtRuLMeEYVO2qEseEql3/ZX/NZObQvXhRyo6uskBcHMNsU5ic5o/BdNP7mq2HFVsZym0lgTM9o8jcRoBU/y7aQdu7c9Zi8apqNwUQRVc5oTqSCad7rYbgYZg2jQTi46zmPoX5JZ+fNH07S6acY6O8ot3AQHPAPJsQNAwxT6XpcLiY1EfwYWqzPHHnKdglA//SKt7+iHvPeLxK9R5lvCbNsarCH8yWrTCf4=; 31:GVNBsrwyTke1pmzoMugk5tPh0OXs+Yn5u2zNdzxKuItv+dPrwGiUnENEm0Ur+toDNHHImISNnxWMTy3ozfZywRuV6niqZ6U4Kx4qyMVdct0I+aYT3OqRtOScsG1oVgs0lBxvTe/llJi3wK0aj5lvsiAMqHZuBR9+ycLj9XwBgJn8n8eJ5VZO3x7YWBNbRNOECu0uEmsUmC3BiITosz692KcQ3pLcEt0sM9zAKU1jvuA= X-MS-TrafficTypeDiagnostic: BLUPR0701MB1650: X-Microsoft-Exchange-Diagnostics: 1; BLUPR0701MB1650; 20:98ksoSRFlMeN9HrVxnPmVu94mG+Ez6LoqFL+EdMnDVPzrChwtOMmuFXcCI/8ulwA30lEAEsrAL8qqmJcWT7r08gW2QdLkWd8H5N+J607U3fOuB1YXuEX9ViLoigqI0pcvt7xpEbVNLiFf6tK7KuUaKP2YLCIscPYmb6nI1P1uSHTRjEQ8YXPK2iA5ajiRaewXu7ygYWd+A/5ekgJ/A17R1P37nVPjowiWJp6EbRvqVvDv7Y7aGS/Qh31Ypdpz/lBZnaE93UZZSUMr8A5D/jBPCNJBPA7+ZjFaZe6+u7xo4id5lUBZE0oRBPI/GL1rVp2B4UOXekO9C/AjUf4hK0tc5p0Mya/V045XTdjkcmKpZqE4Xc0/QxAj7NJ36gvXgAUVBbGM0XBUMp1UmIwHo4VpiVdDNyx+mVFSOY6yFVxL/xB7tEGiSUbmP+s2YSupzEXMmyct5rkzJIANYg/cUKVPGF5j4HulPm/vD/A8PCTq/QkjHn8ewowIf19JMtr8E6e; 4:D8b83jddTK1blmlRoqFtpfJDfUQ1b+Cn+GfddyWK3pa6uL5VSxeoVXwdzFiwx1L7XoXTUHKBR7AH3gXXkHOlRZ0nleCgeR3rQPQiDrfv6MmuLdFP1906gu6kTjN6Z5/fzBhFfSLefIXed5PhVLObINGcd/DwKjhvRybMtaSgCRFOPkWfDtox2aL+vmDLY3p9Jhg3vPVGCVUXGpmWLhXwSqsR142+2nzJA+xXXewfveuAJnqXC4e69/rvet/eWZZlFXaGSEQ9cIvsfRu8SIAvYg== X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-MS-Exchange-SenderADCheck: 1 X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(6040522)(2401047)(8121501046)(5005006)(10201501046)(3002001)(93006095)(93001095)(3231355)(944501410)(52105095)(149066)(150057)(6041310)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123558120)(20161123564045)(20161123562045)(20161123560045)(201708071742011)(7699051); SRVR:BLUPR0701MB1650; BCL:0; PCL:0; RULEID:; SRVR:BLUPR0701MB1650; X-Forefront-PRVS: 0810818DA0 X-Forefront-Antispam-Report: SFV:NSPM; SFS:(10009020)(979002)(346002)(136003)(396003)(376002)(39850400004)(366004)(189003)(199004)(16526019)(14444005)(446003)(76176011)(2906002)(6916009)(6666003)(97736004)(8676002)(81166006)(81156014)(36756003)(4326008)(316002)(8936002)(50226002)(34290500001)(86362001)(5660300001)(68736007)(16586007)(118296001)(72206003)(3846002)(6116002)(53936002)(386003)(105586002)(6486002)(47776003)(66066001)(486006)(25786009)(305945005)(50466002)(44832011)(956004)(2616005)(26005)(107886003)(52116002)(51416003)(7696005)(186003)(476003)(478600001)(2361001)(7736002)(2351001)(48376002)(106356001)(11346002)(309714004)(969003)(989001)(999001)(1009001)(1019001); DIR:OUT; SFP:1101; SCL:1; SRVR:BLUPR0701MB1650; H:ubuntubox.rdc.aquantia.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; Received-SPF: None (protection.outlook.com: aquantia.com does not designate permitted sender hosts) X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; BLUPR0701MB1650; 23:ytxnTUIktLn/aDqTqswXa2GDWHGZFCLzDSnVEKs?= 3cdQ4haAPyIDqMnvbqQASmWOUPsy1waLzPX5X2aMCrrIMDLuPoPLFCjTMYReCEuhIhJg8Nil7C2mHPu4CGTKiPoMnvpWxP2po5j6zrwIydX2WMAPJNTy9IIDaS2JUbD9y8fq8XO7D8z7bvqHnnr4Hx+vLbeA/U77xQ4O8M6qPm31U43R53jiLWekqBt6rFGbYFrFaroXQjuGYm1hlBFWnyILZbCpNTCXyToUc5fNv0Nd1qQx0pj1n1XOIGKx//jFrdqsiXQil2lP5xCSqY30++3idsDeTnS0UTh5LcIZUeaoAbPiTX9wxdLuTRQqGtsNGKhPqUsf61cJpA4Ak/AF+IQSm40AX8BoIrHxBKehmqbhOEsVprDqC93yC4NisONk2e7OHwA8Wm0dQM1+XipCWZqcfGgfmuLM+m9U1vaMExM0ACrWxB/ri1pXhyux9OA7px+SRHkMc4UFN2F+ocj/WMI+jSvlEVNJEhDsRAzrDZHTQRSRii2hanuUnqKm2FdP8IE2/G2W9vt7dfahgwONAoPqcx9H6tZup4L/ijXt4reEjNvu5TJl+JODoMGFt1OuuSkvQTFxM+lfMvogkmWzfXYG7l5iEXWwEaKQOdj2ltgMnQsPqy3lZsDApviEz2gJA0rETluvnBSMLyFkca0Ub9jdwXfD4PwBjwgVGXfNaef33Qy1hqi4Jp7nEt+o0pvNK9kIitWtCrXTzpIWYAejVm5tOfgDn1E52C1D3D0UaddAZOoTpF4gBkgRBphZEa1bKT7ZJUX1+f+Ux/dmm8AODJ5l+X1YhZEiXbGgCieSIlQWkUGZs7jWo12h6//x5/r8E+dkQ/EP65KceXsgbEtwXPjcanoiVAYc6BR3Bz5umHVfjAmoHKclfGziko9meFVh/cK1dO9VVQSBoU44R7IMfUoHvOOB0iRMpwD2EffCgbRB382k/2wSEOwUZw+PRvsZlGcI4ss+2ZMD5XmtvhTsV5POhFxZODqOaN5u4gMDcV/xYv0hPp1g0N716LcIaGfAzCizsCCFiAmEeHsm/21nxCgTLWwV/9qIlhgklWBsJj5dC+BkLyswft/NxnZBlCAx71jY7zCExbeFEI2tcF1zE5LELM8BLJgi9qf9mfl/t1nUfyXmjgNiOPf9RXqKrz12g1Wvuc/haxChBv/oF1hUaWaWoMdtWibNdZ8uT9FeEMkn29ErV7eJH/IsmoXOkoH32cAXulSJM3gHlZJYyJKGdVU7lOXJfLEkmijcVN3/PIkYC6tY0MpIiHhkjUj26brp3zdKIsQbORpKkE9KZ7ow5t8RBd7HsSlYtl5X/CzfEEsYQ5gIOCTO8nWRS/YFzg6mn9KpRd6oV2GLygum9SPzv3tf1CRRPBW6ja+xqzJ+VRpho9dkHOs67oQmI0PJNpj+c0+A= X-Microsoft-Antispam-Message-Info: Zk4ISYkwaHSDJf7vCoyIEDTdcjW59PaaAKsd+GMeFvybCXVmcLd3r/mRBdEj5YXVmALiTtJ8Mb8FL4YJqZhDLNn4AIArR0Ig5IZZn7Xcj3/F/NAX7L18eb3lPU3cww4jx7m3QqkvKbWm7bo/GFe9DnSDOJ16TRGdFY476Ekro6Sp510Eh6hwmGxGpF9S/OfQ9xWSjQPZfteNmQZ4JqC21Makk+rbGHoSgEWNeWyCJhKrqjuYZhx06rhvg69SLhXFWmzGRR+gmgEdqYN58I8P1f+AYKE3rMi0izMMGiDlBpXWVOGEcdy7CvmAvCR/ycXeubrf8x1kEE4UnxFenPTDMvox8UuJZBVFDh/EoBIIJI8= X-Microsoft-Exchange-Diagnostics: 1; BLUPR0701MB1650; 6:gI86X7ksyKXNac9qf3I3at6uUyBD7pVDL4f+tIDya41dnwECYKnZrB37eeArae/3re+/lCIjCB1qY5LPu2fPRfhcSnVUOe31z5elJJJZXbYJNoa6j9sBaTwD9qnIxXe63DsZH8nYF/SR1vqDm4irvMFF1KF0dMrcpSQaAJwco3y/u+tkZ8bQrSqWDujPMCZvb0QDRgJKvt7oDjp2cG4RH5xwbxazrxnEOv1N2tDOrdg0zrcItzw3zkEwBMS+iXv4Zeo7/wZjduqwUWE0bicKSQbpvAswXFqcSNeyueAI6H/zoXC4gKw7opwjTlij3P1TuDP/nfD3/tYnifR4ey1yTSdM8D7/q+VMKiwYLdHokJxcByRxqnyet//16qcvD6kO5FDljf3KYxkYNq60bXuyWRTD8IR868xyRNVA2txNyJgh2rPWBdt+AU28cfnUqr7x6LMxmfkoll1X3zkoc2IjQQ==; 5:M6aOsK1YjA7eFkvpXt7cqfot208GgEPTnk3VEx5KhsxOdmHYaD5RMe+cKol/ZRts06qtTH7T0jcTFUTdrrWQrm1fMZkPbisKh8emsuiAkKlWc47UIBXLselqTPp4a4oGaKLMvxpfPki7cfQHh0JjVWIdMJlXGdazwHluEaA/zqE=; 7:+nfDsayPUCJDyVYt7RWJuZIkXnjU0f2XK3WkNA/O0jKjr46yBw1xckwXEZzGkfWNxmJTMWtAIohntkAT+dHq5BiHIv0VPjSXOiYIoItgdcAEuxnU/qo6IyflQ/pbJv1vxjWDn+ARlUPbOt7ByIUeLnyVa7XJYXqgBYo6NGWuEvp7M8QkGtEIvuCfaxOZ0ex9qc8L865O8D7olIhI/f48KPYQtJ5m2dr0uZvF4DQKPu5q7VzOLoND5cegwsYTRMF1 SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: aquantia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Sep 2018 10:32:27.7999 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 78a79145-0fc9-464f-6112-08d625f6de29 X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 83e2e134-991c-4ede-8ced-34d47e38e6b1 X-MS-Exchange-Transport-CrossTenantHeadersStamped: BLUPR0701MB1650 Subject: [dpdk-dev] [PATCH v3 17/22] net/atlantic: MAC address manipulations X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavel Belous Signed-off-by: Igor Russkikh Signed-off-by: Pavel Belous --- drivers/net/atlantic/atl_ethdev.c | 126 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 126 insertions(+) diff --git a/drivers/net/atlantic/atl_ethdev.c b/drivers/net/atlantic/atl_ethdev.c index 243020dc00a9..b71028d9d227 100644 --- a/drivers/net/atlantic/atl_ethdev.c +++ b/drivers/net/atlantic/atl_ethdev.c @@ -54,6 +54,8 @@ static void atl_dev_info_get(struct rte_eth_dev *dev, static const uint32_t *atl_dev_supported_ptypes_get(struct rte_eth_dev *dev); +static int atl_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); + /* Flow control */ static int atl_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf); @@ -70,6 +72,18 @@ static int atl_dev_interrupt_action(struct rte_eth_dev *dev, struct rte_intr_handle *handle); static void atl_dev_interrupt_handler(void *param); + +static int atl_add_mac_addr(struct rte_eth_dev *dev, + struct ether_addr *mac_addr, + uint32_t index, uint32_t pool); +static void atl_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index); +static int atl_set_default_mac_addr(struct rte_eth_dev *dev, + struct ether_addr *mac_addr); + +static int atl_dev_set_mc_addr_list(struct rte_eth_dev *dev, + struct ether_addr *mc_addr_set, + uint32_t nb_mc_addr); + /* RSS */ static int atl_reta_update(struct rte_eth_dev *dev, struct rte_eth_rss_reta_entry64 *reta_conf, @@ -211,6 +225,8 @@ static const struct eth_dev_ops atl_eth_dev_ops = { .dev_infos_get = atl_dev_info_get, .dev_supported_ptypes_get = atl_dev_supported_ptypes_get, + .mtu_set = atl_dev_mtu_set, + /* Queue Control */ .rx_queue_start = atl_rx_queue_start, .rx_queue_stop = atl_rx_queue_stop, @@ -234,6 +250,11 @@ static const struct eth_dev_ops atl_eth_dev_ops = { .flow_ctrl_get = atl_flow_ctrl_get, .flow_ctrl_set = atl_flow_ctrl_set, + /* MAC */ + .mac_addr_add = atl_add_mac_addr, + .mac_addr_remove = atl_remove_mac_addr, + .mac_addr_set = atl_set_default_mac_addr, + .set_mc_addr_list = atl_dev_set_mc_addr_list, .rxq_info_get = atl_rxq_info_get, .txq_info_get = atl_txq_info_get, @@ -1174,6 +1195,111 @@ atl_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) } static int +atl_update_mac_addr(struct rte_eth_dev *dev, uint32_t index, + u8 *mac_addr, bool enable) +{ + struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private); + unsigned int h = 0U; + unsigned int l = 0U; + int err; + + if (mac_addr) { + h = (mac_addr[0] << 8) | (mac_addr[1]); + l = (mac_addr[2] << 24) | (mac_addr[3] << 16) | + (mac_addr[4] << 8) | mac_addr[5]; + } + + hw_atl_rpfl2_uc_flr_en_set(hw, 0U, index); + hw_atl_rpfl2unicast_dest_addresslsw_set(hw, l, index); + hw_atl_rpfl2unicast_dest_addressmsw_set(hw, h, index); + + if (enable) + hw_atl_rpfl2_uc_flr_en_set(hw, 1U, index); + + err = aq_hw_err_from_flags(hw); + + return err; +} + +static int +atl_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr, + uint32_t index __rte_unused, uint32_t pool __rte_unused) +{ + if (is_zero_ether_addr(mac_addr)) { + PMD_DRV_LOG(ERR, "Invalid Ethernet Address"); + return -EINVAL; + } + + return atl_update_mac_addr(dev, index, (u8 *)mac_addr, TRUE); +} + +static void +atl_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index) +{ + atl_update_mac_addr(dev, index, NULL, FALSE); +} + +static int +atl_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr) +{ + atl_remove_mac_addr(dev, 0); + atl_add_mac_addr(dev, addr, 0, 0); + return 0; +} + +static int +atl_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) +{ + struct rte_eth_dev_info dev_info; + uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; + + atl_dev_info_get(dev, &dev_info); + + if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen)) + return -EINVAL; + + /* update max frame size */ + dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size; + + return 0; +} + +static int +atl_dev_set_mc_addr_list(struct rte_eth_dev *dev, + struct ether_addr *mc_addr_set, + uint32_t nb_mc_addr) +{ + struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private); + u32 i; + + if (nb_mc_addr > AQ_HW_MULTICAST_ADDRESS_MAX - HW_ATL_B0_MAC_MIN) + return -EINVAL; + + /* Update whole uc filters table */ + for (i = 0; i < AQ_HW_MULTICAST_ADDRESS_MAX - HW_ATL_B0_MAC_MIN; i++) { + u8 *mac_addr = NULL; + u32 l = 0, h = 0; + + if (i < nb_mc_addr) { + mac_addr = mc_addr_set[i].addr_bytes; + l = (mac_addr[2] << 24) | (mac_addr[3] << 16) | + (mac_addr[4] << 8) | mac_addr[5]; + h = (mac_addr[0] << 8) | mac_addr[1]; + } + + hw_atl_rpfl2_uc_flr_en_set(hw, 0U, HW_ATL_B0_MAC_MIN + i); + hw_atl_rpfl2unicast_dest_addresslsw_set(hw, l, + HW_ATL_B0_MAC_MIN + i); + hw_atl_rpfl2unicast_dest_addressmsw_set(hw, h, + HW_ATL_B0_MAC_MIN + i); + hw_atl_rpfl2_uc_flr_en_set(hw, !!mac_addr, + HW_ATL_B0_MAC_MIN + i); + } + + return 0; +} + +static int atl_reta_update(struct rte_eth_dev *dev, struct rte_eth_rss_reta_entry64 *reta_conf, uint16_t reta_size) From patchwork Sat Sep 29 10:30:32 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Russkikh X-Patchwork-Id: 45682 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id BE8731B3A6; Sat, 29 Sep 2018 12:32:43 +0200 (CEST) Received: from NAM05-DM3-obe.outbound.protection.outlook.com (mail-eopbgr730046.outbound.protection.outlook.com [40.107.73.46]) by dpdk.org (Postfix) with ESMTP id C631D1B188 for ; Sat, 29 Sep 2018 12:32:41 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=AQUANTIA1COM.onmicrosoft.com; s=selector1-aquantia-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=3EcjG9rta78DkNU81ClDqkC3O4GsrmPr9ACgSKbBidU=; b=hTmTH/gzZk28kdtPNB9YDJISiZL+5OqMwHwaXUq0Nu4GpIteMv+5Qdl55tmi5IT17XXs1hvoNe5F3GeabxpBp4/7ddMf9oeBCPUpucE8dMQ3y6Lg4IF3H4jobksI0hGOLMW5uCiDeqCn+Wwv8KmGqMuj0i7wK7RwMNRXncjQexI= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Igor.Russkikh@aquantia.com; Received: from ubuntubox.rdc.aquantia.com (95.79.108.179) by BLUPR0701MB1650.namprd07.prod.outlook.com (2a01:111:e400:58c6::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1185.22; Sat, 29 Sep 2018 10:32:34 +0000 From: Igor Russkikh To: dev@dpdk.org Cc: pavel.belous@aquantia.com, igor.russkikh@aquantia.com, Pavel Belous Date: Sat, 29 Sep 2018 13:30:32 +0300 Message-Id: X-Mailer: git-send-email 2.7.4 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [95.79.108.179] X-ClientProxiedBy: VI1P193CA0009.EURP193.PROD.OUTLOOK.COM (2603:10a6:800:bd::19) To BLUPR0701MB1650.namprd07.prod.outlook.com (2a01:111:e400:58c6::20) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 36c78846-dbe4-4546-1849-08d625f6e221 X-Microsoft-Antispam: BCL:0; PCL:0; RULEID:(7020095)(4652040)(8989299)(4534165)(4627221)(201703031133081)(201702281549075)(8990200)(5600074)(711020)(2017052603328)(7153060)(7193020); SRVR:BLUPR0701MB1650; X-Microsoft-Exchange-Diagnostics: 1; BLUPR0701MB1650; 3:ay0VmzHPT0+XbB9SJpIRn1Vqdjc1lWovw3uLtD758CanB1ktwtyydBeT2oMadtlIE54aKCoEkMWhGma31SE38/vcWiEsB7ZydKPZOrm3fiXDLIi/Wsv3XCkfpn9DtmBEkpMIQaso0hIxBSGWl7ssd8+BAd//Hn0qr5y8K/Br8W7NB/EpCQnHovjBvkmxxzbBpuni/ShvLS2hSX92wVJ2hmvoxqTNgETLohr5nkZ1J+7TFEcGih/70TDvm7bc2tIg; 25:YbAkDdWN7uG0shGmdFaw7gppiH4MRFZoLGGEzmFNIfLj85tDfN4y4yvaq3R/u1YoggekkL4FS6Ml4qS2ej+R+P4jlkL/H/eQWkisHsFnepjuIodI7EEAaZGjBSQpKKjIkPHHmp6J6xXBzF4cyTG3mCC4XVbY/XbVlMtaytbbh//1aAarIpam+D4jLcCcyeI0NBMHWoL0FnP76daw9h/ZPIIk6jNZvzpbiKYLjwrs0fxvgXNLI6lmJ36p44hY/bqhDz6HLdWm3D/tqyq1QwV35uacFrXM+bt/obBotugafbJP6iayJridUCNOin3Cq1Jgc5rRRvK4IquGh5m6347QJvCV4V8lsy1KnZXOqbfoIaA=; 31:fCVZLkeyw/jmlTI+9M8BD4jKVkU6CA6xv6E48RpuKWdyxmQ6aPwZa5rnFgUC+0MfM2CjX8gpnlZNwqIaYGQSb2s8Z31ZPTVVojooysDYxPfAZAA8tKKvBSKpd4sn0blewk4cP2VhXiNA87rO1bm73J0E1OGaDWl/Sbu2+9e8vfGQdi6tnRLp8ffouWECEVdwLrMTXgBscqakcrzmXJ9XMRm+75eOylrd9/dTDw2hCI4= X-MS-TrafficTypeDiagnostic: BLUPR0701MB1650: X-Microsoft-Exchange-Diagnostics: 1; BLUPR0701MB1650; 20:db3va+zY6/wVaOykh6611lAKJdfPkIeEPDhY+XtNdQC0ttDJCU1r/yFChEs2ZF3uDacTh46XinShDMHYNLKcNEnoZyqiAg2iM8cEzb2Led9X+wqKrttEblhZKw/Cvs6rSmRVMdru5wkq3wdBp0A+sJ5LfNgALGgUuAd21u/VFS+QBqZDWPlUL0j35BPVk4RXdRzEOgGv6vWoDIJ7JtHsNvmuSL65myKy2Tt4gEfHBl1+slpT0c1nW8zWZbyYGh7m7X1AXjm9jK9kTW2sx7nE3Gb2FmNwyOxJ+Y9SuetsUzhOV45RMJs2vNrM7x6SeDF34uLtG52nzs513i6le/k97AztZ81Po+IUSBnCOCVNVUNpkcHNfDSXS/XdkMApHonhm06/btNv4CF1GHJ13+xKDRFzzDyVUgMV2IlmScspbaQp4X/lkUjBzPBM3A37rTrxuDA+NHzCk8X0OmD9EHLgvZdWWE/W9xRa69Uo1GuiHw7hoHJewiZv9hkMG7zFabaq; 4:f1BhsBa5mx1dWmhV1JhjTqifpb5DJledPW6kUDq7gDnF2iS7z8G2jUX2W4tBzKVXowtkaM+R4NVZdB07TgFBvUlvE6iGZdPWOEOygbCMuKwhOOpdRphXWRuanNOiXQ0RPA2KhAeMmBWsC2Tm32J1Qtvf6VYy2D6aXz5meWHFAtasCjmtXcftgBWdyB6lc7zq/X8tKhKWc89+ADB/Wm/WEPYjbKDmGDBKHpWXcdcthR4kTfb21yPO75s0epS8rzYWYyGEn6iFg8rSZESp957o7A== X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-MS-Exchange-SenderADCheck: 1 X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(6040522)(2401047)(8121501046)(5005006)(10201501046)(3002001)(93006095)(93001095)(3231355)(944501410)(52105095)(149066)(150057)(6041310)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123558120)(20161123564045)(20161123562045)(20161123560045)(201708071742011)(7699051); SRVR:BLUPR0701MB1650; BCL:0; PCL:0; RULEID:; SRVR:BLUPR0701MB1650; X-Forefront-PRVS: 0810818DA0 X-Forefront-Antispam-Report: SFV:NSPM; SFS:(10009020)(346002)(136003)(396003)(376002)(39850400004)(366004)(189003)(199004)(16526019)(14444005)(446003)(76176011)(2906002)(6916009)(97736004)(8676002)(81166006)(81156014)(36756003)(4326008)(316002)(8936002)(50226002)(34290500001)(86362001)(5660300001)(68736007)(16586007)(118296001)(72206003)(3846002)(6116002)(53936002)(386003)(105586002)(6486002)(47776003)(66066001)(486006)(25786009)(305945005)(50466002)(44832011)(956004)(2616005)(26005)(107886003)(52116002)(51416003)(7696005)(186003)(476003)(478600001)(2361001)(7736002)(2351001)(48376002)(106356001)(11346002); DIR:OUT; SFP:1101; SCL:1; SRVR:BLUPR0701MB1650; H:ubuntubox.rdc.aquantia.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; Received-SPF: None (protection.outlook.com: aquantia.com does not designate permitted sender hosts) X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; BLUPR0701MB1650; 23:Txe92TCpmM+w3Z0DljFi/3cXYFIRDTseOZFNS6G?= 58pNd1NWHeK3HE9VGrG0+glPXzeCDmkTrzrvK8M7MaMvXxVKA2wInh+e8yUwT7+HgjLxREiHT8WMvE7KfmKriY+SVNKdBdo8a31AbfIprQ6OoDQ4vDOpYeG1QrvecaxK9U2FeGr3vaP34F6cYo+muhBbQnriTGGMwc01pRlqIUNmMSSb7uQWIpVPWUGalhdN8YNXMqCQ9YYfweL1fre8XoMsBkFQVbqyw+I9d8en+nhA+xxhDoDOTK9nHRSxdK29CidNjpxwwNCNHK/Dju8taueF/FILPPiqifI4xkOmhBgoQ4LEVQ2ZLZXsVzLrTwiJ7HXMT8i8ikuHnrLKZkoz1/bAoFbBCF61lZ4dxt785ZazolwKbpZkKKGilcYL0lbsyz0qb8D4o7rijEJPDplH5kOdZDjYcuzpNWcj0s0jmh3pqfcKS7HuIpOQenbXoNywMiuPYm8ShrtCLUrYIgskwQkrlT4XMieN3jZcQ0LESE19oE3D6vr26jnpQqLmJJWxZ8PUkSEqQU7fvfYAmCX/xTJS5ZSrBC418+k9TPo+lWQpfE7FxLFqUJ+WAE2jq8R9NloEZkmmOnES6HBH24GmSe7IMLmzb6M/RYvgaIZLLl+bAnk86QBgDeaBKnMaY+3PGTsy4F0w/gwl6OgofSJpytQBdSNqBF3whEK6vgC4SuKX8iloxBBpjdB4sckqVHitk+Qr8HcJaQZ3DHk5loF9kvjvq32A2S+zoplRHUPgdGCFb9/Ep1KkSIsANVpc5SABrf9XYf5vR6xahmGZqp5pdIKOMwcpiuUkVaFdFJ/pLiCmgBd4MJ6HzN0mSX/VijlduVO8C0WNyYQ3qAUVxZSJG5jpZs/i2sQz5KqCbG6GsxABnu+42k5EAx2qjX0fAJf1TOU8zBULK5iDaEYsBiGMDnrdLDQM8iEMCz1mQLO4EoQ5LgKb42ALv+Dj61qG5MNJjcDxrM2L6gVEITCpnYyVOgUJezaHphvRiem9hXT+uaAKBlj3he15JEaRcKLfc7b8z84hclmZS3UWXi6vKHQLQl8VHAgnls+1P3aKAMVxcA6hc9p3uapR/6Yn0E5cEe4xDNNLQb5JVuZLw+RyZuK69vugIg5g2Oi//tY3CDWbVtE1I91PO8yG2FSVR0t2ZrYtX8vwOoRLOTpqAHwF4+1mu1Q78OjHTNULS6ctm/Sgb/HbN/PcE8+uv/mIxIt05Udl0UzCkhhtLZFNa2aJBnVYGXzk2uQGgFHi7RYLuixl01FyuYA== X-Microsoft-Antispam-Message-Info: xBAgoQzpWmz0/Jkb6mr56EtPzAeynUTK6xz3c27FtidzmzBgjipoGHkCT5GrpCiu/zd9Ci3YDUu5noXjs26BFmQxLSE3Ggs5Yngmb5YVDYOuHqH5jqyHwF/L1EjpbRiFEQtfXyvYbzTdh07naZKRFKoPVGQg0CJixvkVlQeR+Y+5b0EH4pOb2rEYwXxFmiD92gZtQZ1L1Otxhf4cqX7f7pSDhn4/yUCPqhsvVOrZIdLAGt1/G8oL7yeqT36wmXA5DSic0tQJurJAHSxhDLCwT8YMMLa+qi9ubH6AugjVHA5JsDDFRRead21HJv0dxcXG+TrsI2Hv73LtrHiUFrU5ZtvCfAdhbZuqaGswGk9Ti50= X-Microsoft-Exchange-Diagnostics: 1; BLUPR0701MB1650; 6:mwzEzeO8IDs4xEj8AG3iT6bSfZT+tmg52oPo//nVFi085VEyGAtktH645YmPvTUw24Ju+bCqaT8VaufUEeXqKw6rFSBsXqmsB8tKrUhir0a+C1FdWI4+BEzNzjx6Im5GViqHWIL5e0E5yTRUz36DbshaLLT0wMv9qHkXaR+z3sQPbxIjSPmsVp7RBnA7t2Y0NNka2M92/YvkLd8p+GZrIbSY9Tl8+bBqx1cHvA93cTtzZx2u9cQ/ad8rHaZDTciwP1oI7Rb03QgFLiMCHiDSwKmoSZRtEFUUjT1lEYC5WMSwiRtqjp4+6LK1i/EEmnQ4QirSfQt4E9ULmuBrWT0TEs7Jc+Bxp7zoCxXNwNX66ijFktG4fxLd35czAuy8CGrKECDJ8MY88mWYud9cgt4d9M4W+sLZ+T8ttrsmG6LtJyk2zzL6BoGY6o0pRZI7ZC82YM9DLaQGPkRrTju2n5Mukg==; 5:prmq0kRALJ0Wr5/swyzD7Dc8hOhTyrkS9UJ5QzAlMxm/VrNb7gfgp0x1cPDCO2SSP5R84Buq8mR+6luU3o4K49lVV23Yz9sNypfw0EeXApYYs9iBh2bFlFVXR9WoA2NDiON8EB8sbSggptaSpSDlOoj+NfvYkW28rd5M0v3kMbM=; 7:HYVFXxnUc8aTzteTbDbnPuOND6JBQOoAtlWAPKCq4ekffm5lTcGWBN929vWulHRZkWmWSrpsQtLu4wmRXoRr2p7r54m07LLaLiYGX2otTJAQtku5Y9l+sXsQjRSrefAYOypK73YKNZ08+NV8e8iicyDsBvwoGSU78iNKsVCMm3KHBZWb20CXr9v1G+A5NHprVlqXKmmEXek0iWBEhx8LMWrrteMJd+btyJnXc6JCK29NfxZiXGbVmqM9uX/V1E5b SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: aquantia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Sep 2018 10:32:34.4721 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 36c78846-dbe4-4546-1849-08d625f6e221 X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 83e2e134-991c-4ede-8ced-34d47e38e6b1 X-MS-Exchange-Transport-CrossTenantHeadersStamped: BLUPR0701MB1650 Subject: [dpdk-dev] [PATCH v3 18/22] net/atlantic: VLAN filters and offloads X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavel Belous Signed-off-by: Igor Russkikh Signed-off-by: Pavel Belous --- drivers/net/atlantic/atl_ethdev.c | 161 ++++++++++++++++++++++++++++++++++++++ drivers/net/atlantic/atl_types.h | 2 + 2 files changed, 163 insertions(+) diff --git a/drivers/net/atlantic/atl_ethdev.c b/drivers/net/atlantic/atl_ethdev.c index b71028d9d227..792dd7be127a 100644 --- a/drivers/net/atlantic/atl_ethdev.c +++ b/drivers/net/atlantic/atl_ethdev.c @@ -56,6 +56,20 @@ static const uint32_t *atl_dev_supported_ptypes_get(struct rte_eth_dev *dev); static int atl_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); + +/* VLAN stuff */ +static int atl_vlan_filter_set(struct rte_eth_dev *dev, + uint16_t vlan_id, int on); + +static int atl_vlan_offload_set(struct rte_eth_dev *dev, int mask); + +static void atl_vlan_strip_queue_set(struct rte_eth_dev *dev, + uint16_t queue_id, int on); + +static int atl_vlan_tpid_set(struct rte_eth_dev *dev, + enum rte_vlan_type vlan_type, uint16_t tpid); + + /* Flow control */ static int atl_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf); @@ -227,6 +241,12 @@ static const struct eth_dev_ops atl_eth_dev_ops = { .mtu_set = atl_dev_mtu_set, + /* VLAN */ + .vlan_filter_set = atl_vlan_filter_set, + .vlan_offload_set = atl_vlan_offload_set, + .vlan_tpid_set = atl_vlan_tpid_set, + .vlan_strip_queue_set = atl_vlan_strip_queue_set, + /* Queue Control */ .rx_queue_start = atl_rx_queue_start, .rx_queue_stop = atl_rx_queue_stop, @@ -1265,6 +1285,147 @@ atl_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) } static int +atl_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) +{ + struct aq_hw_cfg_s *cfg = + ATL_DEV_PRIVATE_TO_CFG(dev->data->dev_private); + struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private); + int err = 0; + int i = 0; + + PMD_INIT_FUNC_TRACE(); + + for (i = 0; i < HW_ATL_B0_MAX_VLAN_IDS; i++) { + if (cfg->vlan_filter[i] == vlan_id) { + if (!on) { + /* Disable VLAN filter. */ + hw_atl_rpf_vlan_flr_en_set(hw, 0U, i); + + /* Clear VLAN filter entry */ + cfg->vlan_filter[i] = 0; + } + break; + } + } + + /* VLAN_ID was not found. So, nothing to delete. */ + if (i == HW_ATL_B0_MAX_VLAN_IDS && !on) + goto exit; + + /* VLAN_ID already exist, or already removed above. Nothing to do. */ + if (i != HW_ATL_B0_MAX_VLAN_IDS) + goto exit; + + /* Try to found free VLAN filter to add new VLAN_ID */ + for (i = 0; i < HW_ATL_B0_MAX_VLAN_IDS; i++) { + if (cfg->vlan_filter[i] == 0) + break; + } + + if (i == HW_ATL_B0_MAX_VLAN_IDS) { + /* We have no free VLAN filter to add new VLAN_ID*/ + err = -ENOMEM; + goto exit; + } + + cfg->vlan_filter[i] = vlan_id; + hw_atl_rpf_vlan_flr_act_set(hw, 1U, i); + hw_atl_rpf_vlan_id_flr_set(hw, vlan_id, i); + hw_atl_rpf_vlan_flr_en_set(hw, 1U, i); + +exit: + /* Enable VLAN promisc mode if vlan_filter empty */ + for (i = 0; i < HW_ATL_B0_MAX_VLAN_IDS; i++) { + if (cfg->vlan_filter[i] != 0) + break; + } + + hw_atl_rpf_vlan_prom_mode_en_set(hw, i == HW_ATL_B0_MAX_VLAN_IDS); + + return err; +} + +static int +atl_enable_vlan_filter(struct rte_eth_dev *dev, int en) +{ + struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct aq_hw_cfg_s *cfg = + ATL_DEV_PRIVATE_TO_CFG(dev->data->dev_private); + int i; + + PMD_INIT_FUNC_TRACE(); + + for (i = 0; i < HW_ATL_B0_MAX_VLAN_IDS; i++) { + if (cfg->vlan_filter[i]) + hw_atl_rpf_vlan_flr_en_set(hw, en, i); + } + return 0; +} + +static int +atl_vlan_offload_set(struct rte_eth_dev *dev, int mask) +{ + struct aq_hw_cfg_s *cfg = + ATL_DEV_PRIVATE_TO_CFG(dev->data->dev_private); + struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private); + int ret = 0; + int i; + + PMD_INIT_FUNC_TRACE(); + + ret = atl_enable_vlan_filter(dev, mask & ETH_VLAN_FILTER_MASK); + + cfg->vlan_strip = !!(mask & ETH_VLAN_STRIP_MASK); + + for (i = 0; i < dev->data->nb_rx_queues; i++) + hw_atl_rpo_rx_desc_vlan_stripping_set(hw, cfg->vlan_strip, i); + + if (mask & ETH_VLAN_EXTEND_MASK) + ret = -ENOTSUP; + + return ret; +} + +static int +atl_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type, + uint16_t tpid) +{ + struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private); + int err = 0; + + PMD_INIT_FUNC_TRACE(); + + switch (vlan_type) { + case ETH_VLAN_TYPE_INNER: + hw_atl_rpf_vlan_inner_etht_set(hw, tpid); + break; + case ETH_VLAN_TYPE_OUTER: + hw_atl_rpf_vlan_outer_etht_set(hw, tpid); + break; + default: + PMD_DRV_LOG(ERR, "Unsupported VLAN type"); + err = -ENOTSUP; + } + + return err; +} + +static void +atl_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue_id, int on) +{ + struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private); + + PMD_INIT_FUNC_TRACE(); + + if (queue_id > dev->data->nb_rx_queues) { + PMD_DRV_LOG(ERR, "Invalid queue id"); + return; + } + + hw_atl_rpo_rx_desc_vlan_stripping_set(hw, on, queue_id); +} + +static int atl_dev_set_mc_addr_list(struct rte_eth_dev *dev, struct ether_addr *mc_addr_set, uint32_t nb_mc_addr) diff --git a/drivers/net/atlantic/atl_types.h b/drivers/net/atlantic/atl_types.h index 99e920315014..eb6feec177ff 100644 --- a/drivers/net/atlantic/atl_types.h +++ b/drivers/net/atlantic/atl_types.h @@ -77,6 +77,8 @@ struct aq_hw_cfg_s { int irq_mask; unsigned int vecs; + bool vlan_strip; + uint32_t vlan_filter[HW_ATL_B0_MAX_VLAN_IDS]; uint32_t flow_control; struct aq_rss_parameters aq_rss; From patchwork Sat Sep 29 10:30:33 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Russkikh X-Patchwork-Id: 45683 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 9F3DB1B216; Sat, 29 Sep 2018 12:32:52 +0200 (CEST) Received: from NAM05-DM3-obe.outbound.protection.outlook.com (mail-eopbgr730044.outbound.protection.outlook.com [40.107.73.44]) by dpdk.org (Postfix) with ESMTP id 361C01B42B for ; Sat, 29 Sep 2018 12:32:51 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=AQUANTIA1COM.onmicrosoft.com; s=selector1-aquantia-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=y8nyMRSJWwCd0nq74Q2FS2VFZ7Lk46srYmC2dJOQR+U=; b=Q7/LZT3w5YaDy84f2lxOEEsswaqtbNumtN2Iyv/Q6QNRbFvwpP3r6PGn3U0oYBDhlsinEl2OSvi1lazLwgoJIXOBLNx5wnHTCdFhWz4gyWGX/xl5YvT0nLC82gI4uJJfdoFty+lfAS4fELhtKe2D8rF86Ww2BQBUoXbTHxYjyl0= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Igor.Russkikh@aquantia.com; Received: from ubuntubox.rdc.aquantia.com (95.79.108.179) by BLUPR0701MB1650.namprd07.prod.outlook.com (2a01:111:e400:58c6::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1185.22; Sat, 29 Sep 2018 10:32:41 +0000 From: Igor Russkikh To: dev@dpdk.org Cc: pavel.belous@aquantia.com, igor.russkikh@aquantia.com, Pavel Belous Date: Sat, 29 Sep 2018 13:30:33 +0300 Message-Id: X-Mailer: git-send-email 2.7.4 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [95.79.108.179] X-ClientProxiedBy: VI1P193CA0009.EURP193.PROD.OUTLOOK.COM (2603:10a6:800:bd::19) To BLUPR0701MB1650.namprd07.prod.outlook.com (2a01:111:e400:58c6::20) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: ae7f9a8d-d007-4948-d39c-08d625f6e60e X-Microsoft-Antispam: BCL:0; PCL:0; RULEID:(7020095)(4652040)(8989299)(4534165)(4627221)(201703031133081)(201702281549075)(8990200)(5600074)(711020)(2017052603328)(7153060)(7193020); SRVR:BLUPR0701MB1650; X-Microsoft-Exchange-Diagnostics: 1; BLUPR0701MB1650; 3:I3JSpTn684Pkjrzzy4lB8iXtORSG4W2FZlZa8QQMnLqse2C5CE7BzEKKBqpUoTYzTqfvT7OuRpkh+QeGMw4U169cuqqcivaxwjcCHhObybU81JAL6co6Xe178e0AB2AY72KlDEWjoH/ZbhHZy6+PhLcm38/w0pv0CQKQIxHlZVVLGEAPdkBZuhJR+n5eh2MCupd+SIEC13FS/qXySBZcy+/WWPC6vrnx1ZO+Qvi+GiPlHS8nasgYNeYhunLlwsGQ; 25:tyCRr5bUrqGvwHlBXy0NwC0zKN+Elr2bYOJ24kIvb8/ZSGgo76Qrc3MAwWPbE5hB9tWpYxb/vy/ux/OrdRxpmUWPZAKNp2p6aMQrpkk12oOcN5E05gguhefm0yRgK0oqksVsNjyltmXAdzuB/eNrYLWkNZxo5y0wTQSV5NNTYSqN/yY+EN1TdCxF8IbvMvrP4gS9lP+NPdi+prYaly9x4gM9WcH8mUsBg2LJ7yGneTb5BNsR+z4ChLTyUce7wY+iDTyqS19nQndtPCX1XN2z6xXwzoTSg9nx3sZJqtapdCLjdoAZcJM4sozRb+OIFBsZIijc0bNKHjqQNEl2CDpdHQ==; 31:Na35Bo26wN+psW2XQ0da8C0ylFVFS2RR3pz0aZSVJW170TLK5ATr50Ev01htQ3VFpNVEJ52ouv/F1sf7lrTrC6vcw0j79XcZFEO7/Gg5ZCnJ6lMjwckqOKjhwMjiPsY7pS6wWgE6FAv9J09uMoLwfq8awE4P+gkOceIsBFV2Jlut9MG/V5hUSc56+swh6gUwlHu5ebgmgNjWUJ02rzXGo1BixGMMMD/Vt9b9v0/DJPs= X-MS-TrafficTypeDiagnostic: BLUPR0701MB1650: X-Microsoft-Exchange-Diagnostics: 1; BLUPR0701MB1650; 20:4rtUVTEUbDNbHujw317enDOBSdZh07DVCYeiq9aiHFOc3+6NpjLTARWlMurb97AXVvbfTM7ufq4X/pxHmngiBQnZlrsJmwcfuZ+GPgI3kNRafd1i6m9roODsUZ0Kp1flIzrpqknSmGJ5Mv9W5VrqbjWdK8KWZG2eD2zErw0/CL/n7/uQ4uB6AgHGwO9GI9IONWOdkCgVpTMeaz5uzJ2tpOcz3AnWr55nAMoFx0Uix/xM8d3TgPrHf/92zHkjEURiRTi/NjlepdslHNwQBskQ1lLZee5t23+scwSALog7bVFmJAqjqGmwaRP86hOG1Swa9JT9b/xgzKg8h3tK1ZOhpwhdi1UwaxFS1Xq5CArGvbIX2qa59IdIMmr2qFyIaiY745L3fOP5a5PAiXhSSM9HXzF5hKsB4T6zCk/9okagfYqiLbUPJ4Ka9b5iCqUFHd9uEH2D+aN8OlPalWrZrFyoXiuOcdPl23p8H+iXoT7C3lHCcPE5HAhMTDYToUrqOFD0; 4:5R7ywR0ovuSyb9FUdzOgJZ/ZQpJUVil0zXXoP9ATOP71Onh9qAh4e8toIaHyTF07SvHhwnymXRudSAX+mVQuZo12IG5qR+dSnmtO6zxTx4gLY0lL4uSKk54MZmsXbVnw8FUwPnqApUp+xZhqjkh8x1haUps9zKi409ok6wZiLo1JEe45Pf8fOorceOHJEi8KW8Xb58WNJjqUBnXJwvIi1DVEE3+fc0xTX5tSq+8BPCZX9yJEW81Y863BNVeSLKEx2f/OWmAZ1o3vwas5axxCxg== X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-MS-Exchange-SenderADCheck: 1 X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(6040522)(2401047)(8121501046)(5005006)(10201501046)(3002001)(93006095)(93001095)(3231355)(944501410)(52105095)(149066)(150057)(6041310)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123558120)(20161123564045)(20161123562045)(20161123560045)(201708071742011)(7699051); SRVR:BLUPR0701MB1650; BCL:0; PCL:0; RULEID:; SRVR:BLUPR0701MB1650; X-Forefront-PRVS: 0810818DA0 X-Forefront-Antispam-Report: SFV:NSPM; SFS:(10009020)(346002)(136003)(396003)(376002)(39850400004)(366004)(189003)(199004)(16526019)(446003)(76176011)(2906002)(6916009)(6666003)(97736004)(8676002)(81166006)(81156014)(36756003)(4326008)(316002)(8936002)(50226002)(34290500001)(86362001)(5660300001)(68736007)(16586007)(118296001)(72206003)(3846002)(6116002)(53936002)(386003)(105586002)(6486002)(47776003)(66066001)(486006)(25786009)(305945005)(50466002)(44832011)(956004)(2616005)(26005)(107886003)(52116002)(51416003)(7696005)(186003)(476003)(478600001)(2361001)(7736002)(2351001)(48376002)(106356001)(11346002); DIR:OUT; SFP:1101; SCL:1; SRVR:BLUPR0701MB1650; H:ubuntubox.rdc.aquantia.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; Received-SPF: None (protection.outlook.com: aquantia.com does not designate permitted sender hosts) X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; BLUPR0701MB1650; 23:9vQ/9KEVqL8c7/nWrpf/DIhfhhx04uraKuzxG6L?= BnRPxUdJaJ/ZYuB84SU837z+OwdE2vWytAxFwJ2jgzQhneJRj8eJJ53klI6g5QzOr73aVWRU7Albs2QtAtzTKknQUbReRDBGEPuH5Zp3mOQmCi2/feuql3GhJ80aTSD9m+tgdGS3dDICCCGT1zsfjA+lObMLjwt9hf9ucx8lglI7ZeIGCkWcDrWxFTpvzokGPaYL6CWhqn+rTtbeg9TVRN/YbkxNdaASItcXO4C59Hwjg2B6k0pN0T49mEerOc6jEgaRB05UFQ42hqPRFNnhRWVU0JYHrqnMZiYDBduBJPRC0szQbP2gcS1955xcRS6P/eAKwGqPstN5IoyDF+xXv+ibEojfPi64gswGBEN+/QRzTPoDl0jM6g6I6ImKpcioli2YffFmeN5wGgPy7eMLfAOsZWUI5PfIsbeXRgM7P0CiKYgSkMZ4EY8uW+AT0YpRRkBWYgZT79uiKQJEOHkvP3gyiWqDru6Akc5NNsK7CSLoK654tT2gm5/rBpiYLR89ubIS8OGKhiyqcC/uuRpmw37vZ2OIaZpwjRWNaT+C2zq5TZAbDLV1z57NkGUVsWM6HFHLrcctqghjQVQNkUMdP4MQu+57tRNYb/u0kMRMRflz9jx44PKgqTMk8TTM992hM3TN6c97LPYQK0uXATEutp52DeCttW1JSNLyQm0t16BIoJj0X8KARn9iSAfouEntQDeY7DbTDRz/b+qYwcV60UuShPA4/kF9TeQMQKzowUZL3MOTKzBOVJ1XojXkoX5ItTlXZVLzbzkg9xgSr7DcSkQfVFHGdloPv/78YQxNSgwepG+WV3KQ3NurOR27PezXtl4XQYL8TwVkyYawBdhHVardWtn4uPxr8TpExiYkA65mIUzeDIO4HJyXcYURMAh9hY40pSTbFoGYbTDD3yvbw9PfGCQT7oAuXhERxeDmE/7E1P/joHoE7QtfMyb8AFirca2y7oIGjmiLLishk+7X8RriOLOP4EbQ0fHIOkdnfFp8sFOHzwVQ3FHRcfwvig9iOZ9VyxRb8islZcMrou9+zsNBOynhQJCqhioj+JIBO8p1X4JEhrOK62Z7Ao2I2/9I+PsUiELYvuIux/dJGZP+/h1Kunn8DkKDvi0wsU3FedC5O5pstKBDj+C3rXduwT2/xdDq16F4OgddKbw20iVa3dj0H8vXTpxhPzjMaxBJP9hJ+P0T7NQYr60UjBfEpvm/TEdpL90HtFCCSSgp3yTRSEFf1yrdlkw8aFKXIc33QtUIuZw== X-Microsoft-Antispam-Message-Info: eJSbKY+CxFejmu6MgKI89SKmxMGkMFtUlHXWq2iroIypsnuFuPVPf2rnFq2UMTpDxbIYMrzv27CezKBzfqR9sGBSTbh9FBegiu93sefiUdDwGxJ+cIFYPXyzRo/9VTpB0L6Y7BQfy33x3kwYzzctx+zLU1bi6Lf1m+qRf+bSA7S7Jd+KvvbCuFm3FpCp7eF/kv91zpKjG12C9aDSZHssdG/5kQr+bC7ZzEabDkPcdFMHNxZjXWSR6IlNKgZ0ZcZSLvgEyG+MPT+xXOJXlTiWkYvy7fBe+8T8Wj8BrBGtaPbA0kyhREnT1J+4+ZsbKhHCXLeZOOUtm9f9a7yjdnxhGoXmJWiD6+Zn8IwKFOP3tnA= X-Microsoft-Exchange-Diagnostics: 1; BLUPR0701MB1650; 6:iiSIPYY9KeJCtLDjTBFinWPIHepWnGr02u5a6kS7yuyrUgxf5LnQtrUcuSsPkbU8N6gwhOx9U36328We+60n6aOpkEmFh/Na1SKtgDPiHdYAm0teK5qcMAlFMUYl3GNhY5vC0bjBpGDtQj3EzgA0T9xEeAW9nebS0qYpR4EnHRZsv2/2h/xAMCkV68tBVpGt3p8LtQgz/GRP/Q2jP2NQ/jPoo0xUjihQyTKZnjLfvWw36m34atmnMmyA3I+juUKxmAzHQOSr0rVsVaFzEy17CMmCwaA82l7Xe2ug1K8fqJR2tOzOEXiJlD9HEYUNs4eqUnIuZ5IKMGe09ra6HtFbj89fNOX9K1UGiv7zJWdsJQXigK7DT4muyZ6bwkki1IxXbijnHfHmDDYcbOZEcMJQsfo/r6ZxqVJt5MiqOYj5WUyccN/JzoUxHsgJs+NHMtsqmHqemouAh2YPMF6QkOhbSw==; 5:Wg1+m308dGmTkTZ0nHe4a+kqnHPHI1xNNX2X5AixpP4KCu412THR5ArBVcZ/UD1RjwiaEDimiMJTHzJJBNnhjjeuaY0fUYmTj9B3jC/NssHwQI/lTUxRv6GXgblQ/QA7qXG4dNWjzoec9iUE1xFpeFbNNhSy1LLDNvdXOpMtGXM=; 7:OX8aGQ9jRSKZbNpf4GJyu/4GTICMPyF7lvgRkfT1jT+Ynl0NrNPW69thjv7+NEzndd4QvxhwjkNkWaOc/kes61xKR9aa0PSDRe4vTrX+AOoCk7aWbVNsLTs0XdEyjnP6i4tGO9K5eIVzDnoUzfPyO3cMJZxEyfhJGvQXWV4B+6atvAcF/KqK3Zu6tMT8u1FXOSl+gpReME3bTEsgEiM6XbOIhh67i4KZiqbaGr1DDPJsCQhuZXU++/QDG+3tmhoy SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: aquantia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Sep 2018 10:32:41.0506 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ae7f9a8d-d007-4948-d39c-08d625f6e60e X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 83e2e134-991c-4ede-8ced-34d47e38e6b1 X-MS-Exchange-Transport-CrossTenantHeadersStamped: BLUPR0701MB1650 Subject: [dpdk-dev] [PATCH v3 19/22] net/atlantic: eeprom and register manipulation routines X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavel Belous Signed-off-by: Igor Russkikh Signed-off-by: Pavel Belous --- drivers/net/atlantic/atl_ethdev.c | 47 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/drivers/net/atlantic/atl_ethdev.c b/drivers/net/atlantic/atl_ethdev.c index 792dd7be127a..b3a19f96e8c8 100644 --- a/drivers/net/atlantic/atl_ethdev.c +++ b/drivers/net/atlantic/atl_ethdev.c @@ -69,6 +69,13 @@ static void atl_vlan_strip_queue_set(struct rte_eth_dev *dev, static int atl_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type, uint16_t tpid); +/* EEPROM */ +static int atl_dev_get_eeprom_length(struct rte_eth_dev *dev); +static int atl_dev_get_eeprom(struct rte_eth_dev *dev, + struct rte_dev_eeprom_info *eeprom); +static int atl_dev_set_eeprom(struct rte_eth_dev *dev, + struct rte_dev_eeprom_info *eeprom); + /* Flow control */ static int atl_flow_ctrl_get(struct rte_eth_dev *dev, @@ -266,6 +273,11 @@ static const struct eth_dev_ops atl_eth_dev_ops = { .rx_descriptor_status = atl_dev_rx_descriptor_status, .tx_descriptor_status = atl_dev_tx_descriptor_status, + /* EEPROM */ + .get_eeprom_length = atl_dev_get_eeprom_length, + .get_eeprom = atl_dev_get_eeprom, + .set_eeprom = atl_dev_set_eeprom, + /* Flow Control */ .flow_ctrl_get = atl_flow_ctrl_get, .flow_ctrl_set = atl_flow_ctrl_set, @@ -1171,6 +1183,41 @@ atl_dev_interrupt_handler(void *param) atl_dev_interrupt_action(dev, dev->intr_handle); } +#define SFP_EEPROM_SIZE 0xff + +static int +atl_dev_get_eeprom_length(struct rte_eth_dev *dev __rte_unused) +{ + return SFP_EEPROM_SIZE; +} + +static int +atl_dev_get_eeprom(struct rte_eth_dev *dev, struct rte_dev_eeprom_info *eeprom) +{ + struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private); + + if (hw->aq_fw_ops->get_eeprom == NULL) + return -ENOTSUP; + + if (eeprom->length != SFP_EEPROM_SIZE || eeprom->data == NULL) + return -EINVAL; + + return hw->aq_fw_ops->get_eeprom(hw, eeprom->data, eeprom->length); +} + +static int +atl_dev_set_eeprom(struct rte_eth_dev *dev, struct rte_dev_eeprom_info *eeprom) +{ + struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private); + + if (hw->aq_fw_ops->set_eeprom == NULL) + return -ENOTSUP; + + if (eeprom->length != SFP_EEPROM_SIZE || eeprom->data == NULL) + return -EINVAL; + + return hw->aq_fw_ops->set_eeprom(hw, eeprom->data, eeprom->length); +} static int atl_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) From patchwork Sat Sep 29 10:30:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Russkikh X-Patchwork-Id: 45684 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id D28AC1B42D; Sat, 29 Sep 2018 12:32:59 +0200 (CEST) Received: from NAM05-DM3-obe.outbound.protection.outlook.com (mail-eopbgr730042.outbound.protection.outlook.com [40.107.73.42]) by dpdk.org (Postfix) with ESMTP id 060551B139 for ; Sat, 29 Sep 2018 12:32:58 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=AQUANTIA1COM.onmicrosoft.com; s=selector1-aquantia-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=C29//cH0FUQxE02q0ReAh4OpUCV597oqowamgIF+CFY=; b=Cvu2+0Zya/UlzytW9NtLKXdQUfbKWxpvkSBLNquouvz2PZzfYd2cmCMTheBmIKB01OI5RZ7iCaoQcanYDCDFNYbNAqDIYM2Zj8G5S0ve1VSuUJq8GRJY7KOzaqqeLe8qFO+A65hbX4r+IDFKB8+HpO80QMpbbTSzYxkNZcT6F+4= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Igor.Russkikh@aquantia.com; Received: from ubuntubox.rdc.aquantia.com (95.79.108.179) by BLUPR0701MB1650.namprd07.prod.outlook.com (2a01:111:e400:58c6::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1185.22; Sat, 29 Sep 2018 10:32:49 +0000 From: Igor Russkikh To: dev@dpdk.org Cc: pavel.belous@aquantia.com, igor.russkikh@aquantia.com, Pavel Belous Date: Sat, 29 Sep 2018 13:30:34 +0300 Message-Id: <1385c7733c0ad133b20b424957ac26662ecc8df7.1538215990.git.igor.russkikh@aquantia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [95.79.108.179] X-ClientProxiedBy: VI1P193CA0009.EURP193.PROD.OUTLOOK.COM (2603:10a6:800:bd::19) To BLUPR0701MB1650.namprd07.prod.outlook.com (2a01:111:e400:58c6::20) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 61c57ffc-0f00-4536-7c86-08d625f6ebb8 X-Microsoft-Antispam: BCL:0; PCL:0; RULEID:(7020095)(4652040)(8989299)(4534165)(4627221)(201703031133081)(201702281549075)(8990200)(5600074)(711020)(2017052603328)(7153060)(7193020); SRVR:BLUPR0701MB1650; X-Microsoft-Exchange-Diagnostics: 1; BLUPR0701MB1650; 3:rH4eS3A/OJr2+ihlgKU9DlY3/7ZmKdemF78iZA/G9OwYV71CGdhk8XpNtUgVzK0rBDKRiqpwAQ+5BBj9RIoiDgJUYex8+FvMLApviXexdMd8SE+kOf4Gpg4315pF1wmEDfm4gv+h8JjRIbrXeF2Ghi62QJpLMoaUjVUzo7lkmkjBidd/DWhkhdGyg4caRc4B1nI8zytRp0IzXNqfZusy2/EgmgPTiUkiMrwf3cOykiXsfyRHZndy1G5ttA/UqiNI; 25:FOpM6EdjKQCE77r29+Ai4eo4PN2wCIg20IzOhLko3UQhth5EQqO/pUkL0NR7mJ7m+Qo6oTSCbkVjzCzz50fyseA+WxYrqyZ23SBlIY/zxdM36WtxcJZ7sWp/tUz/Q+f5JN+M8BhQmKhbwX9hEem0RoGWqF8+xW3QRyel1bZrdNLtwH9vZt8trvKMqDKKFdr66pPqpnTz0yLoahLsicVVRq+XpyPutLF08JzHv8Kvy5zXu7YxvZAsteC7A5+vQj7cjCxXcKk3KckMXVVUpNJkjFZTFAj9ESgURUrAubqdxZiKYvYCFmlkYwQwQISLh56nK7RSaoULnaeodni7aUiIcQ==; 31:yvZw0LAH1W9G6IwVaOQyH+Q5J6n+GO6Pz8ewxusCDb2dT3ovqGLvHdlquLXqKWB/aFGIgrTWk2NdkWh6SsdKyiqUjR8os7WGwJwBIU9iXIDIFE8XjUuC9cNOl4JMxsV3U86A6WQrmoPgGv+e23jy56hlP//FgZpdmwyCiewsg3cwRXLRMQGSVYDKVhnWxmQ/vqlXrdm8ljKGuGRWpYLaAotA7WbrJCZxVV0WQ5Mi6KA= X-MS-TrafficTypeDiagnostic: BLUPR0701MB1650: X-Microsoft-Exchange-Diagnostics: 1; BLUPR0701MB1650; 20:FKi/pIThI7sq7TCQWCQFDEwVnyqUbjDp6pv0Ohf5gv0rwnT2uMrUxRFhp9aT6nsmuRCI0iu378JmxE4LODI6uwJTn9xEflBvr5boH9vvaBW82m3vt3mMdy0MkgMZ4T3ddWq1fxPndjUHZNxvWOBEG4VDorP1mbWmPuxHS263giFxLQns4aS1SC6w+0BBQs7k/Pp0N+btNGeY1TdJsOlkks2We7b8f1Edgt7YPiSvGAIhjRWCRedGO+zHuutoxvTybVdOWjLWA3OSZqdA4+miEl4rwxl0PDVZICJreXIqoDb3oJ27HwqkZ9iT8zcvpWx+yqP7YtlECkgtETr0dI+1f0knh9eLhp8wEsUxNPTRZz2imI8DKekHXcqfojYM2r6ggm5ryKx7yJIkCYHRAetgvee6Fn5U5ee42uvLjbTs08jpsnWry0WTbT8LVohXCvx1j5mUGhU+LJaX4sOfnsbRBlM8Nwjy3EwNtgMtlRyJL10YkxzDhJs/v7fodlQbOtAO; 4:NfAMfKuL5CfkWcDBIQQ2toSbo6SihDXR5dI7K+J4ljDaLpHcgevKVkU2gV/QNSn6xeMt5RNYmy1/eoUeIcwSezS0/GDxyRzw4zCp/HtNye3vrL1m2SWOy87jM3MxITQUmNEPdAxjG92VtwgTkjOZ6L280ZbMyuWCMB0lvnp+ZPAcW7XVZJcmACZoakC5V9uhtp0ZX1r2CQyFsCvP5tPT8oAQ+SnnAAhiAnQQwLU9+hmZwUWmW+E16f8kc69PIlR88DVe5BCWuZCzuXax4u1iOQ== X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-MS-Exchange-SenderADCheck: 1 X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(6040522)(2401047)(8121501046)(5005006)(10201501046)(3002001)(93006095)(93001095)(3231355)(944501410)(52105095)(149066)(150057)(6041310)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123558120)(20161123564045)(20161123562045)(20161123560045)(201708071742011)(7699051); SRVR:BLUPR0701MB1650; BCL:0; PCL:0; RULEID:; SRVR:BLUPR0701MB1650; X-Forefront-PRVS: 0810818DA0 X-Forefront-Antispam-Report: SFV:NSPM; SFS:(10009020)(346002)(136003)(396003)(376002)(39850400004)(366004)(189003)(199004)(16526019)(446003)(76176011)(2906002)(6916009)(6666003)(97736004)(8676002)(81166006)(81156014)(36756003)(4326008)(316002)(8936002)(50226002)(34290500001)(575784001)(86362001)(5660300001)(68736007)(16586007)(118296001)(72206003)(3846002)(6116002)(53936002)(386003)(105586002)(6486002)(47776003)(66066001)(486006)(25786009)(305945005)(50466002)(44832011)(956004)(2616005)(26005)(107886003)(52116002)(51416003)(7696005)(186003)(476003)(478600001)(2361001)(7736002)(2351001)(48376002)(106356001)(11346002); DIR:OUT; SFP:1101; SCL:1; SRVR:BLUPR0701MB1650; H:ubuntubox.rdc.aquantia.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; Received-SPF: None (protection.outlook.com: aquantia.com does not designate permitted sender hosts) X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; BLUPR0701MB1650; 23:KqlsG/+ZYIAGPkB+196qJPOYTUcJFd96GX3aicN?= XydXW6SAqSeGmbXxJczjadhCUhexpOz88CBR/EYse3/BXHzXnQANEx9DOLKp+q+2B7PgxmLFhHL924TuY0HWod55/13VW03CUXCsAjO8ldY/E0MTg3+5skPbFuXX0cDpJZhxlMCys+pG4m0nzMQaDlOFXlJFQbHSFeu0yAni5qXUm6MkkNIsZ3HnanRjwoQ+klbRbp/9PEpZgY/BlPZg9o/Ly5+GII9UjRtAN7tsxfDMqp3YHlbANTULminAHHmIDQTexDSlAZXixFswHxEe5NzDEt8IYZnD75PVmtj+PtVNpeZurONb4G+PAJ9HUbzELvYTyTTBGYkzd7QxHJL8vCrNjvBRhBRFFyVfiia1gV6/q5sKRWYH1Fo3CrAvFmWsUbTz08UxZhSYab+hKc8OwuoH9X32nRcXTXxHz8o6DZzaKC4k81DpNuEVBq4JU7VTTjNItH7ztZwkSw1nMU8oYZG6K1NltapjDv0OPeJHDFJJ477OvYv4BQRI7Zntj+HJYFoTA7VEcefI370Buazj1aF+iW5tJFDVbEhK/r5bPgDM5VfRNtmDZlkZaVO2HlFODGE3JhuACcpHpoiNvaUznAmMyLovhjyTWUzLytn1Ub1avbuHEwjm8kmQmHeNPP/tVDGZ3B7fBxQfBmxtJw4tqzcwccHapGXkEzI84Qn1szhh4yTPgMeUeltI41u3j5tw9imkOqQ/evePDBj6q3SmAjlLw2pfEyzUFZz+MExvLiKxMbpjwa1IhsN35IdwAK5npXOFWcYp/eal7f61U0u/uoh482k9OzjfkxBRBOxnUF5KCRu4dPpu9PlpFJawB1nK6yCjfgdTxzLmPpa3EW839ZMldJmE+JtETAp/LNqC6fL+iB3vCH+ci9xospcxxFj72QBMKjqpCFlbIMmjxdXo0f77T1j5NrNUHhCY2sdkxWMLSZbSTHta1yff8yW53DUlx/rWntUP9MBuWuw+ektuhPpeY7HT/AgAg8+8PqlVzqtCKk7NokVak9pnqp6D4rdwGT/BEJvZoT9bYSJi/B+xI+YikluAkPpsu6eE9Pa/ym7oARiL1JxUNyFYBXuOWbWnYZgqJdEl13CtIqMODaSUTTnGjBHPY/BhLyho+YsJ2gc2V4K8310HoocfHa0TwKoNT2+ikoRe1kBpldV59LpOmZBAEdEd5lnvqDLD8iOh38eCe0i65xywbBAf+M4E+n6fqqP98TYS43plbGl3iGcctd0fi4ARwIYP0q0pdIcslw5311BJ/n4cXekK+a2YeteY00+A= X-Microsoft-Antispam-Message-Info: MX5t/R4aOOfv3zZfI7lcpZzpey8tAsqYc++ILBUTd2qUEZhHXpUShXfopGGhuwgI945vZaYedWQoSA4axvIBc0i2GFSWHM6odspe9rCVaSNdhpJDzdBSb6kVV8G8RxenkURYGZ3b1tcNSI1R3QNZg2U4gyy9qGtzfJWefpVMh5KX1dpeunEPKDv4XQL3DdEGlY4DxhhYcX4teMUeJ3fHd3Uvw2mnrjeauVI1yYh69iqm9Bk+Ga3vz1DsdfTE6rl5dU/tCet7Pz+MGC1rGiW2FCW5Jlo7YsttGJ1PDs77EjKgMRQ8SZ2VOgPtkd3PVhpwZRmBwf7ua5yjmpeoGZcDKHPU0Fi0S5iaBilujPMGVkI= X-Microsoft-Exchange-Diagnostics: 1; BLUPR0701MB1650; 6:ogCqalUo7JaS+Y2ZVBhyG2GVl83/gbuZFv8gaHOjwQvBbByBsESOz5DEXErd6rck5YFN7lhK15cqB0SHvN5EuhJ2RCfQ8XTTolW8Giu1CLhAQtOjwk4inRAl1W9Xx4vU+ul89SInhcROtSr7tENNGcb3NEEb9iKq+KXAUDbf1WUia34vnF72XALUWrwVkwACe9KxD84kYppyck5HjBL262SRVxhL9KvLVSRQdhhPj5ksqS8fj7BtIWO2ieVS2qmnwYB2CVj4d4UUNYM50Tx8kUdoftR72y1H/RzlOmovxW3Wz9qMnRwWlm3Z0IAJm4XcmjFfYvXhw3T0SdS7GFdXX5I1nXcg2KFm5mZyWvojcAcb2sBGevO0Q7UHaCsG6k1VEgXZITGPz+NTIy5cXlrKFO1l7R2orbH3tUzG7z/z73hxMKfKl05tMauqIwZ18jiU2WWO56p3rdQDpcsNPLH3AA==; 5:eo7gUMOihSrf3Lb1OiFY9u4ntz6V40uwA73Tgj55vUd1hwtpjAUMjG6tt9TWkE5im+Io3uqA+YekhUzUGwulj5CZmEDZRKujTdxp4pyTQj0l6YoUPIyFlo4aqeMl8EzQdS3gfQuuo825gP2dvqWPXDh6A385I2OZJR51szKPahM=; 7:GFavFV4+yVdDO0anqE3Pruxxz/M/EPNr6roFNFsqgJ71a6Nrub6jetoHq/pw2eLPvhensE2sVrOEQxEDapOcbVa9iskgQzjAN+qIn7wYpzjzXfWGSUVBp8raJL9ONPwCriEKCV5PnDr8S4REK2NzV8Zhk6F+9j99Hvu6/fK8jx0WrBx8B5GDEfIXg3mhjMCy9kjDeQTUegfsY9Xg6tqzRMQALI4KTBFNYdrCjFqBp85hZHrra+vC+alRnRMc1Txc SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: aquantia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Sep 2018 10:32:49.0324 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 61c57ffc-0f00-4536-7c86-08d625f6ebb8 X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 83e2e134-991c-4ede-8ced-34d47e38e6b1 X-MS-Exchange-Transport-CrossTenantHeadersStamped: BLUPR0701MB1650 Subject: [dpdk-dev] [PATCH v3 20/22] net/atlantic: LED control DPDK and private APIs X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Signed-off-by: Igor Russkikh Signed-off-by: Pavel Belous --- drivers/net/atlantic/Makefile | 4 +++ drivers/net/atlantic/atl_ethdev.c | 53 +++++++++++++++++++++++++++++++++ drivers/net/atlantic/atl_ethdev.h | 3 ++ drivers/net/atlantic/meson.build | 3 ++ drivers/net/atlantic/rte_pmd_atlantic.c | 19 ++++++++++++ drivers/net/atlantic/rte_pmd_atlantic.h | 44 +++++++++++++++++++++++++++ 6 files changed, 126 insertions(+) create mode 100644 drivers/net/atlantic/rte_pmd_atlantic.c create mode 100644 drivers/net/atlantic/rte_pmd_atlantic.h diff --git a/drivers/net/atlantic/Makefile b/drivers/net/atlantic/Makefile index 62dcdbffa69c..6e821e013af9 100644 --- a/drivers/net/atlantic/Makefile +++ b/drivers/net/atlantic/Makefile @@ -31,5 +31,9 @@ SRCS-$(CONFIG_RTE_LIBRTE_ATLANTIC_PMD) += hw_atl_utils.c SRCS-$(CONFIG_RTE_LIBRTE_ATLANTIC_PMD) += hw_atl_llh.c SRCS-$(CONFIG_RTE_LIBRTE_ATLANTIC_PMD) += hw_atl_utils_fw2x.c SRCS-$(CONFIG_RTE_LIBRTE_ATLANTIC_PMD) += hw_atl_b0.c +SRCS-$(CONFIG_RTE_LIBRTE_ATLANTIC_PMD) += rte_pmd_atlantic.c + +# install this header file +SYMLINK-$(CONFIG_RTE_LIBRTE_ATLANTIC_PMD)-include := rte_pmd_atlantic.h include $(RTE_SDK)/mk/rte.lib.mk diff --git a/drivers/net/atlantic/atl_ethdev.c b/drivers/net/atlantic/atl_ethdev.c index b3a19f96e8c8..90ab8d9c0b1d 100644 --- a/drivers/net/atlantic/atl_ethdev.c +++ b/drivers/net/atlantic/atl_ethdev.c @@ -69,6 +69,10 @@ static void atl_vlan_strip_queue_set(struct rte_eth_dev *dev, static int atl_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type, uint16_t tpid); +/* LEDs */ +static int atl_dev_led_on(struct rte_eth_dev *dev); +static int atl_dev_led_off(struct rte_eth_dev *dev); + /* EEPROM */ static int atl_dev_get_eeprom_length(struct rte_eth_dev *dev); static int atl_dev_get_eeprom(struct rte_eth_dev *dev, @@ -273,6 +277,10 @@ static const struct eth_dev_ops atl_eth_dev_ops = { .rx_descriptor_status = atl_dev_rx_descriptor_status, .tx_descriptor_status = atl_dev_tx_descriptor_status, + /* LEDs */ + .dev_led_on = atl_dev_led_on, + .dev_led_off = atl_dev_led_off, + /* EEPROM */ .get_eeprom_length = atl_dev_get_eeprom_length, .get_eeprom = atl_dev_get_eeprom, @@ -1183,6 +1191,51 @@ atl_dev_interrupt_handler(void *param) atl_dev_interrupt_action(dev, dev->intr_handle); } +/** + * LED ON Enables software controllable LED blinking. + * LED status then is independent of link status or traffic + */ +static int +atl_dev_led_on(struct rte_eth_dev *dev) +{ + struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private); + + if (hw->aq_fw_ops->led_control == NULL) + return -ENOTSUP; + + return hw->aq_fw_ops->led_control(hw, + AQ_HW_LED_BLINK | + (AQ_HW_LED_BLINK << 2) | + (AQ_HW_LED_BLINK << 4)); +} + +/** + * LED OFF disables software controllable LED blinking + * LED is controlled by default logic and depends on link status and + * traffic activity + */ +static int +atl_dev_led_off(struct rte_eth_dev *dev) +{ + struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private); + + if (hw->aq_fw_ops->led_control == NULL) + return -ENOTSUP; + + return hw->aq_fw_ops->led_control(hw, AQ_HW_LED_DEFAULT); +} + +int +atl_dev_led_control(struct rte_eth_dev *dev, int control) +{ + struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private); + + if (hw->aq_fw_ops->led_control == NULL) + return -ENOTSUP; + + return hw->aq_fw_ops->led_control(hw, control); +} + #define SFP_EEPROM_SIZE 0xff static int diff --git a/drivers/net/atlantic/atl_ethdev.h b/drivers/net/atlantic/atl_ethdev.h index 69612a016089..51d6042088c7 100644 --- a/drivers/net/atlantic/atl_ethdev.h +++ b/drivers/net/atlantic/atl_ethdev.h @@ -104,4 +104,7 @@ uint16_t atl_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t atl_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts); +int +atl_dev_led_control(struct rte_eth_dev *dev, int control); + #endif /* _ATLANTIC_ETHDEV_H_ */ diff --git a/drivers/net/atlantic/meson.build b/drivers/net/atlantic/meson.build index 7575e471e306..8e992f2406f6 100644 --- a/drivers/net/atlantic/meson.build +++ b/drivers/net/atlantic/meson.build @@ -11,8 +11,11 @@ sources = files( 'hw_atl/hw_atl_llh.c', 'hw_atl/hw_atl_utils_fw2x.c', 'hw_atl/hw_atl_utils.c', + 'rte_pmd_atlantic.c', ) deps += ['eal'] allow_experimental_apis = true + +install_headers('rte_pmd_atlantic.h') diff --git a/drivers/net/atlantic/rte_pmd_atlantic.c b/drivers/net/atlantic/rte_pmd_atlantic.c new file mode 100644 index 000000000000..4cb09baf2afc --- /dev/null +++ b/drivers/net/atlantic/rte_pmd_atlantic.c @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2018 Aquantia Corporation + */ + +#include + +#include "rte_pmd_atlantic.h" +#include "atl_ethdev.h" + +int rte_pmd_atl_dev_led_control(int port, int control) +{ + struct rte_eth_dev *dev; + + RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV); + + dev = &rte_eth_devices[port]; + + return atl_dev_led_control(dev, control); +} diff --git a/drivers/net/atlantic/rte_pmd_atlantic.h b/drivers/net/atlantic/rte_pmd_atlantic.h new file mode 100644 index 000000000000..1c80330911a0 --- /dev/null +++ b/drivers/net/atlantic/rte_pmd_atlantic.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2018 Aquantia Corporation + */ + +/** + * @file rte_pmd_atlantic.h + * atlantic PMD specific functions. + * + **/ + +#ifndef _PMD_ATLANTIC_H_ +#define _PMD_ATLANTIC_H_ + +#include + +#define RTE_PMD_AQ_HW_LED_OFF 0x3U +#define RTE_PMD_AQ_HW_LED_BLINK 0x2U +#define RTE_PMD_AQ_HW_LED_ON 0x1U +#define RTE_PMD_AQ_HW_LED_DEFAULT 0x0U + +/** + * This is a custom API for adapter's LED controls. + * + * @param dev + * Ethernet device to apply control to + * @param control + * 6 bit value (3 leds each 2bit): + * - bits 0-1: LED0 control + * - bits 2-3: LED1 control + * - bits 4-5: LED2 control + * Each two bit control value is: + * - 0: Firmware manages this LED activity + * - 1: Permanent ON + * - 2: Blinking + * - 3: Permanent OFF + * + * @return + * - (0) if successful. + * - (-ENOTSUP) if hardware doesn't support. + */ +int rte_pmd_atl_dev_led_control(int port, int control); + + +#endif /* _PMD_ATLANTIC_H_ */ From patchwork Sat Sep 29 10:30:35 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Russkikh X-Patchwork-Id: 45685 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 8FD601B445; Sat, 29 Sep 2018 12:33:06 +0200 (CEST) Received: from NAM05-DM3-obe.outbound.protection.outlook.com (mail-eopbgr730071.outbound.protection.outlook.com [40.107.73.71]) by dpdk.org (Postfix) with ESMTP id D339F1B437 for ; Sat, 29 Sep 2018 12:33:04 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=AQUANTIA1COM.onmicrosoft.com; s=selector1-aquantia-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ekuSTalPJaeS/UYmekRY6x3RppeOyZ3i5bALwXJWbHg=; b=iBI4yFtAGVov/Om6qJryhKXKRDPLoYBw8I7hXBylgkHFNmAVvP0fF7igis3drM2xNAqwkVKe7WwzRmpn3sLKLonnkizecp4kG7YUtFUZ8D/6Z2N3nhxI69P56LGoi9Wi0cBR+MAO5b021/lQdXxccXWnRPgHBgqty332jwK3G54= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Igor.Russkikh@aquantia.com; Received: from ubuntubox.rdc.aquantia.com (95.79.108.179) by BLUPR0701MB1650.namprd07.prod.outlook.com (2a01:111:e400:58c6::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1185.22; Sat, 29 Sep 2018 10:32:57 +0000 From: Igor Russkikh To: dev@dpdk.org Cc: pavel.belous@aquantia.com, igor.russkikh@aquantia.com, Pavel Belous Date: Sat, 29 Sep 2018 13:30:35 +0300 Message-Id: <05d371790dc84affdfaccc387c94b4449298f695.1538215990.git.igor.russkikh@aquantia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [95.79.108.179] X-ClientProxiedBy: VI1P193CA0009.EURP193.PROD.OUTLOOK.COM (2603:10a6:800:bd::19) To BLUPR0701MB1650.namprd07.prod.outlook.com (2a01:111:e400:58c6::20) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: f30a9a6c-2b03-4822-0c90-08d625f6efa9 X-Microsoft-Antispam: BCL:0; PCL:0; RULEID:(7020095)(4652040)(8989299)(4534165)(4627221)(201703031133081)(201702281549075)(8990200)(5600074)(711020)(2017052603328)(7153060)(7193020); SRVR:BLUPR0701MB1650; X-Microsoft-Exchange-Diagnostics: 1; BLUPR0701MB1650; 3:21/jebH/CyECfXthcUx0UDkS6ixhnpl3m1NphrrmICvBBXR4uAZdfScqFXbrbSqi7k5fbc8droR8mlli+NyOC/mK0B1B1QE4BgDl5t36LmW4Zh/M7iAxRJMxg/E8sszYD3otQ8uLyi8ZSdmo4g0RxKI7K6TAqIpoxP/wUgJ+/K3f/UFNxE49pIRoCZ9ExF/YLGkRtu/zxdOR83qhmbue4/CIyvVT0K+U0lp9ROwQitkJgpM1II30CRiLt3ge7+/N; 25:ty3uP29dwkc0vO4W7rBJKCHU5ElcqXZLz4MwsYB054jvR5xeAmqDC6kzgc/mirkAU2qJerurTz0nyeiKzWQ9VsdLvG+26AnOigwvzEq6jC9qJQur1epR0QiD5QQkumyRj8QaJT9s0Rl1JIE5GWXjvakKqjeKngwhS/vKUKE81gtsDIgotWaqCE6PMqMR/rHdENdw+cDovSWG1mV/708Hr7/O9UiuO1L1VaprLcsabm3HnZEYU3DN75Z5AA3PPgvcxtyuALq9pKrOoqQ16tukgtEWZKo5UwGcPWPmPJvrd4h2pf3vdZklwotgHyhtBvgI0bx25tJywQ/hn5EwQLXUrSM6BHnZYlYpNXxtkA2IoAU=; 31:g1bIS0iJf+nTryoklytBP2MKCJ2GWDOZCiiBRaoY8smedWyUOFS204V++jonGQlw+QcpzbDuVhwA3rnm+fP+j+0bCn9S5RmE/o3VWSd1Tq+vlXjK1T/JusLbB93bIa/dwgsjttcuj9KMrX5yI3qhKpfX2yKQl7q5l2BPb3o5UKyrfj8qzvBrkLvn+DEkmTG4Rj6SYkxNSYypbQrzDYEFxffD5Fvkfr5GeRioWpsz1m0= X-MS-TrafficTypeDiagnostic: BLUPR0701MB1650: X-Microsoft-Exchange-Diagnostics: 1; BLUPR0701MB1650; 20:V1eFhr7gxh0+c4lI7ncNq7BpJ9OtDys4ijgjvntJ4raBw1mWzntSU+I9u+v5oNgcrJUx/ZbmsJkvwE4ZisqWa0RpvkPTAtnOFD5oE8M68B2V0irYMCC0ClQ/BJrGXjUd12NSJagqJCeJUvZkKdpoVERt+HIiuqR4ZZ4dAD6iTDdxG3En1gcrMeQ4RsJRHFw+r+6/IAiLFYbPPpSm/ZgGmXUcB7qn6WscvZIHUDGq6Fi8lAaJh+Oh2CYrLhLxke+dNzpL3sYoy6BWJntMzbH5k2SZNQXpD2c3eGzfLpFKYAvm9Oq+96prt88fXC2U8jB5KaZmbc/wtSHhAwkaO2VEf5/e/p9C19MMeEhQ9FdWDc38VEO/WWZ//eu2kFBBfDWGOMRfKCeVqglKtlCgk/R/xsX+G6KmYLqsDDJXn4sQIveA5/kl/o9qIhZeiEqJPt2ZQyvte0vFf00wDj5QPX9l+6ZSp6CjkQOYkcM2PvIRfy3A6nYRFHX5fw2AxDz2ktSW; 4:YNh23zMNox4+8XqHK+LBvTs3OknUt1sbb1TRtnZBavMv/ocVeM1DI+C+eubp9F3TyV2QmIsS11YamTErFimliJaLL5wGYzl5i4MeJzD18+JTnCcGz5TlF7xW8fFpOtPvB5wAWwjAyDpCXBPRCREYRoeULEicTqvRf1LWAPeYi2B5hfsePE8LGFGO6odiyhpBjAqwnBoLWjKjGGsftU1j+rIac6Eov3Vz3xtaqkKVX8Hk3PF2y74veu9SDhm9fqfY5ftJqebvkTU8F5cOxejcBw== X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-MS-Exchange-SenderADCheck: 1 X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(6040522)(2401047)(8121501046)(5005006)(10201501046)(3002001)(93006095)(93001095)(3231355)(944501410)(52105095)(149066)(150057)(6041310)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123558120)(20161123564045)(20161123562045)(20161123560045)(201708071742011)(7699051); SRVR:BLUPR0701MB1650; BCL:0; PCL:0; RULEID:; SRVR:BLUPR0701MB1650; X-Forefront-PRVS: 0810818DA0 X-Forefront-Antispam-Report: SFV:NSPM; SFS:(10009020)(346002)(136003)(396003)(376002)(39850400004)(366004)(189003)(199004)(16526019)(14444005)(446003)(76176011)(2906002)(6916009)(6666003)(97736004)(8676002)(81166006)(81156014)(36756003)(4326008)(316002)(8936002)(50226002)(34290500001)(575784001)(86362001)(5660300001)(68736007)(16586007)(118296001)(72206003)(3846002)(6116002)(53936002)(386003)(105586002)(6486002)(47776003)(66066001)(486006)(25786009)(305945005)(50466002)(44832011)(956004)(2616005)(26005)(107886003)(52116002)(51416003)(7696005)(186003)(476003)(478600001)(2361001)(7736002)(2351001)(48376002)(106356001)(11346002); DIR:OUT; SFP:1101; SCL:1; SRVR:BLUPR0701MB1650; H:ubuntubox.rdc.aquantia.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; Received-SPF: None (protection.outlook.com: aquantia.com does not designate permitted sender hosts) X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; BLUPR0701MB1650; 23:O9RMpUGB0dfx+Jir3SwkTLHw3VOvtpT9933vtXs?= +RM4FwbMxs6J6e89oGXtpODHGFHqtdEiJ2GfDg9yvq/m/4lj+sb2bt7vgF1AgMm3RG3+A4LW+t7g4CbOV/VTHDbn4a1CPuKqeCBwxMIxnJmi2mGUT4ou72IU53Tkvuy4Af8EnnY9TFl13CfrMII30lHgvmrd4IBfxgUq0lSuXE09F1pSHYybKYXQ/PVJ5lhJshnQGM/o+eih3ClSWnoZ50rwHfPSQX7O41WMKnoy0aPvIaa1Pad8KhkbK9h4ubz9n+btWDjOh9dvL5SX5RYc7RVCaHIyjHTokYt1OUSDH+uYEHCfDknZFBZrRIemSCXChTew0ej8vGMb2gjkaXm0I26URoHsomhi7HrRXf4/+4yGgNgmx0oHB410gc+RfR0Dg/qr8I//+nNeKJC7wPj8gEHApdtDYrPnFhKKkdojebRcke5Mvwui1Y50mZXcvXK2iILWMc87glJkc1O8E4uOHMCjJBcyndbDw/YBVg2dXNWszq0omkgr9auVHvaqDE0mUrlblQBrPdOp4ioMSeXY0x2HPhFpSwpb2opuEa+5dfnXo7G3SowTtHDrf+TuD+nPT4QeVH3xl1NDftBY4R4NVFrMp3lyJwi2RKm5buvVnsVFc5EBuhiEdZJ8auqfd5WLZALWrcKh5TMJWQAJ5mK/pDjnfc/gY9Ic66SwvuOHAN1TnenJUy9xFBq6AX5GAcCkxbQ7GrQUjrhnQqmK2wmxBAUPOwJR9pEuXH56YFR0wrJUUfHCA9E2ceIcSTH1ZUMjEhNWq6xYRcKff50qRMVlXuaY5yJhdwZ6U8CiAl4IP0RPj2pg37PH1xKmzA3M3OvixqUw/uyWCH68iP8adVVYmgqvB3TUSIlKfpdk3bCygdzp0tu9S9tmCj1AnVj2NJ4EAVKxA5eDf09TpArd/2i1/AiZaCwXLKSUNKDHC0yUPx1QIhS3ovtsosluf2RgVA0gGUUEkS/I6xMPPbUmS5Fo2yuiYUjc4SGmk0C3RuhAjXMvRNhzNZoW1G1MmXSugtHXgzcQZPADSFBwF5fq/9lpABaNeaCpVvDmf0Au/rw2Oc7tu5jXOFK1/HXkHe7WBpltTTLMJ9hB7TdH6xgFQL0RLL8Gi8x12f68jvO3ficUNJqOdfYUt4qPOhrh5FGqxcIb8FJ6Hg0PfjihPE0B+P4CUNSlZivHgQ7KLQMCKw3Wbe04MCMRhSrly0jyGJlZnV2ypzx+iWRNEMs35Y9vpo4or0+aVF85IocL2tfgrS57yzixapAEzA+9Ysh+fJHlyUigcIQRWT3iXg4KVsXR2wM//8A34 X-Microsoft-Antispam-Message-Info: LuOSKiaCTTqUmjiEuhcjcU5VtLhZCFoN9xCL45Ra8UsgouhTiP7qRby1m709QxceAtF33gojaLnwlUpsWvEDK7uxBwYnSZjmgraGmzgOyNzwWKQCoHNo6fRdrlRcpbMx3Z7wi1hM/PB1YadBw0QP6Up16n8RDbxcgICF+iD0yvftl+AsJdsgYzI5aN3aUKdAzSYXxaJbZXpPm+RvVyiSoxHghDpdFY6NGxtGdhPfl9ELAjqtd4xGn9Xp5LpmXLa2jLx6A+Tmk24WzWY4AYvQm3ip/BfSjhOxJed2dNLEF1vsAqyo2Y45MKlOJc+eqD1hbM4dvV9QioLre1JmSTN4tkyRbdlar4oQ99RBPrI65BI= X-Microsoft-Exchange-Diagnostics: 1; BLUPR0701MB1650; 6:2icL2ODBagvoaDxMVYbZ478y0ixhRWQA/LtChTcRADH6l6dAK6dATe3m5CCIrEPi58giFIKRzrnb2x6yMg5bvK67O1ivI7ZX9wsYgyRMd1mG3lwW6TCIfb055I0okbEWJ3/2f3dpsCC4sP9nKxkQdHzx2fxwcM38UHnEPy6tOHwIEwUSj2eq3mXXpkM59JnHdZ6UGcK0KeCEBf9fFb58oH0BZIZlRS9XMB+lrBI2MVSm7i7lQ+TePY3Sva5THx7cl3JBexiHmFAEfD5XtpbW3O2AqDx0tV82fquh8wzSgSLsBYPxqNqA6hJizNP6yAPfKaYl3kYvIqAOfXMKDrO0TBSIbPsdY4ijdnownzzkzn6twpYbO2xur/fjykDosDjqomQlV5DJl5BRZK+8Ok5sW7TospYdPp72S//cqha0jGyPWsNwtjT+O8CrHeOrrQXSf+B3lQsb0X8/fi+RnUie8A==; 5:Fc8LGDoCmf6cRZTXWoDNcM2P/amW2sOANSLMMfSfBeJT1HGIB5EjzHog0sH75uhBX+/wpNOCVak2p6hUs44EsoN4ppWJbS638+9xN4NHGJefV527ywH/ax89D9uB6h2ZXQOnQXB2ENH4In8+eHUVx3YBJKXzSiH7/Vfwn9kjUn4=; 7:+GeWHLiyu2Sw40oWSwJ2sid+cF2ucw0A2SsvFwxnPld/sPOImYoKZBLFwXSN2P1Y7jji2cDnKjCdE/PgRCJNaznbIV8wN3T9YY+w4X5Nh8FzyDk6F3D+ZrtCFglhBbQ3tG7kJcmSAbpuuUViFCoc8EKL6qJod3bRZzreMPXAKSk84EH9s1crcClVWxxLNRLyQZbp7xqbjt1CAzbht6rVwL5KOKN1iYtTpmGS38zkau2LhxgsmVLTPOFAz8HxKoLd SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: aquantia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Sep 2018 10:32:57.1891 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f30a9a6c-2b03-4822-0c90-08d625f6efa9 X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 83e2e134-991c-4ede-8ced-34d47e38e6b1 X-MS-Exchange-Transport-CrossTenantHeadersStamped: BLUPR0701MB1650 Subject: [dpdk-dev] [PATCH v3 21/22] net/atlantic: support for read MAC registers for debug purposes X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavel Belous Signed-off-by: Igor Russkikh Signed-off-by: Pavel Belous --- drivers/net/atlantic/atl_ethdev.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/drivers/net/atlantic/atl_ethdev.c b/drivers/net/atlantic/atl_ethdev.c index 90ab8d9c0b1d..c69b2536a3e3 100644 --- a/drivers/net/atlantic/atl_ethdev.c +++ b/drivers/net/atlantic/atl_ethdev.c @@ -80,6 +80,9 @@ static int atl_dev_get_eeprom(struct rte_eth_dev *dev, static int atl_dev_set_eeprom(struct rte_eth_dev *dev, struct rte_dev_eeprom_info *eeprom); +/* Regs */ +static int atl_dev_get_regs(struct rte_eth_dev *dev, + struct rte_dev_reg_info *regs); /* Flow control */ static int atl_flow_ctrl_get(struct rte_eth_dev *dev, @@ -238,6 +241,8 @@ static const struct eth_dev_ops atl_eth_dev_ops = { /* Link */ .link_update = atl_dev_link_update, + .get_reg = atl_dev_get_regs, + /* Stats */ .stats_get = atl_dev_stats_get, .xstats_get = atl_dev_xstats_get, @@ -1273,6 +1278,32 @@ atl_dev_set_eeprom(struct rte_eth_dev *dev, struct rte_dev_eeprom_info *eeprom) } static int +atl_dev_get_regs(struct rte_eth_dev *dev, struct rte_dev_reg_info *regs) +{ + struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private); + u32 mif_id; + int err; + + if (regs->data == NULL) { + regs->length = hw_atl_utils_hw_get_reg_length(); + regs->width = sizeof(u32); + return 0; + } + + /* Only full register dump is supported */ + if (regs->length && regs->length != hw_atl_utils_hw_get_reg_length()) + return -ENOTSUP; + + err = hw_atl_utils_hw_get_regs(hw, regs->data); + + /* Device version */ + mif_id = hw_atl_reg_glb_mif_id_get(hw); + regs->version = mif_id & 0xFFU; + + return err; +} + +static int atl_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) { struct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private); From patchwork Sat Sep 29 10:30:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Russkikh X-Patchwork-Id: 45686 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 6C8271B3D7; Sat, 29 Sep 2018 12:33:09 +0200 (CEST) Received: from NAM05-DM3-obe.outbound.protection.outlook.com (mail-eopbgr730053.outbound.protection.outlook.com [40.107.73.53]) by dpdk.org (Postfix) with ESMTP id EDE371B1EB for ; Sat, 29 Sep 2018 12:33:05 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=AQUANTIA1COM.onmicrosoft.com; s=selector1-aquantia-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=iG8xWfGTZKHdSQHcYB+yY06CX+HIaOl3aNjfMTpPDnk=; b=c44VP/0hON9Mesl59S1uL+E+nWkX0DPi/gB4L/sGSPGIn5j5cMypzG/cARk3CYqOTli75yWUF1TSovmmGBPomlBjO24bhtF6Mf1qtWtcK1aKJWNNkEJSKirROObXAWXDTyu+d3UT2l94oD/FxnVu5Qjlsf2gTyO7fSH3Vo4t0g8= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Igor.Russkikh@aquantia.com; Received: from ubuntubox.rdc.aquantia.com (95.79.108.179) by BLUPR0701MB1650.namprd07.prod.outlook.com (2a01:111:e400:58c6::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1185.22; Sat, 29 Sep 2018 10:33:03 +0000 From: Igor Russkikh To: dev@dpdk.org Cc: pavel.belous@aquantia.com, igor.russkikh@aquantia.com Date: Sat, 29 Sep 2018 13:30:36 +0300 Message-Id: <58e11d3d913782f7b756dd2ea4c196e73fde305f.1538215990.git.igor.russkikh@aquantia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [95.79.108.179] X-ClientProxiedBy: VI1P193CA0009.EURP193.PROD.OUTLOOK.COM (2603:10a6:800:bd::19) To BLUPR0701MB1650.namprd07.prod.outlook.com (2a01:111:e400:58c6::20) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: b0869e77-6380-4c85-ca3c-08d625f6f086 X-Microsoft-Antispam: BCL:0; PCL:0; RULEID:(7020095)(4652040)(8989299)(4534165)(4627221)(201703031133081)(201702281549075)(8990200)(5600074)(711020)(2017052603328)(7153060)(7193020); SRVR:BLUPR0701MB1650; X-Microsoft-Exchange-Diagnostics: 1; BLUPR0701MB1650; 3:jqYysph96MZU35nAWkm9DKr2regF1qH6RtFfmZK4G5oqDOsxanxWEl3MVJ6pV+1+POW4hYk+vKrrTnPqZXhHUpYnq870ZXFbugMhDh/sEwj4clum5fXkp9kdcT4zKWoRAj8yn/iaL6AwlZjMQH1XrsEJ5MIsNI/aV7Oex/bhjJEMf8odwWx43ud1bxXMoXtCpbvg1vChXqP4inc+Mw+VeySNW10gfAhJBegqCxdJo+PCFFAYX+ihQWz3sN+o209e; 25:Ylg/UmzL05ERO2FvaqRYz6uB8gw4tvp9ghDV6xVUx1HVqQPIXQMO60jvAT/cSOoaxwKO67On7Yzt+vKAPEEghcJGi7BZRK6lyALE0aP8r53B6yaz/YJp7849690rEfBhqK9EaU9eC7AJ0BDGS6C66NfrjbhRo60fN8Nss9aalwiPse10KPwmQFiUTkCjGl9TjiCLEIezqIbVbttrY+Rm/XEP0XoSm6KYNseft3xskv+YXNrKaK33UAJoQ2mFmA2WxZ9906cYohbbquRZkBhXzA4JWW7KXFgRuxOLvppFRtHet9WC5/afrsWzV4EbzPU9cAUaPgR0X+7IlXGWhk89dA==; 31:H4obAByVm7wdkP6+F272a2shXE3EKwW11SK7R1FaWZ+w6NOOj8i6qd9bup9RBS8sL5XgMGWRkURIkEnJ8JJWrj4VlNtyIlY9yEnXUoYOHNIXIexLDW8N7LOr3PJLOhZeBX1zGutfAqsjzmZFWHammdq5xLoG17xJ7p15dv4SmysPxl2qj9uVIAdAddjpfjm9s5JoWI9aQiIYtdGNQvE/0V304cbga6qQlyHjpF5cm5s= X-MS-TrafficTypeDiagnostic: BLUPR0701MB1650: X-Microsoft-Exchange-Diagnostics: 1; BLUPR0701MB1650; 20:ODTl2T9ZTNaCjJ/h8WCzFr9EgO4GheqtQID5S4HS2C9SkuufPai2MtqnR8Q9P+au9AljGh7dqdRx9FyNkVWGziHNRpfYatU32tNXf9brvAa3tcqJ3dTAkpqaZrNV9QqWZMR8tgkl8lKplmfD2zLEp36pRWnXyY02nyk02mOJo2n1aLNLhOPmLXpcf7zT+KwilIzZiCSNAXGsOP553L0F+4JqcNvlYeojf6JjRVjkgqATrJoMLFljLzP6LuBVA7C6tGWxlqh0w4Nh0AcxvRMxH3CwzsCLAFwOuKfrgG4bMk8MSKcs1szdgvxkNfH2+CrjdrdQqBvPgi3nEZKRkrxLGU8elshb3QVnEkgnScg2Zh7R16oTo96x6G8chOt2KT1ETii5qjD395ND1YiJJ3+qsk7NZfn6RbNbwMJ7CCfaEraZP7R5LHdM+UntR1mpGQ7xz8UeB2YXl073kaljOW9YbGZwO6alwbT5cUurcbeck4nqTdk32j2DkZ3w67tZGyy7; 4:BD50lWO8h0aLPVDD1TgPyZteOZulMrzEMtgp+a3MNP6bS0wGT4DWEitlM/lQoBWNagCkyQumjetjSlxR6ML4J0DSDq1UwHfrZ9uBcflZPFrDJw+wB1AijEEVuvKkXx1kuunLtpJ+B4oIKHmvvmnU3bqZLiR2GQLtYp0HyH0MVDaYPRegpJyUBuyhqGFC7FawtX/EQ+N91M8fe4/hblq1crXd0jZBgOgoolsf/TcK3sGSj4s96vJd25hi1Y94xb823U2KhTmTNZSH7ytiWCBXIw== X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-MS-Exchange-SenderADCheck: 1 X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(6040522)(2401047)(8121501046)(5005006)(10201501046)(3002001)(93006095)(93001095)(3231355)(944501410)(52105095)(149066)(150057)(6041310)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123558120)(20161123564045)(20161123562045)(20161123560045)(201708071742011)(7699051); SRVR:BLUPR0701MB1650; BCL:0; PCL:0; RULEID:; SRVR:BLUPR0701MB1650; X-Forefront-PRVS: 0810818DA0 X-Forefront-Antispam-Report: SFV:NSPM; SFS:(10009020)(346002)(136003)(396003)(376002)(39850400004)(366004)(189003)(199004)(16526019)(14444005)(446003)(76176011)(2906002)(6916009)(6666003)(97736004)(8676002)(81166006)(81156014)(36756003)(4326008)(316002)(8936002)(50226002)(34290500001)(86362001)(5660300001)(68736007)(16586007)(118296001)(72206003)(3846002)(6116002)(53936002)(386003)(105586002)(6486002)(47776003)(66066001)(486006)(25786009)(305945005)(50466002)(44832011)(956004)(2616005)(26005)(107886003)(52116002)(51416003)(7696005)(186003)(476003)(478600001)(2361001)(7736002)(2351001)(48376002)(106356001)(11346002); DIR:OUT; SFP:1101; SCL:1; SRVR:BLUPR0701MB1650; H:ubuntubox.rdc.aquantia.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; Received-SPF: None (protection.outlook.com: aquantia.com does not designate permitted sender hosts) X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; BLUPR0701MB1650; 23:d5hJ+uKcSvOwLjhMdsRKV4yZbF1u5QOiYvZkGbU?= 52t7byWrJacwB0ioZJKtMVG/D7c1N27bGn9aTBALIBegCnItlqnpXWkr4EsRl3cL6+5GkNakZv7aDUNlsZKCIZJCmB9HdS+pXqzZEGlNg2/LWREiaAEpnMG/fNu2U5eKIzh56LEHJ5PyGHu4kVKNDypzqic/8+yFLRQO/O5GD5EHIrAlDc2l03VhUcWShaq8dBMEGM03zRZi5Fm10fheZuYhVsCtiAbt45DE4OiRpao/hRz5GdWIR9jUvqtze36WvbMus4EMr0/XsjthaDXjZMn0wGCrIfa2pyvjo6Z0ywvaffyUDFPNj9BRAXrYfkJZbJQQlYa8lu5DR8RfaXrPkXkoHXZd4jI6tBWTL+AAYE6AsGLEJiGC46yIkxr/J0yQLgKyWzIJKSFkU9W2ESgRAwSTHfaAHrJGWlYu9ccKGSMACFyxTqdUrKkO/f/vkTClg50fzKXTuQ7DLV0c6S54snvZ66mPNe7w43X1u0CSOxMJZk7xmEtiHWEbvNTXz2nVtGrrWO1xJzFkgfznV4kcSadx8brm+7pQliYPlsuwtGXwxNroefr8kLfX8lZj/QBVi7qxhTO17wos67gCmdj+RVnJQiWQJl0+c+/8qiOoNg63IGzjzLcbiO9s7D012BoI+/7LWfDBgpnN5eFHzg4kKvJfDX0Xx9748ZVszFc6QYBaZBRy9cAZ5cs2F4nfHR7kZ9Qfkbf3z6rXrTkvkpn/pikaLHZNC+T0Dz7w4nZ5taYo1oRN1Rv/3d2gwGIaTi/dd8wrwlqQ7LEjFDYgElpBsV1mAaVqCTRSDiIogr5LTjkcpro5zOtZi7B7EjBomeiGJ7JS/HOsQ+WWVz0U+ndij8gRLiNBICLWa8V9UrucSsYlDvDzCO23cZSvJch21lswNGacg7kBtU/H2CJ/GZ4si5kH7mecGCGDjvaGalKdeKdvhKYhxB5AB2aq0VcA7EeGF5rmaZJY2UFbg2uGvUyEAz5Uyl9MulcSqdxZiT5m3OhFLiNIeCC0qiFLTApzlofGvsvcPdLfOA/tIFQJ3X+ZxK01Ir2+Md7GWIjgRqvAAMtZS4AYCHOkYvz7gDQ/22LSMp9RYvO1/JKL+E2u29cvKZRzal2QcxnlDRJDrUB/HI1+lXM36vsZRuaEPCo3bmxEG7K1MABXdIRPkewntG+Lp9F2ZPRm8WQuL4VzeCxmb9t0Bm2KcOdEBNm80neEMYNxXh8Gh5/gWzjMntkp3NcCsqVu4if2R+az4wE6nm4Yz3vsLGCaxUQP8ncdyp0VQXRakko0= X-Microsoft-Antispam-Message-Info: LQUz9YQO/KR4RCF6la6FpJBLvmB8gN/1QZAhZMRT3BcddpXF8rgm2KYv//fmQzwCq64L86oQBc908Nz2NXUjq7/7o/c33CffDtv91NofhFO0kgqFchJpIwRRRdpbHp+sD9EblaJoyq+dGg0ukzV+yxGOlBYopf76gCp2sw9FFcuaxWIDIERvROn7HdBnqd9fnJCuYv/wUYotirRqRxCKZq8WHy6IAJDQJ+r2g5NAnfAClJeCHYUQc17YIgJop4Yzw7U34E8EETcZq5a8KjywrAcKt5iweWrBuEn95fWspNuHT6DosnU9Lj93g4uV7LfjZXyPrGndYwac1Bi922b6O/K48xuj9RJdGph8zQ1zIs4= X-Microsoft-Exchange-Diagnostics: 1; BLUPR0701MB1650; 6:M9ZOROgkoq5nBtub0p8bkfDmv3YKsa17upC2mi8oYIoENgcGoUKLRej3bU0YQ+tKxsvOxT9L5kKtgsPB9GdvZ6+AFNciWZm0yc5TRAlwqSy5xCEkIzplIDe/eFSt7RcCTAiaLz61uIkZ9fksfNMsOnC+WVJJBg0q5vpbQwOWJv5XjtVc/9KdOF+OXcqOrOLW0cp8NL/aviPGhToU4Vls8u4CL7IhdK6/q5J8KKOZo/T3POGNNo+UuJR42C8FnZVEJpFscnh0df4c1PVTE88CtXkGvfj2SA2nlTdu+FMCsd1Fjex58hsnVMhBqLNqrMy1bcrOktxplikXnvqg+FRQ8JbVuBOKYmYPYYND3B/p5dN8+64vRGuQpw2hCADCOsc2kVPgdmBgUCy6JVzso6/ItHn1Ne3ItqgQ7+D3VD5S2PwYE72aOuVy5ndMulG32M6KzyptZhGyzfrZeu3+GRSTYQ==; 5:Z40mTyKapmBTViv7Xi2/aGxAF5KealzgCBqhQWXp1rp7Km8LcgbKTd6mlk2MiLwzH2A+523gNierEfdlkQ8BESUAFfSYlSMWCsS3Zgm3s3Kez/Irn9ezcer5Z4b8ihjk5VosEcGv2faXrT7EQd2pCuX2xa9Ev5C+K67zUPRZeBY=; 7:DXpLj796iH/jZylV71E7F/njJsnT4VsRZMF+ThIY5WPy+SSMeBTZjrtZubsZwRjOxdgq/E+91WqGcQ+xmg3wDFHFgLEqyNBluD/tZb3ab4xXYw/i0pjqBhaoCzDPXahF2cCHefPMAztEvzm4sf4wjxXIh6A9LjaPVpy7nP5gQLqMdg/owe4qrRvTgktz16IBAiGx3/7ju5buPkM59RSocj1yrTAbB+rXfyyDF7S2xpU4SzzwX6VMr5B39s29aGAA SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: aquantia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Sep 2018 10:33:03.7520 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b0869e77-6380-4c85-ca3c-08d625f6f086 X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 83e2e134-991c-4ede-8ced-34d47e38e6b1 X-MS-Exchange-Transport-CrossTenantHeadersStamped: BLUPR0701MB1650 Subject: [dpdk-dev] [PATCH v3 22/22] net/atlantic: documentation and rel notes X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Signed-off-by: Igor Russkikh --- doc/guides/nics/atlantic.rst | 53 ++++++++++++++++++++++++++++++++++ doc/guides/nics/features/atlantic.ini | 37 ++++++++++++++++++++++++ doc/guides/nics/index.rst | 1 + doc/guides/rel_notes/release_18_11.rst | 5 ++++ 4 files changed, 96 insertions(+) create mode 100644 doc/guides/nics/atlantic.rst create mode 100644 doc/guides/nics/features/atlantic.ini diff --git a/doc/guides/nics/atlantic.rst b/doc/guides/nics/atlantic.rst new file mode 100644 index 000000000000..88939359d942 --- /dev/null +++ b/doc/guides/nics/atlantic.rst @@ -0,0 +1,53 @@ +.. SPDX-License-Identifier: BSD-3-Clause + Copyright(c) 2018 Aquantia Corporation. + +Aquantia Atlantic DPDK Driver +============================= + +Atlantic DPDK driver provides DPDK support for Aquantia's AQtion family of chipsets: AQC107/AQC108/AQC109 + +Supported features +^^^^^^^^^^^^^^^^^^ + + +- Base L2 features +- Promiscuous mode +- Port statistics +- Multicast mode +- RSS (Receive Side Scaling) +- Checksum offload +- Jumbo Frame upto 16K + +Configuration Information +^^^^^^^^^^^^^^^^^^^^^^^^^ + +- ``CONFIG_RTE_LIBRTE_ATLANTIC_PMD`` (default ``y``) + +Not yet supported features +^^^^^^^^^^^^^^^^^^^^^^^^^^ + +NOP + +Application Programming Interface +--------------------------------- + +Atlantic NIC supports custom LED pin configuration interface. +For details, refer rte_pmd_atlantic.h header file + +Limitations or Known issues +--------------------------- + +Statistics +~~~~~~~~~~ + +MTU setting +~~~~~~~~~~~ + +Atlantic NIC supports up to 16K jumbo frame size + +Supported Chipsets and NICs +--------------------------- + +- Aquantia AQtion AQC107 10 Gigabit Ethernet Controller +- Aquantia AQtion AQC108 5 Gigabit Ethernet Controller +- Aquantia AQtion AQC109 2.5 Gigabit Ethernet Controller diff --git a/doc/guides/nics/features/atlantic.ini b/doc/guides/nics/features/atlantic.ini new file mode 100644 index 000000000000..2d943ce13212 --- /dev/null +++ b/doc/guides/nics/features/atlantic.ini @@ -0,0 +1,37 @@ +; +; Supported features of the 'atlantic' network poll mode driver. +; +; Refer to default.ini for the full list of available PMD features. +; +[Features] +Speed capabilities = Y +Link status = Y +Link status event = Y +MTU update = Y +Jumbo frame = Y +Promiscuous mode = Y +Allmulticast mode = Y +Unicast MAC filter = Y +VLAN filter = Y +Flow control = Y +CRC offload = Y +VLAN offload = Y +L3 checksum offload = Y +L4 checksum offload = Y +Rx descriptor status = Y +Tx descriptor status = Y +Basic stats = Y +Extended stats = Y +Stats per queue = Y +Linux UIO = Y +x86-32 = Y +x86-64 = Y +Queue start/stop = Y +RSS hash = Y +RSS key update = Y +RSS reta update = Y +Packet type parsing = Y +FW version = Y +EEPROM dump = Y +Registers dump = Y +LED = Y diff --git a/doc/guides/nics/index.rst b/doc/guides/nics/index.rst index 59f6063dce92..7925c2bd86ff 100644 --- a/doc/guides/nics/index.rst +++ b/doc/guides/nics/index.rst @@ -12,6 +12,7 @@ Network Interface Controller Drivers features build_and_test ark + atlantic avp axgbe bnx2x diff --git a/doc/guides/rel_notes/release_18_11.rst b/doc/guides/rel_notes/release_18_11.rst index bc9b74ec44fc..8473516ddb78 100644 --- a/doc/guides/rel_notes/release_18_11.rst +++ b/doc/guides/rel_notes/release_18_11.rst @@ -67,6 +67,11 @@ New Features SR-IOV option in Hyper-V and Azure. This is an alternative to the previous vdev_netvsc, tap, and failsafe drivers combination. +* **Added Ethernet poll mode driver for Aquantia aQtion family of 10G devices.** + + Added the new ``atlantic`` ethernet poll mode driver for Aquantia XGBE devices. + See the :doc:`../nics/atlantic` nic driver guide for more details on this + driver. API Changes -----------