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GET /api/patches/45662/?format=api
{ "id": 45662, "url": "http://patches.dpdk.org/api/patches/45662/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1538208822-9726-2-git-send-email-rasesh.mody@cavium.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1538208822-9726-2-git-send-email-rasesh.mody@cavium.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1538208822-9726-2-git-send-email-rasesh.mody@cavium.com", "date": "2018-09-29T08:14:27", "name": "[01/18] net/qede/base: upgrade to FW 8.37.7.0", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "71da5f082a3b735e5a8c67c74f443db1992a20d5", "submitter": { "id": 569, "url": "http://patches.dpdk.org/api/people/569/?format=api", "name": "Mody, Rasesh", "email": "rasesh.mody@cavium.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1538208822-9726-2-git-send-email-rasesh.mody@cavium.com/mbox/", "series": [ { "id": 1596, "url": "http://patches.dpdk.org/api/series/1596/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=1596", "date": "2018-09-29T08:13:57", "name": "net/qede: base driver update", "version": 1, "mbox": "http://patches.dpdk.org/series/1596/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/45662/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/45662/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 1ACD71B108;\n\tSat, 29 Sep 2018 10:15:52 +0200 (CEST)", "from NAM04-CO1-obe.outbound.protection.outlook.com\n\t(mail-eopbgr690054.outbound.protection.outlook.com [40.107.69.54])\n\tby dpdk.org (Postfix) with ESMTP id DF284D0B2\n\tfor <dev@dpdk.org>; Sat, 29 Sep 2018 10:15:49 +0200 (CEST)", "from BYAPR07MB5365.namprd07.prod.outlook.com (20.177.125.18) by\n\tBYAPR07MB5320.namprd07.prod.outlook.com (20.177.124.225) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n\t15.20.1143.18; Sat, 29 Sep 2018 08:14:27 +0000", "from BYAPR07MB5365.namprd07.prod.outlook.com\n\t([fe80::2047:9647:f196:bde0]) by\n\tBYAPR07MB5365.namprd07.prod.outlook.com\n\t([fe80::2047:9647:f196:bde0%6]) with mapi id 15.20.1143.022;\n\tSat, 29 Sep 2018 08:14:27 +0000" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=CAVIUMNETWORKS.onmicrosoft.com; s=selector1-cavium-com;\n\th=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n\tbh=CiHqdlhOIFuIi1fpR9CmgNstwvxw9yHIY7sxPIXsIr0=;\n\tb=LensDR7542y53SLmH5UdFjYgypWztEUchcMdmMEwVQqDuJ5ln97Zlurpyl63xoB9yAQ5bgmMN0HicNnhZU8MvSv0g8Jdk1MNN0bJ0aQ7pZigfmKYfw+le0fhw5Wi1Jja8jDPQgiACQnOaNk69RZdldr/VGsKdl9O3za21KNz3EE=", "From": "\"Mody, Rasesh\" <Rasesh.Mody@cavium.com>", "To": "\"dev@dpdk.org\" <dev@dpdk.org>", "CC": "\"Mody, Rasesh\" <Rasesh.Mody@cavium.com>, \"ferruh.yigit@intel.com\"\n\t<ferruh.yigit@intel.com>, Dept-Eng DPDK Dev <Dept-EngDPDKDev@cavium.com>", "Thread-Topic": "[PATCH 01/18] net/qede/base: upgrade to FW 8.37.7.0", "Thread-Index": "AQHUV8xw36CJDUN1g0Cnu1sfy3Qlww==", "Date": "Sat, 29 Sep 2018 08:14:27 +0000", "Message-ID": "<1538208822-9726-2-git-send-email-rasesh.mody@cavium.com>", "References": "<1538208822-9726-1-git-send-email-rasesh.mody@cavium.com>", "In-Reply-To": "<1538208822-9726-1-git-send-email-rasesh.mody@cavium.com>", "Accept-Language": "en-US", "Content-Language": "en-US", "X-MS-Has-Attach": "", "X-MS-TNEF-Correlator": "", "x-clientproxiedby": "BYAPR11CA0059.namprd11.prod.outlook.com\n\t(2603:10b6:a03:80::36) To BYAPR07MB5365.namprd07.prod.outlook.com\n\t(2603:10b6:a03:64::18)", "authentication-results": "spf=none (sender IP is )\n\tsmtp.mailfrom=Rasesh.Mody@cavium.com; ", "x-ms-exchange-messagesentrepresentingtype": "1", "x-originating-ip": "[198.186.1.5]", "x-ms-publictraffictype": "Email", "x-microsoft-exchange-diagnostics": "1; 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"0810818DA0", "x-forefront-antispam-report": "SFV:NSPM;\n\tSFS:(10009020)(376002)(366004)(396003)(136003)(346002)(39860400002)(50944005)(199004)(189003)(97736004)(256004)(14454004)(4326008)(11346002)(2501003)(2900100001)(99286004)(54906003)(1730700003)(86362001)(68736007)(446003)(3846002)(575784001)(25786009)(76176011)(5660300001)(2616005)(8676002)(305945005)(8936002)(486006)(107886003)(2351001)(26005)(2906002)(14444005)(5250100002)(71190400001)(5640700003)(36756003)(6436002)(6486002)(53936002)(316002)(16200700003)(53946003)(72206003)(386003)(105586002)(71200400001)(6916009)(102836004)(6512007)(6116002)(6506007)(7736002)(81156014)(81166006)(186003)(52116002)(476003)(478600001)(66066001)(34290500001)(106356001)(39844003)(569006);\n\tDIR:OUT; SFP:1101; SCL:1; SRVR:BYAPR07MB5320;\n\tH:BYAPR07MB5365.namprd07.prod.outlook.com; FPR:; SPF:None; LANG:en;\n\tPTR:InfoNoRecords; A:1; MX:1; ", "received-spf": "None (protection.outlook.com: cavium.com does not designate\n\tpermitted sender hosts)", "x-microsoft-antispam-message-info": "d+6SpHwAy++SfRdjHQ4j52qEtQZcV2guzC1jQQBsEZkAheqoWp6owHaZZxkZZ4S93ps9fKBuVh7AUVOxqOagYG/x/y17Lt3UjQe2hi7tCBf1pX74cvDDASGb5y2Er+yBRx9u/EnPeDdZxGCyUwfqhM3zlbRWPE/1xgrLrbgM/6E2lNZavbDLHeNOBbt1QFwdL339O84kEJfwX3KkeopyoGhnBSimTqr056lA82hD0hBZl/vwpjon1HnzU/V3k5LLc8zoex1FNOI9e3iTe3DP7g4pUAn8U8fVFfD/HCaCRjHFWHxTnAM2IDM2LAo5NXPBgd0jc4QU0z8ebuIKoK/vyGxxsSyyYFZqJexNGoWRmq0=", "spamdiagnosticoutput": "1:99", "spamdiagnosticmetadata": "NSPM", "Content-Type": "text/plain; charset=\"iso-8859-1\"", "Content-Transfer-Encoding": "quoted-printable", "MIME-Version": "1.0", "X-OriginatorOrg": "cavium.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "e7329782-ee05-4976-5e68-08d625e392d4", "X-MS-Exchange-CrossTenant-originalarrivaltime": "29 Sep 2018 08:14:27.7223\n\t(UTC)", "X-MS-Exchange-CrossTenant-fromentityheader": "Hosted", "X-MS-Exchange-CrossTenant-id": "711e4ccf-2e9b-4bcf-a551-4094005b6194", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BYAPR07MB5320", "Subject": "[dpdk-dev] [PATCH 01/18] net/qede/base: upgrade to FW 8.37.7.0", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This patch adds changes to base driver for upgrading to 8.37.3.0 FW.\n\nSigned-off-by: Rasesh Mody <rasesh.mody@cavium.com>\n---\n drivers/net/qede/base/bcm_osal.h | 1 +\n drivers/net/qede/base/common_hsi.h | 15 +-\n drivers/net/qede/base/ecore.h | 5 +-\n drivers/net/qede/base/ecore_dev.c | 16 +-\n drivers/net/qede/base/ecore_hsi_common.h | 57 +++++-\n drivers/net/qede/base/ecore_hsi_debug_tools.h | 15 ++\n drivers/net/qede/base/ecore_hsi_eth.h | 57 +++++-\n drivers/net/qede/base/ecore_init_fw_funcs.c | 93 +++++----\n drivers/net/qede/base/ecore_init_fw_funcs.h | 42 ++--\n drivers/net/qede/base/ecore_iro.h | 164 +++++++++------\n drivers/net/qede/base/ecore_iro_values.h | 42 ++--\n drivers/net/qede/base/ecore_l2.c | 3 +\n drivers/net/qede/base/ecore_l2_api.h | 1 +\n drivers/net/qede/base/ecore_rt_defs.h | 265 ++++++++++++-------------\n drivers/net/qede/base/eth_common.h | 5 +\n drivers/net/qede/base/reg_addr.h | 51 ++---\n drivers/net/qede/qede_main.c | 2 +-\n 17 files changed, 523 insertions(+), 311 deletions(-)", "diff": "diff --git a/drivers/net/qede/base/bcm_osal.h b/drivers/net/qede/base/bcm_osal.h\nindex b43e0b3..70805f6 100644\n--- a/drivers/net/qede/base/bcm_osal.h\n+++ b/drivers/net/qede/base/bcm_osal.h\n@@ -453,5 +453,6 @@ void qede_get_mcp_proto_stats(struct ecore_dev *, enum ecore_mcp_protocol_type,\n \n #define OSAL_DIV_S64(a, b)\t((a) / (b))\n #define OSAL_LLDP_RX_TLVS(p_hwfn, tlv_buf, tlv_size) nothing\n+#define OSAL_DBG_ALLOC_USER_DATA(p_hwfn, user_data_ptr) (0)\n \n #endif /* __BCM_OSAL_H */\ndiff --git a/drivers/net/qede/base/common_hsi.h b/drivers/net/qede/base/common_hsi.h\nindex ca8e59d..2aaf298 100644\n--- a/drivers/net/qede/base/common_hsi.h\n+++ b/drivers/net/qede/base/common_hsi.h\n@@ -95,8 +95,8 @@\n \n \n #define FW_MAJOR_VERSION 8\n-#define FW_MINOR_VERSION 33\n-#define FW_REVISION_VERSION 12\n+#define FW_MINOR_VERSION 37\n+#define FW_REVISION_VERSION 7\n #define FW_ENGINEERING_VERSION 0\n \n /***********************/\n@@ -1033,13 +1033,14 @@ struct db_rdma_dpm_params {\n #define DB_RDMA_DPM_PARAMS_WQE_SIZE_SHIFT 16\n #define DB_RDMA_DPM_PARAMS_RESERVED0_MASK 0x1\n #define DB_RDMA_DPM_PARAMS_RESERVED0_SHIFT 27\n-/* RoCE completion flag */\n-#define DB_RDMA_DPM_PARAMS_COMPLETION_FLG_MASK 0x1\n-#define DB_RDMA_DPM_PARAMS_COMPLETION_FLG_SHIFT 28\n+/* RoCE ack request (will be set 1) */\n+#define DB_RDMA_DPM_PARAMS_ACK_REQUEST_MASK 0x1\n+#define DB_RDMA_DPM_PARAMS_ACK_REQUEST_SHIFT 28\n #define DB_RDMA_DPM_PARAMS_S_FLG_MASK 0x1 /* RoCE S flag */\n #define DB_RDMA_DPM_PARAMS_S_FLG_SHIFT 29\n-#define DB_RDMA_DPM_PARAMS_RESERVED1_MASK 0x1\n-#define DB_RDMA_DPM_PARAMS_RESERVED1_SHIFT 30\n+/* RoCE completion flag for FW use */\n+#define DB_RDMA_DPM_PARAMS_COMPLETION_FLG_MASK 0x1\n+#define DB_RDMA_DPM_PARAMS_COMPLETION_FLG_SHIFT 30\n /* Connection type is iWARP */\n #define DB_RDMA_DPM_PARAMS_CONN_TYPE_IS_IWARP_MASK 0x1\n #define DB_RDMA_DPM_PARAMS_CONN_TYPE_IS_IWARP_SHIFT 31\ndiff --git a/drivers/net/qede/base/ecore.h b/drivers/net/qede/base/ecore.h\nindex cf66c4c..8982214 100644\n--- a/drivers/net/qede/base/ecore.h\n+++ b/drivers/net/qede/base/ecore.h\n@@ -27,8 +27,8 @@\n #include \"mcp_public.h\"\n \n #define ECORE_MAJOR_VERSION\t\t8\n-#define ECORE_MINOR_VERSION\t\t30\n-#define ECORE_REVISION_VERSION\t\t8\n+#define ECORE_MINOR_VERSION\t\t37\n+#define ECORE_REVISION_VERSION\t\t20\n #define ECORE_ENGINEERING_VERSION\t0\n \n #define ECORE_VERSION\t\t\t\t\t\t\t\\\n@@ -660,6 +660,7 @@ struct ecore_hwfn {\n #endif\n \n \tstruct dbg_tools_data\t\tdbg_info;\n+\tvoid\t\t\t\t*dbg_user_info;\n \n \tstruct z_stream_s\t\t*stream;\n \ndiff --git a/drivers/net/qede/base/ecore_dev.c b/drivers/net/qede/base/ecore_dev.c\nindex d91fe27..b83f003 100644\n--- a/drivers/net/qede/base/ecore_dev.c\n+++ b/drivers/net/qede/base/ecore_dev.c\n@@ -456,6 +456,12 @@ static void ecore_qm_info_free(struct ecore_hwfn *p_hwfn)\n \tOSAL_FREE(p_hwfn->p_dev, qm_info->wfq_data);\n }\n \n+static void ecore_dbg_user_data_free(struct ecore_hwfn *p_hwfn)\n+{\n+\tOSAL_FREE(p_hwfn->p_dev, p_hwfn->dbg_user_info);\n+\tp_hwfn->dbg_user_info = OSAL_NULL;\n+}\n+\n void ecore_resc_free(struct ecore_dev *p_dev)\n {\n \tint i;\n@@ -483,6 +489,7 @@ void ecore_resc_free(struct ecore_dev *p_dev)\n \t\tecore_l2_free(p_hwfn);\n \t\tecore_dmae_info_free(p_hwfn);\n \t\tecore_dcbx_info_free(p_hwfn);\n+\t\tecore_dbg_user_data_free(p_hwfn);\n \t\t/* @@@TBD Flush work-queue ? */\n \n \t\t/* destroy doorbell recovery mechanism */\n@@ -1334,7 +1341,14 @@ enum _ecore_status_t ecore_resc_alloc(struct ecore_dev *p_dev)\n \t\t\t\t \"Failed to allocate memory for dcbx structure\\n\");\n \t\t\tgoto alloc_err;\n \t\t}\n-\t}\n+\n+\t\trc = OSAL_DBG_ALLOC_USER_DATA(p_hwfn, &p_hwfn->dbg_user_info);\n+\t\tif (rc) {\n+\t\t\tDP_NOTICE(p_hwfn, false,\n+\t\t\t\t \"Failed to allocate dbg user info structure\\n\");\n+\t\t\tgoto alloc_err;\n+\t\t}\n+\t} /* hwfn loop */\n \n \tp_dev->reset_stats = OSAL_ZALLOC(p_dev, GFP_KERNEL,\n \t\t\t\t\t sizeof(*p_dev->reset_stats));\ndiff --git a/drivers/net/qede/base/ecore_hsi_common.h b/drivers/net/qede/base/ecore_hsi_common.h\nindex 2d761b9..6d4a4dd 100644\n--- a/drivers/net/qede/base/ecore_hsi_common.h\n+++ b/drivers/net/qede/base/ecore_hsi_common.h\n@@ -922,7 +922,11 @@ struct core_rx_start_ramrod_data {\n \tstruct core_rx_action_on_error action_on_error;\n /* set when in GSI offload mode on ROCE connection */\n \tu8 gsi_offload_flag;\n-\tu8 reserved[6];\n+/* If set, the inner vlan (802.1q tag) priority that is written to cqe will be\n+ * zero out, used for TenantDcb\n+ */\n+\tu8 wipe_inner_vlan_pri_en;\n+\tu8 reserved[5];\n };\n \n \n@@ -1044,7 +1048,11 @@ struct core_tx_start_ramrod_data {\n \t__le16 qm_pq_id /* QM PQ ID */;\n /* set when in GSI offload mode on ROCE connection */\n \tu8 gsi_offload_flag;\n-\tu8 resrved[3];\n+/* vport id of the current connection, used to access non_rdma_in_to_in_pri_map\n+ * which is per vport\n+ */\n+\tu8 vport_id;\n+\tu8 resrved[2];\n };\n \n \n@@ -1171,6 +1179,25 @@ struct eth_rx_rate_limit {\n };\n \n \n+/* Update RSS indirection table entry command. One outstanding command supported\n+ * per PF.\n+ */\n+struct eth_tstorm_rss_update_data {\n+/* Valid flag. Driver must set this flag, FW clear valid flag when ready for new\n+ * RSS update command.\n+ */\n+\tu8 valid;\n+/* Global VPORT ID. If RSS is disable for VPORT, RSS update command will be\n+ * ignored.\n+ */\n+\tu8 vport_id;\n+\tu8 ind_table_index /* RSS indirect table index that will be updated. */;\n+\tu8 reserved;\n+\t__le16 ind_table_value /* RSS indirect table new value. */;\n+\t__le16 reserved1 /* reserved. */;\n+};\n+\n+\n struct eth_ustorm_per_pf_stat {\n /* number of total ucast bytes received on loopback port without errors */\n \tstruct regpair rcv_lb_ucast_bytes;\n@@ -1463,6 +1490,10 @@ struct pf_start_tunnel_config {\n * FW will use a default port\n */\n \tu8 set_geneve_udp_port_flg;\n+/* Set no-innet-L2 VXLAN tunnel UDP destination port to\n+ * no_inner_l2_vxlan_udp_port. If not set - FW will use a default port\n+ */\n+\tu8 set_no_inner_l2_vxlan_udp_port_flg;\n \tu8 tunnel_clss_vxlan /* Rx classification scheme for VXLAN tunnel. */;\n /* Rx classification scheme for l2 GENEVE tunnel. */\n \tu8 tunnel_clss_l2geneve;\n@@ -1470,11 +1501,15 @@ struct pf_start_tunnel_config {\n \tu8 tunnel_clss_ipgeneve;\n \tu8 tunnel_clss_l2gre /* Rx classification scheme for l2 GRE tunnel. */;\n \tu8 tunnel_clss_ipgre /* Rx classification scheme for ip GRE tunnel. */;\n-\tu8 reserved;\n /* VXLAN tunnel UDP destination port. Valid if set_vxlan_udp_port_flg=1 */\n \t__le16 vxlan_udp_port;\n /* GENEVE tunnel UDP destination port. Valid if set_geneve_udp_port_flg=1 */\n \t__le16 geneve_udp_port;\n+/* no-innet-L2 VXLAN tunnel UDP destination port. Valid if\n+ * set_no_inner_l2_vxlan_udp_port_flg=1\n+ */\n+\t__le16 no_inner_l2_vxlan_udp_port;\n+\t__le16 reserved[3];\n };\n \n /*\n@@ -1547,6 +1582,8 @@ struct pf_update_tunnel_config {\n \tu8 set_vxlan_udp_port_flg;\n /* Update GENEVE tunnel UDP destination port. */\n \tu8 set_geneve_udp_port_flg;\n+/* Update no-innet-L2 VXLAN tunnel UDP destination port. */\n+\tu8 set_no_inner_l2_vxlan_udp_port_flg;\n \tu8 tunnel_clss_vxlan /* Classification scheme for VXLAN tunnel. */;\n /* Classification scheme for l2 GENEVE tunnel. */\n \tu8 tunnel_clss_l2geneve;\n@@ -1554,9 +1591,12 @@ struct pf_update_tunnel_config {\n \tu8 tunnel_clss_ipgeneve;\n \tu8 tunnel_clss_l2gre /* Classification scheme for l2 GRE tunnel. */;\n \tu8 tunnel_clss_ipgre /* Classification scheme for ip GRE tunnel. */;\n+\tu8 reserved;\n \t__le16 vxlan_udp_port /* VXLAN tunnel UDP destination port. */;\n \t__le16 geneve_udp_port /* GENEVE tunnel UDP destination port. */;\n-\t__le16 reserved;\n+/* no-innet-L2 VXLAN tunnel UDP destination port. */\n+\t__le16 no_inner_l2_vxlan_udp_port;\n+\t__le16 reserved1[3];\n };\n \n /*\n@@ -1686,6 +1726,13 @@ struct rl_update_ramrod_data {\n /* ID of last RL, that will be updated. If clear, single RL will updated. */\n \tu8 rl_id_last;\n \tu8 rl_dc_qcn_flg /* If set, RL will used for DCQCN. */;\n+/* If set, alpha will be reset to 1 when the state machine is idle. */\n+\tu8 dcqcn_reset_alpha_on_idle;\n+/* Byte counter threshold to change rate increase stage. */\n+\tu8 rl_bc_stage_th;\n+/* Timer threshold to change rate increase stage. */\n+\tu8 rl_timer_stage_th;\n+\tu8 reserved1;\n \t__le32 rl_bc_rate /* Byte Counter Limit. */;\n \t__le16 rl_max_rate /* Maximum rate in 1.6 Mbps resolution. */;\n \t__le16 rl_r_ai /* Active increase rate. */;\n@@ -1694,7 +1741,7 @@ struct rl_update_ramrod_data {\n \t__le32 dcqcn_k_us /* DCQCN Alpha update interval. */;\n \t__le32 dcqcn_timeuot_us /* DCQCN timeout. */;\n \t__le32 qcn_timeuot_us /* QCN timeout. */;\n-\t__le32 reserved[2];\n+\t__le32 reserved2;\n };\n \n \ndiff --git a/drivers/net/qede/base/ecore_hsi_debug_tools.h b/drivers/net/qede/base/ecore_hsi_debug_tools.h\nindex bf54872..085af0a 100644\n--- a/drivers/net/qede/base/ecore_hsi_debug_tools.h\n+++ b/drivers/net/qede/base/ecore_hsi_debug_tools.h\n@@ -1091,6 +1091,15 @@ struct idle_chk_data {\n };\n \n /*\n+ * Pretend parameters\n+ */\n+struct pretend_params {\n+\tu8 split_type /* Pretend split type (from enum init_split_types) */;\n+\tu8 reserved;\n+\tu16 split_id /* Preted split ID (within the pretend split type) */;\n+};\n+\n+/*\n * Debug Tools data (per HW function)\n */\n struct dbg_tools_data {\n@@ -1102,11 +1111,17 @@ struct dbg_tools_data {\n \tu8 block_in_reset[88];\n \tu8 chip_id /* Chip ID (from enum chip_ids) */;\n \tu8 platform_id /* Platform ID */;\n+\tu8 num_ports /* Number of ports in the chip */;\n+\tu8 num_pfs_per_port /* Number of PFs in each port */;\n+\tu8 num_vfs /* Number of VFs in the chip */;\n \tu8 initialized /* Indicates if the data was initialized */;\n \tu8 use_dmae /* Indicates if DMAE should be used */;\n+\tu8 reserved;\n+\tstruct pretend_params pretend /* Current pretend parameters */;\n /* Numbers of registers that were read since last log */\n \tu32 num_regs_read;\n };\n \n \n+\n #endif /* __ECORE_HSI_DEBUG_TOOLS__ */\ndiff --git a/drivers/net/qede/base/ecore_hsi_eth.h b/drivers/net/qede/base/ecore_hsi_eth.h\nindex 6b51230..158ca67 100644\n--- a/drivers/net/qede/base/ecore_hsi_eth.h\n+++ b/drivers/net/qede/base/ecore_hsi_eth.h\n@@ -832,6 +832,26 @@ enum eth_filter_type {\n \n \n /*\n+ * inner to inner vlan priority translation configurations\n+ */\n+struct eth_in_to_in_pri_map_cfg {\n+/* If set, non_rdma_in_to_in_pri_map or rdma_in_to_in_pri_map will be used for\n+ * inner to inner priority mapping depending on protocol type\n+ */\n+\tu8 inner_vlan_pri_remap_en;\n+\tu8 reserved[7];\n+/* Map for inner to inner vlan priority translation for Non RDMA protocols, used\n+ * for TenantDcb. Set inner_vlan_pri_remap_en, when init the map.\n+ */\n+\tu8 non_rdma_in_to_in_pri_map[8];\n+/* Map for inner to inner vlan priority translation for RDMA protocols, used for\n+ * TenantDcb. Set inner_vlan_pri_remap_en, when init the map.\n+ */\n+\tu8 rdma_in_to_in_pri_map[8];\n+};\n+\n+\n+/*\n * eth IPv4 Fragment Type\n */\n enum eth_ipv4_frag_type {\n@@ -1030,8 +1050,11 @@ struct eth_vport_rx_mode {\n /* accept all broadcast packets (subject to vlan) */\n #define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_MASK 0x1\n #define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_SHIFT 5\n-#define ETH_VPORT_RX_MODE_RESERVED1_MASK 0x3FF\n-#define ETH_VPORT_RX_MODE_RESERVED1_SHIFT 6\n+/* accept any VNI in tunnel VNI classification. Used for default queue. */\n+#define ETH_VPORT_RX_MODE_ACCEPT_ANY_VNI_MASK 0x1\n+#define ETH_VPORT_RX_MODE_ACCEPT_ANY_VNI_SHIFT 6\n+#define ETH_VPORT_RX_MODE_RESERVED1_MASK 0x1FF\n+#define ETH_VPORT_RX_MODE_RESERVED1_SHIFT 7\n };\n \n \n@@ -1357,6 +1380,20 @@ struct tx_queue_update_ramrod_data {\n };\n \n \n+/*\n+ * Inner to Inner VLAN priority map update mode\n+ */\n+enum update_in_to_in_pri_map_mode_enum {\n+/* Inner to Inner VLAN priority map update Disabled */\n+\tETH_IN_TO_IN_PRI_MAP_UPDATE_DISABLED,\n+/* Update Inner to Inner VLAN priority map for non RDMA protocols */\n+\tETH_IN_TO_IN_PRI_MAP_UPDATE_NON_RDMA_TBL,\n+/* Update Inner to Inner VLAN priority map for RDMA protocols */\n+\tETH_IN_TO_IN_PRI_MAP_UPDATE_RDMA_TBL,\n+\tMAX_UPDATE_IN_TO_IN_PRI_MAP_MODE_ENUM\n+};\n+\n+\n \n /*\n * Ramrod data for vport update ramrod\n@@ -1405,7 +1442,12 @@ struct vport_start_ramrod_data {\n \tu8 ctl_frame_mac_check_en;\n /* If set, control frames will be filtered according to ethtype check. */\n \tu8 ctl_frame_ethtype_check_en;\n-\tu8 reserved[1];\n+/* If set, the inner vlan (802.1q tag) priority that is written to cqe will be\n+ * zero out, used for TenantDcb\n+ */\n+\tu8 wipe_inner_vlan_pri_en;\n+/* inner to inner vlan priority translation configurations */\n+\tstruct eth_in_to_in_pri_map_cfg in_to_in_vlan_pri_map_cfg;\n };\n \n \n@@ -1473,7 +1515,14 @@ struct vport_update_ramrod_data_cmn {\n \tu8 ctl_frame_mac_check_en;\n /* If set, control frames will be filtered according to ethtype check. */\n \tu8 ctl_frame_ethtype_check_en;\n-\tu8 reserved[15];\n+/* Indicates to update RDMA or NON-RDMA vlan remapping priority table according\n+ * to update_in_to_in_pri_map_mode_enum, used for TenantDcb (use enum\n+ * update_in_to_in_pri_map_mode_enum)\n+ */\n+\tu8 update_in_to_in_pri_map_mode;\n+/* Map for inner to inner vlan priority translation, used for TenantDcb. */\n+\tu8 in_to_in_pri_map[8];\n+\tu8 reserved[6];\n };\n \n struct vport_update_ramrod_mcast {\ndiff --git a/drivers/net/qede/base/ecore_init_fw_funcs.c b/drivers/net/qede/base/ecore_init_fw_funcs.c\nindex b8496cb..cfc1156 100644\n--- a/drivers/net/qede/base/ecore_init_fw_funcs.c\n+++ b/drivers/net/qede/base/ecore_init_fw_funcs.c\n@@ -1665,7 +1665,7 @@ void ecore_gft_config(struct ecore_hwfn *p_hwfn,\n \t\t\t bool ipv6,\n \t\t\t enum gft_profile_type profile_type)\n {\n-\tu32 reg_val, cam_line, ram_line_lo, ram_line_hi;\n+\tu32 reg_val, cam_line, ram_line_lo, ram_line_hi, search_non_ip_as_gft;\n \n \tif (!ipv6 && !ipv4)\n \t\tDP_NOTICE(p_hwfn, true, \"gft_config: must accept at least on of - ipv4 or ipv6'\\n\");\n@@ -1729,6 +1729,9 @@ void ecore_gft_config(struct ecore_hwfn *p_hwfn,\n \tram_line_lo = 0;\n \tram_line_hi = 0;\n \n+\t/* Search no IP as GFT */\n+\tsearch_non_ip_as_gft = 0;\n+\n \t/* Tunnel type */\n \tSET_FIELD(ram_line_lo, GFT_RAM_LINE_TUNNEL_DST_PORT, 1);\n \tSET_FIELD(ram_line_lo, GFT_RAM_LINE_TUNNEL_OVER_IP_PROTOCOL, 1);\n@@ -1752,8 +1755,13 @@ void ecore_gft_config(struct ecore_hwfn *p_hwfn,\n \t\tSET_FIELD(ram_line_lo, GFT_RAM_LINE_ETHERTYPE, 1);\n \t} else if (profile_type == GFT_PROFILE_TYPE_TUNNEL_TYPE) {\n \t\tSET_FIELD(ram_line_lo, GFT_RAM_LINE_TUNNEL_ETHERTYPE, 1);\n+\n+\t\t/* Allow tunneled traffic without inner IP */\n+\t\tsearch_non_ip_as_gft = 1;\n \t}\n \n+\tecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_NON_IP_AS_GFT,\n+\t\t search_non_ip_as_gft);\n \tecore_wr(p_hwfn, p_ptt,\n \t\t PRS_REG_GFT_PROFILE_MASK_RAM + RAM_LINE_SIZE * pf_id,\n \t\t ram_line_lo);\n@@ -1996,52 +2004,49 @@ void ecore_enable_context_validation(struct ecore_hwfn *p_hwfn,\n \tecore_wr(p_hwfn, p_ptt, CDU_REG_TCFC_CTX_VALID0, ctx_validation);\n }\n \n-#define RSS_IND_TABLE_BASE_ADDR 4112\n-#define RSS_IND_TABLE_VPORT_SIZE 16\n-#define RSS_IND_TABLE_ENTRY_PER_LINE 8\n \n-/* Update RSS indirection table entry. */\n-void ecore_update_eth_rss_ind_table_entry(struct ecore_hwfn *p_hwfn,\n-\t\t\t\t\t struct ecore_ptt *p_ptt,\n-\t\t\t\t\t u8 rss_id,\n-\t\t\t\t\t u8 ind_table_index,\n-\t\t\t\t\t u16 ind_table_value)\n+/*******************************************************************************\n+ * File name : rdma_init.c\n+ * Author : Michael Shteinbok\n+ *******************************************************************************\n+ *******************************************************************************\n+ * Description:\n+ * RDMA HSI functions\n+ *\n+ *******************************************************************************\n+ * Notes: This is the input to the auto generated file drv_init_fw_funcs.c\n+ *\n+ *******************************************************************************\n+ */\n+static u32 ecore_get_rdma_assert_ram_addr(struct ecore_hwfn *p_hwfn,\n+\t\t\t\t\t u8 storm_id)\n {\n-\tu32 cnt, rss_addr;\n-\tu32 *reg_val;\n-\tu16 rss_ind_entry[RSS_IND_TABLE_ENTRY_PER_LINE];\n-\tu16 rss_ind_mask[RSS_IND_TABLE_ENTRY_PER_LINE];\n-\n-\t/* get entry address */\n-\trss_addr = RSS_IND_TABLE_BASE_ADDR +\n-\t\t RSS_IND_TABLE_VPORT_SIZE * rss_id +\n-\t\t ind_table_index / RSS_IND_TABLE_ENTRY_PER_LINE;\n-\n-\t/* prepare update command */\n-\tind_table_index %= RSS_IND_TABLE_ENTRY_PER_LINE;\n-\n-\tfor (cnt = 0; cnt < RSS_IND_TABLE_ENTRY_PER_LINE; cnt++) {\n-\t\tif (cnt == ind_table_index) {\n-\t\t\trss_ind_entry[cnt] = ind_table_value;\n-\t\t\trss_ind_mask[cnt] = 0xFFFF;\n-\t\t} else {\n-\t\t\trss_ind_entry[cnt] = 0;\n-\t\t\trss_ind_mask[cnt] = 0;\n-\t\t}\n+\tswitch (storm_id) {\n+\tcase 0: return TSEM_REG_FAST_MEMORY + SEM_FAST_REG_INT_RAM +\n+\t\t TSTORM_RDMA_ASSERT_LEVEL_OFFSET(p_hwfn->rel_pf_id);\n+\tcase 1: return MSEM_REG_FAST_MEMORY + SEM_FAST_REG_INT_RAM +\n+\t\t MSTORM_RDMA_ASSERT_LEVEL_OFFSET(p_hwfn->rel_pf_id);\n+\tcase 2: return USEM_REG_FAST_MEMORY + SEM_FAST_REG_INT_RAM +\n+\t\t USTORM_RDMA_ASSERT_LEVEL_OFFSET(p_hwfn->rel_pf_id);\n+\tcase 3: return XSEM_REG_FAST_MEMORY + SEM_FAST_REG_INT_RAM +\n+\t\t XSTORM_RDMA_ASSERT_LEVEL_OFFSET(p_hwfn->rel_pf_id);\n+\tcase 4: return YSEM_REG_FAST_MEMORY + SEM_FAST_REG_INT_RAM +\n+\t\t YSTORM_RDMA_ASSERT_LEVEL_OFFSET(p_hwfn->rel_pf_id);\n+\tcase 5: return PSEM_REG_FAST_MEMORY + SEM_FAST_REG_INT_RAM +\n+\t\t PSTORM_RDMA_ASSERT_LEVEL_OFFSET(p_hwfn->rel_pf_id);\n+\n+\tdefault: return 0;\n \t}\n+}\n \n-\t/* Update entry in HW*/\n-\tecore_wr(p_hwfn, p_ptt, RSS_REG_RSS_RAM_ADDR, rss_addr);\n-\n-\treg_val = (u32 *)rss_ind_mask;\n-\tecore_wr(p_hwfn, p_ptt, RSS_REG_RSS_RAM_MASK, reg_val[0]);\n-\tecore_wr(p_hwfn, p_ptt, RSS_REG_RSS_RAM_MASK + 4, reg_val[1]);\n-\tecore_wr(p_hwfn, p_ptt, RSS_REG_RSS_RAM_MASK + 8, reg_val[2]);\n-\tecore_wr(p_hwfn, p_ptt, RSS_REG_RSS_RAM_MASK + 12, reg_val[3]);\n+void ecore_set_rdma_error_level(struct ecore_hwfn *p_hwfn,\n+\t\t\t\tstruct ecore_ptt *p_ptt,\n+\t\t\t\tu8 assert_level[NUM_STORMS])\n+{\n+\tu8 storm_id;\n+\tfor (storm_id = 0; storm_id < NUM_STORMS; storm_id++) {\n+\t\tu32 ram_addr = ecore_get_rdma_assert_ram_addr(p_hwfn, storm_id);\n \n-\treg_val = (u32 *)rss_ind_entry;\n-\tecore_wr(p_hwfn, p_ptt, RSS_REG_RSS_RAM_DATA, reg_val[0]);\n-\tecore_wr(p_hwfn, p_ptt, RSS_REG_RSS_RAM_DATA + 4, reg_val[1]);\n-\tecore_wr(p_hwfn, p_ptt, RSS_REG_RSS_RAM_DATA + 8, reg_val[2]);\n-\tecore_wr(p_hwfn, p_ptt, RSS_REG_RSS_RAM_DATA + 12, reg_val[3]);\n+\t\tecore_wr(p_hwfn, p_ptt, ram_addr, assert_level[storm_id]);\n+\t}\n }\ndiff --git a/drivers/net/qede/base/ecore_init_fw_funcs.h b/drivers/net/qede/base/ecore_init_fw_funcs.h\nindex 1024bb2..3503a90 100644\n--- a/drivers/net/qede/base/ecore_init_fw_funcs.h\n+++ b/drivers/net/qede/base/ecore_init_fw_funcs.h\n@@ -472,21 +472,35 @@ void ecore_memset_task_ctx(void *p_ctx_mem,\n \t\t\t u32 ctx_size,\n \t\t\t u8 ctx_type);\n \n-/**\n- * @brief ecore_update_eth_rss_ind_table_entry - Update RSS indirection table\n- * entry.\n- * The function must run in exclusive mode to prevent wrong RSS configuration.\n+\n+/*******************************************************************************\n+ * File name : rdma_init.h\n+ * Author : Michael Shteinbok\n+ *******************************************************************************\n+ *******************************************************************************\n+ * Description:\n+ * RDMA HSI functions header\n+ *\n+ *******************************************************************************\n+ * Notes: This is the input to the auto generated file drv_init_fw_funcs.h\n *\n- * @param p_hwfn - HW device data\n- * @param p_ptt - ptt window used for writing the registers.\n- * @param rss_id - RSS engine ID.\n- * @param ind_table_index - RSS indirect table index.\n- * @param ind_table_value - RSS indirect table new value.\n+ *******************************************************************************\n */\n-void ecore_update_eth_rss_ind_table_entry(struct ecore_hwfn *p_hwfn,\n-\t\t\t\t\t struct ecore_ptt *p_ptt,\n-\t\t\t\t\t u8 rss_id,\n-\t\t\t\t\t u8 ind_table_index,\n-\t\t\t\t\t u16 ind_table_value);\n+#define NUM_STORMS 6\n+\n+\n+\n+/**\n+ * @brief ecore_set_rdma_error_level - Sets the RDMA assert level.\n+ * If the severity of the error will be\n+ *\t\t\t\t above the level, the FW will assert.\n+ * @param p_hwfn -\t\t HW device data\n+ * @param p_ptt -\t\t ptt window used for writing the registers\n+ * @param assert_level - An array of assert levels for each storm.\n+ */\n+void ecore_set_rdma_error_level(struct ecore_hwfn *p_hwfn,\n+\t\t\t\tstruct ecore_ptt *p_ptt,\n+\t\t\t\tu8 assert_level[NUM_STORMS]);\n+\n \n #endif\ndiff --git a/drivers/net/qede/base/ecore_iro.h b/drivers/net/qede/base/ecore_iro.h\nindex 0569302..12d45c1 100644\n--- a/drivers/net/qede/base/ecore_iro.h\n+++ b/drivers/net/qede/base/ecore_iro.h\n@@ -113,91 +113,129 @@\n /* Tstorm Eth limit Rx rate */\n #define ETH_RX_RATE_LIMIT_OFFSET(pf_id) (IRO[29].base + ((pf_id) * IRO[29].m1))\n #define ETH_RX_RATE_LIMIT_SIZE (IRO[29].size)\n+/* RSS indirection table entry update command per PF offset in TSTORM PF BAR0.\n+ * Use eth_tstorm_rss_update_data for update.\n+ */\n+#define TSTORM_ETH_RSS_UPDATE_OFFSET(pf_id) (IRO[30].base + \\\n+\t((pf_id) * IRO[30].m1))\n+#define TSTORM_ETH_RSS_UPDATE_SIZE (IRO[30].size)\n /* Xstorm queue zone */\n-#define XSTORM_ETH_QUEUE_ZONE_OFFSET(queue_id) (IRO[30].base + \\\n-\t((queue_id) * IRO[30].m1))\n-#define XSTORM_ETH_QUEUE_ZONE_SIZE (IRO[30].size)\n+#define XSTORM_ETH_QUEUE_ZONE_OFFSET(queue_id) (IRO[31].base + \\\n+\t((queue_id) * IRO[31].m1))\n+#define XSTORM_ETH_QUEUE_ZONE_SIZE (IRO[31].size)\n /* Ystorm cqe producer */\n-#define YSTORM_TOE_CQ_PROD_OFFSET(rss_id) (IRO[31].base + \\\n-\t((rss_id) * IRO[31].m1))\n-#define YSTORM_TOE_CQ_PROD_SIZE (IRO[31].size)\n-/* Ustorm cqe producer */\n-#define USTORM_TOE_CQ_PROD_OFFSET(rss_id) (IRO[32].base + \\\n+#define YSTORM_TOE_CQ_PROD_OFFSET(rss_id) (IRO[32].base + \\\n \t((rss_id) * IRO[32].m1))\n-#define USTORM_TOE_CQ_PROD_SIZE (IRO[32].size)\n+#define YSTORM_TOE_CQ_PROD_SIZE (IRO[32].size)\n+/* Ustorm cqe producer */\n+#define USTORM_TOE_CQ_PROD_OFFSET(rss_id) (IRO[33].base + \\\n+\t((rss_id) * IRO[33].m1))\n+#define USTORM_TOE_CQ_PROD_SIZE (IRO[33].size)\n /* Ustorm grq producer */\n-#define USTORM_TOE_GRQ_PROD_OFFSET(pf_id) (IRO[33].base + \\\n-\t((pf_id) * IRO[33].m1))\n-#define USTORM_TOE_GRQ_PROD_SIZE (IRO[33].size)\n+#define USTORM_TOE_GRQ_PROD_OFFSET(pf_id) (IRO[34].base + \\\n+\t((pf_id) * IRO[34].m1))\n+#define USTORM_TOE_GRQ_PROD_SIZE (IRO[34].size)\n /* Tstorm cmdq-cons of given command queue-id */\n-#define TSTORM_SCSI_CMDQ_CONS_OFFSET(cmdq_queue_id) (IRO[34].base + \\\n-\t((cmdq_queue_id) * IRO[34].m1))\n-#define TSTORM_SCSI_CMDQ_CONS_SIZE (IRO[34].size)\n+#define TSTORM_SCSI_CMDQ_CONS_OFFSET(cmdq_queue_id) (IRO[35].base + \\\n+\t((cmdq_queue_id) * IRO[35].m1))\n+#define TSTORM_SCSI_CMDQ_CONS_SIZE (IRO[35].size)\n /* Tstorm (reflects M-Storm) bdq-external-producer of given function ID,\n * BDqueue-id\n */\n-#define TSTORM_SCSI_BDQ_EXT_PROD_OFFSET(func_id, bdq_id) (IRO[35].base + \\\n-\t((func_id) * IRO[35].m1) + ((bdq_id) * IRO[35].m2))\n-#define TSTORM_SCSI_BDQ_EXT_PROD_SIZE (IRO[35].size)\n-/* Mstorm bdq-external-producer of given BDQ resource ID, BDqueue-id */\n-#define MSTORM_SCSI_BDQ_EXT_PROD_OFFSET(func_id, bdq_id) (IRO[36].base + \\\n+#define TSTORM_SCSI_BDQ_EXT_PROD_OFFSET(func_id, bdq_id) (IRO[36].base + \\\n \t((func_id) * IRO[36].m1) + ((bdq_id) * IRO[36].m2))\n-#define MSTORM_SCSI_BDQ_EXT_PROD_SIZE (IRO[36].size)\n+#define TSTORM_SCSI_BDQ_EXT_PROD_SIZE (IRO[36].size)\n+/* Mstorm bdq-external-producer of given BDQ resource ID, BDqueue-id */\n+#define MSTORM_SCSI_BDQ_EXT_PROD_OFFSET(func_id, bdq_id) (IRO[37].base + \\\n+\t((func_id) * IRO[37].m1) + ((bdq_id) * IRO[37].m2))\n+#define MSTORM_SCSI_BDQ_EXT_PROD_SIZE (IRO[37].size)\n /* Tstorm iSCSI RX stats */\n-#define TSTORM_ISCSI_RX_STATS_OFFSET(pf_id) (IRO[37].base + \\\n-\t((pf_id) * IRO[37].m1))\n-#define TSTORM_ISCSI_RX_STATS_SIZE (IRO[37].size)\n-/* Mstorm iSCSI RX stats */\n-#define MSTORM_ISCSI_RX_STATS_OFFSET(pf_id) (IRO[38].base + \\\n+#define TSTORM_ISCSI_RX_STATS_OFFSET(pf_id) (IRO[38].base + \\\n \t((pf_id) * IRO[38].m1))\n-#define MSTORM_ISCSI_RX_STATS_SIZE (IRO[38].size)\n-/* Ustorm iSCSI RX stats */\n-#define USTORM_ISCSI_RX_STATS_OFFSET(pf_id) (IRO[39].base + \\\n+#define TSTORM_ISCSI_RX_STATS_SIZE (IRO[38].size)\n+/* Mstorm iSCSI RX stats */\n+#define MSTORM_ISCSI_RX_STATS_OFFSET(pf_id) (IRO[39].base + \\\n \t((pf_id) * IRO[39].m1))\n-#define USTORM_ISCSI_RX_STATS_SIZE (IRO[39].size)\n-/* Xstorm iSCSI TX stats */\n-#define XSTORM_ISCSI_TX_STATS_OFFSET(pf_id) (IRO[40].base + \\\n+#define MSTORM_ISCSI_RX_STATS_SIZE (IRO[39].size)\n+/* Ustorm iSCSI RX stats */\n+#define USTORM_ISCSI_RX_STATS_OFFSET(pf_id) (IRO[40].base + \\\n \t((pf_id) * IRO[40].m1))\n-#define XSTORM_ISCSI_TX_STATS_SIZE (IRO[40].size)\n-/* Ystorm iSCSI TX stats */\n-#define YSTORM_ISCSI_TX_STATS_OFFSET(pf_id) (IRO[41].base + \\\n+#define USTORM_ISCSI_RX_STATS_SIZE (IRO[40].size)\n+/* Xstorm iSCSI TX stats */\n+#define XSTORM_ISCSI_TX_STATS_OFFSET(pf_id) (IRO[41].base + \\\n \t((pf_id) * IRO[41].m1))\n-#define YSTORM_ISCSI_TX_STATS_SIZE (IRO[41].size)\n-/* Pstorm iSCSI TX stats */\n-#define PSTORM_ISCSI_TX_STATS_OFFSET(pf_id) (IRO[42].base + \\\n+#define XSTORM_ISCSI_TX_STATS_SIZE (IRO[41].size)\n+/* Ystorm iSCSI TX stats */\n+#define YSTORM_ISCSI_TX_STATS_OFFSET(pf_id) (IRO[42].base + \\\n \t((pf_id) * IRO[42].m1))\n-#define PSTORM_ISCSI_TX_STATS_SIZE (IRO[42].size)\n-/* Tstorm FCoE RX stats */\n-#define TSTORM_FCOE_RX_STATS_OFFSET(pf_id) (IRO[43].base + \\\n+#define YSTORM_ISCSI_TX_STATS_SIZE (IRO[42].size)\n+/* Pstorm iSCSI TX stats */\n+#define PSTORM_ISCSI_TX_STATS_OFFSET(pf_id) (IRO[43].base + \\\n \t((pf_id) * IRO[43].m1))\n-#define TSTORM_FCOE_RX_STATS_SIZE (IRO[43].size)\n-/* Pstorm FCoE TX stats */\n-#define PSTORM_FCOE_TX_STATS_OFFSET(pf_id) (IRO[44].base + \\\n+#define PSTORM_ISCSI_TX_STATS_SIZE (IRO[43].size)\n+/* Tstorm FCoE RX stats */\n+#define TSTORM_FCOE_RX_STATS_OFFSET(pf_id) (IRO[44].base + \\\n \t((pf_id) * IRO[44].m1))\n-#define PSTORM_FCOE_TX_STATS_SIZE (IRO[44].size)\n+#define TSTORM_FCOE_RX_STATS_SIZE (IRO[44].size)\n+/* Pstorm FCoE TX stats */\n+#define PSTORM_FCOE_TX_STATS_OFFSET(pf_id) (IRO[45].base + \\\n+\t((pf_id) * IRO[45].m1))\n+#define PSTORM_FCOE_TX_STATS_SIZE (IRO[45].size)\n /* Pstorm RDMA queue statistics */\n-#define PSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id) \\\n-\t(IRO[45].base + ((rdma_stat_counter_id) * IRO[45].m1))\n-#define PSTORM_RDMA_QUEUE_STAT_SIZE (IRO[45].size)\n-/* Tstorm RDMA queue statistics */\n-#define TSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id) (IRO[46].base + \\\n+#define PSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id) (IRO[46].base + \\\n \t((rdma_stat_counter_id) * IRO[46].m1))\n-#define TSTORM_RDMA_QUEUE_STAT_SIZE (IRO[46].size)\n+#define PSTORM_RDMA_QUEUE_STAT_SIZE (IRO[46].size)\n+/* Tstorm RDMA queue statistics */\n+#define TSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id) (IRO[47].base + \\\n+\t((rdma_stat_counter_id) * IRO[47].m1))\n+#define TSTORM_RDMA_QUEUE_STAT_SIZE (IRO[47].size)\n+/* Xstorm error level for assert */\n+#define XSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) (IRO[48].base + \\\n+\t((pf_id) * IRO[48].m1))\n+#define XSTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[48].size)\n+/* Ystorm error level for assert */\n+#define YSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) (IRO[49].base + \\\n+\t((pf_id) * IRO[49].m1))\n+#define YSTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[49].size)\n+/* Pstorm error level for assert */\n+#define PSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) (IRO[50].base + \\\n+\t((pf_id) * IRO[50].m1))\n+#define PSTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[50].size)\n+/* Tstorm error level for assert */\n+#define TSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) (IRO[51].base + \\\n+\t((pf_id) * IRO[51].m1))\n+#define TSTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[51].size)\n+/* Mstorm error level for assert */\n+#define MSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) (IRO[52].base + \\\n+\t((pf_id) * IRO[52].m1))\n+#define MSTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[52].size)\n+/* Ustorm error level for assert */\n+#define USTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) (IRO[53].base + \\\n+\t((pf_id) * IRO[53].m1))\n+#define USTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[53].size)\n /* Xstorm iWARP rxmit stats */\n-#define XSTORM_IWARP_RXMIT_STATS_OFFSET(pf_id) (IRO[47].base + \\\n-\t((pf_id) * IRO[47].m1))\n-#define XSTORM_IWARP_RXMIT_STATS_SIZE (IRO[47].size)\n+#define XSTORM_IWARP_RXMIT_STATS_OFFSET(pf_id) (IRO[54].base + \\\n+\t((pf_id) * IRO[54].m1))\n+#define XSTORM_IWARP_RXMIT_STATS_SIZE (IRO[54].size)\n /* Tstorm RoCE Event Statistics */\n-#define TSTORM_ROCE_EVENTS_STAT_OFFSET(roce_pf_id) (IRO[48].base + \\\n-\t((roce_pf_id) * IRO[48].m1))\n-#define TSTORM_ROCE_EVENTS_STAT_SIZE (IRO[48].size)\n+#define TSTORM_ROCE_EVENTS_STAT_OFFSET(roce_pf_id) (IRO[55].base + \\\n+\t((roce_pf_id) * IRO[55].m1))\n+#define TSTORM_ROCE_EVENTS_STAT_SIZE (IRO[55].size)\n /* DCQCN Received Statistics */\n-#define YSTORM_ROCE_DCQCN_RECEIVED_STATS_OFFSET(roce_pf_id) (IRO[49].base + \\\n-\t((roce_pf_id) * IRO[49].m1))\n-#define YSTORM_ROCE_DCQCN_RECEIVED_STATS_SIZE (IRO[49].size)\n+#define YSTORM_ROCE_DCQCN_RECEIVED_STATS_OFFSET(roce_pf_id) (IRO[56].base + \\\n+\t((roce_pf_id) * IRO[56].m1))\n+#define YSTORM_ROCE_DCQCN_RECEIVED_STATS_SIZE (IRO[56].size)\n+/* RoCE Error Statistics */\n+#define YSTORM_ROCE_ERROR_STATS_OFFSET(roce_pf_id) (IRO[57].base + \\\n+\t((roce_pf_id) * IRO[57].m1))\n+#define YSTORM_ROCE_ERROR_STATS_SIZE (IRO[57].size)\n /* DCQCN Sent Statistics */\n-#define PSTORM_ROCE_DCQCN_SENT_STATS_OFFSET(roce_pf_id) (IRO[50].base + \\\n-\t((roce_pf_id) * IRO[50].m1))\n-#define PSTORM_ROCE_DCQCN_SENT_STATS_SIZE (IRO[50].size)\n+#define PSTORM_ROCE_DCQCN_SENT_STATS_OFFSET(roce_pf_id) (IRO[58].base + \\\n+\t((roce_pf_id) * IRO[58].m1))\n+#define PSTORM_ROCE_DCQCN_SENT_STATS_SIZE (IRO[58].size)\n+/* RoCE CQEs Statistics */\n+#define USTORM_ROCE_CQE_STATS_OFFSET(roce_pf_id) (IRO[59].base + \\\n+\t((roce_pf_id) * IRO[59].m1))\n+#define USTORM_ROCE_CQE_STATS_SIZE (IRO[59].size)\n \n #endif /* __IRO_H__ */\ndiff --git a/drivers/net/qede/base/ecore_iro_values.h b/drivers/net/qede/base/ecore_iro_values.h\nindex 685fa2e..30e632c 100644\n--- a/drivers/net/qede/base/ecore_iro_values.h\n+++ b/drivers/net/qede/base/ecore_iro_values.h\n@@ -7,7 +7,7 @@\n #ifndef __IRO_VALUES_H__\n #define __IRO_VALUES_H__\n \n-static const struct iro iro_arr[51] = {\n+static const struct iro iro_arr[60] = {\n /* YSTORM_FLOW_CONTROL_MODE_OFFSET */\n \t{ 0x0, 0x0, 0x0, 0x0, 0x8},\n /* TSTORM_PORT_STAT_OFFSET(port_id) */\n@@ -29,7 +29,7 @@\n /* YSTORM_INTEG_TEST_DATA_OFFSET */\n \t{ 0x3e38, 0x0, 0x0, 0x0, 0x78},\n /* PSTORM_INTEG_TEST_DATA_OFFSET */\n-\t{ 0x2b78, 0x0, 0x0, 0x0, 0x78},\n+\t{ 0x3ef8, 0x0, 0x0, 0x0, 0x78},\n /* TSTORM_INTEG_TEST_DATA_OFFSET */\n \t{ 0x4c40, 0x0, 0x0, 0x0, 0x78},\n /* MSTORM_INTEG_TEST_DATA_OFFSET */\n@@ -43,7 +43,7 @@\n /* CORE_LL2_USTORM_PER_QUEUE_STAT_OFFSET(core_rx_queue_id) */\n \t{ 0xb820, 0x30, 0x0, 0x0, 0x30},\n /* CORE_LL2_PSTORM_PER_QUEUE_STAT_OFFSET(core_tx_stats_id) */\n-\t{ 0x96c0, 0x30, 0x0, 0x0, 0x30},\n+\t{ 0xa990, 0x30, 0x0, 0x0, 0x30},\n /* MSTORM_QUEUE_STAT_OFFSET(stat_counter_id) */\n \t{ 0x4b68, 0x80, 0x0, 0x0, 0x40},\n /* MSTORM_ETH_PF_PRODS_OFFSET(queue_id) */\n@@ -59,15 +59,17 @@\n /* USTORM_ETH_PF_STAT_OFFSET(pf_id) */\n \t{ 0xe770, 0x60, 0x0, 0x0, 0x60},\n /* PSTORM_QUEUE_STAT_OFFSET(stat_counter_id) */\n-\t{ 0x2d10, 0x80, 0x0, 0x0, 0x38},\n+\t{ 0x4090, 0x80, 0x0, 0x0, 0x38},\n /* PSTORM_ETH_PF_STAT_OFFSET(pf_id) */\n-\t{ 0xf2b8, 0x78, 0x0, 0x0, 0x78},\n+\t{ 0xfea8, 0x78, 0x0, 0x0, 0x78},\n /* PSTORM_CTL_FRAME_ETHTYPE_OFFSET(ethType_id) */\n \t{ 0x1f8, 0x4, 0x0, 0x0, 0x4},\n /* TSTORM_ETH_PRS_INPUT_OFFSET */\n \t{ 0xaf20, 0x0, 0x0, 0x0, 0xf0},\n /* ETH_RX_RATE_LIMIT_OFFSET(pf_id) */\n \t{ 0xb010, 0x8, 0x0, 0x0, 0x8},\n+/* TSTORM_ETH_RSS_UPDATE_OFFSET(pf_id) */\n+\t{ 0xc00, 0x8, 0x0, 0x0, 0x8},\n /* XSTORM_ETH_QUEUE_ZONE_OFFSET(queue_id) */\n \t{ 0x1f8, 0x8, 0x0, 0x0, 0x8},\n /* YSTORM_TOE_CQ_PROD_OFFSET(rss_id) */\n@@ -91,25 +93,41 @@\n /* XSTORM_ISCSI_TX_STATS_OFFSET(pf_id) */\n \t{ 0xa588, 0x50, 0x0, 0x0, 0x20},\n /* YSTORM_ISCSI_TX_STATS_OFFSET(pf_id) */\n-\t{ 0x8700, 0x40, 0x0, 0x0, 0x28},\n+\t{ 0x8f00, 0x40, 0x0, 0x0, 0x28},\n /* PSTORM_ISCSI_TX_STATS_OFFSET(pf_id) */\n-\t{ 0x10300, 0x18, 0x0, 0x0, 0x10},\n+\t{ 0x10e30, 0x18, 0x0, 0x0, 0x10},\n /* TSTORM_FCOE_RX_STATS_OFFSET(pf_id) */\n \t{ 0xde48, 0x48, 0x0, 0x0, 0x38},\n /* PSTORM_FCOE_TX_STATS_OFFSET(pf_id) */\n-\t{ 0x10768, 0x20, 0x0, 0x0, 0x20},\n+\t{ 0x11298, 0x20, 0x0, 0x0, 0x20},\n /* PSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id) */\n-\t{ 0x2d48, 0x80, 0x0, 0x0, 0x10},\n+\t{ 0x40c8, 0x80, 0x0, 0x0, 0x10},\n /* TSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id) */\n \t{ 0x5048, 0x10, 0x0, 0x0, 0x10},\n+/* XSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) */\n+\t{ 0xa928, 0x8, 0x0, 0x0, 0x1},\n+/* YSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) */\n+\t{ 0xa128, 0x8, 0x0, 0x0, 0x1},\n+/* PSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) */\n+\t{ 0x11a30, 0x8, 0x0, 0x0, 0x1},\n+/* TSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) */\n+\t{ 0xf030, 0x8, 0x0, 0x0, 0x1},\n+/* MSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) */\n+\t{ 0x13028, 0x8, 0x0, 0x0, 0x1},\n+/* USTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) */\n+\t{ 0x12c58, 0x8, 0x0, 0x0, 0x1},\n /* XSTORM_IWARP_RXMIT_STATS_OFFSET(pf_id) */\n \t{ 0xc9b8, 0x30, 0x0, 0x0, 0x10},\n /* TSTORM_ROCE_EVENTS_STAT_OFFSET(roce_pf_id) */\n-\t{ 0xed90, 0x10, 0x0, 0x0, 0x10},\n+\t{ 0xed90, 0x28, 0x0, 0x0, 0x28},\n /* YSTORM_ROCE_DCQCN_RECEIVED_STATS_OFFSET(roce_pf_id) */\n-\t{ 0xa520, 0x10, 0x0, 0x0, 0x10},\n+\t{ 0xad20, 0x18, 0x0, 0x0, 0x18},\n+/* YSTORM_ROCE_ERROR_STATS_OFFSET(roce_pf_id) */\n+\t{ 0xaea0, 0x8, 0x0, 0x0, 0x8},\n /* PSTORM_ROCE_DCQCN_SENT_STATS_OFFSET(roce_pf_id) */\n-\t{ 0x13108, 0x8, 0x0, 0x0, 0x8},\n+\t{ 0x13c38, 0x8, 0x0, 0x0, 0x8},\n+/* USTORM_ROCE_CQE_STATS_OFFSET(roce_pf_id) */\n+\t{ 0x13c50, 0x18, 0x0, 0x0, 0x18},\n };\n \n #endif /* __IRO_VALUES_H__ */\ndiff --git a/drivers/net/qede/base/ecore_l2.c b/drivers/net/qede/base/ecore_l2.c\nindex ca4d901..ec40aac 100644\n--- a/drivers/net/qede/base/ecore_l2.c\n+++ b/drivers/net/qede/base/ecore_l2.c\n@@ -608,6 +608,9 @@ enum _ecore_status_t\n \t\tSET_FIELD(state, ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL,\n \t\t\t !!(accept_filter & ECORE_ACCEPT_BCAST));\n \n+\t\tSET_FIELD(state, ETH_VPORT_RX_MODE_ACCEPT_ANY_VNI,\n+\t\t\t !!(accept_filter & ECORE_ACCEPT_ANY_VNI));\n+\n \t\tp_ramrod->rx_mode.state = OSAL_CPU_TO_LE16(state);\n \t\tDP_VERBOSE(p_hwfn, ECORE_MSG_SP,\n \t\t\t \"vport[%02x] p_ramrod->rx_mode.state = 0x%x\\n\",\ndiff --git a/drivers/net/qede/base/ecore_l2_api.h b/drivers/net/qede/base/ecore_l2_api.h\nindex 85034e6..bde825c 100644\n--- a/drivers/net/qede/base/ecore_l2_api.h\n+++ b/drivers/net/qede/base/ecore_l2_api.h\n@@ -137,6 +137,7 @@ struct ecore_filter_accept_flags {\n #define ECORE_ACCEPT_MCAST_MATCHED\t0x08\n #define ECORE_ACCEPT_MCAST_UNMATCHED\t0x10\n #define ECORE_ACCEPT_BCAST\t\t0x20\n+#define ECORE_ACCEPT_ANY_VNI\t\t0x40\n };\n \n enum ecore_filter_config_mode {\ndiff --git a/drivers/net/qede/base/ecore_rt_defs.h b/drivers/net/qede/base/ecore_rt_defs.h\nindex 721b8c1..3860e1a 100644\n--- a/drivers/net/qede/base/ecore_rt_defs.h\n+++ b/drivers/net/qede/base/ecore_rt_defs.h\n@@ -390,147 +390,146 @@\n #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET 39769\n #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_SIZE 16\n #define NIG_REG_TX_EDPM_CTRL_RT_OFFSET 39785\n-#define NIG_REG_ROCE_DUPLICATE_TO_HOST_RT_OFFSET 39786\n-#define NIG_REG_PPF_TO_ENGINE_SEL_RT_OFFSET 39787\n+#define NIG_REG_PPF_TO_ENGINE_SEL_RT_OFFSET 39786\n #define NIG_REG_PPF_TO_ENGINE_SEL_RT_SIZE 8\n-#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_VALUE_RT_OFFSET 39795\n+#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_VALUE_RT_OFFSET 39794\n #define NIG_REG_LLH_PF_CLS_FUNC_FILTER_VALUE_RT_SIZE 1024\n-#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_EN_RT_OFFSET 40819\n+#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_EN_RT_OFFSET 40818\n #define NIG_REG_LLH_PF_CLS_FUNC_FILTER_EN_RT_SIZE 512\n-#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_MODE_RT_OFFSET 41331\n+#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_MODE_RT_OFFSET 41330\n #define NIG_REG_LLH_PF_CLS_FUNC_FILTER_MODE_RT_SIZE 512\n-#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_PROTOCOL_TYPE_RT_OFFSET 41843\n+#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_PROTOCOL_TYPE_RT_OFFSET 41842\n #define NIG_REG_LLH_PF_CLS_FUNC_FILTER_PROTOCOL_TYPE_RT_SIZE 512\n-#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_HDR_SEL_RT_OFFSET 42355\n+#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_HDR_SEL_RT_OFFSET 42354\n #define NIG_REG_LLH_PF_CLS_FUNC_FILTER_HDR_SEL_RT_SIZE 512\n-#define NIG_REG_LLH_PF_CLS_FILTERS_MAP_RT_OFFSET 42867\n+#define NIG_REG_LLH_PF_CLS_FILTERS_MAP_RT_OFFSET 42866\n #define NIG_REG_LLH_PF_CLS_FILTERS_MAP_RT_SIZE 32\n-#define CDU_REG_CID_ADDR_PARAMS_RT_OFFSET 42899\n-#define CDU_REG_SEGMENT0_PARAMS_RT_OFFSET 42900\n-#define CDU_REG_SEGMENT1_PARAMS_RT_OFFSET 42901\n-#define CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET 42902\n-#define CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET 42903\n-#define CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET 42904\n-#define CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET 42905\n-#define CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET 42906\n-#define CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET 42907\n-#define CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET 42908\n-#define CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET 42909\n-#define CDU_REG_VF_SEG_TYPE_OFFSET_RT_OFFSET 42910\n-#define CDU_REG_VF_FL_SEG_TYPE_OFFSET_RT_OFFSET 42911\n-#define PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET 42912\n-#define PBF_REG_BTB_SHARED_AREA_SIZE_RT_OFFSET 42913\n-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET 42914\n-#define PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET 42915\n-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ0_RT_OFFSET 42916\n-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ1_RT_OFFSET 42917\n-#define PBF_REG_BTB_GUARANTEED_VOQ1_RT_OFFSET 42918\n-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ1_RT_OFFSET 42919\n-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ2_RT_OFFSET 42920\n-#define PBF_REG_BTB_GUARANTEED_VOQ2_RT_OFFSET 42921\n-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ2_RT_OFFSET 42922\n-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ3_RT_OFFSET 42923\n-#define PBF_REG_BTB_GUARANTEED_VOQ3_RT_OFFSET 42924\n-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ3_RT_OFFSET 42925\n-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ4_RT_OFFSET 42926\n-#define PBF_REG_BTB_GUARANTEED_VOQ4_RT_OFFSET 42927\n-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ4_RT_OFFSET 42928\n-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ5_RT_OFFSET 42929\n-#define PBF_REG_BTB_GUARANTEED_VOQ5_RT_OFFSET 42930\n-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ5_RT_OFFSET 42931\n-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ6_RT_OFFSET 42932\n-#define PBF_REG_BTB_GUARANTEED_VOQ6_RT_OFFSET 42933\n-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ6_RT_OFFSET 42934\n-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ7_RT_OFFSET 42935\n-#define PBF_REG_BTB_GUARANTEED_VOQ7_RT_OFFSET 42936\n-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ7_RT_OFFSET 42937\n-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ8_RT_OFFSET 42938\n-#define PBF_REG_BTB_GUARANTEED_VOQ8_RT_OFFSET 42939\n-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ8_RT_OFFSET 42940\n-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ9_RT_OFFSET 42941\n-#define PBF_REG_BTB_GUARANTEED_VOQ9_RT_OFFSET 42942\n-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ9_RT_OFFSET 42943\n-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ10_RT_OFFSET 42944\n-#define PBF_REG_BTB_GUARANTEED_VOQ10_RT_OFFSET 42945\n-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ10_RT_OFFSET 42946\n-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ11_RT_OFFSET 42947\n-#define PBF_REG_BTB_GUARANTEED_VOQ11_RT_OFFSET 42948\n-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ11_RT_OFFSET 42949\n-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ12_RT_OFFSET 42950\n-#define PBF_REG_BTB_GUARANTEED_VOQ12_RT_OFFSET 42951\n-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ12_RT_OFFSET 42952\n-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ13_RT_OFFSET 42953\n-#define PBF_REG_BTB_GUARANTEED_VOQ13_RT_OFFSET 42954\n-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ13_RT_OFFSET 42955\n-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ14_RT_OFFSET 42956\n-#define PBF_REG_BTB_GUARANTEED_VOQ14_RT_OFFSET 42957\n-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ14_RT_OFFSET 42958\n-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ15_RT_OFFSET 42959\n-#define PBF_REG_BTB_GUARANTEED_VOQ15_RT_OFFSET 42960\n-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ15_RT_OFFSET 42961\n-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ16_RT_OFFSET 42962\n-#define PBF_REG_BTB_GUARANTEED_VOQ16_RT_OFFSET 42963\n-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ16_RT_OFFSET 42964\n-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ17_RT_OFFSET 42965\n-#define PBF_REG_BTB_GUARANTEED_VOQ17_RT_OFFSET 42966\n-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ17_RT_OFFSET 42967\n-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ18_RT_OFFSET 42968\n-#define PBF_REG_BTB_GUARANTEED_VOQ18_RT_OFFSET 42969\n-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ18_RT_OFFSET 42970\n-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ19_RT_OFFSET 42971\n-#define PBF_REG_BTB_GUARANTEED_VOQ19_RT_OFFSET 42972\n-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ19_RT_OFFSET 42973\n-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ20_RT_OFFSET 42974\n-#define PBF_REG_BTB_GUARANTEED_VOQ20_RT_OFFSET 42975\n-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ20_RT_OFFSET 42976\n-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ21_RT_OFFSET 42977\n-#define PBF_REG_BTB_GUARANTEED_VOQ21_RT_OFFSET 42978\n-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ21_RT_OFFSET 42979\n-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ22_RT_OFFSET 42980\n-#define PBF_REG_BTB_GUARANTEED_VOQ22_RT_OFFSET 42981\n-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ22_RT_OFFSET 42982\n-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ23_RT_OFFSET 42983\n-#define PBF_REG_BTB_GUARANTEED_VOQ23_RT_OFFSET 42984\n-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ23_RT_OFFSET 42985\n-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ24_RT_OFFSET 42986\n-#define PBF_REG_BTB_GUARANTEED_VOQ24_RT_OFFSET 42987\n-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ24_RT_OFFSET 42988\n-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ25_RT_OFFSET 42989\n-#define PBF_REG_BTB_GUARANTEED_VOQ25_RT_OFFSET 42990\n-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ25_RT_OFFSET 42991\n-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ26_RT_OFFSET 42992\n-#define PBF_REG_BTB_GUARANTEED_VOQ26_RT_OFFSET 42993\n-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ26_RT_OFFSET 42994\n-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ27_RT_OFFSET 42995\n-#define PBF_REG_BTB_GUARANTEED_VOQ27_RT_OFFSET 42996\n-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ27_RT_OFFSET 42997\n-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ28_RT_OFFSET 42998\n-#define PBF_REG_BTB_GUARANTEED_VOQ28_RT_OFFSET 42999\n-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ28_RT_OFFSET 43000\n-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ29_RT_OFFSET 43001\n-#define PBF_REG_BTB_GUARANTEED_VOQ29_RT_OFFSET 43002\n-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ29_RT_OFFSET 43003\n-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ30_RT_OFFSET 43004\n-#define PBF_REG_BTB_GUARANTEED_VOQ30_RT_OFFSET 43005\n-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ30_RT_OFFSET 43006\n-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ31_RT_OFFSET 43007\n-#define PBF_REG_BTB_GUARANTEED_VOQ31_RT_OFFSET 43008\n-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ31_RT_OFFSET 43009\n-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ32_RT_OFFSET 43010\n-#define PBF_REG_BTB_GUARANTEED_VOQ32_RT_OFFSET 43011\n-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ32_RT_OFFSET 43012\n-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ33_RT_OFFSET 43013\n-#define PBF_REG_BTB_GUARANTEED_VOQ33_RT_OFFSET 43014\n-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ33_RT_OFFSET 43015\n-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ34_RT_OFFSET 43016\n-#define PBF_REG_BTB_GUARANTEED_VOQ34_RT_OFFSET 43017\n-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ34_RT_OFFSET 43018\n-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ35_RT_OFFSET 43019\n-#define PBF_REG_BTB_GUARANTEED_VOQ35_RT_OFFSET 43020\n-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ35_RT_OFFSET 43021\n-#define XCM_REG_CON_PHY_Q3_RT_OFFSET 43022\n+#define CDU_REG_CID_ADDR_PARAMS_RT_OFFSET 42898\n+#define CDU_REG_SEGMENT0_PARAMS_RT_OFFSET 42899\n+#define CDU_REG_SEGMENT1_PARAMS_RT_OFFSET 42900\n+#define CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET 42901\n+#define CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET 42902\n+#define CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET 42903\n+#define CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET 42904\n+#define CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET 42905\n+#define CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET 42906\n+#define CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET 42907\n+#define CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET 42908\n+#define CDU_REG_VF_SEG_TYPE_OFFSET_RT_OFFSET 42909\n+#define CDU_REG_VF_FL_SEG_TYPE_OFFSET_RT_OFFSET 42910\n+#define PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET 42911\n+#define PBF_REG_BTB_SHARED_AREA_SIZE_RT_OFFSET 42912\n+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET 42913\n+#define PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET 42914\n+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ0_RT_OFFSET 42915\n+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ1_RT_OFFSET 42916\n+#define PBF_REG_BTB_GUARANTEED_VOQ1_RT_OFFSET 42917\n+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ1_RT_OFFSET 42918\n+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ2_RT_OFFSET 42919\n+#define PBF_REG_BTB_GUARANTEED_VOQ2_RT_OFFSET 42920\n+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ2_RT_OFFSET 42921\n+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ3_RT_OFFSET 42922\n+#define PBF_REG_BTB_GUARANTEED_VOQ3_RT_OFFSET 42923\n+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ3_RT_OFFSET 42924\n+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ4_RT_OFFSET 42925\n+#define PBF_REG_BTB_GUARANTEED_VOQ4_RT_OFFSET 42926\n+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ4_RT_OFFSET 42927\n+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ5_RT_OFFSET 42928\n+#define PBF_REG_BTB_GUARANTEED_VOQ5_RT_OFFSET 42929\n+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ5_RT_OFFSET 42930\n+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ6_RT_OFFSET 42931\n+#define PBF_REG_BTB_GUARANTEED_VOQ6_RT_OFFSET 42932\n+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ6_RT_OFFSET 42933\n+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ7_RT_OFFSET 42934\n+#define PBF_REG_BTB_GUARANTEED_VOQ7_RT_OFFSET 42935\n+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ7_RT_OFFSET 42936\n+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ8_RT_OFFSET 42937\n+#define PBF_REG_BTB_GUARANTEED_VOQ8_RT_OFFSET 42938\n+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ8_RT_OFFSET 42939\n+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ9_RT_OFFSET 42940\n+#define PBF_REG_BTB_GUARANTEED_VOQ9_RT_OFFSET 42941\n+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ9_RT_OFFSET 42942\n+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ10_RT_OFFSET 42943\n+#define PBF_REG_BTB_GUARANTEED_VOQ10_RT_OFFSET 42944\n+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ10_RT_OFFSET 42945\n+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ11_RT_OFFSET 42946\n+#define PBF_REG_BTB_GUARANTEED_VOQ11_RT_OFFSET 42947\n+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ11_RT_OFFSET 42948\n+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ12_RT_OFFSET 42949\n+#define PBF_REG_BTB_GUARANTEED_VOQ12_RT_OFFSET 42950\n+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ12_RT_OFFSET 42951\n+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ13_RT_OFFSET 42952\n+#define PBF_REG_BTB_GUARANTEED_VOQ13_RT_OFFSET 42953\n+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ13_RT_OFFSET 42954\n+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ14_RT_OFFSET 42955\n+#define PBF_REG_BTB_GUARANTEED_VOQ14_RT_OFFSET 42956\n+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ14_RT_OFFSET 42957\n+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ15_RT_OFFSET 42958\n+#define PBF_REG_BTB_GUARANTEED_VOQ15_RT_OFFSET 42959\n+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ15_RT_OFFSET 42960\n+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ16_RT_OFFSET 42961\n+#define PBF_REG_BTB_GUARANTEED_VOQ16_RT_OFFSET 42962\n+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ16_RT_OFFSET 42963\n+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ17_RT_OFFSET 42964\n+#define PBF_REG_BTB_GUARANTEED_VOQ17_RT_OFFSET 42965\n+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ17_RT_OFFSET 42966\n+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ18_RT_OFFSET 42967\n+#define PBF_REG_BTB_GUARANTEED_VOQ18_RT_OFFSET 42968\n+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ18_RT_OFFSET 42969\n+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ19_RT_OFFSET 42970\n+#define PBF_REG_BTB_GUARANTEED_VOQ19_RT_OFFSET 42971\n+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ19_RT_OFFSET 42972\n+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ20_RT_OFFSET 42973\n+#define PBF_REG_BTB_GUARANTEED_VOQ20_RT_OFFSET 42974\n+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ20_RT_OFFSET 42975\n+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ21_RT_OFFSET 42976\n+#define PBF_REG_BTB_GUARANTEED_VOQ21_RT_OFFSET 42977\n+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ21_RT_OFFSET 42978\n+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ22_RT_OFFSET 42979\n+#define PBF_REG_BTB_GUARANTEED_VOQ22_RT_OFFSET 42980\n+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ22_RT_OFFSET 42981\n+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ23_RT_OFFSET 42982\n+#define PBF_REG_BTB_GUARANTEED_VOQ23_RT_OFFSET 42983\n+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ23_RT_OFFSET 42984\n+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ24_RT_OFFSET 42985\n+#define PBF_REG_BTB_GUARANTEED_VOQ24_RT_OFFSET 42986\n+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ24_RT_OFFSET 42987\n+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ25_RT_OFFSET 42988\n+#define PBF_REG_BTB_GUARANTEED_VOQ25_RT_OFFSET 42989\n+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ25_RT_OFFSET 42990\n+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ26_RT_OFFSET 42991\n+#define PBF_REG_BTB_GUARANTEED_VOQ26_RT_OFFSET 42992\n+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ26_RT_OFFSET 42993\n+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ27_RT_OFFSET 42994\n+#define PBF_REG_BTB_GUARANTEED_VOQ27_RT_OFFSET 42995\n+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ27_RT_OFFSET 42996\n+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ28_RT_OFFSET 42997\n+#define PBF_REG_BTB_GUARANTEED_VOQ28_RT_OFFSET 42998\n+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ28_RT_OFFSET 42999\n+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ29_RT_OFFSET 43000\n+#define PBF_REG_BTB_GUARANTEED_VOQ29_RT_OFFSET 43001\n+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ29_RT_OFFSET 43002\n+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ30_RT_OFFSET 43003\n+#define PBF_REG_BTB_GUARANTEED_VOQ30_RT_OFFSET 43004\n+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ30_RT_OFFSET 43005\n+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ31_RT_OFFSET 43006\n+#define PBF_REG_BTB_GUARANTEED_VOQ31_RT_OFFSET 43007\n+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ31_RT_OFFSET 43008\n+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ32_RT_OFFSET 43009\n+#define PBF_REG_BTB_GUARANTEED_VOQ32_RT_OFFSET 43010\n+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ32_RT_OFFSET 43011\n+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ33_RT_OFFSET 43012\n+#define PBF_REG_BTB_GUARANTEED_VOQ33_RT_OFFSET 43013\n+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ33_RT_OFFSET 43014\n+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ34_RT_OFFSET 43015\n+#define PBF_REG_BTB_GUARANTEED_VOQ34_RT_OFFSET 43016\n+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ34_RT_OFFSET 43017\n+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ35_RT_OFFSET 43018\n+#define PBF_REG_BTB_GUARANTEED_VOQ35_RT_OFFSET 43019\n+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ35_RT_OFFSET 43020\n+#define XCM_REG_CON_PHY_Q3_RT_OFFSET 43021\n \n-#define RUNTIME_ARRAY_SIZE 43023\n+#define RUNTIME_ARRAY_SIZE 43022\n \n /* Init Callbacks */\n #define DMAE_READY_CB 0\ndiff --git a/drivers/net/qede/base/eth_common.h b/drivers/net/qede/base/eth_common.h\nindex abfa685..9a401ed 100644\n--- a/drivers/net/qede/base/eth_common.h\n+++ b/drivers/net/qede/base/eth_common.h\n@@ -178,6 +178,11 @@ struct eth_tx_1st_bd_flags {\n #define ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_SHIFT 6\n /* Recalculate Tunnel UDP/GRE Checksum (Depending on Tunnel Type) */\n #define ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_MASK 0x1\n+/* Recalculate Tunnel UDP/GRE Checksum (Depending on Tunnel Type). In case of\n+ * GRE tunnel, this flag means GRE CSO, and in this case GRE checksum field\n+ * Must be present.\n+ */\n+#define ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_MASK 0x1\n #define ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_SHIFT 7\n };\n \ndiff --git a/drivers/net/qede/base/reg_addr.h b/drivers/net/qede/base/reg_addr.h\nindex b82ccc1..c3e0bd2 100644\n--- a/drivers/net/qede/base/reg_addr.h\n+++ b/drivers/net/qede/base/reg_addr.h\n@@ -8,13 +8,13 @@\n \t0\n \n #define CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE\t\t( \\\n-\t\t0xfff << 0)\n+\t\t0xfffUL << 0)\n \n #define CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE_SHIFT \\\n \t12\n \n #define CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE\t\t( \\\n-\t\t0xfff << 12)\n+\t\t0xfffUL << 12)\n \n #define CDU_REG_CID_ADDR_PARAMS_NCIB_SHIFT \\\n \t24\n@@ -366,9 +366,9 @@\n #define IGU_REG_COMMAND_REG_CTRL \\\n \t0x180848UL\n #define IGU_REG_BLOCK_CONFIGURATION_VF_CLEANUP_EN\t( \\\n-\t\t0x1 << 1)\n+\t\t0x1UL << 1)\n #define IGU_REG_BLOCK_CONFIGURATION_PXP_TPH_INTERFACE_EN\t( \\\n-\t\t0x1 << 0)\n+\t\t0x1UL << 0)\n #define IGU_REG_MAPPING_MEMORY \\\n \t0x184000UL\n #define MISCS_REG_GENERIC_POR_0\t\\\n@@ -376,7 +376,7 @@\n #define MCP_REG_NVM_CFG4 \\\n \t0xe0642cUL\n #define MCP_REG_NVM_CFG4_FLASH_SIZE\t( \\\n-\t\t0x7 << 0)\n+\t\t0x7UL << 0)\n #define MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT \\\n \t0\n #define CCFC_REG_STRONG_ENABLE_VF 0x2e070cUL\n@@ -409,7 +409,7 @@\n #define XMAC_REG_TX_CTRL_LO 0x210020UL\n #define XMAC_REG_CTRL 0x210000UL\n #define XMAC_REG_RX_CTRL 0x210030UL\n-#define XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE (0x1 << 12)\n+#define XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE (0x1UL << 12)\n #define MISC_REG_CLK_100G_MODE 0x008c10UL\n #define MISC_REG_OPTE_MODE 0x008c0cUL\n #define NIG_REG_LLH_ENG_CLS_TCP_4_TUPLE_SEARCH 0x501b84UL\n@@ -439,16 +439,16 @@\n #define NIG_REG_LLH_FUNC_FILTER_EN 0x501a80UL\n #define NIG_REG_LLH_FUNC_FILTER_EN_SIZE 16\n #define NIG_REG_LLH_FUNC_FILTER_VALUE 0x501a00UL\n-#define XMAC_REG_CTRL_TX_EN (0x1 << 0)\n-#define XMAC_REG_CTRL_RX_EN (0x1 << 1)\n+#define XMAC_REG_CTRL_TX_EN (0x1UL << 0)\n+#define XMAC_REG_CTRL_RX_EN (0x1UL << 1)\n #define CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE (0xffUL << 24) /* @DPDK */\n-#define CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE (0xff << 16)\n+#define CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE (0xffUL << 16)\n #define CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE_SHIFT 16\n-#define CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE (0xff << 16)\n+#define CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE (0xffUL << 16)\n #define CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE (0xffUL << 24) /* @DPDK */\n-#define CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK (0xfff << 0)\n+#define CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK (0xfffUL << 0)\n #define CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK_SHIFT 0\n-#define CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK (0xfff << 0)\n+#define CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK (0xfffUL << 0)\n #define CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK_SHIFT 0\n #define PSWRQ2_REG_ILT_MEMORY 0x260000UL\n #define QM_REG_WFQPFWEIGHT 0x2f4e80UL\n@@ -536,7 +536,7 @@\n #define MISC_REG_AEU_GENERAL_ATTN_35 0x00848cUL\n #define MCP_REG_CPU_STATE 0xe05004UL\n #define MCP_REG_CPU_MODE 0xe05000UL\n-#define MCP_REG_CPU_MODE_SOFT_HALT (0x1 << 10)\n+#define MCP_REG_CPU_MODE_SOFT_HALT (0x1UL << 10)\n #define MCP_REG_CPU_EVENT_MASK 0xe05008UL\n #define PSWHST_REG_VF_DISABLED_ERROR_VALID 0x2a0060UL\n #define PSWHST_REG_VF_DISABLED_ERROR_ADDRESS 0x2a0064UL\n@@ -565,15 +565,15 @@\n #define PGLUE_B_REG_VF_ILT_ERR_ADD_63_32 0x2aae78UL\n #define PGLUE_B_REG_VF_ILT_ERR_DETAILS 0x2aae7cUL\n #define PGLUE_B_REG_LATCHED_ERRORS_CLR 0x2aa3bcUL\n-#define NIG_REG_INT_MASK_3_P0_LB_TC1_PAUSE_TOO_LONG_INT (0x1 << 10)\n+#define NIG_REG_INT_MASK_3_P0_LB_TC1_PAUSE_TOO_LONG_INT (0x1UL << 10)\n #define DORQ_REG_DB_DROP_REASON 0x100a2cUL\n #define DORQ_REG_DB_DROP_DETAILS 0x100a24UL\n #define TM_REG_INT_STS_1 0x2c0190UL\n-#define TM_REG_INT_STS_1_PEND_TASK_SCAN (0x1 << 6)\n-#define TM_REG_INT_STS_1_PEND_CONN_SCAN (0x1 << 5)\n+#define TM_REG_INT_STS_1_PEND_TASK_SCAN (0x1UL << 6)\n+#define TM_REG_INT_STS_1_PEND_CONN_SCAN (0x1UL << 5)\n #define TM_REG_INT_MASK_1 0x2c0194UL\n-#define TM_REG_INT_MASK_1_PEND_CONN_SCAN (0x1 << 5)\n-#define TM_REG_INT_MASK_1_PEND_TASK_SCAN (0x1 << 6)\n+#define TM_REG_INT_MASK_1_PEND_CONN_SCAN (0x1UL << 5)\n+#define TM_REG_INT_MASK_1_PEND_TASK_SCAN (0x1UL << 6)\n #define MISC_REG_AEU_AFTER_INVERT_1_IGU 0x0087b4UL\n #define MISC_REG_AEU_ENABLE4_IGU_OUT_0 0x0084a8UL\n #define MISC_REG_AEU_ENABLE3_IGU_OUT_0 0x0084a4UL\n@@ -1187,10 +1187,10 @@\n #define XMAC_REG_RX_MAX_SIZE_BB 0x210040UL\n #define XMAC_REG_TX_CTRL_LO_BB 0x210020UL\n #define XMAC_REG_CTRL_BB 0x210000UL\n-#define XMAC_REG_CTRL_TX_EN_BB (0x1 << 0)\n-#define XMAC_REG_CTRL_RX_EN_BB (0x1 << 1)\n+#define XMAC_REG_CTRL_TX_EN_BB (0x1UL << 0)\n+#define XMAC_REG_CTRL_RX_EN_BB (0x1UL << 1)\n #define XMAC_REG_RX_CTRL_BB 0x210030UL\n-#define XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE_BB (0x1 << 12)\n+#define XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE_BB (0x1UL << 12)\n \n #define PGLUE_B_REG_PGL_ADDR_E8_F0_K2_E5 0x2aaf98UL\n #define PGLUE_B_REG_PGL_ADDR_EC_F0_K2_E5 0x2aaf9cUL\n@@ -1217,14 +1217,14 @@\n #define DORQ_REG_DPM_FORCE_ABORT 0x1009d8UL\n #define DORQ_REG_PF_OVFL_STICKY 0x1009d0UL\n #define DORQ_REG_INT_STS 0x100180UL\n- #define DORQ_REG_INT_STS_DB_DROP (0x1 << 1)\n- #define DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR (0x1 << 2)\n- #define DORQ_REG_INT_STS_DORQ_FIFO_AFULL (0x1 << 3)\n+ #define DORQ_REG_INT_STS_DB_DROP (0x1UL << 1)\n+ #define DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR (0x1UL << 2)\n+ #define DORQ_REG_INT_STS_DORQ_FIFO_AFULL (0x1UL << 3)\n #define DORQ_REG_DB_DROP_DETAILS_REL 0x100a28UL\n #define DORQ_REG_INT_STS_WR 0x100188UL\n #define DORQ_REG_DB_DROP_DETAILS_REASON 0x100a20UL\n #define MCP_REG_CPU_PROGRAM_COUNTER 0xe0501cUL\n- #define MCP_REG_CPU_STATE_SOFT_HALTED (0x1 << 10)\n+ #define MCP_REG_CPU_STATE_SOFT_HALTED (0x1UL << 10)\n #define PRS_REG_SEARCH_TENANT_ID 0x1f044cUL\n #define PGLUE_B_REG_VF_BAR1_SIZE 0x2aae68UL\n \n@@ -1234,3 +1234,4 @@\n #define NIG_REG_LLH_FUNC_TAG_VALUE 0x5019d0UL\n #define DORQ_REG_TAG1_OVRD_MODE 0x1008b4UL\n #define DORQ_REG_PF_EXT_VID_BB_K2 0x1008c8UL\n+#define PRS_REG_SEARCH_NON_IP_AS_GFT 0x1f11c0UL\ndiff --git a/drivers/net/qede/qede_main.c b/drivers/net/qede/qede_main.c\nindex 46fa837..c361f24 100644\n--- a/drivers/net/qede/qede_main.c\n+++ b/drivers/net/qede/qede_main.c\n@@ -18,7 +18,7 @@\n char fw_file[PATH_MAX];\n \n const char *QEDE_DEFAULT_FIRMWARE =\n-\t\"/lib/firmware/qed/qed_init_values-8.33.12.0.bin\";\n+\t\"/lib/firmware/qed/qed_init_values-8.37.7.0.bin\";\n \n static void\n qed_update_pf_params(struct ecore_dev *edev, struct ecore_pf_params *params)\n", "prefixes": [ "01/18" ] }