From patchwork Sat Sep 29 08:14:27 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Mody, Rasesh" X-Patchwork-Id: 45662 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 1ACD71B108; Sat, 29 Sep 2018 10:15:52 +0200 (CEST) Received: from NAM04-CO1-obe.outbound.protection.outlook.com (mail-eopbgr690054.outbound.protection.outlook.com [40.107.69.54]) by dpdk.org (Postfix) with ESMTP id DF284D0B2 for ; Sat, 29 Sep 2018 10:15:49 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=CAVIUMNETWORKS.onmicrosoft.com; s=selector1-cavium-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=CiHqdlhOIFuIi1fpR9CmgNstwvxw9yHIY7sxPIXsIr0=; b=LensDR7542y53SLmH5UdFjYgypWztEUchcMdmMEwVQqDuJ5ln97Zlurpyl63xoB9yAQ5bgmMN0HicNnhZU8MvSv0g8Jdk1MNN0bJ0aQ7pZigfmKYfw+le0fhw5Wi1Jja8jDPQgiACQnOaNk69RZdldr/VGsKdl9O3za21KNz3EE= Received: from BYAPR07MB5365.namprd07.prod.outlook.com (20.177.125.18) by BYAPR07MB5320.namprd07.prod.outlook.com (20.177.124.225) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1143.18; Sat, 29 Sep 2018 08:14:27 +0000 Received: from BYAPR07MB5365.namprd07.prod.outlook.com ([fe80::2047:9647:f196:bde0]) by BYAPR07MB5365.namprd07.prod.outlook.com ([fe80::2047:9647:f196:bde0%6]) with mapi id 15.20.1143.022; Sat, 29 Sep 2018 08:14:27 +0000 From: "Mody, Rasesh" To: "dev@dpdk.org" CC: "Mody, Rasesh" , "ferruh.yigit@intel.com" , Dept-Eng DPDK Dev Thread-Topic: [PATCH 01/18] net/qede/base: upgrade to FW 8.37.7.0 Thread-Index: AQHUV8xw36CJDUN1g0Cnu1sfy3Qlww== Date: Sat, 29 Sep 2018 08:14:27 +0000 Message-ID: <1538208822-9726-2-git-send-email-rasesh.mody@cavium.com> References: <1538208822-9726-1-git-send-email-rasesh.mody@cavium.com> In-Reply-To: <1538208822-9726-1-git-send-email-rasesh.mody@cavium.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: BYAPR11CA0059.namprd11.prod.outlook.com (2603:10b6:a03:80::36) To BYAPR07MB5365.namprd07.prod.outlook.com (2603:10b6:a03:64::18) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Rasesh.Mody@cavium.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [198.186.1.5] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; BYAPR07MB5320; 6:w4tGqj7tLfGG2SCwubzcOzS+Zntnk5D9uDDfibs3Tk3arulO1yEM0bfLlciDZwv+HnwNNoDGBGewvGbQHnRwvTFjCrgan3PHrYSs9oRBeK22ARcVdIj6YMaxv3ijjv2Z4Olt70xsGushgZR3eX4iEubGgSoeLOrKwQf65LAtM1bBt4UOpWxgU8lr3FB8OepO9F27QPurJQ1FMWdVX5PFOLmtJ6pFqeSjOUqmzZdBTAevDixAqc1+DPRNC2B56vkc6xm6wBsuEK8XJu27hcc90gY7AQILHvyPuHjo7xPOfykiKSCcDl57QeB2WiTW6VeGwCkfv00pnIAsZQIvhYS0EQ4qjPXssFWWGDCp0JJijx94X3pAayjM/RYfd04Clp4jByMbfEf9jknSgVoR1xMXyu1QAhjwEQVqO0uPNmLGd8Z+sIAVIGVjJfZUw1R+0Zt8eA0DQMX4Sj3g5yfa4FYzTQ==; 5:Dt5j6+PKkGKPDzotJQnDgnRS3oKOEmJgnWK5zzzgmYuWAI1qZ/NIh4EVdPuQQzUu6y+PqAJ4I8eSlTX0VPBnwI4PkBv8Sc0dHwMv2PM9OBwKKLCg3fyBEEgQLCNKI/Z/7c2x9wqU9lMiiwsYLb0xuh7hAhCdAisgATVZ5m+S+AY=; 7:LtvQUGOB60kUdGDH25pBJZ2j4DpULD+WmLL5NVFoUP8GSJvXaOzemqPCxVkFTmsCIu5VzZwMKINV8hBakJBDSEfLa3piVrFC9L4LXJIvRNzo9qq+yxA5czpCIDIm8PPWEXGPXf/WlLCsH3sIPznr149zoMtzK2XVDkf3zkQRIlepm0TAqG83C9gAUwtRmQn6hM0Zw5mq5O7FW9tiUj/J6wTyfxub2Jm7FtyhxuqGa06JM4JzwN/8lnQuXCSkY7sH x-ms-office365-filtering-correlation-id: e7329782-ee05-4976-5e68-08d625e392d4 x-microsoft-antispam: BCL:0; PCL:0; RULEID:(7020095)(4652040)(8989299)(4534165)(4627221)(201703031133081)(201702281549075)(8990200)(5600074)(711020)(2017052603328)(7153060)(7193020); SRVR:BYAPR07MB5320; x-ms-traffictypediagnostic: BYAPR07MB5320: x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:; x-ms-exchange-senderadcheck: 1 x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(8211001083)(6040522)(2401047)(5005006)(8121501046)(823301075)(3231355)(944501410)(52105095)(3002001)(10201501046)(93006095)(93001095)(149066)(150057)(6041310)(20161123564045)(20161123560045)(20161123558120)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123562045)(201708071742011)(7699051); SRVR:BYAPR07MB5320; BCL:0; PCL:0; RULEID:; SRVR:BYAPR07MB5320; x-forefront-prvs: 0810818DA0 x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(376002)(366004)(396003)(136003)(346002)(39860400002)(50944005)(199004)(189003)(97736004)(256004)(14454004)(4326008)(11346002)(2501003)(2900100001)(99286004)(54906003)(1730700003)(86362001)(68736007)(446003)(3846002)(575784001)(25786009)(76176011)(5660300001)(2616005)(8676002)(305945005)(8936002)(486006)(107886003)(2351001)(26005)(2906002)(14444005)(5250100002)(71190400001)(5640700003)(36756003)(6436002)(6486002)(53936002)(316002)(16200700003)(53946003)(72206003)(386003)(105586002)(71200400001)(6916009)(102836004)(6512007)(6116002)(6506007)(7736002)(81156014)(81166006)(186003)(52116002)(476003)(478600001)(66066001)(34290500001)(106356001)(39844003)(569006); DIR:OUT; SFP:1101; SCL:1; SRVR:BYAPR07MB5320; H:BYAPR07MB5365.namprd07.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: cavium.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: d+6SpHwAy++SfRdjHQ4j52qEtQZcV2guzC1jQQBsEZkAheqoWp6owHaZZxkZZ4S93ps9fKBuVh7AUVOxqOagYG/x/y17Lt3UjQe2hi7tCBf1pX74cvDDASGb5y2Er+yBRx9u/EnPeDdZxGCyUwfqhM3zlbRWPE/1xgrLrbgM/6E2lNZavbDLHeNOBbt1QFwdL339O84kEJfwX3KkeopyoGhnBSimTqr056lA82hD0hBZl/vwpjon1HnzU/V3k5LLc8zoex1FNOI9e3iTe3DP7g4pUAn8U8fVFfD/HCaCRjHFWHxTnAM2IDM2LAo5NXPBgd0jc4QU0z8ebuIKoK/vyGxxsSyyYFZqJexNGoWRmq0= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: cavium.com X-MS-Exchange-CrossTenant-Network-Message-Id: e7329782-ee05-4976-5e68-08d625e392d4 X-MS-Exchange-CrossTenant-originalarrivaltime: 29 Sep 2018 08:14:27.7223 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 711e4ccf-2e9b-4bcf-a551-4094005b6194 X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR07MB5320 Subject: [dpdk-dev] [PATCH 01/18] net/qede/base: upgrade to FW 8.37.7.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch adds changes to base driver for upgrading to 8.37.3.0 FW. Signed-off-by: Rasesh Mody --- drivers/net/qede/base/bcm_osal.h | 1 + drivers/net/qede/base/common_hsi.h | 15 +- drivers/net/qede/base/ecore.h | 5 +- drivers/net/qede/base/ecore_dev.c | 16 +- drivers/net/qede/base/ecore_hsi_common.h | 57 +++++- drivers/net/qede/base/ecore_hsi_debug_tools.h | 15 ++ drivers/net/qede/base/ecore_hsi_eth.h | 57 +++++- drivers/net/qede/base/ecore_init_fw_funcs.c | 93 +++++---- drivers/net/qede/base/ecore_init_fw_funcs.h | 42 ++-- drivers/net/qede/base/ecore_iro.h | 164 +++++++++------ drivers/net/qede/base/ecore_iro_values.h | 42 ++-- drivers/net/qede/base/ecore_l2.c | 3 + drivers/net/qede/base/ecore_l2_api.h | 1 + drivers/net/qede/base/ecore_rt_defs.h | 265 ++++++++++++------------- drivers/net/qede/base/eth_common.h | 5 + drivers/net/qede/base/reg_addr.h | 51 ++--- drivers/net/qede/qede_main.c | 2 +- 17 files changed, 523 insertions(+), 311 deletions(-) diff --git a/drivers/net/qede/base/bcm_osal.h b/drivers/net/qede/base/bcm_osal.h index b43e0b3..70805f6 100644 --- a/drivers/net/qede/base/bcm_osal.h +++ b/drivers/net/qede/base/bcm_osal.h @@ -453,5 +453,6 @@ void qede_get_mcp_proto_stats(struct ecore_dev *, enum ecore_mcp_protocol_type, #define OSAL_DIV_S64(a, b) ((a) / (b)) #define OSAL_LLDP_RX_TLVS(p_hwfn, tlv_buf, tlv_size) nothing +#define OSAL_DBG_ALLOC_USER_DATA(p_hwfn, user_data_ptr) (0) #endif /* __BCM_OSAL_H */ diff --git a/drivers/net/qede/base/common_hsi.h b/drivers/net/qede/base/common_hsi.h index ca8e59d..2aaf298 100644 --- a/drivers/net/qede/base/common_hsi.h +++ b/drivers/net/qede/base/common_hsi.h @@ -95,8 +95,8 @@ #define FW_MAJOR_VERSION 8 -#define FW_MINOR_VERSION 33 -#define FW_REVISION_VERSION 12 +#define FW_MINOR_VERSION 37 +#define FW_REVISION_VERSION 7 #define FW_ENGINEERING_VERSION 0 /***********************/ @@ -1033,13 +1033,14 @@ struct db_rdma_dpm_params { #define DB_RDMA_DPM_PARAMS_WQE_SIZE_SHIFT 16 #define DB_RDMA_DPM_PARAMS_RESERVED0_MASK 0x1 #define DB_RDMA_DPM_PARAMS_RESERVED0_SHIFT 27 -/* RoCE completion flag */ -#define DB_RDMA_DPM_PARAMS_COMPLETION_FLG_MASK 0x1 -#define DB_RDMA_DPM_PARAMS_COMPLETION_FLG_SHIFT 28 +/* RoCE ack request (will be set 1) */ +#define DB_RDMA_DPM_PARAMS_ACK_REQUEST_MASK 0x1 +#define DB_RDMA_DPM_PARAMS_ACK_REQUEST_SHIFT 28 #define DB_RDMA_DPM_PARAMS_S_FLG_MASK 0x1 /* RoCE S flag */ #define DB_RDMA_DPM_PARAMS_S_FLG_SHIFT 29 -#define DB_RDMA_DPM_PARAMS_RESERVED1_MASK 0x1 -#define DB_RDMA_DPM_PARAMS_RESERVED1_SHIFT 30 +/* RoCE completion flag for FW use */ +#define DB_RDMA_DPM_PARAMS_COMPLETION_FLG_MASK 0x1 +#define DB_RDMA_DPM_PARAMS_COMPLETION_FLG_SHIFT 30 /* Connection type is iWARP */ #define DB_RDMA_DPM_PARAMS_CONN_TYPE_IS_IWARP_MASK 0x1 #define DB_RDMA_DPM_PARAMS_CONN_TYPE_IS_IWARP_SHIFT 31 diff --git a/drivers/net/qede/base/ecore.h b/drivers/net/qede/base/ecore.h index cf66c4c..8982214 100644 --- a/drivers/net/qede/base/ecore.h +++ b/drivers/net/qede/base/ecore.h @@ -27,8 +27,8 @@ #include "mcp_public.h" #define ECORE_MAJOR_VERSION 8 -#define ECORE_MINOR_VERSION 30 -#define ECORE_REVISION_VERSION 8 +#define ECORE_MINOR_VERSION 37 +#define ECORE_REVISION_VERSION 20 #define ECORE_ENGINEERING_VERSION 0 #define ECORE_VERSION \ @@ -660,6 +660,7 @@ struct ecore_hwfn { #endif struct dbg_tools_data dbg_info; + void *dbg_user_info; struct z_stream_s *stream; diff --git a/drivers/net/qede/base/ecore_dev.c b/drivers/net/qede/base/ecore_dev.c index d91fe27..b83f003 100644 --- a/drivers/net/qede/base/ecore_dev.c +++ b/drivers/net/qede/base/ecore_dev.c @@ -456,6 +456,12 @@ static void ecore_qm_info_free(struct ecore_hwfn *p_hwfn) OSAL_FREE(p_hwfn->p_dev, qm_info->wfq_data); } +static void ecore_dbg_user_data_free(struct ecore_hwfn *p_hwfn) +{ + OSAL_FREE(p_hwfn->p_dev, p_hwfn->dbg_user_info); + p_hwfn->dbg_user_info = OSAL_NULL; +} + void ecore_resc_free(struct ecore_dev *p_dev) { int i; @@ -483,6 +489,7 @@ void ecore_resc_free(struct ecore_dev *p_dev) ecore_l2_free(p_hwfn); ecore_dmae_info_free(p_hwfn); ecore_dcbx_info_free(p_hwfn); + ecore_dbg_user_data_free(p_hwfn); /* @@@TBD Flush work-queue ? */ /* destroy doorbell recovery mechanism */ @@ -1334,7 +1341,14 @@ enum _ecore_status_t ecore_resc_alloc(struct ecore_dev *p_dev) "Failed to allocate memory for dcbx structure\n"); goto alloc_err; } - } + + rc = OSAL_DBG_ALLOC_USER_DATA(p_hwfn, &p_hwfn->dbg_user_info); + if (rc) { + DP_NOTICE(p_hwfn, false, + "Failed to allocate dbg user info structure\n"); + goto alloc_err; + } + } /* hwfn loop */ p_dev->reset_stats = OSAL_ZALLOC(p_dev, GFP_KERNEL, sizeof(*p_dev->reset_stats)); diff --git a/drivers/net/qede/base/ecore_hsi_common.h b/drivers/net/qede/base/ecore_hsi_common.h index 2d761b9..6d4a4dd 100644 --- a/drivers/net/qede/base/ecore_hsi_common.h +++ b/drivers/net/qede/base/ecore_hsi_common.h @@ -922,7 +922,11 @@ struct core_rx_start_ramrod_data { struct core_rx_action_on_error action_on_error; /* set when in GSI offload mode on ROCE connection */ u8 gsi_offload_flag; - u8 reserved[6]; +/* If set, the inner vlan (802.1q tag) priority that is written to cqe will be + * zero out, used for TenantDcb + */ + u8 wipe_inner_vlan_pri_en; + u8 reserved[5]; }; @@ -1044,7 +1048,11 @@ struct core_tx_start_ramrod_data { __le16 qm_pq_id /* QM PQ ID */; /* set when in GSI offload mode on ROCE connection */ u8 gsi_offload_flag; - u8 resrved[3]; +/* vport id of the current connection, used to access non_rdma_in_to_in_pri_map + * which is per vport + */ + u8 vport_id; + u8 resrved[2]; }; @@ -1171,6 +1179,25 @@ struct eth_rx_rate_limit { }; +/* Update RSS indirection table entry command. One outstanding command supported + * per PF. + */ +struct eth_tstorm_rss_update_data { +/* Valid flag. Driver must set this flag, FW clear valid flag when ready for new + * RSS update command. + */ + u8 valid; +/* Global VPORT ID. If RSS is disable for VPORT, RSS update command will be + * ignored. + */ + u8 vport_id; + u8 ind_table_index /* RSS indirect table index that will be updated. */; + u8 reserved; + __le16 ind_table_value /* RSS indirect table new value. */; + __le16 reserved1 /* reserved. */; +}; + + struct eth_ustorm_per_pf_stat { /* number of total ucast bytes received on loopback port without errors */ struct regpair rcv_lb_ucast_bytes; @@ -1463,6 +1490,10 @@ struct pf_start_tunnel_config { * FW will use a default port */ u8 set_geneve_udp_port_flg; +/* Set no-innet-L2 VXLAN tunnel UDP destination port to + * no_inner_l2_vxlan_udp_port. If not set - FW will use a default port + */ + u8 set_no_inner_l2_vxlan_udp_port_flg; u8 tunnel_clss_vxlan /* Rx classification scheme for VXLAN tunnel. */; /* Rx classification scheme for l2 GENEVE tunnel. */ u8 tunnel_clss_l2geneve; @@ -1470,11 +1501,15 @@ struct pf_start_tunnel_config { u8 tunnel_clss_ipgeneve; u8 tunnel_clss_l2gre /* Rx classification scheme for l2 GRE tunnel. */; u8 tunnel_clss_ipgre /* Rx classification scheme for ip GRE tunnel. */; - u8 reserved; /* VXLAN tunnel UDP destination port. Valid if set_vxlan_udp_port_flg=1 */ __le16 vxlan_udp_port; /* GENEVE tunnel UDP destination port. Valid if set_geneve_udp_port_flg=1 */ __le16 geneve_udp_port; +/* no-innet-L2 VXLAN tunnel UDP destination port. Valid if + * set_no_inner_l2_vxlan_udp_port_flg=1 + */ + __le16 no_inner_l2_vxlan_udp_port; + __le16 reserved[3]; }; /* @@ -1547,6 +1582,8 @@ struct pf_update_tunnel_config { u8 set_vxlan_udp_port_flg; /* Update GENEVE tunnel UDP destination port. */ u8 set_geneve_udp_port_flg; +/* Update no-innet-L2 VXLAN tunnel UDP destination port. */ + u8 set_no_inner_l2_vxlan_udp_port_flg; u8 tunnel_clss_vxlan /* Classification scheme for VXLAN tunnel. */; /* Classification scheme for l2 GENEVE tunnel. */ u8 tunnel_clss_l2geneve; @@ -1554,9 +1591,12 @@ struct pf_update_tunnel_config { u8 tunnel_clss_ipgeneve; u8 tunnel_clss_l2gre /* Classification scheme for l2 GRE tunnel. */; u8 tunnel_clss_ipgre /* Classification scheme for ip GRE tunnel. */; + u8 reserved; __le16 vxlan_udp_port /* VXLAN tunnel UDP destination port. */; __le16 geneve_udp_port /* GENEVE tunnel UDP destination port. */; - __le16 reserved; +/* no-innet-L2 VXLAN tunnel UDP destination port. */ + __le16 no_inner_l2_vxlan_udp_port; + __le16 reserved1[3]; }; /* @@ -1686,6 +1726,13 @@ struct rl_update_ramrod_data { /* ID of last RL, that will be updated. If clear, single RL will updated. */ u8 rl_id_last; u8 rl_dc_qcn_flg /* If set, RL will used for DCQCN. */; +/* If set, alpha will be reset to 1 when the state machine is idle. */ + u8 dcqcn_reset_alpha_on_idle; +/* Byte counter threshold to change rate increase stage. */ + u8 rl_bc_stage_th; +/* Timer threshold to change rate increase stage. */ + u8 rl_timer_stage_th; + u8 reserved1; __le32 rl_bc_rate /* Byte Counter Limit. */; __le16 rl_max_rate /* Maximum rate in 1.6 Mbps resolution. */; __le16 rl_r_ai /* Active increase rate. */; @@ -1694,7 +1741,7 @@ struct rl_update_ramrod_data { __le32 dcqcn_k_us /* DCQCN Alpha update interval. */; __le32 dcqcn_timeuot_us /* DCQCN timeout. */; __le32 qcn_timeuot_us /* QCN timeout. */; - __le32 reserved[2]; + __le32 reserved2; }; diff --git a/drivers/net/qede/base/ecore_hsi_debug_tools.h b/drivers/net/qede/base/ecore_hsi_debug_tools.h index bf54872..085af0a 100644 --- a/drivers/net/qede/base/ecore_hsi_debug_tools.h +++ b/drivers/net/qede/base/ecore_hsi_debug_tools.h @@ -1091,6 +1091,15 @@ struct idle_chk_data { }; /* + * Pretend parameters + */ +struct pretend_params { + u8 split_type /* Pretend split type (from enum init_split_types) */; + u8 reserved; + u16 split_id /* Preted split ID (within the pretend split type) */; +}; + +/* * Debug Tools data (per HW function) */ struct dbg_tools_data { @@ -1102,11 +1111,17 @@ struct dbg_tools_data { u8 block_in_reset[88]; u8 chip_id /* Chip ID (from enum chip_ids) */; u8 platform_id /* Platform ID */; + u8 num_ports /* Number of ports in the chip */; + u8 num_pfs_per_port /* Number of PFs in each port */; + u8 num_vfs /* Number of VFs in the chip */; u8 initialized /* Indicates if the data was initialized */; u8 use_dmae /* Indicates if DMAE should be used */; + u8 reserved; + struct pretend_params pretend /* Current pretend parameters */; /* Numbers of registers that were read since last log */ u32 num_regs_read; }; + #endif /* __ECORE_HSI_DEBUG_TOOLS__ */ diff --git a/drivers/net/qede/base/ecore_hsi_eth.h b/drivers/net/qede/base/ecore_hsi_eth.h index 6b51230..158ca67 100644 --- a/drivers/net/qede/base/ecore_hsi_eth.h +++ b/drivers/net/qede/base/ecore_hsi_eth.h @@ -832,6 +832,26 @@ enum eth_filter_type { /* + * inner to inner vlan priority translation configurations + */ +struct eth_in_to_in_pri_map_cfg { +/* If set, non_rdma_in_to_in_pri_map or rdma_in_to_in_pri_map will be used for + * inner to inner priority mapping depending on protocol type + */ + u8 inner_vlan_pri_remap_en; + u8 reserved[7]; +/* Map for inner to inner vlan priority translation for Non RDMA protocols, used + * for TenantDcb. Set inner_vlan_pri_remap_en, when init the map. + */ + u8 non_rdma_in_to_in_pri_map[8]; +/* Map for inner to inner vlan priority translation for RDMA protocols, used for + * TenantDcb. Set inner_vlan_pri_remap_en, when init the map. + */ + u8 rdma_in_to_in_pri_map[8]; +}; + + +/* * eth IPv4 Fragment Type */ enum eth_ipv4_frag_type { @@ -1030,8 +1050,11 @@ struct eth_vport_rx_mode { /* accept all broadcast packets (subject to vlan) */ #define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_MASK 0x1 #define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_SHIFT 5 -#define ETH_VPORT_RX_MODE_RESERVED1_MASK 0x3FF -#define ETH_VPORT_RX_MODE_RESERVED1_SHIFT 6 +/* accept any VNI in tunnel VNI classification. Used for default queue. */ +#define ETH_VPORT_RX_MODE_ACCEPT_ANY_VNI_MASK 0x1 +#define ETH_VPORT_RX_MODE_ACCEPT_ANY_VNI_SHIFT 6 +#define ETH_VPORT_RX_MODE_RESERVED1_MASK 0x1FF +#define ETH_VPORT_RX_MODE_RESERVED1_SHIFT 7 }; @@ -1357,6 +1380,20 @@ struct tx_queue_update_ramrod_data { }; +/* + * Inner to Inner VLAN priority map update mode + */ +enum update_in_to_in_pri_map_mode_enum { +/* Inner to Inner VLAN priority map update Disabled */ + ETH_IN_TO_IN_PRI_MAP_UPDATE_DISABLED, +/* Update Inner to Inner VLAN priority map for non RDMA protocols */ + ETH_IN_TO_IN_PRI_MAP_UPDATE_NON_RDMA_TBL, +/* Update Inner to Inner VLAN priority map for RDMA protocols */ + ETH_IN_TO_IN_PRI_MAP_UPDATE_RDMA_TBL, + MAX_UPDATE_IN_TO_IN_PRI_MAP_MODE_ENUM +}; + + /* * Ramrod data for vport update ramrod @@ -1405,7 +1442,12 @@ struct vport_start_ramrod_data { u8 ctl_frame_mac_check_en; /* If set, control frames will be filtered according to ethtype check. */ u8 ctl_frame_ethtype_check_en; - u8 reserved[1]; +/* If set, the inner vlan (802.1q tag) priority that is written to cqe will be + * zero out, used for TenantDcb + */ + u8 wipe_inner_vlan_pri_en; +/* inner to inner vlan priority translation configurations */ + struct eth_in_to_in_pri_map_cfg in_to_in_vlan_pri_map_cfg; }; @@ -1473,7 +1515,14 @@ struct vport_update_ramrod_data_cmn { u8 ctl_frame_mac_check_en; /* If set, control frames will be filtered according to ethtype check. */ u8 ctl_frame_ethtype_check_en; - u8 reserved[15]; +/* Indicates to update RDMA or NON-RDMA vlan remapping priority table according + * to update_in_to_in_pri_map_mode_enum, used for TenantDcb (use enum + * update_in_to_in_pri_map_mode_enum) + */ + u8 update_in_to_in_pri_map_mode; +/* Map for inner to inner vlan priority translation, used for TenantDcb. */ + u8 in_to_in_pri_map[8]; + u8 reserved[6]; }; struct vport_update_ramrod_mcast { diff --git a/drivers/net/qede/base/ecore_init_fw_funcs.c b/drivers/net/qede/base/ecore_init_fw_funcs.c index b8496cb..cfc1156 100644 --- a/drivers/net/qede/base/ecore_init_fw_funcs.c +++ b/drivers/net/qede/base/ecore_init_fw_funcs.c @@ -1665,7 +1665,7 @@ void ecore_gft_config(struct ecore_hwfn *p_hwfn, bool ipv6, enum gft_profile_type profile_type) { - u32 reg_val, cam_line, ram_line_lo, ram_line_hi; + u32 reg_val, cam_line, ram_line_lo, ram_line_hi, search_non_ip_as_gft; if (!ipv6 && !ipv4) DP_NOTICE(p_hwfn, true, "gft_config: must accept at least on of - ipv4 or ipv6'\n"); @@ -1729,6 +1729,9 @@ void ecore_gft_config(struct ecore_hwfn *p_hwfn, ram_line_lo = 0; ram_line_hi = 0; + /* Search no IP as GFT */ + search_non_ip_as_gft = 0; + /* Tunnel type */ SET_FIELD(ram_line_lo, GFT_RAM_LINE_TUNNEL_DST_PORT, 1); SET_FIELD(ram_line_lo, GFT_RAM_LINE_TUNNEL_OVER_IP_PROTOCOL, 1); @@ -1752,8 +1755,13 @@ void ecore_gft_config(struct ecore_hwfn *p_hwfn, SET_FIELD(ram_line_lo, GFT_RAM_LINE_ETHERTYPE, 1); } else if (profile_type == GFT_PROFILE_TYPE_TUNNEL_TYPE) { SET_FIELD(ram_line_lo, GFT_RAM_LINE_TUNNEL_ETHERTYPE, 1); + + /* Allow tunneled traffic without inner IP */ + search_non_ip_as_gft = 1; } + ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_NON_IP_AS_GFT, + search_non_ip_as_gft); ecore_wr(p_hwfn, p_ptt, PRS_REG_GFT_PROFILE_MASK_RAM + RAM_LINE_SIZE * pf_id, ram_line_lo); @@ -1996,52 +2004,49 @@ void ecore_enable_context_validation(struct ecore_hwfn *p_hwfn, ecore_wr(p_hwfn, p_ptt, CDU_REG_TCFC_CTX_VALID0, ctx_validation); } -#define RSS_IND_TABLE_BASE_ADDR 4112 -#define RSS_IND_TABLE_VPORT_SIZE 16 -#define RSS_IND_TABLE_ENTRY_PER_LINE 8 -/* Update RSS indirection table entry. */ -void ecore_update_eth_rss_ind_table_entry(struct ecore_hwfn *p_hwfn, - struct ecore_ptt *p_ptt, - u8 rss_id, - u8 ind_table_index, - u16 ind_table_value) +/******************************************************************************* + * File name : rdma_init.c + * Author : Michael Shteinbok + ******************************************************************************* + ******************************************************************************* + * Description: + * RDMA HSI functions + * + ******************************************************************************* + * Notes: This is the input to the auto generated file drv_init_fw_funcs.c + * + ******************************************************************************* + */ +static u32 ecore_get_rdma_assert_ram_addr(struct ecore_hwfn *p_hwfn, + u8 storm_id) { - u32 cnt, rss_addr; - u32 *reg_val; - u16 rss_ind_entry[RSS_IND_TABLE_ENTRY_PER_LINE]; - u16 rss_ind_mask[RSS_IND_TABLE_ENTRY_PER_LINE]; - - /* get entry address */ - rss_addr = RSS_IND_TABLE_BASE_ADDR + - RSS_IND_TABLE_VPORT_SIZE * rss_id + - ind_table_index / RSS_IND_TABLE_ENTRY_PER_LINE; - - /* prepare update command */ - ind_table_index %= RSS_IND_TABLE_ENTRY_PER_LINE; - - for (cnt = 0; cnt < RSS_IND_TABLE_ENTRY_PER_LINE; cnt++) { - if (cnt == ind_table_index) { - rss_ind_entry[cnt] = ind_table_value; - rss_ind_mask[cnt] = 0xFFFF; - } else { - rss_ind_entry[cnt] = 0; - rss_ind_mask[cnt] = 0; - } + switch (storm_id) { + case 0: return TSEM_REG_FAST_MEMORY + SEM_FAST_REG_INT_RAM + + TSTORM_RDMA_ASSERT_LEVEL_OFFSET(p_hwfn->rel_pf_id); + case 1: return MSEM_REG_FAST_MEMORY + SEM_FAST_REG_INT_RAM + + MSTORM_RDMA_ASSERT_LEVEL_OFFSET(p_hwfn->rel_pf_id); + case 2: return USEM_REG_FAST_MEMORY + SEM_FAST_REG_INT_RAM + + USTORM_RDMA_ASSERT_LEVEL_OFFSET(p_hwfn->rel_pf_id); + case 3: return XSEM_REG_FAST_MEMORY + SEM_FAST_REG_INT_RAM + + XSTORM_RDMA_ASSERT_LEVEL_OFFSET(p_hwfn->rel_pf_id); + case 4: return YSEM_REG_FAST_MEMORY + SEM_FAST_REG_INT_RAM + + YSTORM_RDMA_ASSERT_LEVEL_OFFSET(p_hwfn->rel_pf_id); + case 5: return PSEM_REG_FAST_MEMORY + SEM_FAST_REG_INT_RAM + + PSTORM_RDMA_ASSERT_LEVEL_OFFSET(p_hwfn->rel_pf_id); + + default: return 0; } +} - /* Update entry in HW*/ - ecore_wr(p_hwfn, p_ptt, RSS_REG_RSS_RAM_ADDR, rss_addr); - - reg_val = (u32 *)rss_ind_mask; - ecore_wr(p_hwfn, p_ptt, RSS_REG_RSS_RAM_MASK, reg_val[0]); - ecore_wr(p_hwfn, p_ptt, RSS_REG_RSS_RAM_MASK + 4, reg_val[1]); - ecore_wr(p_hwfn, p_ptt, RSS_REG_RSS_RAM_MASK + 8, reg_val[2]); - ecore_wr(p_hwfn, p_ptt, RSS_REG_RSS_RAM_MASK + 12, reg_val[3]); +void ecore_set_rdma_error_level(struct ecore_hwfn *p_hwfn, + struct ecore_ptt *p_ptt, + u8 assert_level[NUM_STORMS]) +{ + u8 storm_id; + for (storm_id = 0; storm_id < NUM_STORMS; storm_id++) { + u32 ram_addr = ecore_get_rdma_assert_ram_addr(p_hwfn, storm_id); - reg_val = (u32 *)rss_ind_entry; - ecore_wr(p_hwfn, p_ptt, RSS_REG_RSS_RAM_DATA, reg_val[0]); - ecore_wr(p_hwfn, p_ptt, RSS_REG_RSS_RAM_DATA + 4, reg_val[1]); - ecore_wr(p_hwfn, p_ptt, RSS_REG_RSS_RAM_DATA + 8, reg_val[2]); - ecore_wr(p_hwfn, p_ptt, RSS_REG_RSS_RAM_DATA + 12, reg_val[3]); + ecore_wr(p_hwfn, p_ptt, ram_addr, assert_level[storm_id]); + } } diff --git a/drivers/net/qede/base/ecore_init_fw_funcs.h b/drivers/net/qede/base/ecore_init_fw_funcs.h index 1024bb2..3503a90 100644 --- a/drivers/net/qede/base/ecore_init_fw_funcs.h +++ b/drivers/net/qede/base/ecore_init_fw_funcs.h @@ -472,21 +472,35 @@ void ecore_memset_task_ctx(void *p_ctx_mem, u32 ctx_size, u8 ctx_type); -/** - * @brief ecore_update_eth_rss_ind_table_entry - Update RSS indirection table - * entry. - * The function must run in exclusive mode to prevent wrong RSS configuration. + +/******************************************************************************* + * File name : rdma_init.h + * Author : Michael Shteinbok + ******************************************************************************* + ******************************************************************************* + * Description: + * RDMA HSI functions header + * + ******************************************************************************* + * Notes: This is the input to the auto generated file drv_init_fw_funcs.h * - * @param p_hwfn - HW device data - * @param p_ptt - ptt window used for writing the registers. - * @param rss_id - RSS engine ID. - * @param ind_table_index - RSS indirect table index. - * @param ind_table_value - RSS indirect table new value. + ******************************************************************************* */ -void ecore_update_eth_rss_ind_table_entry(struct ecore_hwfn *p_hwfn, - struct ecore_ptt *p_ptt, - u8 rss_id, - u8 ind_table_index, - u16 ind_table_value); +#define NUM_STORMS 6 + + + +/** + * @brief ecore_set_rdma_error_level - Sets the RDMA assert level. + * If the severity of the error will be + * above the level, the FW will assert. + * @param p_hwfn - HW device data + * @param p_ptt - ptt window used for writing the registers + * @param assert_level - An array of assert levels for each storm. + */ +void ecore_set_rdma_error_level(struct ecore_hwfn *p_hwfn, + struct ecore_ptt *p_ptt, + u8 assert_level[NUM_STORMS]); + #endif diff --git a/drivers/net/qede/base/ecore_iro.h b/drivers/net/qede/base/ecore_iro.h index 0569302..12d45c1 100644 --- a/drivers/net/qede/base/ecore_iro.h +++ b/drivers/net/qede/base/ecore_iro.h @@ -113,91 +113,129 @@ /* Tstorm Eth limit Rx rate */ #define ETH_RX_RATE_LIMIT_OFFSET(pf_id) (IRO[29].base + ((pf_id) * IRO[29].m1)) #define ETH_RX_RATE_LIMIT_SIZE (IRO[29].size) +/* RSS indirection table entry update command per PF offset in TSTORM PF BAR0. + * Use eth_tstorm_rss_update_data for update. + */ +#define TSTORM_ETH_RSS_UPDATE_OFFSET(pf_id) (IRO[30].base + \ + ((pf_id) * IRO[30].m1)) +#define TSTORM_ETH_RSS_UPDATE_SIZE (IRO[30].size) /* Xstorm queue zone */ -#define XSTORM_ETH_QUEUE_ZONE_OFFSET(queue_id) (IRO[30].base + \ - ((queue_id) * IRO[30].m1)) -#define XSTORM_ETH_QUEUE_ZONE_SIZE (IRO[30].size) +#define XSTORM_ETH_QUEUE_ZONE_OFFSET(queue_id) (IRO[31].base + \ + ((queue_id) * IRO[31].m1)) +#define XSTORM_ETH_QUEUE_ZONE_SIZE (IRO[31].size) /* Ystorm cqe producer */ -#define YSTORM_TOE_CQ_PROD_OFFSET(rss_id) (IRO[31].base + \ - ((rss_id) * IRO[31].m1)) -#define YSTORM_TOE_CQ_PROD_SIZE (IRO[31].size) -/* Ustorm cqe producer */ -#define USTORM_TOE_CQ_PROD_OFFSET(rss_id) (IRO[32].base + \ +#define YSTORM_TOE_CQ_PROD_OFFSET(rss_id) (IRO[32].base + \ ((rss_id) * IRO[32].m1)) -#define USTORM_TOE_CQ_PROD_SIZE (IRO[32].size) +#define YSTORM_TOE_CQ_PROD_SIZE (IRO[32].size) +/* Ustorm cqe producer */ +#define USTORM_TOE_CQ_PROD_OFFSET(rss_id) (IRO[33].base + \ + ((rss_id) * IRO[33].m1)) +#define USTORM_TOE_CQ_PROD_SIZE (IRO[33].size) /* Ustorm grq producer */ -#define USTORM_TOE_GRQ_PROD_OFFSET(pf_id) (IRO[33].base + \ - ((pf_id) * IRO[33].m1)) -#define USTORM_TOE_GRQ_PROD_SIZE (IRO[33].size) +#define USTORM_TOE_GRQ_PROD_OFFSET(pf_id) (IRO[34].base + \ + ((pf_id) * IRO[34].m1)) +#define USTORM_TOE_GRQ_PROD_SIZE (IRO[34].size) /* Tstorm cmdq-cons of given command queue-id */ -#define TSTORM_SCSI_CMDQ_CONS_OFFSET(cmdq_queue_id) (IRO[34].base + \ - ((cmdq_queue_id) * IRO[34].m1)) -#define TSTORM_SCSI_CMDQ_CONS_SIZE (IRO[34].size) +#define TSTORM_SCSI_CMDQ_CONS_OFFSET(cmdq_queue_id) (IRO[35].base + \ + ((cmdq_queue_id) * IRO[35].m1)) +#define TSTORM_SCSI_CMDQ_CONS_SIZE (IRO[35].size) /* Tstorm (reflects M-Storm) bdq-external-producer of given function ID, * BDqueue-id */ -#define TSTORM_SCSI_BDQ_EXT_PROD_OFFSET(func_id, bdq_id) (IRO[35].base + \ - ((func_id) * IRO[35].m1) + ((bdq_id) * IRO[35].m2)) -#define TSTORM_SCSI_BDQ_EXT_PROD_SIZE (IRO[35].size) -/* Mstorm bdq-external-producer of given BDQ resource ID, BDqueue-id */ -#define MSTORM_SCSI_BDQ_EXT_PROD_OFFSET(func_id, bdq_id) (IRO[36].base + \ +#define TSTORM_SCSI_BDQ_EXT_PROD_OFFSET(func_id, bdq_id) (IRO[36].base + \ ((func_id) * IRO[36].m1) + ((bdq_id) * IRO[36].m2)) -#define MSTORM_SCSI_BDQ_EXT_PROD_SIZE (IRO[36].size) +#define TSTORM_SCSI_BDQ_EXT_PROD_SIZE (IRO[36].size) +/* Mstorm bdq-external-producer of given BDQ resource ID, BDqueue-id */ +#define MSTORM_SCSI_BDQ_EXT_PROD_OFFSET(func_id, bdq_id) (IRO[37].base + \ + ((func_id) * IRO[37].m1) + ((bdq_id) * IRO[37].m2)) +#define MSTORM_SCSI_BDQ_EXT_PROD_SIZE (IRO[37].size) /* Tstorm iSCSI RX stats */ -#define TSTORM_ISCSI_RX_STATS_OFFSET(pf_id) (IRO[37].base + \ - ((pf_id) * IRO[37].m1)) -#define TSTORM_ISCSI_RX_STATS_SIZE (IRO[37].size) -/* Mstorm iSCSI RX stats */ -#define MSTORM_ISCSI_RX_STATS_OFFSET(pf_id) (IRO[38].base + \ +#define TSTORM_ISCSI_RX_STATS_OFFSET(pf_id) (IRO[38].base + \ ((pf_id) * IRO[38].m1)) -#define MSTORM_ISCSI_RX_STATS_SIZE (IRO[38].size) -/* Ustorm iSCSI RX stats */ -#define USTORM_ISCSI_RX_STATS_OFFSET(pf_id) (IRO[39].base + \ +#define TSTORM_ISCSI_RX_STATS_SIZE (IRO[38].size) +/* Mstorm iSCSI RX stats */ +#define MSTORM_ISCSI_RX_STATS_OFFSET(pf_id) (IRO[39].base + \ ((pf_id) * IRO[39].m1)) -#define USTORM_ISCSI_RX_STATS_SIZE (IRO[39].size) -/* Xstorm iSCSI TX stats */ -#define XSTORM_ISCSI_TX_STATS_OFFSET(pf_id) (IRO[40].base + \ +#define MSTORM_ISCSI_RX_STATS_SIZE (IRO[39].size) +/* Ustorm iSCSI RX stats */ +#define USTORM_ISCSI_RX_STATS_OFFSET(pf_id) (IRO[40].base + \ ((pf_id) * IRO[40].m1)) -#define XSTORM_ISCSI_TX_STATS_SIZE (IRO[40].size) -/* Ystorm iSCSI TX stats */ -#define YSTORM_ISCSI_TX_STATS_OFFSET(pf_id) (IRO[41].base + \ +#define USTORM_ISCSI_RX_STATS_SIZE (IRO[40].size) +/* Xstorm iSCSI TX stats */ +#define XSTORM_ISCSI_TX_STATS_OFFSET(pf_id) (IRO[41].base + \ ((pf_id) * IRO[41].m1)) -#define YSTORM_ISCSI_TX_STATS_SIZE (IRO[41].size) -/* Pstorm iSCSI TX stats */ -#define PSTORM_ISCSI_TX_STATS_OFFSET(pf_id) (IRO[42].base + \ +#define XSTORM_ISCSI_TX_STATS_SIZE (IRO[41].size) +/* Ystorm iSCSI TX stats */ +#define YSTORM_ISCSI_TX_STATS_OFFSET(pf_id) (IRO[42].base + \ ((pf_id) * IRO[42].m1)) -#define PSTORM_ISCSI_TX_STATS_SIZE (IRO[42].size) -/* Tstorm FCoE RX stats */ -#define TSTORM_FCOE_RX_STATS_OFFSET(pf_id) (IRO[43].base + \ +#define YSTORM_ISCSI_TX_STATS_SIZE (IRO[42].size) +/* Pstorm iSCSI TX stats */ +#define PSTORM_ISCSI_TX_STATS_OFFSET(pf_id) (IRO[43].base + \ ((pf_id) * IRO[43].m1)) -#define TSTORM_FCOE_RX_STATS_SIZE (IRO[43].size) -/* Pstorm FCoE TX stats */ -#define PSTORM_FCOE_TX_STATS_OFFSET(pf_id) (IRO[44].base + \ +#define PSTORM_ISCSI_TX_STATS_SIZE (IRO[43].size) +/* Tstorm FCoE RX stats */ +#define TSTORM_FCOE_RX_STATS_OFFSET(pf_id) (IRO[44].base + \ ((pf_id) * IRO[44].m1)) -#define PSTORM_FCOE_TX_STATS_SIZE (IRO[44].size) +#define TSTORM_FCOE_RX_STATS_SIZE (IRO[44].size) +/* Pstorm FCoE TX stats */ +#define PSTORM_FCOE_TX_STATS_OFFSET(pf_id) (IRO[45].base + \ + ((pf_id) * IRO[45].m1)) +#define PSTORM_FCOE_TX_STATS_SIZE (IRO[45].size) /* Pstorm RDMA queue statistics */ -#define PSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id) \ - (IRO[45].base + ((rdma_stat_counter_id) * IRO[45].m1)) -#define PSTORM_RDMA_QUEUE_STAT_SIZE (IRO[45].size) -/* Tstorm RDMA queue statistics */ -#define TSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id) (IRO[46].base + \ +#define PSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id) (IRO[46].base + \ ((rdma_stat_counter_id) * IRO[46].m1)) -#define TSTORM_RDMA_QUEUE_STAT_SIZE (IRO[46].size) +#define PSTORM_RDMA_QUEUE_STAT_SIZE (IRO[46].size) +/* Tstorm RDMA queue statistics */ +#define TSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id) (IRO[47].base + \ + ((rdma_stat_counter_id) * IRO[47].m1)) +#define TSTORM_RDMA_QUEUE_STAT_SIZE (IRO[47].size) +/* Xstorm error level for assert */ +#define XSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) (IRO[48].base + \ + ((pf_id) * IRO[48].m1)) +#define XSTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[48].size) +/* Ystorm error level for assert */ +#define YSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) (IRO[49].base + \ + ((pf_id) * IRO[49].m1)) +#define YSTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[49].size) +/* Pstorm error level for assert */ +#define PSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) (IRO[50].base + \ + ((pf_id) * IRO[50].m1)) +#define PSTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[50].size) +/* Tstorm error level for assert */ +#define TSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) (IRO[51].base + \ + ((pf_id) * IRO[51].m1)) +#define TSTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[51].size) +/* Mstorm error level for assert */ +#define MSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) (IRO[52].base + \ + ((pf_id) * IRO[52].m1)) +#define MSTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[52].size) +/* Ustorm error level for assert */ +#define USTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) (IRO[53].base + \ + ((pf_id) * IRO[53].m1)) +#define USTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[53].size) /* Xstorm iWARP rxmit stats */ -#define XSTORM_IWARP_RXMIT_STATS_OFFSET(pf_id) (IRO[47].base + \ - ((pf_id) * IRO[47].m1)) -#define XSTORM_IWARP_RXMIT_STATS_SIZE (IRO[47].size) +#define XSTORM_IWARP_RXMIT_STATS_OFFSET(pf_id) (IRO[54].base + \ + ((pf_id) * IRO[54].m1)) +#define XSTORM_IWARP_RXMIT_STATS_SIZE (IRO[54].size) /* Tstorm RoCE Event Statistics */ -#define TSTORM_ROCE_EVENTS_STAT_OFFSET(roce_pf_id) (IRO[48].base + \ - ((roce_pf_id) * IRO[48].m1)) -#define TSTORM_ROCE_EVENTS_STAT_SIZE (IRO[48].size) +#define TSTORM_ROCE_EVENTS_STAT_OFFSET(roce_pf_id) (IRO[55].base + \ + ((roce_pf_id) * IRO[55].m1)) +#define TSTORM_ROCE_EVENTS_STAT_SIZE (IRO[55].size) /* DCQCN Received Statistics */ -#define YSTORM_ROCE_DCQCN_RECEIVED_STATS_OFFSET(roce_pf_id) (IRO[49].base + \ - ((roce_pf_id) * IRO[49].m1)) -#define YSTORM_ROCE_DCQCN_RECEIVED_STATS_SIZE (IRO[49].size) +#define YSTORM_ROCE_DCQCN_RECEIVED_STATS_OFFSET(roce_pf_id) (IRO[56].base + \ + ((roce_pf_id) * IRO[56].m1)) +#define YSTORM_ROCE_DCQCN_RECEIVED_STATS_SIZE (IRO[56].size) +/* RoCE Error Statistics */ +#define YSTORM_ROCE_ERROR_STATS_OFFSET(roce_pf_id) (IRO[57].base + \ + ((roce_pf_id) * IRO[57].m1)) +#define YSTORM_ROCE_ERROR_STATS_SIZE (IRO[57].size) /* DCQCN Sent Statistics */ -#define PSTORM_ROCE_DCQCN_SENT_STATS_OFFSET(roce_pf_id) (IRO[50].base + \ - ((roce_pf_id) * IRO[50].m1)) -#define PSTORM_ROCE_DCQCN_SENT_STATS_SIZE (IRO[50].size) +#define PSTORM_ROCE_DCQCN_SENT_STATS_OFFSET(roce_pf_id) (IRO[58].base + \ + ((roce_pf_id) * IRO[58].m1)) +#define PSTORM_ROCE_DCQCN_SENT_STATS_SIZE (IRO[58].size) +/* RoCE CQEs Statistics */ +#define USTORM_ROCE_CQE_STATS_OFFSET(roce_pf_id) (IRO[59].base + \ + ((roce_pf_id) * IRO[59].m1)) +#define USTORM_ROCE_CQE_STATS_SIZE (IRO[59].size) #endif /* __IRO_H__ */ diff --git a/drivers/net/qede/base/ecore_iro_values.h b/drivers/net/qede/base/ecore_iro_values.h index 685fa2e..30e632c 100644 --- a/drivers/net/qede/base/ecore_iro_values.h +++ b/drivers/net/qede/base/ecore_iro_values.h @@ -7,7 +7,7 @@ #ifndef __IRO_VALUES_H__ #define __IRO_VALUES_H__ -static const struct iro iro_arr[51] = { +static const struct iro iro_arr[60] = { /* YSTORM_FLOW_CONTROL_MODE_OFFSET */ { 0x0, 0x0, 0x0, 0x0, 0x8}, /* TSTORM_PORT_STAT_OFFSET(port_id) */ @@ -29,7 +29,7 @@ /* YSTORM_INTEG_TEST_DATA_OFFSET */ { 0x3e38, 0x0, 0x0, 0x0, 0x78}, /* PSTORM_INTEG_TEST_DATA_OFFSET */ - { 0x2b78, 0x0, 0x0, 0x0, 0x78}, + { 0x3ef8, 0x0, 0x0, 0x0, 0x78}, /* TSTORM_INTEG_TEST_DATA_OFFSET */ { 0x4c40, 0x0, 0x0, 0x0, 0x78}, /* MSTORM_INTEG_TEST_DATA_OFFSET */ @@ -43,7 +43,7 @@ /* CORE_LL2_USTORM_PER_QUEUE_STAT_OFFSET(core_rx_queue_id) */ { 0xb820, 0x30, 0x0, 0x0, 0x30}, /* CORE_LL2_PSTORM_PER_QUEUE_STAT_OFFSET(core_tx_stats_id) */ - { 0x96c0, 0x30, 0x0, 0x0, 0x30}, + { 0xa990, 0x30, 0x0, 0x0, 0x30}, /* MSTORM_QUEUE_STAT_OFFSET(stat_counter_id) */ { 0x4b68, 0x80, 0x0, 0x0, 0x40}, /* MSTORM_ETH_PF_PRODS_OFFSET(queue_id) */ @@ -59,15 +59,17 @@ /* USTORM_ETH_PF_STAT_OFFSET(pf_id) */ { 0xe770, 0x60, 0x0, 0x0, 0x60}, /* PSTORM_QUEUE_STAT_OFFSET(stat_counter_id) */ - { 0x2d10, 0x80, 0x0, 0x0, 0x38}, + { 0x4090, 0x80, 0x0, 0x0, 0x38}, /* PSTORM_ETH_PF_STAT_OFFSET(pf_id) */ - { 0xf2b8, 0x78, 0x0, 0x0, 0x78}, + { 0xfea8, 0x78, 0x0, 0x0, 0x78}, /* PSTORM_CTL_FRAME_ETHTYPE_OFFSET(ethType_id) */ { 0x1f8, 0x4, 0x0, 0x0, 0x4}, /* TSTORM_ETH_PRS_INPUT_OFFSET */ { 0xaf20, 0x0, 0x0, 0x0, 0xf0}, /* ETH_RX_RATE_LIMIT_OFFSET(pf_id) */ { 0xb010, 0x8, 0x0, 0x0, 0x8}, +/* TSTORM_ETH_RSS_UPDATE_OFFSET(pf_id) */ + { 0xc00, 0x8, 0x0, 0x0, 0x8}, /* XSTORM_ETH_QUEUE_ZONE_OFFSET(queue_id) */ { 0x1f8, 0x8, 0x0, 0x0, 0x8}, /* YSTORM_TOE_CQ_PROD_OFFSET(rss_id) */ @@ -91,25 +93,41 @@ /* XSTORM_ISCSI_TX_STATS_OFFSET(pf_id) */ { 0xa588, 0x50, 0x0, 0x0, 0x20}, /* YSTORM_ISCSI_TX_STATS_OFFSET(pf_id) */ - { 0x8700, 0x40, 0x0, 0x0, 0x28}, + { 0x8f00, 0x40, 0x0, 0x0, 0x28}, /* PSTORM_ISCSI_TX_STATS_OFFSET(pf_id) */ - { 0x10300, 0x18, 0x0, 0x0, 0x10}, + { 0x10e30, 0x18, 0x0, 0x0, 0x10}, /* TSTORM_FCOE_RX_STATS_OFFSET(pf_id) */ { 0xde48, 0x48, 0x0, 0x0, 0x38}, /* PSTORM_FCOE_TX_STATS_OFFSET(pf_id) */ - { 0x10768, 0x20, 0x0, 0x0, 0x20}, + { 0x11298, 0x20, 0x0, 0x0, 0x20}, /* PSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id) */ - { 0x2d48, 0x80, 0x0, 0x0, 0x10}, + { 0x40c8, 0x80, 0x0, 0x0, 0x10}, /* TSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id) */ { 0x5048, 0x10, 0x0, 0x0, 0x10}, +/* XSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) */ + { 0xa928, 0x8, 0x0, 0x0, 0x1}, +/* YSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) */ + { 0xa128, 0x8, 0x0, 0x0, 0x1}, +/* PSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) */ + { 0x11a30, 0x8, 0x0, 0x0, 0x1}, +/* TSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) */ + { 0xf030, 0x8, 0x0, 0x0, 0x1}, +/* MSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) */ + { 0x13028, 0x8, 0x0, 0x0, 0x1}, +/* USTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) */ + { 0x12c58, 0x8, 0x0, 0x0, 0x1}, /* XSTORM_IWARP_RXMIT_STATS_OFFSET(pf_id) */ { 0xc9b8, 0x30, 0x0, 0x0, 0x10}, /* TSTORM_ROCE_EVENTS_STAT_OFFSET(roce_pf_id) */ - { 0xed90, 0x10, 0x0, 0x0, 0x10}, + { 0xed90, 0x28, 0x0, 0x0, 0x28}, /* YSTORM_ROCE_DCQCN_RECEIVED_STATS_OFFSET(roce_pf_id) */ - { 0xa520, 0x10, 0x0, 0x0, 0x10}, + { 0xad20, 0x18, 0x0, 0x0, 0x18}, +/* YSTORM_ROCE_ERROR_STATS_OFFSET(roce_pf_id) */ + { 0xaea0, 0x8, 0x0, 0x0, 0x8}, /* PSTORM_ROCE_DCQCN_SENT_STATS_OFFSET(roce_pf_id) */ - { 0x13108, 0x8, 0x0, 0x0, 0x8}, + { 0x13c38, 0x8, 0x0, 0x0, 0x8}, +/* USTORM_ROCE_CQE_STATS_OFFSET(roce_pf_id) */ + { 0x13c50, 0x18, 0x0, 0x0, 0x18}, }; #endif /* __IRO_VALUES_H__ */ diff --git a/drivers/net/qede/base/ecore_l2.c b/drivers/net/qede/base/ecore_l2.c index ca4d901..ec40aac 100644 --- a/drivers/net/qede/base/ecore_l2.c +++ b/drivers/net/qede/base/ecore_l2.c @@ -608,6 +608,9 @@ enum _ecore_status_t SET_FIELD(state, ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL, !!(accept_filter & ECORE_ACCEPT_BCAST)); + SET_FIELD(state, ETH_VPORT_RX_MODE_ACCEPT_ANY_VNI, + !!(accept_filter & ECORE_ACCEPT_ANY_VNI)); + p_ramrod->rx_mode.state = OSAL_CPU_TO_LE16(state); DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "vport[%02x] p_ramrod->rx_mode.state = 0x%x\n", diff --git a/drivers/net/qede/base/ecore_l2_api.h b/drivers/net/qede/base/ecore_l2_api.h index 85034e6..bde825c 100644 --- a/drivers/net/qede/base/ecore_l2_api.h +++ b/drivers/net/qede/base/ecore_l2_api.h @@ -137,6 +137,7 @@ struct ecore_filter_accept_flags { #define ECORE_ACCEPT_MCAST_MATCHED 0x08 #define ECORE_ACCEPT_MCAST_UNMATCHED 0x10 #define ECORE_ACCEPT_BCAST 0x20 +#define ECORE_ACCEPT_ANY_VNI 0x40 }; enum ecore_filter_config_mode { diff --git a/drivers/net/qede/base/ecore_rt_defs.h b/drivers/net/qede/base/ecore_rt_defs.h index 721b8c1..3860e1a 100644 --- a/drivers/net/qede/base/ecore_rt_defs.h +++ b/drivers/net/qede/base/ecore_rt_defs.h @@ -390,147 +390,146 @@ #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET 39769 #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_SIZE 16 #define NIG_REG_TX_EDPM_CTRL_RT_OFFSET 39785 -#define NIG_REG_ROCE_DUPLICATE_TO_HOST_RT_OFFSET 39786 -#define NIG_REG_PPF_TO_ENGINE_SEL_RT_OFFSET 39787 +#define NIG_REG_PPF_TO_ENGINE_SEL_RT_OFFSET 39786 #define NIG_REG_PPF_TO_ENGINE_SEL_RT_SIZE 8 -#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_VALUE_RT_OFFSET 39795 +#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_VALUE_RT_OFFSET 39794 #define NIG_REG_LLH_PF_CLS_FUNC_FILTER_VALUE_RT_SIZE 1024 -#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_EN_RT_OFFSET 40819 +#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_EN_RT_OFFSET 40818 #define NIG_REG_LLH_PF_CLS_FUNC_FILTER_EN_RT_SIZE 512 -#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_MODE_RT_OFFSET 41331 +#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_MODE_RT_OFFSET 41330 #define NIG_REG_LLH_PF_CLS_FUNC_FILTER_MODE_RT_SIZE 512 -#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_PROTOCOL_TYPE_RT_OFFSET 41843 +#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_PROTOCOL_TYPE_RT_OFFSET 41842 #define NIG_REG_LLH_PF_CLS_FUNC_FILTER_PROTOCOL_TYPE_RT_SIZE 512 -#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_HDR_SEL_RT_OFFSET 42355 +#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_HDR_SEL_RT_OFFSET 42354 #define NIG_REG_LLH_PF_CLS_FUNC_FILTER_HDR_SEL_RT_SIZE 512 -#define NIG_REG_LLH_PF_CLS_FILTERS_MAP_RT_OFFSET 42867 +#define NIG_REG_LLH_PF_CLS_FILTERS_MAP_RT_OFFSET 42866 #define NIG_REG_LLH_PF_CLS_FILTERS_MAP_RT_SIZE 32 -#define CDU_REG_CID_ADDR_PARAMS_RT_OFFSET 42899 -#define CDU_REG_SEGMENT0_PARAMS_RT_OFFSET 42900 -#define CDU_REG_SEGMENT1_PARAMS_RT_OFFSET 42901 -#define CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET 42902 -#define CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET 42903 -#define CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET 42904 -#define CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET 42905 -#define CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET 42906 -#define CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET 42907 -#define CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET 42908 -#define CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET 42909 -#define CDU_REG_VF_SEG_TYPE_OFFSET_RT_OFFSET 42910 -#define CDU_REG_VF_FL_SEG_TYPE_OFFSET_RT_OFFSET 42911 -#define PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET 42912 -#define PBF_REG_BTB_SHARED_AREA_SIZE_RT_OFFSET 42913 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET 42914 -#define PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET 42915 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ0_RT_OFFSET 42916 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ1_RT_OFFSET 42917 -#define PBF_REG_BTB_GUARANTEED_VOQ1_RT_OFFSET 42918 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ1_RT_OFFSET 42919 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ2_RT_OFFSET 42920 -#define PBF_REG_BTB_GUARANTEED_VOQ2_RT_OFFSET 42921 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ2_RT_OFFSET 42922 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ3_RT_OFFSET 42923 -#define PBF_REG_BTB_GUARANTEED_VOQ3_RT_OFFSET 42924 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ3_RT_OFFSET 42925 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ4_RT_OFFSET 42926 -#define PBF_REG_BTB_GUARANTEED_VOQ4_RT_OFFSET 42927 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ4_RT_OFFSET 42928 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ5_RT_OFFSET 42929 -#define PBF_REG_BTB_GUARANTEED_VOQ5_RT_OFFSET 42930 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ5_RT_OFFSET 42931 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ6_RT_OFFSET 42932 -#define PBF_REG_BTB_GUARANTEED_VOQ6_RT_OFFSET 42933 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ6_RT_OFFSET 42934 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ7_RT_OFFSET 42935 -#define PBF_REG_BTB_GUARANTEED_VOQ7_RT_OFFSET 42936 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ7_RT_OFFSET 42937 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ8_RT_OFFSET 42938 -#define PBF_REG_BTB_GUARANTEED_VOQ8_RT_OFFSET 42939 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ8_RT_OFFSET 42940 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ9_RT_OFFSET 42941 -#define PBF_REG_BTB_GUARANTEED_VOQ9_RT_OFFSET 42942 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ9_RT_OFFSET 42943 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ10_RT_OFFSET 42944 -#define PBF_REG_BTB_GUARANTEED_VOQ10_RT_OFFSET 42945 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ10_RT_OFFSET 42946 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ11_RT_OFFSET 42947 -#define PBF_REG_BTB_GUARANTEED_VOQ11_RT_OFFSET 42948 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ11_RT_OFFSET 42949 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ12_RT_OFFSET 42950 -#define PBF_REG_BTB_GUARANTEED_VOQ12_RT_OFFSET 42951 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ12_RT_OFFSET 42952 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ13_RT_OFFSET 42953 -#define PBF_REG_BTB_GUARANTEED_VOQ13_RT_OFFSET 42954 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ13_RT_OFFSET 42955 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ14_RT_OFFSET 42956 -#define PBF_REG_BTB_GUARANTEED_VOQ14_RT_OFFSET 42957 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ14_RT_OFFSET 42958 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ15_RT_OFFSET 42959 -#define PBF_REG_BTB_GUARANTEED_VOQ15_RT_OFFSET 42960 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ15_RT_OFFSET 42961 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ16_RT_OFFSET 42962 -#define PBF_REG_BTB_GUARANTEED_VOQ16_RT_OFFSET 42963 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ16_RT_OFFSET 42964 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ17_RT_OFFSET 42965 -#define PBF_REG_BTB_GUARANTEED_VOQ17_RT_OFFSET 42966 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ17_RT_OFFSET 42967 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ18_RT_OFFSET 42968 -#define PBF_REG_BTB_GUARANTEED_VOQ18_RT_OFFSET 42969 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ18_RT_OFFSET 42970 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ19_RT_OFFSET 42971 -#define PBF_REG_BTB_GUARANTEED_VOQ19_RT_OFFSET 42972 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ19_RT_OFFSET 42973 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ20_RT_OFFSET 42974 -#define PBF_REG_BTB_GUARANTEED_VOQ20_RT_OFFSET 42975 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ20_RT_OFFSET 42976 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ21_RT_OFFSET 42977 -#define PBF_REG_BTB_GUARANTEED_VOQ21_RT_OFFSET 42978 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ21_RT_OFFSET 42979 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ22_RT_OFFSET 42980 -#define PBF_REG_BTB_GUARANTEED_VOQ22_RT_OFFSET 42981 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ22_RT_OFFSET 42982 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ23_RT_OFFSET 42983 -#define PBF_REG_BTB_GUARANTEED_VOQ23_RT_OFFSET 42984 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ23_RT_OFFSET 42985 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ24_RT_OFFSET 42986 -#define PBF_REG_BTB_GUARANTEED_VOQ24_RT_OFFSET 42987 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ24_RT_OFFSET 42988 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ25_RT_OFFSET 42989 -#define PBF_REG_BTB_GUARANTEED_VOQ25_RT_OFFSET 42990 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ25_RT_OFFSET 42991 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ26_RT_OFFSET 42992 -#define PBF_REG_BTB_GUARANTEED_VOQ26_RT_OFFSET 42993 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ26_RT_OFFSET 42994 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ27_RT_OFFSET 42995 -#define PBF_REG_BTB_GUARANTEED_VOQ27_RT_OFFSET 42996 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ27_RT_OFFSET 42997 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ28_RT_OFFSET 42998 -#define PBF_REG_BTB_GUARANTEED_VOQ28_RT_OFFSET 42999 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ28_RT_OFFSET 43000 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ29_RT_OFFSET 43001 -#define PBF_REG_BTB_GUARANTEED_VOQ29_RT_OFFSET 43002 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ29_RT_OFFSET 43003 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ30_RT_OFFSET 43004 -#define PBF_REG_BTB_GUARANTEED_VOQ30_RT_OFFSET 43005 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ30_RT_OFFSET 43006 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ31_RT_OFFSET 43007 -#define PBF_REG_BTB_GUARANTEED_VOQ31_RT_OFFSET 43008 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ31_RT_OFFSET 43009 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ32_RT_OFFSET 43010 -#define PBF_REG_BTB_GUARANTEED_VOQ32_RT_OFFSET 43011 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ32_RT_OFFSET 43012 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ33_RT_OFFSET 43013 -#define PBF_REG_BTB_GUARANTEED_VOQ33_RT_OFFSET 43014 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ33_RT_OFFSET 43015 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ34_RT_OFFSET 43016 -#define PBF_REG_BTB_GUARANTEED_VOQ34_RT_OFFSET 43017 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ34_RT_OFFSET 43018 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ35_RT_OFFSET 43019 -#define PBF_REG_BTB_GUARANTEED_VOQ35_RT_OFFSET 43020 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ35_RT_OFFSET 43021 -#define XCM_REG_CON_PHY_Q3_RT_OFFSET 43022 +#define CDU_REG_CID_ADDR_PARAMS_RT_OFFSET 42898 +#define CDU_REG_SEGMENT0_PARAMS_RT_OFFSET 42899 +#define CDU_REG_SEGMENT1_PARAMS_RT_OFFSET 42900 +#define CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET 42901 +#define CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET 42902 +#define CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET 42903 +#define CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET 42904 +#define CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET 42905 +#define CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET 42906 +#define CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET 42907 +#define CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET 42908 +#define CDU_REG_VF_SEG_TYPE_OFFSET_RT_OFFSET 42909 +#define CDU_REG_VF_FL_SEG_TYPE_OFFSET_RT_OFFSET 42910 +#define PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET 42911 +#define PBF_REG_BTB_SHARED_AREA_SIZE_RT_OFFSET 42912 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET 42913 +#define PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET 42914 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ0_RT_OFFSET 42915 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ1_RT_OFFSET 42916 +#define PBF_REG_BTB_GUARANTEED_VOQ1_RT_OFFSET 42917 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ1_RT_OFFSET 42918 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ2_RT_OFFSET 42919 +#define PBF_REG_BTB_GUARANTEED_VOQ2_RT_OFFSET 42920 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ2_RT_OFFSET 42921 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ3_RT_OFFSET 42922 +#define PBF_REG_BTB_GUARANTEED_VOQ3_RT_OFFSET 42923 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ3_RT_OFFSET 42924 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ4_RT_OFFSET 42925 +#define PBF_REG_BTB_GUARANTEED_VOQ4_RT_OFFSET 42926 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ4_RT_OFFSET 42927 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ5_RT_OFFSET 42928 +#define PBF_REG_BTB_GUARANTEED_VOQ5_RT_OFFSET 42929 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ5_RT_OFFSET 42930 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ6_RT_OFFSET 42931 +#define PBF_REG_BTB_GUARANTEED_VOQ6_RT_OFFSET 42932 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ6_RT_OFFSET 42933 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ7_RT_OFFSET 42934 +#define PBF_REG_BTB_GUARANTEED_VOQ7_RT_OFFSET 42935 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ7_RT_OFFSET 42936 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ8_RT_OFFSET 42937 +#define PBF_REG_BTB_GUARANTEED_VOQ8_RT_OFFSET 42938 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ8_RT_OFFSET 42939 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ9_RT_OFFSET 42940 +#define PBF_REG_BTB_GUARANTEED_VOQ9_RT_OFFSET 42941 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ9_RT_OFFSET 42942 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ10_RT_OFFSET 42943 +#define PBF_REG_BTB_GUARANTEED_VOQ10_RT_OFFSET 42944 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ10_RT_OFFSET 42945 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ11_RT_OFFSET 42946 +#define PBF_REG_BTB_GUARANTEED_VOQ11_RT_OFFSET 42947 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ11_RT_OFFSET 42948 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ12_RT_OFFSET 42949 +#define PBF_REG_BTB_GUARANTEED_VOQ12_RT_OFFSET 42950 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ12_RT_OFFSET 42951 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ13_RT_OFFSET 42952 +#define PBF_REG_BTB_GUARANTEED_VOQ13_RT_OFFSET 42953 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ13_RT_OFFSET 42954 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ14_RT_OFFSET 42955 +#define PBF_REG_BTB_GUARANTEED_VOQ14_RT_OFFSET 42956 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ14_RT_OFFSET 42957 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ15_RT_OFFSET 42958 +#define PBF_REG_BTB_GUARANTEED_VOQ15_RT_OFFSET 42959 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ15_RT_OFFSET 42960 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ16_RT_OFFSET 42961 +#define PBF_REG_BTB_GUARANTEED_VOQ16_RT_OFFSET 42962 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ16_RT_OFFSET 42963 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ17_RT_OFFSET 42964 +#define PBF_REG_BTB_GUARANTEED_VOQ17_RT_OFFSET 42965 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ17_RT_OFFSET 42966 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ18_RT_OFFSET 42967 +#define PBF_REG_BTB_GUARANTEED_VOQ18_RT_OFFSET 42968 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ18_RT_OFFSET 42969 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ19_RT_OFFSET 42970 +#define PBF_REG_BTB_GUARANTEED_VOQ19_RT_OFFSET 42971 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ19_RT_OFFSET 42972 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ20_RT_OFFSET 42973 +#define PBF_REG_BTB_GUARANTEED_VOQ20_RT_OFFSET 42974 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ20_RT_OFFSET 42975 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ21_RT_OFFSET 42976 +#define PBF_REG_BTB_GUARANTEED_VOQ21_RT_OFFSET 42977 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ21_RT_OFFSET 42978 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ22_RT_OFFSET 42979 +#define PBF_REG_BTB_GUARANTEED_VOQ22_RT_OFFSET 42980 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ22_RT_OFFSET 42981 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ23_RT_OFFSET 42982 +#define PBF_REG_BTB_GUARANTEED_VOQ23_RT_OFFSET 42983 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ23_RT_OFFSET 42984 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ24_RT_OFFSET 42985 +#define PBF_REG_BTB_GUARANTEED_VOQ24_RT_OFFSET 42986 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ24_RT_OFFSET 42987 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ25_RT_OFFSET 42988 +#define PBF_REG_BTB_GUARANTEED_VOQ25_RT_OFFSET 42989 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ25_RT_OFFSET 42990 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ26_RT_OFFSET 42991 +#define PBF_REG_BTB_GUARANTEED_VOQ26_RT_OFFSET 42992 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ26_RT_OFFSET 42993 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ27_RT_OFFSET 42994 +#define PBF_REG_BTB_GUARANTEED_VOQ27_RT_OFFSET 42995 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ27_RT_OFFSET 42996 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ28_RT_OFFSET 42997 +#define PBF_REG_BTB_GUARANTEED_VOQ28_RT_OFFSET 42998 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ28_RT_OFFSET 42999 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ29_RT_OFFSET 43000 +#define PBF_REG_BTB_GUARANTEED_VOQ29_RT_OFFSET 43001 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ29_RT_OFFSET 43002 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ30_RT_OFFSET 43003 +#define PBF_REG_BTB_GUARANTEED_VOQ30_RT_OFFSET 43004 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ30_RT_OFFSET 43005 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ31_RT_OFFSET 43006 +#define PBF_REG_BTB_GUARANTEED_VOQ31_RT_OFFSET 43007 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ31_RT_OFFSET 43008 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ32_RT_OFFSET 43009 +#define PBF_REG_BTB_GUARANTEED_VOQ32_RT_OFFSET 43010 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ32_RT_OFFSET 43011 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ33_RT_OFFSET 43012 +#define PBF_REG_BTB_GUARANTEED_VOQ33_RT_OFFSET 43013 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ33_RT_OFFSET 43014 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ34_RT_OFFSET 43015 +#define PBF_REG_BTB_GUARANTEED_VOQ34_RT_OFFSET 43016 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ34_RT_OFFSET 43017 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ35_RT_OFFSET 43018 +#define PBF_REG_BTB_GUARANTEED_VOQ35_RT_OFFSET 43019 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ35_RT_OFFSET 43020 +#define XCM_REG_CON_PHY_Q3_RT_OFFSET 43021 -#define RUNTIME_ARRAY_SIZE 43023 +#define RUNTIME_ARRAY_SIZE 43022 /* Init Callbacks */ #define DMAE_READY_CB 0 diff --git a/drivers/net/qede/base/eth_common.h b/drivers/net/qede/base/eth_common.h index abfa685..9a401ed 100644 --- a/drivers/net/qede/base/eth_common.h +++ b/drivers/net/qede/base/eth_common.h @@ -178,6 +178,11 @@ struct eth_tx_1st_bd_flags { #define ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_SHIFT 6 /* Recalculate Tunnel UDP/GRE Checksum (Depending on Tunnel Type) */ #define ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_MASK 0x1 +/* Recalculate Tunnel UDP/GRE Checksum (Depending on Tunnel Type). In case of + * GRE tunnel, this flag means GRE CSO, and in this case GRE checksum field + * Must be present. + */ +#define ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_MASK 0x1 #define ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_SHIFT 7 }; diff --git a/drivers/net/qede/base/reg_addr.h b/drivers/net/qede/base/reg_addr.h index b82ccc1..c3e0bd2 100644 --- a/drivers/net/qede/base/reg_addr.h +++ b/drivers/net/qede/base/reg_addr.h @@ -8,13 +8,13 @@ 0 #define CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE ( \ - 0xfff << 0) + 0xfffUL << 0) #define CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE_SHIFT \ 12 #define CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE ( \ - 0xfff << 12) + 0xfffUL << 12) #define CDU_REG_CID_ADDR_PARAMS_NCIB_SHIFT \ 24 @@ -366,9 +366,9 @@ #define IGU_REG_COMMAND_REG_CTRL \ 0x180848UL #define IGU_REG_BLOCK_CONFIGURATION_VF_CLEANUP_EN ( \ - 0x1 << 1) + 0x1UL << 1) #define IGU_REG_BLOCK_CONFIGURATION_PXP_TPH_INTERFACE_EN ( \ - 0x1 << 0) + 0x1UL << 0) #define IGU_REG_MAPPING_MEMORY \ 0x184000UL #define MISCS_REG_GENERIC_POR_0 \ @@ -376,7 +376,7 @@ #define MCP_REG_NVM_CFG4 \ 0xe0642cUL #define MCP_REG_NVM_CFG4_FLASH_SIZE ( \ - 0x7 << 0) + 0x7UL << 0) #define MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT \ 0 #define CCFC_REG_STRONG_ENABLE_VF 0x2e070cUL @@ -409,7 +409,7 @@ #define XMAC_REG_TX_CTRL_LO 0x210020UL #define XMAC_REG_CTRL 0x210000UL #define XMAC_REG_RX_CTRL 0x210030UL -#define XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE (0x1 << 12) +#define XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE (0x1UL << 12) #define MISC_REG_CLK_100G_MODE 0x008c10UL #define MISC_REG_OPTE_MODE 0x008c0cUL #define NIG_REG_LLH_ENG_CLS_TCP_4_TUPLE_SEARCH 0x501b84UL @@ -439,16 +439,16 @@ #define NIG_REG_LLH_FUNC_FILTER_EN 0x501a80UL #define NIG_REG_LLH_FUNC_FILTER_EN_SIZE 16 #define NIG_REG_LLH_FUNC_FILTER_VALUE 0x501a00UL -#define XMAC_REG_CTRL_TX_EN (0x1 << 0) -#define XMAC_REG_CTRL_RX_EN (0x1 << 1) +#define XMAC_REG_CTRL_TX_EN (0x1UL << 0) +#define XMAC_REG_CTRL_RX_EN (0x1UL << 1) #define CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE (0xffUL << 24) /* @DPDK */ -#define CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE (0xff << 16) +#define CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE (0xffUL << 16) #define CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE_SHIFT 16 -#define CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE (0xff << 16) +#define CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE (0xffUL << 16) #define CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE (0xffUL << 24) /* @DPDK */ -#define CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK (0xfff << 0) +#define CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK (0xfffUL << 0) #define CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK_SHIFT 0 -#define CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK (0xfff << 0) +#define CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK (0xfffUL << 0) #define CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK_SHIFT 0 #define PSWRQ2_REG_ILT_MEMORY 0x260000UL #define QM_REG_WFQPFWEIGHT 0x2f4e80UL @@ -536,7 +536,7 @@ #define MISC_REG_AEU_GENERAL_ATTN_35 0x00848cUL #define MCP_REG_CPU_STATE 0xe05004UL #define MCP_REG_CPU_MODE 0xe05000UL -#define MCP_REG_CPU_MODE_SOFT_HALT (0x1 << 10) +#define MCP_REG_CPU_MODE_SOFT_HALT (0x1UL << 10) #define MCP_REG_CPU_EVENT_MASK 0xe05008UL #define PSWHST_REG_VF_DISABLED_ERROR_VALID 0x2a0060UL #define PSWHST_REG_VF_DISABLED_ERROR_ADDRESS 0x2a0064UL @@ -565,15 +565,15 @@ #define PGLUE_B_REG_VF_ILT_ERR_ADD_63_32 0x2aae78UL #define PGLUE_B_REG_VF_ILT_ERR_DETAILS 0x2aae7cUL #define PGLUE_B_REG_LATCHED_ERRORS_CLR 0x2aa3bcUL -#define NIG_REG_INT_MASK_3_P0_LB_TC1_PAUSE_TOO_LONG_INT (0x1 << 10) +#define NIG_REG_INT_MASK_3_P0_LB_TC1_PAUSE_TOO_LONG_INT (0x1UL << 10) #define DORQ_REG_DB_DROP_REASON 0x100a2cUL #define DORQ_REG_DB_DROP_DETAILS 0x100a24UL #define TM_REG_INT_STS_1 0x2c0190UL -#define TM_REG_INT_STS_1_PEND_TASK_SCAN (0x1 << 6) -#define TM_REG_INT_STS_1_PEND_CONN_SCAN (0x1 << 5) +#define TM_REG_INT_STS_1_PEND_TASK_SCAN (0x1UL << 6) +#define TM_REG_INT_STS_1_PEND_CONN_SCAN (0x1UL << 5) #define TM_REG_INT_MASK_1 0x2c0194UL -#define TM_REG_INT_MASK_1_PEND_CONN_SCAN (0x1 << 5) -#define TM_REG_INT_MASK_1_PEND_TASK_SCAN (0x1 << 6) +#define TM_REG_INT_MASK_1_PEND_CONN_SCAN (0x1UL << 5) +#define TM_REG_INT_MASK_1_PEND_TASK_SCAN (0x1UL << 6) #define MISC_REG_AEU_AFTER_INVERT_1_IGU 0x0087b4UL #define MISC_REG_AEU_ENABLE4_IGU_OUT_0 0x0084a8UL #define MISC_REG_AEU_ENABLE3_IGU_OUT_0 0x0084a4UL @@ -1187,10 +1187,10 @@ #define XMAC_REG_RX_MAX_SIZE_BB 0x210040UL #define XMAC_REG_TX_CTRL_LO_BB 0x210020UL #define XMAC_REG_CTRL_BB 0x210000UL -#define XMAC_REG_CTRL_TX_EN_BB (0x1 << 0) -#define XMAC_REG_CTRL_RX_EN_BB (0x1 << 1) +#define XMAC_REG_CTRL_TX_EN_BB (0x1UL << 0) +#define XMAC_REG_CTRL_RX_EN_BB (0x1UL << 1) #define XMAC_REG_RX_CTRL_BB 0x210030UL -#define XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE_BB (0x1 << 12) +#define XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE_BB (0x1UL << 12) #define PGLUE_B_REG_PGL_ADDR_E8_F0_K2_E5 0x2aaf98UL #define PGLUE_B_REG_PGL_ADDR_EC_F0_K2_E5 0x2aaf9cUL @@ -1217,14 +1217,14 @@ #define DORQ_REG_DPM_FORCE_ABORT 0x1009d8UL #define DORQ_REG_PF_OVFL_STICKY 0x1009d0UL #define DORQ_REG_INT_STS 0x100180UL - #define DORQ_REG_INT_STS_DB_DROP (0x1 << 1) - #define DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR (0x1 << 2) - #define DORQ_REG_INT_STS_DORQ_FIFO_AFULL (0x1 << 3) + #define DORQ_REG_INT_STS_DB_DROP (0x1UL << 1) + #define DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR (0x1UL << 2) + #define DORQ_REG_INT_STS_DORQ_FIFO_AFULL (0x1UL << 3) #define DORQ_REG_DB_DROP_DETAILS_REL 0x100a28UL #define DORQ_REG_INT_STS_WR 0x100188UL #define DORQ_REG_DB_DROP_DETAILS_REASON 0x100a20UL #define MCP_REG_CPU_PROGRAM_COUNTER 0xe0501cUL - #define MCP_REG_CPU_STATE_SOFT_HALTED (0x1 << 10) + #define MCP_REG_CPU_STATE_SOFT_HALTED (0x1UL << 10) #define PRS_REG_SEARCH_TENANT_ID 0x1f044cUL #define PGLUE_B_REG_VF_BAR1_SIZE 0x2aae68UL @@ -1234,3 +1234,4 @@ #define NIG_REG_LLH_FUNC_TAG_VALUE 0x5019d0UL #define DORQ_REG_TAG1_OVRD_MODE 0x1008b4UL #define DORQ_REG_PF_EXT_VID_BB_K2 0x1008c8UL +#define PRS_REG_SEARCH_NON_IP_AS_GFT 0x1f11c0UL diff --git a/drivers/net/qede/qede_main.c b/drivers/net/qede/qede_main.c index 46fa837..c361f24 100644 --- a/drivers/net/qede/qede_main.c +++ b/drivers/net/qede/qede_main.c @@ -18,7 +18,7 @@ char fw_file[PATH_MAX]; const char *QEDE_DEFAULT_FIRMWARE = - "/lib/firmware/qed/qed_init_values-8.33.12.0.bin"; + "/lib/firmware/qed/qed_init_values-8.37.7.0.bin"; static void qed_update_pf_params(struct ecore_dev *edev, struct ecore_pf_params *params)