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GET /api/patches/45560/?format=api
{ "id": 45560, "url": "http://patches.dpdk.org/api/patches/45560/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20180928051647.32341-2-g.singh@nxp.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20180928051647.32341-2-g.singh@nxp.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20180928051647.32341-2-g.singh@nxp.com", "date": "2018-09-28T05:16:45", "name": "[v3,1/3] net/enetc: enable Rx and Tx", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "afdec26c2f01d91ffd74d0affc44295b5d694bf9", "submitter": { "id": 1068, "url": "http://patches.dpdk.org/api/people/1068/?format=api", "name": "Gagandeep Singh", "email": "g.singh@nxp.com" }, "delegate": null, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20180928051647.32341-2-g.singh@nxp.com/mbox/", "series": [ { "id": 1564, "url": "http://patches.dpdk.org/api/series/1564/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=1564", "date": "2018-09-28T05:16:44", "name": "introduces the enetc PMD driver", "version": 3, "mbox": "http://patches.dpdk.org/series/1564/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/45560/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/45560/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id B22861B149;\n\tFri, 28 Sep 2018 07:17:52 +0200 (CEST)", "from EUR02-AM5-obe.outbound.protection.outlook.com\n\t(mail-eopbgr00046.outbound.protection.outlook.com [40.107.0.46])\n\tby dpdk.org (Postfix) with ESMTP id 6C4411B112\n\tfor <dev@dpdk.org>; Fri, 28 Sep 2018 07:17:43 +0200 (CEST)", "from Tophie.ap.freescale.net (14.142.187.166) by\n\tDB5PR04MB1527.eurprd04.prod.outlook.com (2a01:111:e400:5993::21) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1185.20;\n\tFri, 28 Sep 2018 05:17:39 +0000" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1;\n\th=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n\tbh=CLiTOIzudkAFis0bdniyk+u56x5YgT3qiiLntKLa080=;\n\tb=OpHLgo+9GDykLojpnX87eWcmkbhR4eikjx41wfgKB17gT41YI9tAnJe9bzgnxV+wFlXkrVOa8Jk/H4oh+D1j03LWR3zOyZElW4/D32e29FWOlqWc8vYTAgpAvqsN0LEIS08AsDS3gutsnSaUQ0mJ8EmMSy6FU0qAYwBqw1ui0vg=", "Authentication-Results": "spf=none (sender IP is )\n\tsmtp.mailfrom=G.Singh@nxp.com; ", "From": "Gagandeep Singh <g.singh@nxp.com>", "To": "dev@dpdk.org,\n\tferruh.yigit@intel.com", "Cc": "pankaj.chauhan@nxp.com,\n\tGagandeep Singh <g.singh@nxp.com>", "Date": "Fri, 28 Sep 2018 10:46:45 +0530", "Message-Id": "<20180928051647.32341-2-g.singh@nxp.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20180928051647.32341-1-g.singh@nxp.com>", "References": "<20180913094201.17098-1-g.singh@nxp.com>\n\t<20180928051647.32341-1-g.singh@nxp.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[14.142.187.166]", "X-ClientProxiedBy": "MAXPR0101CA0035.INDPRD01.PROD.OUTLOOK.COM\n\t(2603:1096:a00:d::21) To DB5PR04MB1527.eurprd04.prod.outlook.com\n\t(2a01:111:e400:5993::21)", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "cfbd827c-2a65-45c1-662a-08d62501b6f5", "X-MS-Office365-Filtering-HT": "Tenant", "X-Microsoft-Antispam": "BCL:0; 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"JGtuwrbATfvQwFVmpsHTeshohW4EKiXZ10GRApDiDCSkTCpXwr5M4uhYp2rmDj/cEa4pgLdhwWoCqCeffa0zTFKfttuc8hFEv4lNbP2I7631layN+2gy9m7VHEx55dOGwaYOaijc8/PdVmeIPFdUo8gG4LnAxR6ROwsUd/uPEI9WbgyvOCFNIHDONzThr0PMWpBt1Z+qmod0HFlCR5Oqoo3co0Ijf4w5w50RhksSpEuV1Zrr5pWYF1xLSRvzOGJUIwTB8uGtZZotSMBLZE7U2dg+7LqSS5qpr8wZGX3b89D4I+XCUtJ/TYtUqc0FUQgiyhB42gr9QwLfSFNSMSyi/NYe6uUR3smz7iaym30XbKg=", "SpamDiagnosticOutput": "1:99", "SpamDiagnosticMetadata": "NSPM", "X-OriginatorOrg": "nxp.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "28 Sep 2018 05:17:39.7061\n\t(UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "cfbd827c-2a65-45c1-662a-08d62501b6f5", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "686ea1d3-bc2b-4c6f-a92c-d99c5c301635", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DB5PR04MB1527", "Subject": "[dpdk-dev] [PATCH v3 1/3] net/enetc: enable Rx and Tx", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add RX and TX queue setup, datapath functions\n\nSigned-off-by: Gagandeep Singh <g.singh@nxp.com>\n---\n drivers/net/enetc/Makefile | 3 +-\n drivers/net/enetc/base/enetc_hw.h | 19 +-\n drivers/net/enetc/enetc.h | 25 ++-\n drivers/net/enetc/enetc_ethdev.c | 326 +++++++++++++++++++++++++++++-\n drivers/net/enetc/enetc_rxtx.c | 239 ++++++++++++++++++++++\n drivers/net/enetc/meson.build | 3 +-\n 6 files changed, 602 insertions(+), 13 deletions(-)\n create mode 100644 drivers/net/enetc/enetc_rxtx.c", "diff": "diff --git a/drivers/net/enetc/Makefile b/drivers/net/enetc/Makefile\nindex 519153868..9895501db 100644\n--- a/drivers/net/enetc/Makefile\n+++ b/drivers/net/enetc/Makefile\n@@ -14,8 +14,9 @@ EXPORT_MAP := rte_pmd_enetc_version.map\n LIBABIVER := 1\n \n SRCS-$(CONFIG_RTE_LIBRTE_ENETC_PMD) += enetc_ethdev.c\n+SRCS-$(CONFIG_RTE_LIBRTE_ENETC_PMD) += enetc_rxtx.c\n \n-LDLIBS += -lrte_eal\n+LDLIBS += -lrte_eal -lrte_mbuf -lrte_mempool\n LDLIBS += -lrte_ethdev\n LDLIBS += -lrte_bus_pci\n \ndiff --git a/drivers/net/enetc/base/enetc_hw.h b/drivers/net/enetc/base/enetc_hw.h\nindex c962b9ca1..c74c94875 100644\n--- a/drivers/net/enetc/base/enetc_hw.h\n+++ b/drivers/net/enetc/base/enetc_hw.h\n@@ -104,16 +104,19 @@ enum enetc_bdr_type {TX, RX};\n #define ETH_ADDR_LEN\t\t\t6\n \n /* general register accessors */\n-#define enetc_rd_reg(reg)\trte_read32((reg))\n-#define enetc_wr_reg(reg, val)\trte_write32((val), (reg))\n-#define enetc_rd(hw, off)\tenetc_rd_reg((hw)->reg + (off))\n-#define enetc_wr(hw, off, val)\tenetc_wr_reg((hw)->reg + (off), val)\n+#define enetc_rd_reg(reg)\trte_read32((void *)(reg))\n+#define enetc_wr_reg(reg, val)\trte_write32((val), (void *)(reg))\n+#define enetc_rd(hw, off)\tenetc_rd_reg((size_t)(hw)->reg + (off))\n+#define enetc_wr(hw, off, val)\tenetc_wr_reg((size_t)(hw)->reg + (off), val)\n /* port register accessors - PF only */\n-#define enetc_port_rd(hw, off)\t\tenetc_rd_reg((hw)->port + (off))\n-#define enetc_port_wr(hw, off, val)\tenetc_wr_reg((hw)->port + (off), val)\n+#define enetc_port_rd(hw, off)\tenetc_rd_reg((size_t)(hw)->port + (off))\n+#define enetc_port_wr(hw, off, val) \\\n+\t\t\t\tenetc_wr_reg((size_t)(hw)->port + (off), val)\n /* global register accessors - PF only */\n-#define enetc_global_rd(hw, off)\tenetc_rd_reg((hw)->global + (off))\n-#define enetc_global_wr(hw, off, val)\tenetc_wr_reg((hw)->global + (off), val)\n+#define enetc_global_rd(hw, off) \\\n+\t\t\t\tenetc_rd_reg((size_t)(hw)->global + (off))\n+#define enetc_global_wr(hw, off, val) \\\n+\t\t\t\tenetc_wr_reg((size_t)(hw)->global + (off), val)\n /* BDR register accessors, see ENETC_BDR() */\n #define enetc_bdr_rd(hw, t, n, off) \\\n \t\t\t\tenetc_rd(hw, ENETC_BDR(t, n, off))\ndiff --git a/drivers/net/enetc/enetc.h b/drivers/net/enetc/enetc.h\nindex 9fa7c726c..140daf0dd 100644\n--- a/drivers/net/enetc/enetc.h\n+++ b/drivers/net/enetc/enetc.h\n@@ -18,7 +18,11 @@\n #define MAX_RX_RINGS\t1\n \n /* Max BD counts per Ring. */\n-#define MAX_BD_COUNT\t256\n+#define MAX_BD_COUNT\t64000\n+/* Min BD counts per Ring. */\n+#define MIN_BD_COUNT\t32\n+/* BD ALIGN */\n+#define BD_ALIGN\t8\n \n /*\n * upper_32_bits - return bits 32-63 of a number\n@@ -87,4 +91,23 @@ struct enetc_eth_adapter {\n #define ENETC_REG_WRITE(addr, val) (*(uint32_t *)addr = val)\n #define ENETC_REG_WRITE_RELAXED(addr, val) (*(uint32_t *)addr = val)\n \n+/*\n+ * RX/TX ENETC function prototypes\n+ */\n+uint16_t enetc_xmit_pkts(void *txq, struct rte_mbuf **tx_pkts,\n+\t\tuint16_t nb_pkts);\n+uint16_t enetc_recv_pkts(void *rxq, struct rte_mbuf **rx_pkts,\n+\t\tuint16_t nb_pkts);\n+\n+\n+int enetc_refill_rx_ring(struct enetc_bdr *rx_ring, const int buff_cnt);\n+\n+static inline int\n+enetc_bd_unused(struct enetc_bdr *bdr)\n+{\n+\tif (bdr->next_to_clean > bdr->next_to_use)\n+\t\treturn bdr->next_to_clean - bdr->next_to_use - 1;\n+\n+\treturn bdr->bd_count + bdr->next_to_clean - bdr->next_to_use - 1;\n+}\n #endif /* _ENETC_H_ */\ndiff --git a/drivers/net/enetc/enetc_ethdev.c b/drivers/net/enetc/enetc_ethdev.c\nindex 47e2a8ebf..2d90d8fd5 100644\n--- a/drivers/net/enetc/enetc_ethdev.c\n+++ b/drivers/net/enetc/enetc_ethdev.c\n@@ -19,6 +19,15 @@ static void enetc_dev_infos_get(struct rte_eth_dev *dev,\n \t\t\t\tstruct rte_eth_dev_info *dev_info);\n static int enetc_link_update(struct rte_eth_dev *dev, int wait_to_complete);\n static int enetc_hardware_init(struct enetc_eth_hw *hw);\n+static int enetc_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id,\n+\t\tuint16_t nb_rx_desc, unsigned int socket_id,\n+\t\tconst struct rte_eth_rxconf *rx_conf,\n+\t\tstruct rte_mempool *mb_pool);\n+static void enetc_rx_queue_release(void *rxq);\n+static int enetc_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id,\n+\t\tuint16_t nb_tx_desc, unsigned int socket_id,\n+\t\tconst struct rte_eth_txconf *tx_conf);\n+static void enetc_tx_queue_release(void *txq);\n \n /*\n * The set of PCI devices this driver supports\n@@ -37,6 +46,10 @@ static const struct eth_dev_ops enetc_ops = {\n \t.dev_close = enetc_dev_close,\n \t.link_update = enetc_link_update,\n \t.dev_infos_get = enetc_dev_infos_get,\n+\t.rx_queue_setup = enetc_rx_queue_setup,\n+\t.rx_queue_release = enetc_rx_queue_release,\n+\t.tx_queue_setup = enetc_tx_queue_setup,\n+\t.tx_queue_release = enetc_tx_queue_release,\n };\n \n /**\n@@ -59,8 +72,8 @@ enetc_dev_init(struct rte_eth_dev *eth_dev)\n \n \tPMD_INIT_FUNC_TRACE();\n \teth_dev->dev_ops = &enetc_ops;\n-\teth_dev->rx_pkt_burst = NULL;\n-\teth_dev->tx_pkt_burst = NULL;\n+\teth_dev->rx_pkt_burst = &enetc_recv_pkts;\n+\teth_dev->tx_pkt_burst = &enetc_xmit_pkts;\n \n \t/* Retrieving and storing the HW base address of device */\n \thw->hw.reg = (void *)pci_dev->mem_resource[0].addr;\n@@ -212,11 +225,320 @@ enetc_dev_infos_get(struct rte_eth_dev *dev __rte_unused,\n \t\t struct rte_eth_dev_info *dev_info)\n {\n \tPMD_INIT_FUNC_TRACE();\n+\tdev_info->rx_desc_lim = (struct rte_eth_desc_lim) {\n+\t\t.nb_max = MAX_BD_COUNT,\n+\t\t.nb_min = MIN_BD_COUNT,\n+\t\t.nb_align = BD_ALIGN,\n+\t};\n+\tdev_info->tx_desc_lim = (struct rte_eth_desc_lim) {\n+\t\t.nb_max = MAX_BD_COUNT,\n+\t\t.nb_min = MIN_BD_COUNT,\n+\t\t.nb_align = BD_ALIGN,\n+\t};\n \tdev_info->max_rx_queues = MAX_RX_RINGS;\n \tdev_info->max_tx_queues = MAX_TX_RINGS;\n \tdev_info->max_rx_pktlen = 1500;\n }\n \n+static int\n+enetc_alloc_txbdr(struct enetc_bdr *txr, uint16_t nb_desc)\n+{\n+\tint size;\n+\n+\tsize = nb_desc * sizeof(struct enetc_swbd);\n+\ttxr->q_swbd = rte_malloc(NULL, size, RTE_CACHE_LINE_SIZE);\n+\tif (txr->q_swbd == NULL)\n+\t\treturn -ENOMEM;\n+\n+\tsize = nb_desc * sizeof(struct enetc_tx_bd);\n+\ttxr->bd_base = rte_malloc(NULL, size, RTE_CACHE_LINE_SIZE);\n+\tif (txr->bd_base == NULL) {\n+\t\trte_free(txr->q_swbd);\n+\t\ttxr->q_swbd = NULL;\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\ttxr->bd_count = nb_desc;\n+\ttxr->next_to_clean = 0;\n+\ttxr->next_to_use = 0;\n+\n+\treturn 0;\n+}\n+\n+static void\n+enetc_free_bdr(struct enetc_bdr *rxr)\n+{\n+\trte_free(rxr->q_swbd);\n+\trte_free(rxr->bd_base);\n+\trxr->q_swbd = NULL;\n+\trxr->bd_base = NULL;\n+}\n+\n+static void\n+enetc_setup_txbdr(struct enetc_hw *hw, struct enetc_bdr *tx_ring)\n+{\n+\tint idx = tx_ring->index;\n+\tuintptr_t base_addr;\n+\tuint32_t tbmr;\n+\n+\tbase_addr = (uintptr_t)tx_ring->bd_base;\n+\tenetc_txbdr_wr(hw, idx, ENETC_TBBAR0,\n+\t\t lower_32_bits((uint64_t)base_addr));\n+\tenetc_txbdr_wr(hw, idx, ENETC_TBBAR1,\n+\t\t upper_32_bits((uint64_t)base_addr));\n+\tenetc_txbdr_wr(hw, idx, ENETC_TBLENR,\n+\t\t ENETC_RTBLENR_LEN(tx_ring->bd_count));\n+\n+\ttbmr = ENETC_TBMR_EN;\n+\t/* enable ring */\n+\tenetc_txbdr_wr(hw, idx, ENETC_TBMR, tbmr);\n+\tenetc_txbdr_wr(hw, idx, ENETC_TBCIR, 0);\n+\tenetc_txbdr_wr(hw, idx, ENETC_TBCISR, 0);\n+\ttx_ring->tcir = (void *)((size_t)hw->reg +\n+\t\t\tENETC_BDR(TX, idx, ENETC_TBCIR));\n+\ttx_ring->tcisr = (void *)((size_t)hw->reg +\n+\t\t\t ENETC_BDR(TX, idx, ENETC_TBCISR));\n+}\n+\n+static int\n+enetc_alloc_tx_resources(struct rte_eth_dev *dev,\n+\t\t\t uint16_t queue_idx,\n+\t\t\t uint16_t nb_desc)\n+{\n+\tint err;\n+\tstruct enetc_bdr *tx_ring;\n+\tstruct rte_eth_dev_data *data = dev->data;\n+\tstruct enetc_eth_adapter *priv =\n+\t\t\tENETC_DEV_PRIVATE(data->dev_private);\n+\n+\ttx_ring = rte_zmalloc(NULL, sizeof(struct enetc_bdr), 0);\n+\tif (tx_ring == NULL) {\n+\t\tENETC_PMD_ERR(\"Failed to allocate TX ring memory\");\n+\t\terr = -ENOMEM;\n+\t\treturn -1;\n+\t}\n+\n+\terr = enetc_alloc_txbdr(tx_ring, nb_desc);\n+\tif (err)\n+\t\tgoto fail;\n+\n+\ttx_ring->index = queue_idx;\n+\ttx_ring->ndev = dev;\n+\tenetc_setup_txbdr(&priv->hw.hw, tx_ring);\n+\tdata->tx_queues[queue_idx] = tx_ring;\n+\n+\treturn 0;\n+fail:\n+\trte_free(tx_ring);\n+\n+\treturn err;\n+}\n+\n+static int\n+enetc_tx_queue_setup(struct rte_eth_dev *dev,\n+\t\t uint16_t queue_idx,\n+\t\t uint16_t nb_desc,\n+\t\t unsigned int socket_id __rte_unused,\n+\t\t const struct rte_eth_txconf *tx_conf __rte_unused)\n+{\n+\tint err = 0;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\tif (nb_desc > MAX_BD_COUNT)\n+\t\treturn -1;\n+\n+\terr = enetc_alloc_tx_resources(dev, queue_idx, nb_desc);\n+\n+\treturn err;\n+}\n+\n+static void\n+enetc_tx_queue_release(void *txq)\n+{\n+\tif (txq == NULL)\n+\t\treturn;\n+\n+\tstruct enetc_bdr *tx_ring = (struct enetc_bdr *)txq;\n+\tstruct enetc_eth_hw *eth_hw =\n+\t\tENETC_DEV_PRIVATE_TO_HW(tx_ring->ndev->data->dev_private);\n+\tstruct enetc_hw *hw;\n+\tstruct enetc_swbd *tx_swbd;\n+\tint i;\n+\tuint32_t val;\n+\n+\t/* Disable the ring */\n+\thw = ð_hw->hw;\n+\tval = enetc_txbdr_rd(hw, tx_ring->index, ENETC_TBMR);\n+\tval &= (~ENETC_TBMR_EN);\n+\tenetc_txbdr_wr(hw, tx_ring->index, ENETC_TBMR, val);\n+\n+\t/* clean the ring*/\n+\ti = tx_ring->next_to_clean;\n+\ttx_swbd = &tx_ring->q_swbd[i];\n+\twhile (tx_swbd->buffer_addr != NULL) {\n+\t\trte_pktmbuf_free(tx_swbd->buffer_addr);\n+\t\ttx_swbd->buffer_addr = NULL;\n+\t\ttx_swbd++;\n+\t\ti++;\n+\t\tif (unlikely(i == tx_ring->bd_count)) {\n+\t\t\ti = 0;\n+\t\t\ttx_swbd = &tx_ring->q_swbd[i];\n+\t\t}\n+\t}\n+\n+\tenetc_free_bdr(tx_ring);\n+\trte_free(tx_ring);\n+}\n+\n+static int\n+enetc_alloc_rxbdr(struct enetc_bdr *rxr,\n+\t\t uint16_t nb_rx_desc)\n+{\n+\tint size;\n+\n+\tsize = nb_rx_desc * sizeof(struct enetc_swbd);\n+\trxr->q_swbd = rte_malloc(NULL, size, RTE_CACHE_LINE_SIZE);\n+\tif (rxr->q_swbd == NULL)\n+\t\treturn -ENOMEM;\n+\n+\tsize = nb_rx_desc * sizeof(union enetc_rx_bd);\n+\trxr->bd_base = rte_malloc(NULL, size, RTE_CACHE_LINE_SIZE);\n+\tif (rxr->bd_base == NULL) {\n+\t\trte_free(rxr->q_swbd);\n+\t\trxr->q_swbd = NULL;\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\trxr->bd_count = nb_rx_desc;\n+\trxr->next_to_clean = 0;\n+\trxr->next_to_use = 0;\n+\trxr->next_to_alloc = 0;\n+\n+\treturn 0;\n+}\n+\n+static void\n+enetc_setup_rxbdr(struct enetc_hw *hw, struct enetc_bdr *rx_ring,\n+\t\t struct rte_mempool *mb_pool)\n+{\n+\tint idx = rx_ring->index;\n+\tuintptr_t base_addr;\n+\tuint16_t buf_size;\n+\n+\tbase_addr = (uintptr_t)rx_ring->bd_base;\n+\tenetc_rxbdr_wr(hw, idx, ENETC_RBBAR0,\n+\t\t lower_32_bits((uint64_t)base_addr));\n+\tenetc_rxbdr_wr(hw, idx, ENETC_RBBAR1,\n+\t\t upper_32_bits((uint64_t)base_addr));\n+\tenetc_rxbdr_wr(hw, idx, ENETC_RBLENR,\n+\t\t ENETC_RTBLENR_LEN(rx_ring->bd_count));\n+\n+\trx_ring->mb_pool = mb_pool;\n+\t/* enable ring */\n+\tenetc_rxbdr_wr(hw, idx, ENETC_RBMR, ENETC_RBMR_EN);\n+\tenetc_rxbdr_wr(hw, idx, ENETC_RBPIR, 0);\n+\trx_ring->rcir = (void *)((size_t)hw->reg +\n+\t\t\tENETC_BDR(RX, idx, ENETC_RBCIR));\n+\tenetc_refill_rx_ring(rx_ring, (enetc_bd_unused(rx_ring)));\n+\tbuf_size = (uint16_t)(rte_pktmbuf_data_room_size(rx_ring->mb_pool) -\n+\t\t RTE_PKTMBUF_HEADROOM);\n+\tenetc_rxbdr_wr(hw, idx, ENETC_RBBSR, buf_size);\n+}\n+\n+static int\n+enetc_alloc_rx_resources(struct rte_eth_dev *dev,\n+\t\t\t uint16_t rx_queue_id,\n+\t\t\t uint16_t nb_rx_desc,\n+\t\t\t struct rte_mempool *mb_pool)\n+{\n+\tint err;\n+\tstruct enetc_bdr *rx_ring;\n+\tstruct rte_eth_dev_data *data = dev->data;\n+\tstruct enetc_eth_adapter *adapter =\n+\t\t\tENETC_DEV_PRIVATE(data->dev_private);\n+\n+\trx_ring = rte_zmalloc(NULL, sizeof(struct enetc_bdr), 0);\n+\tif (rx_ring == NULL) {\n+\t\tENETC_PMD_ERR(\"Failed to allocate RX ring memory\");\n+\t\terr = -ENOMEM;\n+\t\treturn err;\n+\t}\n+\n+\terr = enetc_alloc_rxbdr(rx_ring, nb_rx_desc);\n+\tif (err)\n+\t\tgoto fail;\n+\n+\trx_ring->index = rx_queue_id;\n+\trx_ring->ndev = dev;\n+\tenetc_setup_rxbdr(&adapter->hw.hw, rx_ring, mb_pool);\n+\tdata->rx_queues[rx_queue_id] = rx_ring;\n+\n+\treturn 0;\n+fail:\n+\trte_free(rx_ring);\n+\n+\treturn err;\n+}\n+\n+static int\n+enetc_rx_queue_setup(struct rte_eth_dev *dev,\n+\t\t uint16_t rx_queue_id,\n+\t\t uint16_t nb_rx_desc,\n+\t\t unsigned int socket_id __rte_unused,\n+\t\t const struct rte_eth_rxconf *rx_conf __rte_unused,\n+\t\t struct rte_mempool *mb_pool)\n+{\n+\tint err = 0;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\tif (nb_rx_desc > MAX_BD_COUNT)\n+\t\treturn -1;\n+\n+\terr = enetc_alloc_rx_resources(dev, rx_queue_id,\n+\t\t\t\t nb_rx_desc,\n+\t\t\t\t mb_pool);\n+\n+\treturn err;\n+}\n+\n+static void\n+enetc_rx_queue_release(void *rxq)\n+{\n+\tif (rxq == NULL)\n+\t\treturn;\n+\n+\tstruct enetc_bdr *rx_ring = (struct enetc_bdr *)rxq;\n+\tstruct enetc_eth_hw *eth_hw =\n+\t\tENETC_DEV_PRIVATE_TO_HW(rx_ring->ndev->data->dev_private);\n+\tstruct enetc_swbd *q_swbd;\n+\tstruct enetc_hw *hw;\n+\tuint32_t val;\n+\tint i;\n+\n+\t/* Disable the ring */\n+\thw = ð_hw->hw;\n+\tval = enetc_rxbdr_rd(hw, rx_ring->index, ENETC_RBMR);\n+\tval &= (~ENETC_RBMR_EN);\n+\tenetc_rxbdr_wr(hw, rx_ring->index, ENETC_RBMR, val);\n+\n+\t/* Clean the ring */\n+\ti = rx_ring->next_to_clean;\n+\tq_swbd = &rx_ring->q_swbd[i];\n+\twhile (i != rx_ring->next_to_use) {\n+\t\trte_pktmbuf_free(q_swbd->buffer_addr);\n+\t\tq_swbd->buffer_addr = NULL;\n+\t\tq_swbd++;\n+\t\ti++;\n+\t\tif (unlikely(i == rx_ring->bd_count)) {\n+\t\t\ti = 0;\n+\t\t\tq_swbd = &rx_ring->q_swbd[i];\n+\t\t}\n+\t}\n+\n+\tenetc_free_bdr(rx_ring);\n+\trte_free(rx_ring);\n+}\n+\n static int\n enetc_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,\n \t\t\t struct rte_pci_device *pci_dev)\ndiff --git a/drivers/net/enetc/enetc_rxtx.c b/drivers/net/enetc/enetc_rxtx.c\nnew file mode 100644\nindex 000000000..631e2430d\n--- /dev/null\n+++ b/drivers/net/enetc/enetc_rxtx.c\n@@ -0,0 +1,239 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright 2018 NXP\n+ */\n+\n+#include <stdbool.h>\n+#include <stdint.h>\n+#include <unistd.h>\n+\n+#include \"rte_ethdev.h\"\n+#include \"rte_malloc.h\"\n+#include \"rte_memzone.h\"\n+\n+#include \"base/enetc_hw.h\"\n+#include \"enetc.h\"\n+#include \"enetc_logs.h\"\n+\n+#define ENETC_RXBD_BUNDLE 8 /* Number of BDs to update at once */\n+\n+static int\n+enetc_clean_tx_ring(struct enetc_bdr *tx_ring)\n+{\n+\tint tx_frm_cnt = 0;\n+\tstruct enetc_swbd *tx_swbd;\n+\tint i;\n+\n+\ti = tx_ring->next_to_clean;\n+\ttx_swbd = &tx_ring->q_swbd[i];\n+\twhile ((int)(enetc_rd_reg(tx_ring->tcisr) &\n+\t ENETC_TBCISR_IDX_MASK) != i) {\n+\t\trte_pktmbuf_free(tx_swbd->buffer_addr);\n+\t\ttx_swbd->buffer_addr = NULL;\n+\t\ttx_swbd++;\n+\t\ti++;\n+\t\tif (unlikely(i == tx_ring->bd_count)) {\n+\t\t\ti = 0;\n+\t\t\ttx_swbd = &tx_ring->q_swbd[0];\n+\t\t}\n+\n+\t\ttx_frm_cnt++;\n+\t}\n+\n+\ttx_ring->next_to_clean = i;\n+\treturn tx_frm_cnt++;\n+}\n+\n+uint16_t\n+enetc_xmit_pkts(void *tx_queue,\n+\t\tstruct rte_mbuf **tx_pkts,\n+\t\tuint16_t nb_pkts)\n+{\n+\tstruct enetc_swbd *tx_swbd;\n+\tint i, start;\n+\tstruct enetc_tx_bd *txbd;\n+\tstruct enetc_bdr *tx_ring = (struct enetc_bdr *)tx_queue;\n+\n+\ti = tx_ring->next_to_use;\n+\tstart = 0;\n+\twhile (nb_pkts--) {\n+\t\tenetc_clean_tx_ring(tx_ring);\n+\t\ttx_ring->q_swbd[i].buffer_addr = tx_pkts[start];\n+\t\ttxbd = ENETC_TXBD(*tx_ring, i);\n+\t\ttx_swbd = &tx_ring->q_swbd[i];\n+\t\ttxbd->frm_len = tx_pkts[start]->pkt_len;\n+\t\ttxbd->buf_len = txbd->frm_len;\n+\t\ttxbd->flags = rte_cpu_to_le_16(ENETC_TXBD_FLAGS_F);\n+\t\ttxbd->addr = (uint64_t)(uintptr_t)\n+\t\trte_cpu_to_le_64((size_t)tx_swbd->buffer_addr->buf_addr +\n+\t\t\t\t tx_swbd->buffer_addr->data_off);\n+\t\ti++;\n+\t\tstart++;\n+\t\tif (unlikely(i == tx_ring->bd_count))\n+\t\t\ti = 0;\n+\t}\n+\n+\ttx_ring->next_to_use = i;\n+\tenetc_wr_reg(tx_ring->tcir, i);\n+\treturn start;\n+}\n+\n+int\n+enetc_refill_rx_ring(struct enetc_bdr *rx_ring, const int buff_cnt)\n+{\n+\tstruct enetc_swbd *rx_swbd;\n+\tunion enetc_rx_bd *rxbd;\n+\tint i, j;\n+\n+\ti = rx_ring->next_to_use;\n+\trx_swbd = &rx_ring->q_swbd[i];\n+\trxbd = ENETC_RXBD(*rx_ring, i);\n+\tfor (j = 0; j < buff_cnt; j++) {\n+\t\trx_swbd->buffer_addr =\n+\t\t\trte_cpu_to_le_64(rte_mbuf_raw_alloc(rx_ring->mb_pool));\n+\t\trxbd->w.addr = (uint64_t)(uintptr_t)\n+\t\t\t rx_swbd->buffer_addr->buf_addr +\n+\t\t\t rx_swbd->buffer_addr->data_off;\n+\t\t/* clear 'R\" as well */\n+\t\trxbd->r.lstatus = 0;\n+\t\trx_swbd++;\n+\t\trxbd++;\n+\t\ti++;\n+\t\tif (unlikely(i == rx_ring->bd_count)) {\n+\t\t\ti = 0;\n+\t\t\trxbd = ENETC_RXBD(*rx_ring, 0);\n+\t\t\trx_swbd = &rx_ring->q_swbd[i];\n+\t\t}\n+\t}\n+\n+\tif (likely(j)) {\n+\t\trx_ring->next_to_alloc = i;\n+\t\trx_ring->next_to_use = i;\n+\t\tenetc_wr_reg(rx_ring->rcir, i);\n+\t}\n+\n+\treturn j;\n+}\n+\n+\n+static inline void __attribute__((hot))\n+enetc_dev_rx_parse(struct rte_mbuf *m, uint16_t parse_results)\n+{\n+\tENETC_PMD_DP_DEBUG(\"parse summary = 0x%x \", parse_results);\n+\n+\tm->packet_type = RTE_PTYPE_UNKNOWN;\n+\tswitch (parse_results) {\n+\tcase ENETC_PKT_TYPE_ETHER:\n+\t\tm->packet_type = RTE_PTYPE_L2_ETHER;\n+\t\tbreak;\n+\tcase ENETC_PKT_TYPE_IPV4:\n+\t\tm->packet_type = RTE_PTYPE_L2_ETHER |\n+\t\t\t\t RTE_PTYPE_L3_IPV4;\n+\t\tbreak;\n+\tcase ENETC_PKT_TYPE_IPV6:\n+\t\tm->packet_type = RTE_PTYPE_L2_ETHER |\n+\t\t\t\t RTE_PTYPE_L3_IPV6;\n+\t\tbreak;\n+\tcase ENETC_PKT_TYPE_IPV4_TCP:\n+\t\tm->packet_type = RTE_PTYPE_L2_ETHER |\n+\t\t\t\t RTE_PTYPE_L3_IPV4 |\n+\t\t\t\t RTE_PTYPE_L4_TCP;\n+\t\tbreak;\n+\tcase ENETC_PKT_TYPE_IPV6_TCP:\n+\t\tm->packet_type = RTE_PTYPE_L2_ETHER |\n+\t\t\t\t RTE_PTYPE_L3_IPV6 |\n+\t\t\t\t RTE_PTYPE_L4_TCP;\n+\t\tbreak;\n+\tcase ENETC_PKT_TYPE_IPV4_UDP:\n+\t\tm->packet_type = RTE_PTYPE_L2_ETHER |\n+\t\t\t\t RTE_PTYPE_L3_IPV4 |\n+\t\t\t\t RTE_PTYPE_L4_UDP;\n+\t\tbreak;\n+\tcase ENETC_PKT_TYPE_IPV6_UDP:\n+\t\tm->packet_type = RTE_PTYPE_L2_ETHER |\n+\t\t\t\t RTE_PTYPE_L3_IPV6 |\n+\t\t\t\t RTE_PTYPE_L4_UDP;\n+\t\tbreak;\n+\tcase ENETC_PKT_TYPE_IPV4_SCTP:\n+\t\tm->packet_type = RTE_PTYPE_L2_ETHER |\n+\t\t\t\t RTE_PTYPE_L3_IPV4 |\n+\t\t\t\t RTE_PTYPE_L4_SCTP;\n+\t\tbreak;\n+\tcase ENETC_PKT_TYPE_IPV6_SCTP:\n+\t\tm->packet_type = RTE_PTYPE_L2_ETHER |\n+\t\t\t\t RTE_PTYPE_L3_IPV6 |\n+\t\t\t\t RTE_PTYPE_L4_SCTP;\n+\t\tbreak;\n+\tcase ENETC_PKT_TYPE_IPV4_ICMP:\n+\t\tm->packet_type = RTE_PTYPE_L2_ETHER |\n+\t\t\t\t RTE_PTYPE_L3_IPV4 |\n+\t\t\t\t RTE_PTYPE_L4_ICMP;\n+\t\tbreak;\n+\tcase ENETC_PKT_TYPE_IPV6_ICMP:\n+\t\tm->packet_type = RTE_PTYPE_L2_ETHER |\n+\t\t\t\t RTE_PTYPE_L3_IPV6 |\n+\t\t\t\t RTE_PTYPE_L4_ICMP;\n+\t\tbreak;\n+\t/* More switch cases can be added */\n+\tdefault:\n+\t\tm->packet_type = RTE_PTYPE_UNKNOWN;\n+\t}\n+}\n+\n+static int\n+enetc_clean_rx_ring(struct enetc_bdr *rx_ring,\n+\t\t struct rte_mbuf **rx_pkts,\n+\t\t int work_limit)\n+{\n+\tint rx_frm_cnt = 0;\n+\tint cleaned_cnt, i;\n+\tstruct enetc_swbd *rx_swbd;\n+\n+\tcleaned_cnt = enetc_bd_unused(rx_ring);\n+\t/* next descriptor to process */\n+\ti = rx_ring->next_to_clean;\n+\trx_swbd = &rx_ring->q_swbd[i];\n+\twhile (likely(rx_frm_cnt < work_limit)) {\n+\t\tunion enetc_rx_bd *rxbd;\n+\t\tuint32_t bd_status;\n+\n+\t\tif (cleaned_cnt >= ENETC_RXBD_BUNDLE) {\n+\t\t\tint count = enetc_refill_rx_ring(rx_ring, cleaned_cnt);\n+\n+\t\t\tcleaned_cnt -= count;\n+\t\t}\n+\n+\t\trxbd = ENETC_RXBD(*rx_ring, i);\n+\t\tbd_status = rte_le_to_cpu_32(rxbd->r.lstatus);\n+\t\tif (!bd_status)\n+\t\t\tbreak;\n+\n+\t\trx_swbd->buffer_addr->pkt_len = rxbd->r.buf_len;\n+\t\trx_swbd->buffer_addr->data_len = rxbd->r.buf_len;\n+\t\trx_swbd->buffer_addr->hash.rss = rxbd->r.rss_hash;\n+\t\trx_swbd->buffer_addr->ol_flags = 0;\n+\t\tenetc_dev_rx_parse(rx_swbd->buffer_addr,\n+\t\t\t\t rxbd->r.parse_summary);\n+\t\trx_pkts[rx_frm_cnt] = rx_swbd->buffer_addr;\n+\t\tcleaned_cnt++;\n+\t\trx_swbd++;\n+\t\ti++;\n+\t\tif (unlikely(i == rx_ring->bd_count)) {\n+\t\t\ti = 0;\n+\t\t\trx_swbd = &rx_ring->q_swbd[i];\n+\t\t}\n+\n+\t\trx_ring->next_to_clean = i;\n+\t\trx_frm_cnt++;\n+\t}\n+\n+\treturn rx_frm_cnt;\n+}\n+\n+uint16_t\n+enetc_recv_pkts(void *rxq, struct rte_mbuf **rx_pkts,\n+\t\tuint16_t nb_pkts)\n+{\n+\tstruct enetc_bdr *rx_ring = (struct enetc_bdr *)rxq;\n+\n+\treturn enetc_clean_rx_ring(rx_ring, rx_pkts, nb_pkts);\n+}\ndiff --git a/drivers/net/enetc/meson.build b/drivers/net/enetc/meson.build\nindex 506b174ed..733156bbf 100644\n--- a/drivers/net/enetc/meson.build\n+++ b/drivers/net/enetc/meson.build\n@@ -5,6 +5,7 @@ if host_machine.system() != 'linux'\n \tbuild = false\n endif\n \n-sources = files('enetc_ethdev.c')\n+sources = files('enetc_ethdev.c',\n+\t\t'enetc_rxtx.c')\n \n includes += include_directories('base')\n", "prefixes": [ "v3", "1/3" ] }