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DB5PR04MB1527; 6:4j3Iq6I9jWVTLWfJ+VQsFc7ofreTgsOA+6UCZrGX5+vA3wwK7CaBZMUy7XIwmSXkU9IgxQcV7rH7Q/+l7GxAvjP6hl+c6saZ08Eu5kvnGQnLYq3Dl8JCWkbg/Od3r0xl31RVlFRiIH2Tsua0ESEyEzVfidggmbV0qeBSzJGvXgRS29y8NhKvBkYldOm0Hcxy0ohIzhaiWyhqHKEhRP1TRRW12AgI1T60ZR7VKJFuzSfwg88066DUqchw7SAVxfFcEC9yvIgyYWVmY4l+rdzREeyrkr+Q9Boj90fKI0SufjX3WI79R1S7DzeBpDT414Q9v7taCpLs5X/QBYkVOvI1mLlpcnFKmTF5gqnlIXxK3CKrtbDlwg37pavYiPHMsqZV3HVOF6BHQz9NUQHsEDgOrx1E5PE+gt5luPiw5MWooyYGL7xS7J/gWjdzQ4j5uXvIOeyIX+dKHFWkkuI2cZf2wQ==; 5:TIYj7CBbTPPLBDMhXJjObO7nHbW7Vk8NpHApNFJzDpIDNsoK0/IWvBk8+PS29+5FGFgzyXWYDOXUwfN3puaZjYpJToSO1EkiTekkhoqXgKIBdoGZm9Oi6zqAPJmkG8oj6p/po+Xj7fW72pilVhh0cnrAsNura7DeJ8H3rmLH1Es=; 7:m1li6X2m3mZ4aRv0yrvnLRtPygqZQU3akGYEzs3BjfU7ZsDLVuUFOlFkke3DZIlkhTbACEJyyEkVxe0B5yRaP2b4lyNmUzovw124gkjmly21ZvicCAgGZfKxUro2BEZuIOpez4rlrUnc8Kq/sI3YzqZuTbDe2sM3fwF/zEklRmJNfIaw6yoSRyIhplnPBHdjJfwUQoyE0GiZte4zWkL2F+S9fqx8wW+p2IIEYEB4Rpm5++tn4sKxsMzUruqo/ekz SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Sep 2018 05:17:39.7061 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cfbd827c-2a65-45c1-662a-08d62501b6f5 X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB5PR04MB1527 Subject: [dpdk-dev] [PATCH v3 1/3] net/enetc: enable Rx and Tx X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add RX and TX queue setup, datapath functions Signed-off-by: Gagandeep Singh --- drivers/net/enetc/Makefile | 3 +- drivers/net/enetc/base/enetc_hw.h | 19 +- drivers/net/enetc/enetc.h | 25 ++- drivers/net/enetc/enetc_ethdev.c | 326 +++++++++++++++++++++++++++++- drivers/net/enetc/enetc_rxtx.c | 239 ++++++++++++++++++++++ drivers/net/enetc/meson.build | 3 +- 6 files changed, 602 insertions(+), 13 deletions(-) create mode 100644 drivers/net/enetc/enetc_rxtx.c diff --git a/drivers/net/enetc/Makefile b/drivers/net/enetc/Makefile index 519153868..9895501db 100644 --- a/drivers/net/enetc/Makefile +++ b/drivers/net/enetc/Makefile @@ -14,8 +14,9 @@ EXPORT_MAP := rte_pmd_enetc_version.map LIBABIVER := 1 SRCS-$(CONFIG_RTE_LIBRTE_ENETC_PMD) += enetc_ethdev.c +SRCS-$(CONFIG_RTE_LIBRTE_ENETC_PMD) += enetc_rxtx.c -LDLIBS += -lrte_eal +LDLIBS += -lrte_eal -lrte_mbuf -lrte_mempool LDLIBS += -lrte_ethdev LDLIBS += -lrte_bus_pci diff --git a/drivers/net/enetc/base/enetc_hw.h b/drivers/net/enetc/base/enetc_hw.h index c962b9ca1..c74c94875 100644 --- a/drivers/net/enetc/base/enetc_hw.h +++ b/drivers/net/enetc/base/enetc_hw.h @@ -104,16 +104,19 @@ enum enetc_bdr_type {TX, RX}; #define ETH_ADDR_LEN 6 /* general register accessors */ -#define enetc_rd_reg(reg) rte_read32((reg)) -#define enetc_wr_reg(reg, val) rte_write32((val), (reg)) -#define enetc_rd(hw, off) enetc_rd_reg((hw)->reg + (off)) -#define enetc_wr(hw, off, val) enetc_wr_reg((hw)->reg + (off), val) +#define enetc_rd_reg(reg) rte_read32((void *)(reg)) +#define enetc_wr_reg(reg, val) rte_write32((val), (void *)(reg)) +#define enetc_rd(hw, off) enetc_rd_reg((size_t)(hw)->reg + (off)) +#define enetc_wr(hw, off, val) enetc_wr_reg((size_t)(hw)->reg + (off), val) /* port register accessors - PF only */ -#define enetc_port_rd(hw, off) enetc_rd_reg((hw)->port + (off)) -#define enetc_port_wr(hw, off, val) enetc_wr_reg((hw)->port + (off), val) +#define enetc_port_rd(hw, off) enetc_rd_reg((size_t)(hw)->port + (off)) +#define enetc_port_wr(hw, off, val) \ + enetc_wr_reg((size_t)(hw)->port + (off), val) /* global register accessors - PF only */ -#define enetc_global_rd(hw, off) enetc_rd_reg((hw)->global + (off)) -#define enetc_global_wr(hw, off, val) enetc_wr_reg((hw)->global + (off), val) +#define enetc_global_rd(hw, off) \ + enetc_rd_reg((size_t)(hw)->global + (off)) +#define enetc_global_wr(hw, off, val) \ + enetc_wr_reg((size_t)(hw)->global + (off), val) /* BDR register accessors, see ENETC_BDR() */ #define enetc_bdr_rd(hw, t, n, off) \ enetc_rd(hw, ENETC_BDR(t, n, off)) diff --git a/drivers/net/enetc/enetc.h b/drivers/net/enetc/enetc.h index 9fa7c726c..140daf0dd 100644 --- a/drivers/net/enetc/enetc.h +++ b/drivers/net/enetc/enetc.h @@ -18,7 +18,11 @@ #define MAX_RX_RINGS 1 /* Max BD counts per Ring. */ -#define MAX_BD_COUNT 256 +#define MAX_BD_COUNT 64000 +/* Min BD counts per Ring. */ +#define MIN_BD_COUNT 32 +/* BD ALIGN */ +#define BD_ALIGN 8 /* * upper_32_bits - return bits 32-63 of a number @@ -87,4 +91,23 @@ struct enetc_eth_adapter { #define ENETC_REG_WRITE(addr, val) (*(uint32_t *)addr = val) #define ENETC_REG_WRITE_RELAXED(addr, val) (*(uint32_t *)addr = val) +/* + * RX/TX ENETC function prototypes + */ +uint16_t enetc_xmit_pkts(void *txq, struct rte_mbuf **tx_pkts, + uint16_t nb_pkts); +uint16_t enetc_recv_pkts(void *rxq, struct rte_mbuf **rx_pkts, + uint16_t nb_pkts); + + +int enetc_refill_rx_ring(struct enetc_bdr *rx_ring, const int buff_cnt); + +static inline int +enetc_bd_unused(struct enetc_bdr *bdr) +{ + if (bdr->next_to_clean > bdr->next_to_use) + return bdr->next_to_clean - bdr->next_to_use - 1; + + return bdr->bd_count + bdr->next_to_clean - bdr->next_to_use - 1; +} #endif /* _ENETC_H_ */ diff --git a/drivers/net/enetc/enetc_ethdev.c b/drivers/net/enetc/enetc_ethdev.c index 47e2a8ebf..2d90d8fd5 100644 --- a/drivers/net/enetc/enetc_ethdev.c +++ b/drivers/net/enetc/enetc_ethdev.c @@ -19,6 +19,15 @@ static void enetc_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info); static int enetc_link_update(struct rte_eth_dev *dev, int wait_to_complete); static int enetc_hardware_init(struct enetc_eth_hw *hw); +static int enetc_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id, + uint16_t nb_rx_desc, unsigned int socket_id, + const struct rte_eth_rxconf *rx_conf, + struct rte_mempool *mb_pool); +static void enetc_rx_queue_release(void *rxq); +static int enetc_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id, + uint16_t nb_tx_desc, unsigned int socket_id, + const struct rte_eth_txconf *tx_conf); +static void enetc_tx_queue_release(void *txq); /* * The set of PCI devices this driver supports @@ -37,6 +46,10 @@ static const struct eth_dev_ops enetc_ops = { .dev_close = enetc_dev_close, .link_update = enetc_link_update, .dev_infos_get = enetc_dev_infos_get, + .rx_queue_setup = enetc_rx_queue_setup, + .rx_queue_release = enetc_rx_queue_release, + .tx_queue_setup = enetc_tx_queue_setup, + .tx_queue_release = enetc_tx_queue_release, }; /** @@ -59,8 +72,8 @@ enetc_dev_init(struct rte_eth_dev *eth_dev) PMD_INIT_FUNC_TRACE(); eth_dev->dev_ops = &enetc_ops; - eth_dev->rx_pkt_burst = NULL; - eth_dev->tx_pkt_burst = NULL; + eth_dev->rx_pkt_burst = &enetc_recv_pkts; + eth_dev->tx_pkt_burst = &enetc_xmit_pkts; /* Retrieving and storing the HW base address of device */ hw->hw.reg = (void *)pci_dev->mem_resource[0].addr; @@ -212,11 +225,320 @@ enetc_dev_infos_get(struct rte_eth_dev *dev __rte_unused, struct rte_eth_dev_info *dev_info) { PMD_INIT_FUNC_TRACE(); + dev_info->rx_desc_lim = (struct rte_eth_desc_lim) { + .nb_max = MAX_BD_COUNT, + .nb_min = MIN_BD_COUNT, + .nb_align = BD_ALIGN, + }; + dev_info->tx_desc_lim = (struct rte_eth_desc_lim) { + .nb_max = MAX_BD_COUNT, + .nb_min = MIN_BD_COUNT, + .nb_align = BD_ALIGN, + }; dev_info->max_rx_queues = MAX_RX_RINGS; dev_info->max_tx_queues = MAX_TX_RINGS; dev_info->max_rx_pktlen = 1500; } +static int +enetc_alloc_txbdr(struct enetc_bdr *txr, uint16_t nb_desc) +{ + int size; + + size = nb_desc * sizeof(struct enetc_swbd); + txr->q_swbd = rte_malloc(NULL, size, RTE_CACHE_LINE_SIZE); + if (txr->q_swbd == NULL) + return -ENOMEM; + + size = nb_desc * sizeof(struct enetc_tx_bd); + txr->bd_base = rte_malloc(NULL, size, RTE_CACHE_LINE_SIZE); + if (txr->bd_base == NULL) { + rte_free(txr->q_swbd); + txr->q_swbd = NULL; + return -ENOMEM; + } + + txr->bd_count = nb_desc; + txr->next_to_clean = 0; + txr->next_to_use = 0; + + return 0; +} + +static void +enetc_free_bdr(struct enetc_bdr *rxr) +{ + rte_free(rxr->q_swbd); + rte_free(rxr->bd_base); + rxr->q_swbd = NULL; + rxr->bd_base = NULL; +} + +static void +enetc_setup_txbdr(struct enetc_hw *hw, struct enetc_bdr *tx_ring) +{ + int idx = tx_ring->index; + uintptr_t base_addr; + uint32_t tbmr; + + base_addr = (uintptr_t)tx_ring->bd_base; + enetc_txbdr_wr(hw, idx, ENETC_TBBAR0, + lower_32_bits((uint64_t)base_addr)); + enetc_txbdr_wr(hw, idx, ENETC_TBBAR1, + upper_32_bits((uint64_t)base_addr)); + enetc_txbdr_wr(hw, idx, ENETC_TBLENR, + ENETC_RTBLENR_LEN(tx_ring->bd_count)); + + tbmr = ENETC_TBMR_EN; + /* enable ring */ + enetc_txbdr_wr(hw, idx, ENETC_TBMR, tbmr); + enetc_txbdr_wr(hw, idx, ENETC_TBCIR, 0); + enetc_txbdr_wr(hw, idx, ENETC_TBCISR, 0); + tx_ring->tcir = (void *)((size_t)hw->reg + + ENETC_BDR(TX, idx, ENETC_TBCIR)); + tx_ring->tcisr = (void *)((size_t)hw->reg + + ENETC_BDR(TX, idx, ENETC_TBCISR)); +} + +static int +enetc_alloc_tx_resources(struct rte_eth_dev *dev, + uint16_t queue_idx, + uint16_t nb_desc) +{ + int err; + struct enetc_bdr *tx_ring; + struct rte_eth_dev_data *data = dev->data; + struct enetc_eth_adapter *priv = + ENETC_DEV_PRIVATE(data->dev_private); + + tx_ring = rte_zmalloc(NULL, sizeof(struct enetc_bdr), 0); + if (tx_ring == NULL) { + ENETC_PMD_ERR("Failed to allocate TX ring memory"); + err = -ENOMEM; + return -1; + } + + err = enetc_alloc_txbdr(tx_ring, nb_desc); + if (err) + goto fail; + + tx_ring->index = queue_idx; + tx_ring->ndev = dev; + enetc_setup_txbdr(&priv->hw.hw, tx_ring); + data->tx_queues[queue_idx] = tx_ring; + + return 0; +fail: + rte_free(tx_ring); + + return err; +} + +static int +enetc_tx_queue_setup(struct rte_eth_dev *dev, + uint16_t queue_idx, + uint16_t nb_desc, + unsigned int socket_id __rte_unused, + const struct rte_eth_txconf *tx_conf __rte_unused) +{ + int err = 0; + + PMD_INIT_FUNC_TRACE(); + if (nb_desc > MAX_BD_COUNT) + return -1; + + err = enetc_alloc_tx_resources(dev, queue_idx, nb_desc); + + return err; +} + +static void +enetc_tx_queue_release(void *txq) +{ + if (txq == NULL) + return; + + struct enetc_bdr *tx_ring = (struct enetc_bdr *)txq; + struct enetc_eth_hw *eth_hw = + ENETC_DEV_PRIVATE_TO_HW(tx_ring->ndev->data->dev_private); + struct enetc_hw *hw; + struct enetc_swbd *tx_swbd; + int i; + uint32_t val; + + /* Disable the ring */ + hw = ð_hw->hw; + val = enetc_txbdr_rd(hw, tx_ring->index, ENETC_TBMR); + val &= (~ENETC_TBMR_EN); + enetc_txbdr_wr(hw, tx_ring->index, ENETC_TBMR, val); + + /* clean the ring*/ + i = tx_ring->next_to_clean; + tx_swbd = &tx_ring->q_swbd[i]; + while (tx_swbd->buffer_addr != NULL) { + rte_pktmbuf_free(tx_swbd->buffer_addr); + tx_swbd->buffer_addr = NULL; + tx_swbd++; + i++; + if (unlikely(i == tx_ring->bd_count)) { + i = 0; + tx_swbd = &tx_ring->q_swbd[i]; + } + } + + enetc_free_bdr(tx_ring); + rte_free(tx_ring); +} + +static int +enetc_alloc_rxbdr(struct enetc_bdr *rxr, + uint16_t nb_rx_desc) +{ + int size; + + size = nb_rx_desc * sizeof(struct enetc_swbd); + rxr->q_swbd = rte_malloc(NULL, size, RTE_CACHE_LINE_SIZE); + if (rxr->q_swbd == NULL) + return -ENOMEM; + + size = nb_rx_desc * sizeof(union enetc_rx_bd); + rxr->bd_base = rte_malloc(NULL, size, RTE_CACHE_LINE_SIZE); + if (rxr->bd_base == NULL) { + rte_free(rxr->q_swbd); + rxr->q_swbd = NULL; + return -ENOMEM; + } + + rxr->bd_count = nb_rx_desc; + rxr->next_to_clean = 0; + rxr->next_to_use = 0; + rxr->next_to_alloc = 0; + + return 0; +} + +static void +enetc_setup_rxbdr(struct enetc_hw *hw, struct enetc_bdr *rx_ring, + struct rte_mempool *mb_pool) +{ + int idx = rx_ring->index; + uintptr_t base_addr; + uint16_t buf_size; + + base_addr = (uintptr_t)rx_ring->bd_base; + enetc_rxbdr_wr(hw, idx, ENETC_RBBAR0, + lower_32_bits((uint64_t)base_addr)); + enetc_rxbdr_wr(hw, idx, ENETC_RBBAR1, + upper_32_bits((uint64_t)base_addr)); + enetc_rxbdr_wr(hw, idx, ENETC_RBLENR, + ENETC_RTBLENR_LEN(rx_ring->bd_count)); + + rx_ring->mb_pool = mb_pool; + /* enable ring */ + enetc_rxbdr_wr(hw, idx, ENETC_RBMR, ENETC_RBMR_EN); + enetc_rxbdr_wr(hw, idx, ENETC_RBPIR, 0); + rx_ring->rcir = (void *)((size_t)hw->reg + + ENETC_BDR(RX, idx, ENETC_RBCIR)); + enetc_refill_rx_ring(rx_ring, (enetc_bd_unused(rx_ring))); + buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rx_ring->mb_pool) - + RTE_PKTMBUF_HEADROOM); + enetc_rxbdr_wr(hw, idx, ENETC_RBBSR, buf_size); +} + +static int +enetc_alloc_rx_resources(struct rte_eth_dev *dev, + uint16_t rx_queue_id, + uint16_t nb_rx_desc, + struct rte_mempool *mb_pool) +{ + int err; + struct enetc_bdr *rx_ring; + struct rte_eth_dev_data *data = dev->data; + struct enetc_eth_adapter *adapter = + ENETC_DEV_PRIVATE(data->dev_private); + + rx_ring = rte_zmalloc(NULL, sizeof(struct enetc_bdr), 0); + if (rx_ring == NULL) { + ENETC_PMD_ERR("Failed to allocate RX ring memory"); + err = -ENOMEM; + return err; + } + + err = enetc_alloc_rxbdr(rx_ring, nb_rx_desc); + if (err) + goto fail; + + rx_ring->index = rx_queue_id; + rx_ring->ndev = dev; + enetc_setup_rxbdr(&adapter->hw.hw, rx_ring, mb_pool); + data->rx_queues[rx_queue_id] = rx_ring; + + return 0; +fail: + rte_free(rx_ring); + + return err; +} + +static int +enetc_rx_queue_setup(struct rte_eth_dev *dev, + uint16_t rx_queue_id, + uint16_t nb_rx_desc, + unsigned int socket_id __rte_unused, + const struct rte_eth_rxconf *rx_conf __rte_unused, + struct rte_mempool *mb_pool) +{ + int err = 0; + + PMD_INIT_FUNC_TRACE(); + if (nb_rx_desc > MAX_BD_COUNT) + return -1; + + err = enetc_alloc_rx_resources(dev, rx_queue_id, + nb_rx_desc, + mb_pool); + + return err; +} + +static void +enetc_rx_queue_release(void *rxq) +{ + if (rxq == NULL) + return; + + struct enetc_bdr *rx_ring = (struct enetc_bdr *)rxq; + struct enetc_eth_hw *eth_hw = + ENETC_DEV_PRIVATE_TO_HW(rx_ring->ndev->data->dev_private); + struct enetc_swbd *q_swbd; + struct enetc_hw *hw; + uint32_t val; + int i; + + /* Disable the ring */ + hw = ð_hw->hw; + val = enetc_rxbdr_rd(hw, rx_ring->index, ENETC_RBMR); + val &= (~ENETC_RBMR_EN); + enetc_rxbdr_wr(hw, rx_ring->index, ENETC_RBMR, val); + + /* Clean the ring */ + i = rx_ring->next_to_clean; + q_swbd = &rx_ring->q_swbd[i]; + while (i != rx_ring->next_to_use) { + rte_pktmbuf_free(q_swbd->buffer_addr); + q_swbd->buffer_addr = NULL; + q_swbd++; + i++; + if (unlikely(i == rx_ring->bd_count)) { + i = 0; + q_swbd = &rx_ring->q_swbd[i]; + } + } + + enetc_free_bdr(rx_ring); + rte_free(rx_ring); +} + static int enetc_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, struct rte_pci_device *pci_dev) diff --git a/drivers/net/enetc/enetc_rxtx.c b/drivers/net/enetc/enetc_rxtx.c new file mode 100644 index 000000000..631e2430d --- /dev/null +++ b/drivers/net/enetc/enetc_rxtx.c @@ -0,0 +1,239 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright 2018 NXP + */ + +#include +#include +#include + +#include "rte_ethdev.h" +#include "rte_malloc.h" +#include "rte_memzone.h" + +#include "base/enetc_hw.h" +#include "enetc.h" +#include "enetc_logs.h" + +#define ENETC_RXBD_BUNDLE 8 /* Number of BDs to update at once */ + +static int +enetc_clean_tx_ring(struct enetc_bdr *tx_ring) +{ + int tx_frm_cnt = 0; + struct enetc_swbd *tx_swbd; + int i; + + i = tx_ring->next_to_clean; + tx_swbd = &tx_ring->q_swbd[i]; + while ((int)(enetc_rd_reg(tx_ring->tcisr) & + ENETC_TBCISR_IDX_MASK) != i) { + rte_pktmbuf_free(tx_swbd->buffer_addr); + tx_swbd->buffer_addr = NULL; + tx_swbd++; + i++; + if (unlikely(i == tx_ring->bd_count)) { + i = 0; + tx_swbd = &tx_ring->q_swbd[0]; + } + + tx_frm_cnt++; + } + + tx_ring->next_to_clean = i; + return tx_frm_cnt++; +} + +uint16_t +enetc_xmit_pkts(void *tx_queue, + struct rte_mbuf **tx_pkts, + uint16_t nb_pkts) +{ + struct enetc_swbd *tx_swbd; + int i, start; + struct enetc_tx_bd *txbd; + struct enetc_bdr *tx_ring = (struct enetc_bdr *)tx_queue; + + i = tx_ring->next_to_use; + start = 0; + while (nb_pkts--) { + enetc_clean_tx_ring(tx_ring); + tx_ring->q_swbd[i].buffer_addr = tx_pkts[start]; + txbd = ENETC_TXBD(*tx_ring, i); + tx_swbd = &tx_ring->q_swbd[i]; + txbd->frm_len = tx_pkts[start]->pkt_len; + txbd->buf_len = txbd->frm_len; + txbd->flags = rte_cpu_to_le_16(ENETC_TXBD_FLAGS_F); + txbd->addr = (uint64_t)(uintptr_t) + rte_cpu_to_le_64((size_t)tx_swbd->buffer_addr->buf_addr + + tx_swbd->buffer_addr->data_off); + i++; + start++; + if (unlikely(i == tx_ring->bd_count)) + i = 0; + } + + tx_ring->next_to_use = i; + enetc_wr_reg(tx_ring->tcir, i); + return start; +} + +int +enetc_refill_rx_ring(struct enetc_bdr *rx_ring, const int buff_cnt) +{ + struct enetc_swbd *rx_swbd; + union enetc_rx_bd *rxbd; + int i, j; + + i = rx_ring->next_to_use; + rx_swbd = &rx_ring->q_swbd[i]; + rxbd = ENETC_RXBD(*rx_ring, i); + for (j = 0; j < buff_cnt; j++) { + rx_swbd->buffer_addr = + rte_cpu_to_le_64(rte_mbuf_raw_alloc(rx_ring->mb_pool)); + rxbd->w.addr = (uint64_t)(uintptr_t) + rx_swbd->buffer_addr->buf_addr + + rx_swbd->buffer_addr->data_off; + /* clear 'R" as well */ + rxbd->r.lstatus = 0; + rx_swbd++; + rxbd++; + i++; + if (unlikely(i == rx_ring->bd_count)) { + i = 0; + rxbd = ENETC_RXBD(*rx_ring, 0); + rx_swbd = &rx_ring->q_swbd[i]; + } + } + + if (likely(j)) { + rx_ring->next_to_alloc = i; + rx_ring->next_to_use = i; + enetc_wr_reg(rx_ring->rcir, i); + } + + return j; +} + + +static inline void __attribute__((hot)) +enetc_dev_rx_parse(struct rte_mbuf *m, uint16_t parse_results) +{ + ENETC_PMD_DP_DEBUG("parse summary = 0x%x ", parse_results); + + m->packet_type = RTE_PTYPE_UNKNOWN; + switch (parse_results) { + case ENETC_PKT_TYPE_ETHER: + m->packet_type = RTE_PTYPE_L2_ETHER; + break; + case ENETC_PKT_TYPE_IPV4: + m->packet_type = RTE_PTYPE_L2_ETHER | + RTE_PTYPE_L3_IPV4; + break; + case ENETC_PKT_TYPE_IPV6: + m->packet_type = RTE_PTYPE_L2_ETHER | + RTE_PTYPE_L3_IPV6; + break; + case ENETC_PKT_TYPE_IPV4_TCP: + m->packet_type = RTE_PTYPE_L2_ETHER | + RTE_PTYPE_L3_IPV4 | + RTE_PTYPE_L4_TCP; + break; + case ENETC_PKT_TYPE_IPV6_TCP: + m->packet_type = RTE_PTYPE_L2_ETHER | + RTE_PTYPE_L3_IPV6 | + RTE_PTYPE_L4_TCP; + break; + case ENETC_PKT_TYPE_IPV4_UDP: + m->packet_type = RTE_PTYPE_L2_ETHER | + RTE_PTYPE_L3_IPV4 | + RTE_PTYPE_L4_UDP; + break; + case ENETC_PKT_TYPE_IPV6_UDP: + m->packet_type = RTE_PTYPE_L2_ETHER | + RTE_PTYPE_L3_IPV6 | + RTE_PTYPE_L4_UDP; + break; + case ENETC_PKT_TYPE_IPV4_SCTP: + m->packet_type = RTE_PTYPE_L2_ETHER | + RTE_PTYPE_L3_IPV4 | + RTE_PTYPE_L4_SCTP; + break; + case ENETC_PKT_TYPE_IPV6_SCTP: + m->packet_type = RTE_PTYPE_L2_ETHER | + RTE_PTYPE_L3_IPV6 | + RTE_PTYPE_L4_SCTP; + break; + case ENETC_PKT_TYPE_IPV4_ICMP: + m->packet_type = RTE_PTYPE_L2_ETHER | + RTE_PTYPE_L3_IPV4 | + RTE_PTYPE_L4_ICMP; + break; + case ENETC_PKT_TYPE_IPV6_ICMP: + m->packet_type = RTE_PTYPE_L2_ETHER | + RTE_PTYPE_L3_IPV6 | + RTE_PTYPE_L4_ICMP; + break; + /* More switch cases can be added */ + default: + m->packet_type = RTE_PTYPE_UNKNOWN; + } +} + +static int +enetc_clean_rx_ring(struct enetc_bdr *rx_ring, + struct rte_mbuf **rx_pkts, + int work_limit) +{ + int rx_frm_cnt = 0; + int cleaned_cnt, i; + struct enetc_swbd *rx_swbd; + + cleaned_cnt = enetc_bd_unused(rx_ring); + /* next descriptor to process */ + i = rx_ring->next_to_clean; + rx_swbd = &rx_ring->q_swbd[i]; + while (likely(rx_frm_cnt < work_limit)) { + union enetc_rx_bd *rxbd; + uint32_t bd_status; + + if (cleaned_cnt >= ENETC_RXBD_BUNDLE) { + int count = enetc_refill_rx_ring(rx_ring, cleaned_cnt); + + cleaned_cnt -= count; + } + + rxbd = ENETC_RXBD(*rx_ring, i); + bd_status = rte_le_to_cpu_32(rxbd->r.lstatus); + if (!bd_status) + break; + + rx_swbd->buffer_addr->pkt_len = rxbd->r.buf_len; + rx_swbd->buffer_addr->data_len = rxbd->r.buf_len; + rx_swbd->buffer_addr->hash.rss = rxbd->r.rss_hash; + rx_swbd->buffer_addr->ol_flags = 0; + enetc_dev_rx_parse(rx_swbd->buffer_addr, + rxbd->r.parse_summary); + rx_pkts[rx_frm_cnt] = rx_swbd->buffer_addr; + cleaned_cnt++; + rx_swbd++; + i++; + if (unlikely(i == rx_ring->bd_count)) { + i = 0; + rx_swbd = &rx_ring->q_swbd[i]; + } + + rx_ring->next_to_clean = i; + rx_frm_cnt++; + } + + return rx_frm_cnt; +} + +uint16_t +enetc_recv_pkts(void *rxq, struct rte_mbuf **rx_pkts, + uint16_t nb_pkts) +{ + struct enetc_bdr *rx_ring = (struct enetc_bdr *)rxq; + + return enetc_clean_rx_ring(rx_ring, rx_pkts, nb_pkts); +} diff --git a/drivers/net/enetc/meson.build b/drivers/net/enetc/meson.build index 506b174ed..733156bbf 100644 --- a/drivers/net/enetc/meson.build +++ b/drivers/net/enetc/meson.build @@ -5,6 +5,7 @@ if host_machine.system() != 'linux' build = false endif -sources = files('enetc_ethdev.c') +sources = files('enetc_ethdev.c', + 'enetc_rxtx.c') includes += include_directories('base') From patchwork Fri Sep 28 05:16:46 2018 Content-Type: text/plain; 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static void enetc_tx_queue_release(void *txq); +static const uint32_t *enetc_supported_ptypes_get(struct rte_eth_dev *dev); /* * The set of PCI devices this driver supports @@ -50,6 +51,7 @@ static const struct eth_dev_ops enetc_ops = { .rx_queue_release = enetc_rx_queue_release, .tx_queue_setup = enetc_tx_queue_setup, .tx_queue_release = enetc_tx_queue_release, + .dev_supported_ptypes_get = enetc_supported_ptypes_get, }; /** @@ -165,6 +167,23 @@ enetc_dev_close(struct rte_eth_dev *dev __rte_unused) PMD_INIT_FUNC_TRACE(); } +static const uint32_t * +enetc_supported_ptypes_get(struct rte_eth_dev *dev __rte_unused) +{ + static const uint32_t ptypes[] = { + RTE_PTYPE_L2_ETHER, + RTE_PTYPE_L3_IPV4, + RTE_PTYPE_L3_IPV6, + RTE_PTYPE_L4_TCP, + RTE_PTYPE_L4_UDP, + RTE_PTYPE_L4_SCTP, + RTE_PTYPE_L4_ICMP, + RTE_PTYPE_UNKNOWN + }; + + return ptypes; +} + /* return 0 means link status changed, -1 means not changed */ static int enetc_link_update(struct rte_eth_dev *dev, int wait_to_complete __rte_unused) From patchwork Fri Sep 28 05:16:47 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Gagandeep Singh X-Patchwork-Id: 45562 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 5A83A1B186; Fri, 28 Sep 2018 07:17:56 +0200 (CEST) Received: from EUR02-AM5-obe.outbound.protection.outlook.com (mail-eopbgr00053.outbound.protection.outlook.com [40.107.0.53]) by dpdk.org (Postfix) with ESMTP id 6F6491B135 for ; Fri, 28 Sep 2018 07:17:47 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=x7utFb7l76VbXN+kc1+KYEAHAQ6lfPNUqxTiQRlfPDc=; b=U+q+8D/IQb7rm2yjuQcDukc6aRYegAYC9uS1v1UdPxVCIHMakbUieEln1YTTUR9ykg+M1dXWcxiz9HdNNTlh7bahmvfNrPI9wwe4SXwQ8vRRBSyuCeFxbXXz2bfk3xsPfBw+WWLTHMQymfVPMmqrFPF2XtqZPVEqfbuMA4qz2SI= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=G.Singh@nxp.com; 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This document introduces the enetc driver, supported platforms and supported features. Signed-off-by: Gagandeep Singh --- MAINTAINERS | 7 ++ doc/guides/nics/enetc.rst | 110 +++++++++++++++++++++++++ doc/guides/nics/features/enetc.ini | 11 +++ doc/guides/nics/index.rst | 1 + doc/guides/rel_notes/release_18_11.rst | 6 ++ 5 files changed, 135 insertions(+) create mode 100644 doc/guides/nics/enetc.rst create mode 100644 doc/guides/nics/features/enetc.ini diff --git a/MAINTAINERS b/MAINTAINERS index 9fd258fad..b67f2afa4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -643,6 +643,13 @@ F: drivers/net/dpaa2/ F: doc/guides/nics/dpaa2.rst F: doc/guides/nics/features/dpaa2.ini +NXP enetc +M: Gagandeep Singh +M: Pankaj Chauhan +F: drivers/net/enetc/ +F: doc/guides/nics/enetc.rst +F: doc/guides/nics/features/enetc.ini + QLogic bnx2x M: Harish Patil M: Rasesh Mody diff --git a/doc/guides/nics/enetc.rst b/doc/guides/nics/enetc.rst new file mode 100644 index 000000000..8038bf205 --- /dev/null +++ b/doc/guides/nics/enetc.rst @@ -0,0 +1,110 @@ +.. SPDX-License-Identifier: BSD-3-Clause + Copyright 2018 NXP + +ENETC Poll Mode Driver +====================== + +The ENETC NIC PMD (**librte_pmd_enetc**) provides poll mode driver +support for the inbuilt NIC found in the **NXP LS1028** SoC. + +More information can be found at `NXP Official Website +`_. + +ENETC +----- + +This section provides an overview of the NXP ENETC +and how it is integrated into the DPDK. + +Contents summary + +- ENETC overview +- ENETC features +- PCI bus driver +- NIC driver +- Supported ENETC SoCs +- Prerequisites +- Driver compilation and testing + +ENETC Overview +~~~~~~~~~~~~~~ + +ENETC is a PCI Integrated End Point(IEP). IEP implements +peripheral devices in an SoC such that software sees them as PCIe device. +ENETC is an evolution of BDR(Buffer Descriptor Ring) based networking +IPs. + +This infrastructure simplifies adding support for IEP and facilitates in following: + +- Device discovery and location +- Resource requirement discovery and allocation (e.g. interrupt assignment, + device register address) +- Event reporting + +ENETC Features +~~~~~~~~~~~~~~ + +- Link Status +- Packet type information + +NIC Driver (PMD) +~~~~~~~~~~~~~~~~ + +ENETC PMD is traditional DPDK PMD which provides necessary interface between +RTE framework and ENETC internal drivers. + +- Driver registers the device vendor table in PCI subsystem. +- RTE framework scans the PCI bus for connected devices. +- This scanning will invoke the probe function of ENETC driver. +- The probe function will set the basic device registers and also setups BD rings. +- On packet Rx the respective BD Ring status bit is set which is then used for + packet processing. +- Then Tx is done first followed by Rx. + +Supported ENETC SoCs +~~~~~~~~~~~~~~~~~~~~ + +- LS1028 + +Prerequisites +~~~~~~~~~~~~~ + +There are three main pre-requisities for executing ENETC PMD on a ENETC +compatible board: + +1. **ARM 64 Tool Chain** + + For example, the `*aarch64* Linaro Toolchain `_. + +2. **Linux Kernel** + + It can be obtained from `NXP's Github hosting `_. + +3. **Rootfile system** + + Any *aarch64* supporting filesystem can be used. For example, + Ubuntu 16.04 LTS (Xenial) or 18.04 (Bionic) userland which can be obtained + from `here `_. + +The following dependencies are not part of DPDK and must be installed +separately: + +- **NXP Linux LSDK** + + NXP Layerscape software development kit (LSDK) includes support for family + of QorIQ® ARM-Architecture-based system on chip (SoC) processors + and corresponding boards. + + It includes the Linux board support packages (BSPs) for NXP SoCs, + a fully operational tool chain, kernel and board specific modules. + + LSDK and related information can be obtained from: `LSDK `_ + +Driver compilation and testing +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Follow instructions available in the document +:ref:`compiling and testing a PMD for a NIC ` +to launch **testpmd** + +To compile in performance mode, please set ``CONFIG_RTE_CACHE_LINE_SIZE=64`` diff --git a/doc/guides/nics/features/enetc.ini b/doc/guides/nics/features/enetc.ini new file mode 100644 index 000000000..69476a2a1 --- /dev/null +++ b/doc/guides/nics/features/enetc.ini @@ -0,0 +1,11 @@ +; +; Supported features of the 'enetc' network poll mode driver. +; +; Refer to default.ini for the full list of available PMD features. +; +[Features] +Packet type parsing = Y +Link status = Y +Linux VFIO = Y +ARMv8 = Y +Usage doc = Y diff --git a/doc/guides/nics/index.rst b/doc/guides/nics/index.rst index 59f6063dc..0323035d3 100644 --- a/doc/guides/nics/index.rst +++ b/doc/guides/nics/index.rst @@ -21,6 +21,7 @@ Network Interface Controller Drivers dpaa2 e1000em ena + enetc enic fm10k i40e diff --git a/doc/guides/rel_notes/release_18_11.rst b/doc/guides/rel_notes/release_18_11.rst index 3ae6b3f58..f4a2535f4 100644 --- a/doc/guides/rel_notes/release_18_11.rst +++ b/doc/guides/rel_notes/release_18_11.rst @@ -50,6 +50,11 @@ New Features * Other libs * Apps, Examples, Tools (if significative) + * **Added NXP ENETC PMD.** + + Added the new enetc driver for NXP enetc platform. See the + "ENETC Poll Mode Driver" document for more details on this new driver. + This section is a comment. Do not overwrite or remove it. Also, make sure to start the actual text at the margin. ========================================================= @@ -156,6 +161,7 @@ The libraries prepended with a plus sign were incremented in this version. librte_pmd_ixgbe.so.2 librte_pmd_dpaa2_cmdif.so.1 librte_pmd_dpaa2_qdma.so.1 + + librte_pmd_enetc.so.1 librte_pmd_ring.so.2 librte_pmd_softnic.so.1 librte_pmd_vhost.so.2