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GET /api/patches/139426/?format=api
{ "id": 139426, "url": "http://patches.dpdk.org/api/patches/139426/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20240416153054.3216706-2-michaelba@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240416153054.3216706-2-michaelba@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240416153054.3216706-2-michaelba@nvidia.com", "date": "2024-04-16T15:30:51", "name": "[1/4] net/mlx5: fix secondary process port close", "commit_ref": null, "pull_url": null, "state": "awaiting-upstream", "archived": false, "hash": "b2f1e4fac4a1d78b3932f4a6b0e02f20302008fe", "submitter": { "id": 1949, "url": "http://patches.dpdk.org/api/people/1949/?format=api", "name": "Michael Baum", "email": "michaelba@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20240416153054.3216706-2-michaelba@nvidia.com/mbox/", "series": [ { "id": 31758, "url": "http://patches.dpdk.org/api/series/31758/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=31758", "date": "2024-04-16T15:30:53", "name": "net/mlx5: some unrelated fixes and improvements", "version": 1, "mbox": "http://patches.dpdk.org/series/31758/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/139426/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/139426/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 4E49E43E83;\n\tTue, 16 Apr 2024 17:31:57 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 3DB4A40685;\n\tTue, 16 Apr 2024 17:31:50 +0200 (CEST)", "from NAM11-CO1-obe.outbound.protection.outlook.com\n (mail-co1nam11on2049.outbound.protection.outlook.com [40.107.220.49])\n by mails.dpdk.org (Postfix) with ESMTP id A5D1D40268;\n Tue, 16 Apr 2024 17:31:48 +0200 (CEST)", "from SA1P222CA0135.NAMP222.PROD.OUTLOOK.COM (2603:10b6:806:3c2::13)\n by IA1PR12MB6329.namprd12.prod.outlook.com (2603:10b6:208:3e5::19)\n with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7452.50; 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helo=mail.nvidia.com; pr=C", "From": "Michael Baum <michaelba@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "Matan Azrad <matan@nvidia.com>, Dariusz Sosnowski <dsosnowski@nvidia.com>,\n Raslan Darawsheh <rasland@nvidia.com>, Viacheslav Ovsiienko\n <viacheslavo@nvidia.com>, Ori Kam <orika@nvidia.com>, Suanming Mou\n <suanmingm@nvidia.com>, <michaelba@nvidia.com>, <stable@dpdk.org>", "Subject": "[PATCH 1/4] net/mlx5: fix secondary process port close", "Date": "Tue, 16 Apr 2024 18:30:51 +0300", "Message-ID": "<20240416153054.3216706-2-michaelba@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20240416153054.3216706-1-michaelba@nvidia.com>", "References": "<20240416153054.3216706-1-michaelba@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-NV-OnPremToCloud": "ExternallySecured", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "SA2PEPF00001508:EE_|IA1PR12MB6329:EE_", "X-MS-Office365-Filtering-Correlation-Id": "e11f8a35-68b1-4b98-54e2-08dc5e2a5222", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n 33YXn1AOQ7fjNrv1rOPPKJI72FNFWlx7tMUF7NxhriMFOdTcZmbwn6jqbH7ql/1xKIR2PJV0jQFmZwlyq7ka6jmLq9xR63g2xLAfVLM8l11Jae9s/V1fio8Jg4Nc95OTk1P/AeIHffuyeBIxRtCoxOqNbo35hPg4cz/rHeHz+uCq7IxVk+aJJwclWptJvMDSLdoyxTmZFfaPbANt6+xzLWyMdcCT53W1b02tuAUr/quXmWm+XXSaoveAB/SIMNRWrmqgg4FL0fa77mI3/x68gLb6HSUna7Vfq9SMzwckHSQU8um9cp8Uf2AC1lakYHLAnEBlUU7LKTUK0JqoutkIPDErWekVLgBFVfIKPl3AVi/Krr3jG21S5dkV02Vwc/NBynM2nNoH8JWYzsldzswQPWJFYnbgXGWfsxfRG5u4ZgYhgyo68InZlrsYtOCkTmEaA/zLYMUxKnbCASxrNnOjxtwih+dtDQk/gPbEAFcnY/9GTgLMmd68uT5/aPCZ6v9YylDi/TvIG7GFOaTO/HvG9nf7GCSYq98WRYWZIzxyRL0w3dL9Q4YZFFdHWCYz8Qlr2WdycfFy73InrlFJNyOBZvmaJmmsZ2gBcIoK/tN+EBZd1IQrobzZPUreY0vVCIzyKJ9cTB6GPtdjxAxgTYmmu7v1mjIThLVD6/+QWKGtugEemEMexG/K2a7u4JF5LQDVEnfL+f0oUGYk7Y+sjb2bb53Zc63v/HNxD91z+dT+C5Z5RgrYFZaaowIkkNz4c+Co", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE;\n SFS:(13230031)(36860700004)(376005)(82310400014)(1800799015); DIR:OUT;\n SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "16 Apr 2024 15:31:43.7980 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n e11f8a35-68b1-4b98-54e2-08dc5e2a5222", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n SA2PEPF00001508.namprd04.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "IA1PR12MB6329", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "The \"mlx5_dev_close()\" function is used for both primary and secondary\nprocesses.\n\nIf secondary process use this function after primary process is closed,\nthe priv structure isn't valid anymore.\nThe function is accessing priv structure to get \"sh\" pointer in part\nshared between processes causing a crash for secondary.\n\nThis patch avoids this access and print warning in this case.\n\nFixes: f5177bdc8b76 (\"net/mlx5: add GENEVE TLV options parser API\")\nCc: michaelba@nvidia.com\nCc: stable@dpdk.org\n\nSigned-off-by: Michael Baum <michaelba@nvidia.com>\nAcked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>\n---\n drivers/net/mlx5/mlx5.c | 15 ++++++++-------\n 1 file changed, 8 insertions(+), 7 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c\nindex d1a63822a5..585b4d5497 100644\n--- a/drivers/net/mlx5/mlx5.c\n+++ b/drivers/net/mlx5/mlx5.c\n@@ -2295,11 +2295,13 @@ int\n mlx5_dev_close(struct rte_eth_dev *dev)\n {\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n-\tstruct mlx5_dev_ctx_shared *sh = priv->sh;\n+\tstruct mlx5_dev_ctx_shared *sh;\n \tunsigned int i;\n \tint ret;\n \n \tif (rte_eal_process_type() == RTE_PROC_SECONDARY) {\n+\t\tif (!priv)\n+\t\t\tDRV_LOG(WARNING, \"primary process is already closed\");\n \t\t/* Check if process_private released. */\n \t\tif (!dev->process_private)\n \t\t\treturn 0;\n@@ -2308,6 +2310,7 @@ mlx5_dev_close(struct rte_eth_dev *dev)\n \t\trte_eth_dev_release_port(dev);\n \t\treturn 0;\n \t}\n+\tsh = priv->sh;\n \tif (!sh)\n \t\treturn 0;\n \tif (priv->shared_refcnt) {\n@@ -2326,9 +2329,7 @@ mlx5_dev_close(struct rte_eth_dev *dev)\n \t}\n #endif\n \tDRV_LOG(DEBUG, \"port %u closing device \\\"%s\\\"\",\n-\t\tdev->data->port_id,\n-\t\t((priv->sh->cdev->ctx != NULL) ?\n-\t\tmlx5_os_get_ctx_device_name(priv->sh->cdev->ctx) : \"\"));\n+\t\tdev->data->port_id, sh->ibdev_name);\n \t/*\n \t * If default mreg copy action is removed at the stop stage,\n \t * the search will return none and nothing will be done anymore.\n@@ -2402,7 +2403,7 @@ mlx5_dev_close(struct rte_eth_dev *dev)\n \t\tmlx5_free(priv->rss_conf.rss_key);\n \tif (priv->reta_idx != NULL)\n \t\tmlx5_free(priv->reta_idx);\n-\tif (priv->sh->dev_cap.vf)\n+\tif (sh->dev_cap.vf)\n \t\tmlx5_os_mac_addr_flush(dev);\n \tif (priv->nl_socket_route >= 0)\n \t\tclose(priv->nl_socket_route);\n@@ -2445,7 +2446,7 @@ mlx5_dev_close(struct rte_eth_dev *dev)\n \tif (priv->hrxqs)\n \t\tmlx5_list_destroy(priv->hrxqs);\n \tmlx5_free(priv->ext_rxqs);\n-\tpriv->sh->port[priv->dev_port - 1].nl_ih_port_id = RTE_MAX_ETHPORTS;\n+\tsh->port[priv->dev_port - 1].nl_ih_port_id = RTE_MAX_ETHPORTS;\n \t/*\n \t * The interrupt handler port id must be reset before priv is reset\n \t * since 'mlx5_dev_interrupt_nl_cb' uses priv.\n@@ -2457,7 +2458,7 @@ mlx5_dev_close(struct rte_eth_dev *dev)\n \t * mlx5_os_mac_addr_flush() uses ibdev_path for retrieving\n \t * ifindex if Netlink fails.\n \t */\n-\tmlx5_free_shared_dev_ctx(priv->sh);\n+\tmlx5_free_shared_dev_ctx(sh);\n \tif (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {\n \t\tunsigned int c = 0;\n \t\tuint16_t port_id;\n", "prefixes": [ "1/4" ] }