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Tue, 16 Apr 2024 08:31:03 -0700 From: Michael Baum To: CC: Matan Azrad , Dariusz Sosnowski , Raslan Darawsheh , Viacheslav Ovsiienko , Ori Kam , Suanming Mou , , Subject: [PATCH 1/4] net/mlx5: fix secondary process port close Date: Tue, 16 Apr 2024 18:30:51 +0300 Message-ID: <20240416153054.3216706-2-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240416153054.3216706-1-michaelba@nvidia.com> References: <20240416153054.3216706-1-michaelba@nvidia.com> MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00001508:EE_|IA1PR12MB6329:EE_ X-MS-Office365-Filtering-Correlation-Id: e11f8a35-68b1-4b98-54e2-08dc5e2a5222 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 33YXn1AOQ7fjNrv1rOPPKJI72FNFWlx7tMUF7NxhriMFOdTcZmbwn6jqbH7ql/1xKIR2PJV0jQFmZwlyq7ka6jmLq9xR63g2xLAfVLM8l11Jae9s/V1fio8Jg4Nc95OTk1P/AeIHffuyeBIxRtCoxOqNbo35hPg4cz/rHeHz+uCq7IxVk+aJJwclWptJvMDSLdoyxTmZFfaPbANt6+xzLWyMdcCT53W1b02tuAUr/quXmWm+XXSaoveAB/SIMNRWrmqgg4FL0fa77mI3/x68gLb6HSUna7Vfq9SMzwckHSQU8um9cp8Uf2AC1lakYHLAnEBlUU7LKTUK0JqoutkIPDErWekVLgBFVfIKPl3AVi/Krr3jG21S5dkV02Vwc/NBynM2nNoH8JWYzsldzswQPWJFYnbgXGWfsxfRG5u4ZgYhgyo68InZlrsYtOCkTmEaA/zLYMUxKnbCASxrNnOjxtwih+dtDQk/gPbEAFcnY/9GTgLMmd68uT5/aPCZ6v9YylDi/TvIG7GFOaTO/HvG9nf7GCSYq98WRYWZIzxyRL0w3dL9Q4YZFFdHWCYz8Qlr2WdycfFy73InrlFJNyOBZvmaJmmsZ2gBcIoK/tN+EBZd1IQrobzZPUreY0vVCIzyKJ9cTB6GPtdjxAxgTYmmu7v1mjIThLVD6/+QWKGtugEemEMexG/K2a7u4JF5LQDVEnfL+f0oUGYk7Y+sjb2bb53Zc63v/HNxD91z+dT+C5Z5RgrYFZaaowIkkNz4c+Co X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230031)(36860700004)(376005)(82310400014)(1800799015); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Apr 2024 15:31:43.7980 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e11f8a35-68b1-4b98-54e2-08dc5e2a5222 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00001508.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6329 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The "mlx5_dev_close()" function is used for both primary and secondary processes. If secondary process use this function after primary process is closed, the priv structure isn't valid anymore. The function is accessing priv structure to get "sh" pointer in part shared between processes causing a crash for secondary. This patch avoids this access and print warning in this case. Fixes: f5177bdc8b76 ("net/mlx5: add GENEVE TLV options parser API") Cc: michaelba@nvidia.com Cc: stable@dpdk.org Signed-off-by: Michael Baum Acked-by: Viacheslav Ovsiienko --- drivers/net/mlx5/mlx5.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c index d1a63822a5..585b4d5497 100644 --- a/drivers/net/mlx5/mlx5.c +++ b/drivers/net/mlx5/mlx5.c @@ -2295,11 +2295,13 @@ int mlx5_dev_close(struct rte_eth_dev *dev) { struct mlx5_priv *priv = dev->data->dev_private; - struct mlx5_dev_ctx_shared *sh = priv->sh; + struct mlx5_dev_ctx_shared *sh; unsigned int i; int ret; if (rte_eal_process_type() == RTE_PROC_SECONDARY) { + if (!priv) + DRV_LOG(WARNING, "primary process is already closed"); /* Check if process_private released. */ if (!dev->process_private) return 0; @@ -2308,6 +2310,7 @@ mlx5_dev_close(struct rte_eth_dev *dev) rte_eth_dev_release_port(dev); return 0; } + sh = priv->sh; if (!sh) return 0; if (priv->shared_refcnt) { @@ -2326,9 +2329,7 @@ mlx5_dev_close(struct rte_eth_dev *dev) } #endif DRV_LOG(DEBUG, "port %u closing device \"%s\"", - dev->data->port_id, - ((priv->sh->cdev->ctx != NULL) ? - mlx5_os_get_ctx_device_name(priv->sh->cdev->ctx) : "")); + dev->data->port_id, sh->ibdev_name); /* * If default mreg copy action is removed at the stop stage, * the search will return none and nothing will be done anymore. @@ -2402,7 +2403,7 @@ mlx5_dev_close(struct rte_eth_dev *dev) mlx5_free(priv->rss_conf.rss_key); if (priv->reta_idx != NULL) mlx5_free(priv->reta_idx); - if (priv->sh->dev_cap.vf) + if (sh->dev_cap.vf) mlx5_os_mac_addr_flush(dev); if (priv->nl_socket_route >= 0) close(priv->nl_socket_route); @@ -2445,7 +2446,7 @@ mlx5_dev_close(struct rte_eth_dev *dev) if (priv->hrxqs) mlx5_list_destroy(priv->hrxqs); mlx5_free(priv->ext_rxqs); - priv->sh->port[priv->dev_port - 1].nl_ih_port_id = RTE_MAX_ETHPORTS; + sh->port[priv->dev_port - 1].nl_ih_port_id = RTE_MAX_ETHPORTS; /* * The interrupt handler port id must be reset before priv is reset * since 'mlx5_dev_interrupt_nl_cb' uses priv. @@ -2457,7 +2458,7 @@ mlx5_dev_close(struct rte_eth_dev *dev) * mlx5_os_mac_addr_flush() uses ibdev_path for retrieving * ifindex if Netlink fails. */ - mlx5_free_shared_dev_ctx(priv->sh); + mlx5_free_shared_dev_ctx(sh); if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) { unsigned int c = 0; uint16_t port_id; From patchwork Tue Apr 16 15:30:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Baum X-Patchwork-Id: 139428 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 58CE143E83; Tue, 16 Apr 2024 17:32:16 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C578C406BA; Tue, 16 Apr 2024 17:31:54 +0200 (CEST) Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2066.outbound.protection.outlook.com [40.107.94.66]) by mails.dpdk.org (Postfix) with ESMTP id 5034140695; Tue, 16 Apr 2024 17:31:51 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; 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Tue, 16 Apr 2024 08:31:09 -0700 Received: from rnnvmail204.nvidia.com (10.129.68.6) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Tue, 16 Apr 2024 08:31:09 -0700 Received: from nvidia.com (10.127.8.13) by mail.nvidia.com (10.129.68.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12 via Frontend Transport; Tue, 16 Apr 2024 08:31:06 -0700 From: Michael Baum To: CC: Matan Azrad , Dariusz Sosnowski , Raslan Darawsheh , Viacheslav Ovsiienko , Ori Kam , Suanming Mou , , Subject: [PATCH 2/4] net/mlx5/hws: fix GENEVE option class partial mask Date: Tue, 16 Apr 2024 18:30:52 +0300 Message-ID: <20240416153054.3216706-3-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240416153054.3216706-1-michaelba@nvidia.com> References: <20240416153054.3216706-1-michaelba@nvidia.com> MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001CD:EE_|SA1PR12MB8164:EE_ X-MS-Office365-Filtering-Correlation-Id: 507f3dbc-83ed-4455-79f5-08dc5e2a4f4a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Apr 2024 15:31:39.0436 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 507f3dbc-83ed-4455-79f5-08dc5e2a4f4a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001CD.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB8164 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org When GENEVE option parser is configured, the class field has 3 optional modes: 1. ignored - ignore this field. 2. fixed - this field is part of option identifier along with type field. In this mode, the exact value is provided in "spec" field during pattern template creation and mask must be 0xffff. 3. matchable - class field isn't part of the identifier and only mask is provided in pattern template creation. The mask can be any value like all other fields. In current implementation, when class mask isn't 0, pattern template creation is failed for mask != 0xffff regardless to class mode. This patch fixes this validation to be only when class mode is fixed. Fixes: 8f8dad4289e0 ("net/mlx5/hws: support GENEVE options matching") Cc: valex@nvidia.com Cc: stable@dpdk.org Signed-off-by: Michael Baum Reviewed-by: Alex Vesker --- drivers/net/mlx5/hws/mlx5dr_definer.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c index 35a2ed2048..f1f544deab 100644 --- a/drivers/net/mlx5/hws/mlx5dr_definer.c +++ b/drivers/net/mlx5/hws/mlx5dr_definer.c @@ -2500,11 +2500,6 @@ mlx5dr_definer_conv_item_geneve_opt(struct mlx5dr_definer_conv_data *cd, goto out_not_supp; } - if (m->option_class && m->option_class != RTE_BE16(UINT16_MAX)) { - DR_LOG(ERR, "Geneve option class has invalid mask"); - goto out_not_supp; - } - ret = mlx5_get_geneve_hl_data(cd->ctx, v->option_type, v->option_class, @@ -2517,6 +2512,11 @@ mlx5dr_definer_conv_item_geneve_opt(struct mlx5dr_definer_conv_data *cd, goto out_not_supp; } + if (ok_bit_on_class && m->option_class != RTE_BE16(UINT16_MAX)) { + DR_LOG(ERR, "Geneve option class has invalid mask"); + goto out_not_supp; + } + if (!ok_bit_on_class && m->option_class) { /* DW0 is used, we will match type, class */ if (!num_of_dws || hl_dws[0].dw_mask != UINT32_MAX) { From patchwork Tue Apr 16 15:30:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Baum X-Patchwork-Id: 139425 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A8E9843E83; Tue, 16 Apr 2024 17:31:45 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 97D03402BD; Tue, 16 Apr 2024 17:31:45 +0200 (CEST) Received: from NAM04-BN8-obe.outbound.protection.outlook.com (mail-bn8nam04on2073.outbound.protection.outlook.com [40.107.100.73]) by mails.dpdk.org (Postfix) with ESMTP id 7CEF840262 for ; Tue, 16 Apr 2024 17:31:44 +0200 (CEST) ARC-Seal: i=1; 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Tue, 16 Apr 2024 08:31:12 -0700 Received: from rnnvmail204.nvidia.com (10.129.68.6) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Tue, 16 Apr 2024 08:31:11 -0700 Received: from nvidia.com (10.127.8.13) by mail.nvidia.com (10.129.68.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12 via Frontend Transport; Tue, 16 Apr 2024 08:31:09 -0700 From: Michael Baum To: CC: Matan Azrad , Dariusz Sosnowski , Raslan Darawsheh , Viacheslav Ovsiienko , Ori Kam , Suanming Mou , Alex Vesker Subject: [PATCH 3/4] net/mlx5/hws: add fragment packet ID matching support Date: Tue, 16 Apr 2024 18:30:53 +0300 Message-ID: <20240416153054.3216706-4-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240416153054.3216706-1-michaelba@nvidia.com> References: <20240416153054.3216706-1-michaelba@nvidia.com> MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001CD:EE_|MW4PR12MB8610:EE_ X-MS-Office365-Filtering-Correlation-Id: 49c32771-b3c0-495e-b59b-08dc5e2a50eb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Signed-off-by: Michael Baum Reviewed-by: Alex Vesker Acked-by: Matan Azrad --- drivers/net/mlx5/hws/mlx5dr_definer.c | 11 ++++++++++- drivers/net/mlx5/hws/mlx5dr_definer.h | 2 ++ 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c index f1f544deab..7bb328e85e 100644 --- a/drivers/net/mlx5/hws/mlx5dr_definer.c +++ b/drivers/net/mlx5/hws/mlx5dr_definer.c @@ -171,6 +171,7 @@ struct mlx5dr_definer_conv_data { X(SET, ipv4_version, STE_IPV4, rte_ipv4_hdr) \ X(SET_BE16, ipv4_frag, v->fragment_offset, rte_ipv4_hdr) \ X(SET_BE16, ipv4_len, v->total_length, rte_ipv4_hdr) \ + X(SET_BE16, ipv4_identification, v->packet_id, rte_ipv4_hdr) \ X(SET, ip_fragmented, !!v->fragment_offset, rte_ipv4_hdr) \ X(SET_BE16, ipv6_payload_len, v->hdr.payload_len, rte_flow_item_ipv6) \ X(SET, ipv6_proto, v->hdr.proto, rte_flow_item_ipv6) \ @@ -1026,7 +1027,7 @@ mlx5dr_definer_conv_item_ipv4(struct mlx5dr_definer_conv_data *cd, if (!m) return 0; - if (m->packet_id || m->hdr_checksum || + if (m->hdr_checksum || (l && (l->next_proto_id || l->type_of_service))) { rte_errno = ENOTSUP; return rte_errno; @@ -1060,6 +1061,14 @@ mlx5dr_definer_conv_item_ipv4(struct mlx5dr_definer_conv_data *cd, DR_CALC_SET(fc, eth_l3, protocol_next_header, inner); } + if (m->packet_id) { + fc = &cd->fc[DR_CALC_FNAME(IP_ID, inner)]; + fc->item_idx = item_idx; + fc->is_range = l && l->packet_id; + fc->tag_set = &mlx5dr_definer_ipv4_identification_set; + DR_CALC_SET(fc, eth_l3, identification, inner); + } + if (m->total_length) { fc = &cd->fc[DR_CALC_FNAME(IP_LEN, inner)]; fc->item_idx = item_idx; diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.h b/drivers/net/mlx5/hws/mlx5dr_definer.h index ca530ebf30..a42ba9b81a 100644 --- a/drivers/net/mlx5/hws/mlx5dr_definer.h +++ b/drivers/net/mlx5/hws/mlx5dr_definer.h @@ -75,6 +75,8 @@ enum mlx5dr_definer_fname { MLX5DR_DEFINER_FNAME_IP_VERSION_I, MLX5DR_DEFINER_FNAME_IP_FRAG_O, MLX5DR_DEFINER_FNAME_IP_FRAG_I, + MLX5DR_DEFINER_FNAME_IP_ID_O, + MLX5DR_DEFINER_FNAME_IP_ID_I, MLX5DR_DEFINER_FNAME_IP_LEN_O, MLX5DR_DEFINER_FNAME_IP_LEN_I, MLX5DR_DEFINER_FNAME_IP_TOS_O, From patchwork Tue Apr 16 15:30:54 2024 Content-Type: text/plain; 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Tue, 16 Apr 2024 08:31:12 -0700 From: Michael Baum To: CC: Matan Azrad , Dariusz Sosnowski , Raslan Darawsheh , Viacheslav Ovsiienko , Ori Kam , Suanming Mou , Alex Vesker Subject: [PATCH 4/4] net/mlx5/hws: remove table type DONTCARE Date: Tue, 16 Apr 2024 18:30:54 +0300 Message-ID: <20240416153054.3216706-5-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240416153054.3216706-1-michaelba@nvidia.com> References: <20240416153054.3216706-1-michaelba@nvidia.com> MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00001509:EE_|PH7PR12MB5901:EE_ X-MS-Office365-Filtering-Correlation-Id: ce175727-0918-494b-9045-08dc5e2a5446 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: qR90nx3ITC2xecx7xkrpAfMDIfryzJuRmzwxZP9TqbFNCMK+D4ib1vzJdgVAoQS2dliGLWHSELpv1iONEYcjfQyZWv9sfdiIE7c7JoOFu1kVhC6Lc4aq1H2fQ0n4c5sYVbOUO7xvauwVBG+OK+pwOpY2j1ulIF4i075/aGV38SzzIxfIJJjV9LxXtTzGbXVrEfBXfv5rbkbGwzf+szF6T+PmVsF0bYSKDl+xHzPiVm78ZEjFv/5JxZC7Wr0rIiNS/6GfzJvDpVRhb9N5XA1C7Dax2ph7jhKsgqeuGapS1SbU+E1oXdFn6IITji9bACJfaex1UrsDQ0pBMIsiJRooECDe2yWew1wOJ/CHc//NstkhpFCGXoMA26Um5bZwPH+2JwHURiAM75cCqkhO56hsKKVVL6snWHQmVFpq2LyrkwPFBYPH/JCwkjyZGCbTm3MNvwj4wzlPyM4+l42JysdupXwjAamCmsf/i1vbk18i44jZViDfPjSxQ/OJbSbJ1ly7mtQCg3b/kLM+jpULrb4W3VNqZ0+qrWZ+hpq6vdbmcnrdnYqUg9Udbt0cP2qNl8b4EMxkKnDRh7ZR5rXQVUfVaqGRvfyjSZhfRzPapbzB6wRp43ErPE5YNFlacZoXqhX4YBGPFsbG54rgQCEbsuNrqWWmTwlkS45wPFycymVBN2XxUuD/vyGjM/N8VR5c/jxs/lW5FAnTQ8K8ugI5pw48aDMO4TfcQg/VVK9tPsk/tT2IEatLJZAYfwjSFDSNIePi X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230031)(36860700004)(1800799015)(82310400014)(376005); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Apr 2024 15:31:47.3909 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ce175727-0918-494b-9045-08dc5e2a5446 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00001509.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB5901 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch removes the "MLX5DR_TABLE_TYPE_DONTCARE" enum value and use the correct type instead even for places the type is "don't care". Signed-off-by: Michael Baum Reviewed-by: Alex Vesker Acked-by: Dariusz Sosnowski --- drivers/net/mlx5/hws/mlx5dr.h | 1 - drivers/net/mlx5/hws/mlx5dr_definer.c | 26 +++++++++++--------------- drivers/net/mlx5/mlx5_flow.h | 2 +- 3 files changed, 12 insertions(+), 17 deletions(-) diff --git a/drivers/net/mlx5/hws/mlx5dr.h b/drivers/net/mlx5/hws/mlx5dr.h index 80e118a980..36ecccf9ac 100644 --- a/drivers/net/mlx5/hws/mlx5dr.h +++ b/drivers/net/mlx5/hws/mlx5dr.h @@ -18,7 +18,6 @@ enum mlx5dr_table_type { MLX5DR_TABLE_TYPE_NIC_TX, MLX5DR_TABLE_TYPE_FDB, MLX5DR_TABLE_TYPE_MAX, - MLX5DR_TABLE_TYPE_DONTCARE = MLX5DR_TABLE_TYPE_MAX, }; enum mlx5dr_matcher_resource_mode { diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c index 7bb328e85e..a0f95c6923 100644 --- a/drivers/net/mlx5/hws/mlx5dr_definer.c +++ b/drivers/net/mlx5/hws/mlx5dr_definer.c @@ -152,6 +152,7 @@ struct mlx5dr_definer_conv_data { uint8_t geneve_opt_ok_idx; uint8_t geneve_opt_data_idx; enum rte_flow_item_type last_item; + enum mlx5dr_table_type table_type; }; /* Xmacro used to create generic item setter from items */ @@ -1754,7 +1755,7 @@ mlx5dr_definer_conv_item_tag(struct mlx5dr_definer_conv_data *cd, if (item->type == RTE_FLOW_ITEM_TYPE_TAG) reg = flow_hw_get_reg_id_from_ctx(cd->ctx, RTE_FLOW_ITEM_TYPE_TAG, - MLX5DR_TABLE_TYPE_DONTCARE, + cd->table_type, v->index); else reg = (int)v->index; @@ -1817,8 +1818,7 @@ mlx5dr_definer_conv_item_quota(struct mlx5dr_definer_conv_data *cd, { int mtr_reg = flow_hw_get_reg_id_from_ctx(cd->ctx, RTE_FLOW_ITEM_TYPE_METER_COLOR, - MLX5DR_TABLE_TYPE_DONTCARE, - 0); + cd->table_type, 0); struct mlx5dr_definer_fc *fc; if (mtr_reg < 0) { @@ -1837,7 +1837,6 @@ mlx5dr_definer_conv_item_quota(struct mlx5dr_definer_conv_data *cd, static int mlx5dr_definer_conv_item_metadata(struct mlx5dr_definer_conv_data *cd, - enum mlx5dr_table_type table_domain_type, struct rte_flow_item *item, int item_idx) { @@ -1850,7 +1849,7 @@ mlx5dr_definer_conv_item_metadata(struct mlx5dr_definer_conv_data *cd, return 0; reg = flow_hw_get_reg_id_from_ctx(cd->ctx, RTE_FLOW_ITEM_TYPE_META, - table_domain_type, -1); + cd->table_type, -1); if (reg <= 0) { DR_LOG(ERR, "Invalid register for item metadata"); rte_errno = EINVAL; @@ -2159,7 +2158,7 @@ mlx5dr_definer_conv_item_conntrack(struct mlx5dr_definer_conv_data *cd, reg = flow_hw_get_reg_id_from_ctx(cd->ctx, RTE_FLOW_ITEM_TYPE_CONNTRACK, - MLX5DR_TABLE_TYPE_DONTCARE, -1); + cd->table_type, -1); if (reg <= 0) { DR_LOG(ERR, "Invalid register for item conntrack"); rte_errno = EINVAL; @@ -2302,7 +2301,7 @@ mlx5dr_definer_conv_item_meter_color(struct mlx5dr_definer_conv_data *cd, reg = flow_hw_get_reg_id_from_ctx(cd->ctx, RTE_FLOW_ITEM_TYPE_METER_COLOR, - MLX5DR_TABLE_TYPE_DONTCARE, 0); + cd->table_type, 0); MLX5_ASSERT(reg > 0); fc = mlx5dr_definer_get_register_fc(cd, reg); @@ -2897,7 +2896,6 @@ mlx5dr_definer_conv_item_compare_field(const struct rte_flow_field_data *f, const struct rte_flow_field_data *other_f, struct mlx5dr_definer_conv_data *cd, int item_idx, - enum mlx5dr_table_type table_domain_type, enum mlx5dr_definer_compare_dw_selectors dw_offset) { struct mlx5dr_definer_fc *fc = NULL; @@ -2913,7 +2911,7 @@ mlx5dr_definer_conv_item_compare_field(const struct rte_flow_field_data *f, case RTE_FLOW_FIELD_META: reg = flow_hw_get_reg_id_from_ctx(cd->ctx, RTE_FLOW_ITEM_TYPE_META, - table_domain_type, -1); + cd->table_type, -1); if (reg <= 0) { DR_LOG(ERR, "Invalid register for compare metadata field"); rte_errno = EINVAL; @@ -2932,7 +2930,7 @@ mlx5dr_definer_conv_item_compare_field(const struct rte_flow_field_data *f, case RTE_FLOW_FIELD_TAG: reg = flow_hw_get_reg_id_from_ctx(cd->ctx, RTE_FLOW_ITEM_TYPE_TAG, - MLX5DR_TABLE_TYPE_DONTCARE, + cd->table_type, f->tag_index); if (reg <= 0) { DR_LOG(ERR, "Invalid register for compare tag field"); @@ -2988,7 +2986,6 @@ mlx5dr_definer_conv_item_compare_field(const struct rte_flow_field_data *f, static int mlx5dr_definer_conv_item_compare(struct mlx5dr_definer_conv_data *cd, - enum mlx5dr_table_type table_domain_type, struct rte_flow_item *item, int item_idx) { @@ -3005,13 +3002,11 @@ mlx5dr_definer_conv_item_compare(struct mlx5dr_definer_conv_data *cd, } ret = mlx5dr_definer_conv_item_compare_field(a, b, cd, item_idx, - table_domain_type, MLX5DR_DEFINER_COMPARE_ARGUMENT_0); if (ret) return ret; ret = mlx5dr_definer_conv_item_compare_field(b, NULL, cd, item_idx, - table_domain_type, MLX5DR_DEFINER_COMPARE_BASE_0); if (ret) return ret; @@ -3034,6 +3029,7 @@ mlx5dr_definer_conv_items_to_hl(struct mlx5dr_context *ctx, cd.fc = fc; cd.ctx = ctx; cd.relaxed = mt->flags & MLX5DR_MATCH_TEMPLATE_FLAG_RELAXED_MATCH; + cd.table_type = matcher->tbl->type; /* Collect all RTE fields to the field array and set header layout */ for (i = 0; items->type != RTE_FLOW_ITEM_TYPE_END; i++, items++) { @@ -3107,7 +3103,7 @@ mlx5dr_definer_conv_items_to_hl(struct mlx5dr_context *ctx, item_flags |= MLX5_FLOW_ITEM_TAG; break; case RTE_FLOW_ITEM_TYPE_META: - ret = mlx5dr_definer_conv_item_metadata(&cd, matcher->tbl->type, items, i); + ret = mlx5dr_definer_conv_item_metadata(&cd, items, i); item_flags |= MLX5_FLOW_ITEM_METADATA; break; case RTE_FLOW_ITEM_TYPE_GRE: @@ -3198,7 +3194,7 @@ mlx5dr_definer_conv_items_to_hl(struct mlx5dr_context *ctx, DR_LOG(ERR, "Compare matcher not supported for more than one item"); goto not_supp; } - ret = mlx5dr_definer_conv_item_compare(&cd, matcher->tbl->type, items, i); + ret = mlx5dr_definer_conv_item_compare(&cd, items, i); item_flags |= MLX5_FLOW_ITEM_COMPARE; matcher->flags |= MLX5DR_MATCHER_FLAGS_COMPARE; break; diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h index 34b5e0f45b..ee153cb3a4 100644 --- a/drivers/net/mlx5/mlx5_flow.h +++ b/drivers/net/mlx5/mlx5_flow.h @@ -1992,7 +1992,7 @@ flow_hw_get_reg_id(struct rte_eth_dev *dev, { #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) return flow_hw_get_reg_id_by_domain(dev, type, - MLX5DR_TABLE_TYPE_DONTCARE, id); + MLX5DR_TABLE_TYPE_MAX, id); #else RTE_SET_USED(dev); RTE_SET_USED(type);