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GET /api/patches/138280/?format=api
{ "id": 138280, "url": "http://patches.dpdk.org/api/patches/138280/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20240312180716.8515-31-shaibran@amazon.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240312180716.8515-31-shaibran@amazon.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240312180716.8515-31-shaibran@amazon.com", "date": "2024-03-12T18:07:15", "name": "[v4,30/31] net/ena: control path pure polling mode", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "ee7419cba8daf708157ec2b2066ef29eea56f6f4", "submitter": { "id": 2930, "url": "http://patches.dpdk.org/api/people/2930/?format=api", "name": "Brandes, Shai", "email": "shaibran@amazon.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20240312180716.8515-31-shaibran@amazon.com/mbox/", "series": [ { "id": 31487, "url": "http://patches.dpdk.org/api/series/31487/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=31487", "date": "2024-03-12T18:06:45", "name": "net/ena: v2.9.0 driver release", "version": 4, "mbox": "http://patches.dpdk.org/series/31487/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/138280/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/138280/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 57F3843C94;\n\tTue, 12 Mar 2024 19:10:32 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 7746C42E94;\n\tTue, 12 Mar 2024 19:08:34 +0100 (CET)", "from smtp-fw-80008.amazon.com (smtp-fw-80008.amazon.com\n [99.78.197.219]) by mails.dpdk.org (Postfix) with ESMTP id 5CD2742E9D\n for <dev@dpdk.org>; Tue, 12 Mar 2024 19:08:32 +0100 (CET)", "from pdx4-co-svc-p1-lb2-vlan3.amazon.com (HELO\n smtpout.prod.us-east-1.prod.farcaster.email.amazon.dev) ([10.25.36.214])\n by smtp-border-fw-80008.pdx80.corp.amazon.com with\n ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Mar 2024 18:08:31 +0000", "from EX19MTAEUB001.ant.amazon.com [10.0.10.100:29174]\n by smtpin.naws.eu-west-1.prod.farcaster.email.amazon.dev [10.0.41.28:2525]\n with esmtp (Farcaster)\n id dceba6e2-d83c-4760-bffe-f54f1597027f;\n Tue, 12 Mar 2024 18:08:29 +0000 (UTC)", "from EX19D007EUA001.ant.amazon.com (10.252.50.133) by\n EX19MTAEUB001.ant.amazon.com (10.252.51.28) with Microsoft SMTP Server\n (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.2.1258.28; Tue, 12 Mar 2024 18:08:29 +0000", "from EX19MTAUWA001.ant.amazon.com (10.250.64.204) by\n EX19D007EUA001.ant.amazon.com (10.252.50.133) with Microsoft SMTP Server\n (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.2.1258.28; Tue, 12 Mar 2024 18:08:28 +0000", "from HFA15-CG15235BS.amazon.com (10.85.143.174) by\n mail-relay.amazon.com (10.250.64.204) with Microsoft SMTP Server id\n 15.2.1258.28 via Frontend Transport; Tue, 12 Mar 2024 18:08:27 +0000" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=amazon.com; i=@amazon.com; q=dns/txt; s=amazon201209;\n t=1710266912; x=1741802912;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version;\n bh=ja3svov/9/rsXrw/sAw2OMYUt04O3A9qcwdHAxw/1EM=;\n b=s1onGYFjNiAY9X1HL73OB9jIPdonxBzG7wyzKqg4HuvGsEPO249D+5mP\n iuIL1+hKTMw4vWhR1LtiwNUQgvBfPB4ovPa3ee5GriKDI/vWJ8mnNari6\n Z8/mlFRB9NzrwHqO1f45Fsum647hqPheRM1aXeum3Yky8/WQicHonJ7Bf E=;", "X-IronPort-AV": "E=Sophos;i=\"6.07,119,1708387200\"; d=\"scan'208\";a=\"72647620\"", "X-Farcaster-Flow-ID": "dceba6e2-d83c-4760-bffe-f54f1597027f", "From": "<shaibran@amazon.com>", "To": "<ferruh.yigit@amd.com>", "CC": "<dev@dpdk.org>, Shai Brandes <shaibran@amazon.com>", "Subject": "[PATCH v4 30/31] net/ena: control path pure polling mode", "Date": "Tue, 12 Mar 2024 20:07:15 +0200", "Message-ID": "<20240312180716.8515-31-shaibran@amazon.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20240312180716.8515-1-shaibran@amazon.com>", "References": "<20240312180716.8515-1-shaibran@amazon.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Shai Brandes <shaibran@amazon.com>\n\nThis commit implements a new operation mode that enables purely\npolling-based functionality, eliminating the need for interrupts in\nthe control path. This mode is not activated by default and can be\ntoggled using the \"control_poll_interval\" devarg. When operating in\nthis mode, periodic alarms are used to monitor the control queues.\n\nA non-zero value for this devarg is mandatory for control path\nfunctionality when binding ports to uio_pci_generic kernel module which\nlacks interrupt support.\n\nSigned-off-by: Shai Brandes <shaibran@amazon.com>\nReviewed-by: Amit Bernstein <amitbern@amazon.com>\n---\n doc/guides/nics/ena.rst | 43 ++++++---\n doc/guides/rel_notes/release_24_03.rst | 2 +\n drivers/net/ena/ena_ethdev.c | 115 ++++++++++++++++++++-----\n drivers/net/ena/ena_ethdev.h | 5 ++\n 4 files changed, 132 insertions(+), 33 deletions(-)", "diff": "diff --git a/doc/guides/nics/ena.rst b/doc/guides/nics/ena.rst\nindex 725215b36d..f1dc6996ca 100644\n--- a/doc/guides/nics/ena.rst\n+++ b/doc/guides/nics/ena.rst\n@@ -135,6 +135,19 @@ Runtime Configuration\n huge performance degradation. In general disabling LLQ is highly not\n recommended!**\n \n+ * **control_poll_interval** (default 0)\n+\n+ Enable polling-based functionality of the admin queues, eliminating the\n+ need for interrupts in the control-path:\n+\n+ 0 - Disable (Admin queue will work in interrupt mode).\n+\n+ [1..1000] - Number of milliseconds to wait between periodic inspection of the admin queues.\n+\n+ **A non-zero value for this devarg is mandatory for control path functionality\n+ when binding ports to uio_pci_generic kernel module which lacks interrupt support.**\n+\n+\n ENA Configuration Parameters\n ^^^^^^^^^^^^^^^^^^^^^^^^^^^^\n \n@@ -173,23 +186,23 @@ Prerequisites\n #. Prepare the system as recommended by DPDK suite. This includes environment\n variables, hugepages configuration, tool-chains and configuration.\n \n-#. ENA PMD can operate with ``vfio-pci``(*) or ``igb_uio`` driver.\n+#. ENA PMD can operate with ``vfio-pci`` (*), ``igb_uio``, or ``uio_pci_generic`` driver.\n \n (*) ENAv2 hardware supports Low Latency Queue v2 (LLQv2). This feature\n reduces the latency of the packets by pushing the header directly through\n the PCI to the device, before the DMA is even triggered. For proper work\n- kernel PCI driver must support write combining (WC).\n+ kernel PCI driver must support write-combining (WC).\n In DPDK ``igb_uio`` it must be enabled by loading module with\n ``wc_activate=1`` flag (example below). However, mainline's vfio-pci\n- driver in kernel doesn't have WC support yet (planed to be added).\n+ driver in kernel doesn't have WC support yet (planned to be added).\n If vfio-pci is used user should follow `AWS ENA PMD documentation\n <https://github.com/amzn/amzn-drivers/tree/master/userspace/dpdk/README.md>`_.\n \n-#. Insert ``vfio-pci`` or ``igb_uio`` kernel module using the command\n- ``modprobe vfio-pci`` or ``modprobe uio; insmod igb_uio.ko wc_activate=1``\n- respectively.\n+#. For ``igb_uio``:\n+ Insert ``igb_uio`` kernel module using the command ``modprobe uio; insmod igb_uio.ko wc_activate=1``\n \n-#. For ``vfio-pci`` users only:\n+#. For ``vfio-pci``:\n+ Insert ``vfio-pci`` kernel module using the command ``modprobe vfio-pci``\n Please make sure that ``IOMMU`` is enabled in your system,\n or use ``vfio`` driver in ``noiommu`` mode::\n \n@@ -198,7 +211,17 @@ Prerequisites\n To use ``noiommu`` mode, the ``vfio-pci`` must be built with flag\n ``CONFIG_VFIO_NOIOMMU``.\n \n-#. Bind the intended ENA device to ``vfio-pci`` or ``igb_uio`` module.\n+#. For ``uio_pci_generic``:\n+ Insert ``uio_pci_generic`` kernel module using the command ``modprobe uio_pci_generic``.\n+ Make sure that the IOMMU is disabled or is in passthrough mode.\n+ For example: ``modprobe uio_pci_generic intel_iommu=off``.\n+\n+ Note that when launching the application, the ``control_poll_interval`` devarg must be used with a non-zero value (1000 is recommended)\n+ as ``uio_pci_generic`` lacks interrupt support. The control-path (admin queues) of the ENA require poll-mode\n+ to process command completion and asynchronous notification from the device.\n+ For example: ``dpdk-app -a \"00:06.0,control_path_poll_interval=1000\"``.\n+\n+#. Bind the intended ENA device to ``vfio-pci``, ``igb_uio``, or ``uio_pci_generic`` module.\n \n At this point the system should be ready to run DPDK applications. Once the\n application runs to completion, the ENA can be detached from attached module if\n@@ -207,7 +230,7 @@ necessary.\n **Rx interrupts support**\n \n ENA PMD supports Rx interrupts, which can be used to wake up lcores waiting for\n-input. Please note that it won't work with ``igb_uio``, so to use this feature,\n+input. Please note that it won't work with ``igb_uio`` and ``uio_pci_generic`` so to use this feature,\n the ``vfio-pci`` should be used.\n \n ENA handles admin interrupts and AENQ notifications on separate interrupt.\n@@ -218,7 +241,7 @@ will fail.\n **Note about usage on \\*.metal instances**\n \n On AWS, the metal instances are supporting IOMMU for both arm64 and x86_64\n-hosts.\n+hosts. Note that ``uio_pci_generic`` lacks IOMMU support and cannot be used for metal instances.\n \n * x86_64 (e.g. c5.metal, i3.metal):\n IOMMU should be disabled by default. In that situation, the ``igb_uio`` can\ndiff --git a/doc/guides/rel_notes/release_24_03.rst b/doc/guides/rel_notes/release_24_03.rst\nindex bee2429ba0..33d094a645 100644\n--- a/doc/guides/rel_notes/release_24_03.rst\n+++ b/doc/guides/rel_notes/release_24_03.rst\n@@ -111,6 +111,8 @@ New Features\n * Added `normal_llq_hdr` devarg that enforce normal llq header policy.\n * Added support for LLQ header size recommendation from the device.\n * Allowed large LLQ with 1024 entries when the device supports enlarged memory BAR.\n+ * Added `control_poll_interval` devarg that configure control-path to work in poll-mode.\n+ * Added support for binding ports to `uio_pci_generic` kernel module.\n \n * **Updated Atomic Rules' Arkville driver.**\n \ndiff --git a/drivers/net/ena/ena_ethdev.c b/drivers/net/ena/ena_ethdev.c\nindex c7c2eef92f..1707d5f2c2 100644\n--- a/drivers/net/ena/ena_ethdev.c\n+++ b/drivers/net/ena/ena_ethdev.c\n@@ -3,6 +3,7 @@\n * All rights reserved.\n */\n \n+#include <rte_alarm.h>\n #include <rte_string_fns.h>\n #include <rte_errno.h>\n #include <rte_version.h>\n@@ -36,6 +37,8 @@\n \n #define ENA_MIN_RING_DESC\t128\n \n+#define USEC_PER_MSEC\t\t1000UL\n+\n #define BITS_PER_BYTE 8\n \n #define BITS_PER_TYPE(type) (sizeof(type) * BITS_PER_BYTE)\n@@ -90,6 +93,14 @@ struct ena_stats {\n * huge performance degradation on 6th generation AWS instances.\n */\n #define ENA_DEVARG_ENABLE_LLQ \"enable_llq\"\n+/*\n+ * Controls the period of time (in milliseconds) between two consecutive inspections of\n+ * the control queues when the driver is in poll mode and not using interrupts.\n+ * By default, this value is zero, indicating that the driver will not be in poll mode and will\n+ * use interrupts. A non-zero value for this argument is mandatory when using uio_pci_generic\n+ * driver.\n+ */\n+#define ENA_DEVARG_CONTROL_PATH_POLL_INTERVAL \"control_path_poll_interval\"\n \n /*\n * Each rte_memzone should have unique name.\n@@ -266,7 +277,8 @@ static uint64_t ena_get_rx_queue_offloads(struct ena_adapter *adapter);\n static uint64_t ena_get_tx_queue_offloads(struct ena_adapter *adapter);\n static int ena_infos_get(struct rte_eth_dev *dev,\n \t\t\t struct rte_eth_dev_info *dev_info);\n-static void ena_interrupt_handler_rte(void *cb_arg);\n+static void ena_control_path_handler(void *cb_arg);\n+static void ena_control_path_poll_handler(void *cb_arg);\n static void ena_timer_wd_callback(struct rte_timer *timer, void *arg);\n static void ena_destroy_device(struct rte_eth_dev *eth_dev);\n static int eth_ena_dev_init(struct rte_eth_dev *eth_dev);\n@@ -878,10 +890,14 @@ static int ena_close(struct rte_eth_dev *dev)\n \t\tret = ena_stop(dev);\n \tadapter->state = ENA_ADAPTER_STATE_CLOSED;\n \n-\trte_intr_disable(intr_handle);\n-\trc = rte_intr_callback_unregister_sync(intr_handle, ena_interrupt_handler_rte, dev);\n-\tif (unlikely(rc != 0))\n-\t\tPMD_INIT_LOG(ERR, \"Failed to unregister interrupt handler\\n\");\n+\tif (!adapter->control_path_poll_interval) {\n+\t\trte_intr_disable(intr_handle);\n+\t\trc = rte_intr_callback_unregister_sync(intr_handle, ena_control_path_handler, dev);\n+\t\tif (unlikely(rc != 0))\n+\t\t\tPMD_INIT_LOG(ERR, \"Failed to unregister interrupt handler\\n\");\n+\t} else {\n+\t\trte_eal_alarm_cancel(ena_control_path_poll_handler, dev);\n+\t}\n \n \tena_rx_queue_release_all(dev);\n \tena_tx_queue_release_all(dev);\n@@ -1885,15 +1901,33 @@ static int ena_device_init(struct ena_adapter *adapter,\n \treturn rc;\n }\n \n-static void ena_interrupt_handler_rte(void *cb_arg)\n+static void ena_control_path_handler(void *cb_arg)\n {\n \tstruct rte_eth_dev *dev = cb_arg;\n \tstruct ena_adapter *adapter = dev->data->dev_private;\n \tstruct ena_com_dev *ena_dev = &adapter->ena_dev;\n \n-\tena_com_admin_q_comp_intr_handler(ena_dev);\n-\tif (likely(adapter->state != ENA_ADAPTER_STATE_CLOSED))\n+\tif (likely(adapter->state != ENA_ADAPTER_STATE_CLOSED)) {\n+\t\tena_com_admin_q_comp_intr_handler(ena_dev);\n \t\tena_com_aenq_intr_handler(ena_dev, dev);\n+\t}\n+}\n+\n+static void ena_control_path_poll_handler(void *cb_arg)\n+{\n+\tstruct rte_eth_dev *dev = cb_arg;\n+\tstruct ena_adapter *adapter = dev->data->dev_private;\n+\tint rc;\n+\n+\tif (likely(adapter->state != ENA_ADAPTER_STATE_CLOSED)) {\n+\t\tena_control_path_handler(cb_arg);\n+\t\trc = rte_eal_alarm_set(adapter->control_path_poll_interval,\n+\t\t\t\t ena_control_path_poll_handler, cb_arg);\n+\t\tif (unlikely(rc != 0)) {\n+\t\t\tPMD_DRV_LOG(ERR, \"Failed to retrigger control path alarm\\n\");\n+\t\t\tena_trigger_reset(adapter, ENA_REGS_RESET_GENERIC);\n+\t\t}\n+\t}\n }\n \n static void check_for_missing_keep_alive(struct ena_adapter *adapter)\n@@ -2363,20 +2397,29 @@ static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)\n \n \trte_spinlock_init(&adapter->admin_lock);\n \n-\trte_intr_callback_register(intr_handle,\n-\t\t\t\t ena_interrupt_handler_rte,\n-\t\t\t\t eth_dev);\n-\trte_intr_enable(intr_handle);\n-\tena_com_set_admin_polling_mode(ena_dev, false);\n+\tif (!adapter->control_path_poll_interval) {\n+\t\t/* Control path interrupt mode */\n+\t\trte_intr_callback_register(intr_handle, ena_control_path_handler, eth_dev);\n+\t\trte_intr_enable(intr_handle);\n+\t\tena_com_set_admin_polling_mode(ena_dev, false);\n+\t} else {\n+\t\t/* Control path polling mode */\n+\t\trc = rte_eal_alarm_set(adapter->control_path_poll_interval,\n+\t\t\t\t ena_control_path_poll_handler, eth_dev);\n+\t\tif (unlikely(rc != 0)) {\n+\t\t\tPMD_DRV_LOG(ERR, \"Failed to set control path alarm\\n\");\n+\t\t\tgoto err_control_path_destroy;\n+\t\t}\n+\t}\n \tena_com_admin_aenq_enable(ena_dev);\n-\n \trte_timer_init(&adapter->timer_wd);\n \n \tadapters_found++;\n \tadapter->state = ENA_ADAPTER_STATE_INIT;\n \n \treturn 0;\n-\n+err_control_path_destroy:\n+\trte_free(adapter->drv_stats);\n err_rss_destroy:\n \tena_com_rss_destroy(ena_dev);\n err_delete_debug_area:\n@@ -3657,9 +3700,9 @@ static int ena_process_uint_devarg(const char *key,\n {\n \tstruct ena_adapter *adapter = opaque;\n \tchar *str_end;\n-\tuint64_t uint_value;\n+\tuint64_t uint64_value;\n \n-\tuint_value = strtoull(value, &str_end, DECIMAL_BASE);\n+\tuint64_value = strtoull(value, &str_end, DECIMAL_BASE);\n \tif (value == str_end) {\n \t\tPMD_INIT_LOG(ERR,\n \t\t\t\"Invalid value for key '%s'. Only uint values are accepted.\\n\",\n@@ -3668,12 +3711,12 @@ static int ena_process_uint_devarg(const char *key,\n \t}\n \n \tif (strcmp(key, ENA_DEVARG_MISS_TXC_TO) == 0) {\n-\t\tif (uint_value > ENA_MAX_TX_TIMEOUT_SECONDS) {\n+\t\tif (uint64_value > ENA_MAX_TX_TIMEOUT_SECONDS) {\n \t\t\tPMD_INIT_LOG(ERR,\n \t\t\t\t\"Tx timeout too high: %\" PRIu64 \" sec. Maximum allowed: %d sec.\\n\",\n-\t\t\t\tuint_value, ENA_MAX_TX_TIMEOUT_SECONDS);\n+\t\t\t\tuint64_value, ENA_MAX_TX_TIMEOUT_SECONDS);\n \t\t\treturn -EINVAL;\n-\t\t} else if (uint_value == 0) {\n+\t\t} else if (uint64_value == 0) {\n \t\t\tPMD_INIT_LOG(INFO,\n \t\t\t\t\"Check for missing Tx completions has been disabled.\\n\");\n \t\t\tadapter->missing_tx_completion_to =\n@@ -3681,9 +3724,27 @@ static int ena_process_uint_devarg(const char *key,\n \t\t} else {\n \t\t\tPMD_INIT_LOG(INFO,\n \t\t\t\t\"Tx packet completion timeout set to %\" PRIu64 \" seconds.\\n\",\n-\t\t\t\tuint_value);\n+\t\t\t\tuint64_value);\n \t\t\tadapter->missing_tx_completion_to =\n-\t\t\t\tuint_value * rte_get_timer_hz();\n+\t\t\t\tuint64_value * rte_get_timer_hz();\n+\t\t}\n+\t} else if (strcmp(key, ENA_DEVARG_CONTROL_PATH_POLL_INTERVAL) == 0) {\n+\t\tif (uint64_value > ENA_MAX_CONTROL_PATH_POLL_INTERVAL_MSEC) {\n+\t\t\tPMD_INIT_LOG(ERR,\n+\t\t\t\t\"Control path polling interval is too long: %\" PRIu64 \" msecs. \"\n+\t\t\t\t\"Maximum allowed: %d msecs.\\n\",\n+\t\t\t\tuint64_value, ENA_MAX_CONTROL_PATH_POLL_INTERVAL_MSEC);\n+\t\t\treturn -EINVAL;\n+\t\t} else if (uint64_value == 0) {\n+\t\t\tPMD_INIT_LOG(INFO,\n+\t\t\t\t\"Control path polling interval is set to zero. Operating in \"\n+\t\t\t\t\"interrupt mode.\\n\");\n+\t\t\t\tadapter->control_path_poll_interval = 0;\n+\t\t} else {\n+\t\t\tPMD_INIT_LOG(INFO,\n+\t\t\t\t\"Control path polling interval is set to %\" PRIu64 \" msecs.\\n\",\n+\t\t\t\tuint64_value);\n+\t\t\t\tadapter->control_path_poll_interval = uint64_value * USEC_PER_MSEC;\n \t\t}\n \t}\n \n@@ -3728,6 +3789,7 @@ static int ena_parse_devargs(struct ena_adapter *adapter,\n \t\tENA_DEVARG_NORMAL_LLQ_HDR,\n \t\tENA_DEVARG_MISS_TXC_TO,\n \t\tENA_DEVARG_ENABLE_LLQ,\n+\t\tENA_DEVARG_CONTROL_PATH_POLL_INTERVAL,\n \t\tNULL,\n \t};\n \tstruct rte_kvargs *kvlist;\n@@ -3757,6 +3819,12 @@ static int ena_parse_devargs(struct ena_adapter *adapter,\n \t\tgoto exit;\n \trc = rte_kvargs_process(kvlist, ENA_DEVARG_ENABLE_LLQ,\n \t\tena_process_bool_devarg, adapter);\n+\tif (rc != 0)\n+\t\tgoto exit;\n+\trc = rte_kvargs_process(kvlist, ENA_DEVARG_CONTROL_PATH_POLL_INTERVAL,\n+\t\tena_process_uint_devarg, adapter);\n+\tif (rc != 0)\n+\t\tgoto exit;\n \n exit:\n \trte_kvargs_free(kvlist);\n@@ -3979,7 +4047,8 @@ RTE_PMD_REGISTER_PARAM_STRING(net_ena,\n \tENA_DEVARG_LARGE_LLQ_HDR \"=<0|1> \"\n \tENA_DEVARG_NORMAL_LLQ_HDR \"=<0|1> \"\n \tENA_DEVARG_ENABLE_LLQ \"=<0|1> \"\n-\tENA_DEVARG_MISS_TXC_TO \"=<uint>\");\n+\tENA_DEVARG_MISS_TXC_TO \"=<uint>\"\n+\tENA_DEVARG_CONTROL_PATH_POLL_INTERVAL \"=<0-1000>\");\n RTE_LOG_REGISTER_SUFFIX(ena_logtype_init, init, NOTICE);\n RTE_LOG_REGISTER_SUFFIX(ena_logtype_driver, driver, NOTICE);\n #ifdef RTE_ETHDEV_DEBUG_RX\ndiff --git a/drivers/net/ena/ena_ethdev.h b/drivers/net/ena/ena_ethdev.h\nindex 7358f28caf..7513a3f6d5 100644\n--- a/drivers/net/ena/ena_ethdev.h\n+++ b/drivers/net/ena/ena_ethdev.h\n@@ -44,6 +44,8 @@\n #define ENA_MONITORED_TX_QUEUES\t\t3\n #define ENA_DEFAULT_MISSING_COMP\t256U\n \n+#define ENA_MAX_CONTROL_PATH_POLL_INTERVAL_MSEC 1000\n+\n /* While processing submitted and completed descriptors (rx and tx path\n * respectively) in a loop it is desired to:\n * - perform batch submissions while populating submission queue\n@@ -348,6 +350,9 @@ struct ena_adapter {\n \n \tuint64_t memzone_cnt;\n \n+\t/* Time (in microseconds) of the control path queues monitoring interval */\n+\tuint64_t control_path_poll_interval;\n+\n \t/*\n \t * Helper variables for holding the information about the supported\n \t * metrics.\n", "prefixes": [ "v4", "30/31" ] }