From patchwork Tue Mar 12 18:06:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Brandes, Shai" X-Patchwork-Id: 138251 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A53DF43C94; Tue, 12 Mar 2024 19:07:34 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 58A2A42DD2; Tue, 12 Mar 2024 19:07:32 +0100 (CET) Received: from smtp-fw-80007.amazon.com (smtp-fw-80007.amazon.com [99.78.197.218]) by mails.dpdk.org (Postfix) with ESMTP id 73E3242DDF for ; Tue, 12 Mar 2024 19:07:30 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.com; i=@amazon.com; q=dns/txt; s=amazon201209; t=1710266851; x=1741802851; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=SOx7LsS6G0ty/ZpiCj/kAL1TgAnWPKqvmUmP5IMtYfk=; b=WjpqCpJrNp7BBFuvH87yTrpDkAnxZFtMugJvxPNMo90f1dAIA97f6bie uK6iGAErFcXhO0jY1P25GeNibnPklu7st6Pur+hiOAsSqiG9vHKY2VmOe YVt+RzqgzVi15N+Oz6Qz9MszAxixNMqjbgItDPs+n0BoGdscn2JPz8bVM c=; X-IronPort-AV: E=Sophos;i="6.07,119,1708387200"; d="scan'208";a="280481460" Received: from pdx4-co-svc-p1-lb2-vlan2.amazon.com (HELO smtpout.prod.us-east-1.prod.farcaster.email.amazon.dev) ([10.25.36.210]) by smtp-border-fw-80007.pdx80.corp.amazon.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Mar 2024 18:07:28 +0000 Received: from EX19MTAEUB001.ant.amazon.com [10.0.10.100:47873] by smtpin.naws.eu-west-1.prod.farcaster.email.amazon.dev [10.0.0.5:2525] with esmtp (Farcaster) id fadf1d8f-aa24-4ee6-90af-ec5abe23f09a; Tue, 12 Mar 2024 18:07:26 +0000 (UTC) X-Farcaster-Flow-ID: fadf1d8f-aa24-4ee6-90af-ec5abe23f09a Received: from EX19D007EUB002.ant.amazon.com (10.252.51.117) by EX19MTAEUB001.ant.amazon.com (10.252.51.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Tue, 12 Mar 2024 18:07:26 +0000 Received: from EX19MTAUWA001.ant.amazon.com (10.250.64.204) by EX19D007EUB002.ant.amazon.com (10.252.51.117) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Tue, 12 Mar 2024 18:07:25 +0000 Received: from HFA15-CG15235BS.amazon.com (10.85.143.174) by mail-relay.amazon.com (10.250.64.204) with Microsoft SMTP Server id 15.2.1258.28 via Frontend Transport; Tue, 12 Mar 2024 18:07:23 +0000 From: To: CC: , Shai Brandes Subject: [PATCH v4 01/31] net/ena: rework the metrics multi-process functions Date: Tue, 12 Mar 2024 20:06:46 +0200 Message-ID: <20240312180716.8515-2-shaibran@amazon.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240312180716.8515-1-shaibran@amazon.com> References: <20240312180716.8515-1-shaibran@amazon.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Shai Brandes 1. Changed the rte_memcpy call to use the precomputed buf_size. 2. Removed redundant address operators (ampersand symbol) when providing memcpy source address parameter. 3. Code style related change. Signed-off-by: Shai Brandes Reviewed-by: Amit Bernstein --- drivers/net/ena/ena_ethdev.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/drivers/net/ena/ena_ethdev.c b/drivers/net/ena/ena_ethdev.c index beb17c4125..6d500bfa78 100644 --- a/drivers/net/ena/ena_ethdev.c +++ b/drivers/net/ena/ena_ethdev.c @@ -531,8 +531,8 @@ __extension__ ({ __extension__ ({ ENA_TOUCH(rsp); ENA_TOUCH(ena_dev); - if (stats != (struct ena_admin_eni_stats *)&adapter->metrics_stats) - rte_memcpy(stats, &adapter->metrics_stats, sizeof(*stats)); + if (stats != (struct ena_admin_eni_stats *)adapter->metrics_stats) + rte_memcpy(stats, adapter->metrics_stats, sizeof(*stats)); }), struct ena_com_dev *ena_dev, struct ena_admin_eni_stats *stats); @@ -590,9 +590,8 @@ __extension__ ({ __extension__ ({ ENA_TOUCH(rsp); ENA_TOUCH(ena_dev); - ENA_TOUCH(buf_size); - if (buf != (char *)&adapter->metrics_stats) - rte_memcpy(buf, &adapter->metrics_stats, adapter->metrics_num * sizeof(uint64_t)); + if (buf != (char *)adapter->metrics_stats) + rte_memcpy(buf, adapter->metrics_stats, buf_size); }), struct ena_com_dev *ena_dev, char *buf, size_t buf_size); @@ -4088,7 +4087,7 @@ ena_mp_primary_handle(const struct rte_mp_msg *mp_msg, const void *peer) case ENA_MP_CUSTOMER_METRICS_GET: res = ena_com_get_customer_metrics(ena_dev, (char *)adapter->metrics_stats, - sizeof(uint64_t) * adapter->metrics_num); + adapter->metrics_num * sizeof(uint64_t)); break; case ENA_MP_SRD_STATS_GET: res = ena_com_get_ena_srd_info(ena_dev, From patchwork Tue Mar 12 18:06:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Brandes, Shai" X-Patchwork-Id: 138252 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2430743C94; Tue, 12 Mar 2024 19:07:40 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8081642DEA; Tue, 12 Mar 2024 19:07:35 +0100 (CET) Received: from smtp-fw-2101.amazon.com (smtp-fw-2101.amazon.com [72.21.196.25]) by mails.dpdk.org (Postfix) with ESMTP id BCFAB42DDF for ; Tue, 12 Mar 2024 19:07:33 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.com; i=@amazon.com; q=dns/txt; s=amazon201209; t=1710266854; x=1741802854; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=BOmRK8UcwIvmjS69kjh/4s0l51THaz0Y5/Awy+ac56U=; b=TYS0If5RHBekqwLCzSWuUAKifELKKD+xFU20bnAEiCvkCi1Y/u0IAING fiQpZ7QGXE3kTUC/h0iWWUAYefnfExF3Q527/oi8q6DQJxmmwoyY06Coa gisdAri3cXh2xfpWvqXxQ1y0kT6TJMsUYp/TJ5VoHuTIVgZK5U2A08ygy A=; X-IronPort-AV: E=Sophos;i="6.07,119,1708387200"; d="scan'208";a="387284501" Received: from iad12-co-svc-p1-lb1-vlan3.amazon.com (HELO smtpout.prod.us-west-2.prod.farcaster.email.amazon.dev) ([10.43.8.6]) by smtp-border-fw-2101.iad2.amazon.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Mar 2024 18:07:31 +0000 Received: from EX19MTAEUB002.ant.amazon.com [10.0.43.254:55204] by smtpin.naws.eu-west-1.prod.farcaster.email.amazon.dev [10.0.13.227:2525] with esmtp (Farcaster) id 7315281c-54af-43a0-9bc2-0e615f3905b8; Tue, 12 Mar 2024 18:07:29 +0000 (UTC) X-Farcaster-Flow-ID: 7315281c-54af-43a0-9bc2-0e615f3905b8 Received: from EX19D007EUB002.ant.amazon.com (10.252.51.117) by EX19MTAEUB002.ant.amazon.com (10.252.51.79) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Tue, 12 Mar 2024 18:07:29 +0000 Received: from EX19MTAUWA001.ant.amazon.com (10.250.64.204) by EX19D007EUB002.ant.amazon.com (10.252.51.117) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Tue, 12 Mar 2024 18:07:29 +0000 Received: from HFA15-CG15235BS.amazon.com (10.85.143.174) by mail-relay.amazon.com (10.250.64.204) with Microsoft SMTP Server id 15.2.1258.28 via Frontend Transport; Tue, 12 Mar 2024 18:07:27 +0000 From: To: CC: , Shai Brandes Subject: [PATCH v4 02/31] net/ena: report new supported link speed capabilities Date: Tue, 12 Mar 2024 20:06:47 +0200 Message-ID: <20240312180716.8515-3-shaibran@amazon.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240312180716.8515-1-shaibran@amazon.com> References: <20240312180716.8515-1-shaibran@amazon.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Shai Brandes Updated the rte_eth_dev_info device supported speed bitmap to include 200Gbps and 400Gbps capabilities. Signed-off-by: Shai Brandes Reviewed-by: Amit Bernstein --- drivers/net/ena/ena_ethdev.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/net/ena/ena_ethdev.c b/drivers/net/ena/ena_ethdev.c index 6d500bfa78..b1e7de0541 100644 --- a/drivers/net/ena/ena_ethdev.c +++ b/drivers/net/ena/ena_ethdev.c @@ -2542,7 +2542,9 @@ static int ena_infos_get(struct rte_eth_dev *dev, RTE_ETH_LINK_SPEED_25G | RTE_ETH_LINK_SPEED_40G | RTE_ETH_LINK_SPEED_50G | - RTE_ETH_LINK_SPEED_100G; + RTE_ETH_LINK_SPEED_100G | + RTE_ETH_LINK_SPEED_200G | + RTE_ETH_LINK_SPEED_400G; /* Inform framework about available features */ dev_info->rx_offload_capa = ena_get_rx_port_offloads(adapter); From patchwork Tue Mar 12 18:06:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Brandes, Shai" X-Patchwork-Id: 138253 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 66C1143C94; Tue, 12 Mar 2024 19:07:46 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id AECE542DF7; Tue, 12 Mar 2024 19:07:36 +0100 (CET) Received: from smtp-fw-80007.amazon.com (smtp-fw-80007.amazon.com [99.78.197.218]) by mails.dpdk.org (Postfix) with ESMTP id 5439A42DE4 for ; Tue, 12 Mar 2024 19:07:34 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.com; i=@amazon.com; q=dns/txt; s=amazon201209; t=1710266855; x=1741802855; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=h9XSl5qGMjQmMxht+VT2/cVX6CehdutCO4yagmFilLs=; b=nDdQlZ8Xe6TlTARRX0mR4VyOjyOcY1HKIUpVQueEZrsSGe+jdptaTof3 lNqvIqLrXVFM7Cm0WedsG7nPiTWl0l+KjZ/FfBF4TAm7bLaKn2zTBJz4v 5tLYBns+LlrDRW7SMVQijHoY+05MJ5lajQYNewaDUKa03ZlqV5T/wTUdZ o=; X-IronPort-AV: E=Sophos;i="6.07,119,1708387200"; d="scan'208";a="280481482" Received: from pdx4-co-svc-p1-lb2-vlan2.amazon.com (HELO smtpout.prod.us-east-1.prod.farcaster.email.amazon.dev) ([10.25.36.210]) by smtp-border-fw-80007.pdx80.corp.amazon.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Mar 2024 18:07:34 +0000 Received: from EX19MTAEUA002.ant.amazon.com [10.0.43.254:36784] by smtpin.naws.eu-west-1.prod.farcaster.email.amazon.dev [10.0.24.76:2525] with esmtp (Farcaster) id c57af74d-7073-4232-a362-db3858f4cafb; Tue, 12 Mar 2024 18:07:32 +0000 (UTC) X-Farcaster-Flow-ID: c57af74d-7073-4232-a362-db3858f4cafb Received: from EX19D007EUA002.ant.amazon.com (10.252.50.68) by EX19MTAEUA002.ant.amazon.com (10.252.50.124) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Tue, 12 Mar 2024 18:07:32 +0000 Received: from EX19MTAUWA001.ant.amazon.com (10.250.64.204) by EX19D007EUA002.ant.amazon.com (10.252.50.68) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Tue, 12 Mar 2024 18:07:31 +0000 Received: from HFA15-CG15235BS.amazon.com (10.85.143.174) by mail-relay.amazon.com (10.250.64.204) with Microsoft SMTP Server id 15.2.1258.28 via Frontend Transport; Tue, 12 Mar 2024 18:07:30 +0000 From: To: CC: , Shai Brandes Subject: [PATCH v4 03/31] net/ena: update imissed stat with Rx overruns Date: Tue, 12 Mar 2024 20:06:48 +0200 Message-ID: <20240312180716.8515-4-shaibran@amazon.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240312180716.8515-1-shaibran@amazon.com> References: <20240312180716.8515-1-shaibran@amazon.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Shai Brandes Depending on its acceleration support, the device updates a different statistic when an ingress packet is dropped because no buffers are available to hold it. - In AWS instance types from later generations 'rx_overruns' is updated. - Otherwise, in legacy instance types, 'rx_dropped_cnt' is updated. That is, there is no need to report rx_overruns separately as an xstat and the driver can simply sum up the two self-contained counters as the 'imissed' statistic. Signed-off-by: Shai Brandes Reviewed-by: Amit Bernstein --- doc/guides/rel_notes/release_24_03.rst | 4 ++++ drivers/net/ena/ena_ethdev.c | 8 +++++--- drivers/net/ena/ena_ethdev.h | 1 - 3 files changed, 9 insertions(+), 4 deletions(-) diff --git a/doc/guides/rel_notes/release_24_03.rst b/doc/guides/rel_notes/release_24_03.rst index 932688ca4d..0fe8bc9739 100644 --- a/doc/guides/rel_notes/release_24_03.rst +++ b/doc/guides/rel_notes/release_24_03.rst @@ -103,6 +103,10 @@ New Features * ``rte_flow_template_table_resize_complete()``. Complete table resize. +* **Updated Amazon ena (Elastic Network Adapter) net driver.** + + * Removed the reporting of `rx_overruns` errors from xstats and instead updated `imissed` stat with its value. + * **Updated Atomic Rules' Arkville driver.** * Added support for Atomic Rules' TK242 packet-capture family of devices diff --git a/drivers/net/ena/ena_ethdev.c b/drivers/net/ena/ena_ethdev.c index b1e7de0541..d3f395a832 100644 --- a/drivers/net/ena/ena_ethdev.c +++ b/drivers/net/ena/ena_ethdev.c @@ -93,7 +93,6 @@ static const struct ena_stats ena_stats_global_strings[] = { ENA_STAT_GLOBAL_ENTRY(dev_start), ENA_STAT_GLOBAL_ENTRY(dev_stop), ENA_STAT_GLOBAL_ENTRY(tx_drops), - ENA_STAT_GLOBAL_ENTRY(rx_overruns), }; /* @@ -4014,9 +4013,12 @@ static void ena_keep_alive(void *adapter_data, tx_drops = ((uint64_t)desc->tx_drops_high << 32) | desc->tx_drops_low; rx_overruns = ((uint64_t)desc->rx_overruns_high << 32) | desc->rx_overruns_low; - adapter->drv_stats->rx_drops = rx_drops; + /* + * Depending on its acceleration support, the device updates a different statistic when + * Rx packet is dropped because there are no available buffers to accommodate it. + */ + adapter->drv_stats->rx_drops = rx_drops + rx_overruns; adapter->dev_stats.tx_drops = tx_drops; - adapter->dev_stats.rx_overruns = rx_overruns; } /** diff --git a/drivers/net/ena/ena_ethdev.h b/drivers/net/ena/ena_ethdev.h index 4988fbffb5..20b8307836 100644 --- a/drivers/net/ena/ena_ethdev.h +++ b/drivers/net/ena/ena_ethdev.h @@ -219,7 +219,6 @@ struct ena_stats_dev { * As a workaround it is being published as an extended statistic. */ u64 tx_drops; - u64 rx_overruns; }; struct ena_stats_metrics { From patchwork Tue Mar 12 18:06:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Brandes, Shai" X-Patchwork-Id: 138254 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 97D5143C94; Tue, 12 Mar 2024 19:07:52 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E8B6D42E01; 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Tue, 12 Mar 2024 18:07:34 +0000 (UTC) X-Farcaster-Flow-ID: 6d77db7a-a58b-46e3-9da3-f32c327dfd03 Received: from EX19D007EUA001.ant.amazon.com (10.252.50.133) by EX19MTAEUA001.ant.amazon.com (10.252.50.192) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Tue, 12 Mar 2024 18:07:34 +0000 Received: from EX19MTAUWA001.ant.amazon.com (10.250.64.204) by EX19D007EUA001.ant.amazon.com (10.252.50.133) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Tue, 12 Mar 2024 18:07:33 +0000 Received: from HFA15-CG15235BS.amazon.com (10.85.143.174) by mail-relay.amazon.com (10.250.64.204) with Microsoft SMTP Server id 15.2.1258.28 via Frontend Transport; Tue, 12 Mar 2024 18:07:32 +0000 From: To: CC: , Shai Brandes Subject: [PATCH v4 04/31] net/ena: sub-optimal configuration notifications support Date: Tue, 12 Mar 2024 20:06:49 +0200 Message-ID: <20240312180716.8515-5-shaibran@amazon.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240312180716.8515-1-shaibran@amazon.com> References: <20240312180716.8515-1-shaibran@amazon.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Shai Brandes ENA device will send asynchronous notifications to the driver in order to notify users about sub-optimal configurations and refer them to public AWS documentation for further action. Signed-off-by: Shai Brandes Reviewed-by: Amit Bernstein --- doc/guides/rel_notes/release_24_03.rst | 1 + .../net/ena/base/ena_defs/ena_admin_defs.h | 11 +++++++- drivers/net/ena/ena_ethdev.c | 26 +++++++++++++++++-- 3 files changed, 35 insertions(+), 3 deletions(-) diff --git a/doc/guides/rel_notes/release_24_03.rst b/doc/guides/rel_notes/release_24_03.rst index 0fe8bc9739..a30be47241 100644 --- a/doc/guides/rel_notes/release_24_03.rst +++ b/doc/guides/rel_notes/release_24_03.rst @@ -106,6 +106,7 @@ New Features * **Updated Amazon ena (Elastic Network Adapter) net driver.** * Removed the reporting of `rx_overruns` errors from xstats and instead updated `imissed` stat with its value. + * Added support for sub-optimal configuration notifications from the device. * **Updated Atomic Rules' Arkville driver.** diff --git a/drivers/net/ena/base/ena_defs/ena_admin_defs.h b/drivers/net/ena/base/ena_defs/ena_admin_defs.h index fa43e22918..4172916551 100644 --- a/drivers/net/ena/base/ena_defs/ena_admin_defs.h +++ b/drivers/net/ena/base/ena_defs/ena_admin_defs.h @@ -1214,7 +1214,8 @@ enum ena_admin_aenq_group { ENA_ADMIN_NOTIFICATION = 3, ENA_ADMIN_KEEP_ALIVE = 4, ENA_ADMIN_REFRESH_CAPABILITIES = 5, - ENA_ADMIN_AENQ_GROUPS_NUM = 6, + ENA_ADMIN_CONF_NOTIFICATIONS = 6, + ENA_ADMIN_AENQ_GROUPS_NUM = 7, }; enum ena_admin_aenq_notification_syndrome { @@ -1251,6 +1252,14 @@ struct ena_admin_aenq_keep_alive_desc { uint32_t rx_overruns_high; }; +struct ena_admin_aenq_conf_notifications_desc { + struct ena_admin_aenq_common_desc aenq_common_desc; + + uint64_t notifications_bitmap; + + uint64_t reserved; +}; + struct ena_admin_ena_mmio_req_read_less_resp { uint16_t req_id; diff --git a/drivers/net/ena/ena_ethdev.c b/drivers/net/ena/ena_ethdev.c index d3f395a832..3157237c0d 100644 --- a/drivers/net/ena/ena_ethdev.c +++ b/drivers/net/ena/ena_ethdev.c @@ -36,6 +36,10 @@ #define ENA_MIN_RING_DESC 128 +#define BITS_PER_BYTE 8 + +#define BITS_PER_TYPE(type) (sizeof(type) * BITS_PER_BYTE) + /* * We should try to keep ENA_CLEANUP_BUF_SIZE lower than * RTE_MEMPOOL_CACHE_MAX_SIZE, so we can fit this in mempool local cache. @@ -1842,7 +1846,8 @@ static int ena_device_init(struct ena_adapter *adapter, BIT(ENA_ADMIN_NOTIFICATION) | BIT(ENA_ADMIN_KEEP_ALIVE) | BIT(ENA_ADMIN_FATAL_ERROR) | - BIT(ENA_ADMIN_WARNING); + BIT(ENA_ADMIN_WARNING) | + BIT(ENA_ADMIN_CONF_NOTIFICATIONS); aenq_groups &= get_feat_ctx->aenq.supported_groups; @@ -4021,6 +4026,22 @@ static void ena_keep_alive(void *adapter_data, adapter->dev_stats.tx_drops = tx_drops; } +static void ena_suboptimal_configuration(__rte_unused void *adapter_data, + struct ena_admin_aenq_entry *aenq_e) +{ + struct ena_admin_aenq_conf_notifications_desc *desc; + int bit, num_bits; + + desc = (struct ena_admin_aenq_conf_notifications_desc *)aenq_e; + num_bits = BITS_PER_TYPE(desc->notifications_bitmap); + for (bit = 0; bit < num_bits; bit++) { + if (desc->notifications_bitmap & RTE_BIT64(bit)) { + PMD_DRV_LOG(WARNING, + "Sub-optimal configuration notification code: %d\n", bit + 1); + } + } +} + /** * This handler will called for unknown event group or unimplemented handlers **/ @@ -4035,7 +4056,8 @@ static struct ena_aenq_handlers aenq_handlers = { .handlers = { [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change, [ENA_ADMIN_NOTIFICATION] = ena_notification, - [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive + [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive, + [ENA_ADMIN_CONF_NOTIFICATIONS] = ena_suboptimal_configuration }, .unimplemented_handler = unimplemented_aenq_handler }; From patchwork Tue Mar 12 18:06:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Brandes, Shai" X-Patchwork-Id: 138256 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4EF3743C94; Tue, 12 Mar 2024 19:08:09 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id AE81D42E1D; Tue, 12 Mar 2024 19:07:48 +0100 (CET) Received: from smtp-fw-33001.amazon.com (smtp-fw-33001.amazon.com [207.171.190.10]) by mails.dpdk.org (Postfix) with ESMTP id 04B9B42E00; Tue, 12 Mar 2024 19:07:45 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.com; i=@amazon.com; q=dns/txt; s=amazon201209; t=1710266867; x=1741802867; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; 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Tue, 12 Mar 2024 18:07:36 +0000 Received: from EX19MTAUWA001.ant.amazon.com (10.250.64.204) by EX19D007EUA002.ant.amazon.com (10.252.50.68) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Tue, 12 Mar 2024 18:07:35 +0000 Received: from HFA15-CG15235BS.amazon.com (10.85.143.174) by mail-relay.amazon.com (10.250.64.204) with Microsoft SMTP Server id 15.2.1258.28 via Frontend Transport; Tue, 12 Mar 2024 18:07:34 +0000 From: To: CC: , Shai Brandes , Subject: [PATCH v4 05/31] net/ena: fix fast mbuf free Date: Tue, 12 Mar 2024 20:06:50 +0200 Message-ID: <20240312180716.8515-6-shaibran@amazon.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240312180716.8515-1-shaibran@amazon.com> References: <20240312180716.8515-1-shaibran@amazon.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Shai Brandes In case the application enables fast mbuf release optimization, the driver releases 256 TX mbufs in bulk upon reaching the TX free threshold. The existing implementation utilizes rte_mempool_put_bulk for bulk freeing TXs, which exclusively supports direct mbufs. In case the application transmits indirect bufs, the driver must also decrement the mbuf reference count and unlink the mbuf segment. For such case, the driver should employ rte_pktmbuf_free_bulk. Fixes: c339f53823f3 ("net/ena: support fast mbuf free") Cc: stable@dpdk.org Signed-off-by: Shai Brandes Reviewed-by: Amit Bernstein --- doc/guides/rel_notes/release_24_03.rst | 1 + drivers/net/ena/ena_ethdev.c | 6 ++---- 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/doc/guides/rel_notes/release_24_03.rst b/doc/guides/rel_notes/release_24_03.rst index a30be47241..cbd4669cbb 100644 --- a/doc/guides/rel_notes/release_24_03.rst +++ b/doc/guides/rel_notes/release_24_03.rst @@ -107,6 +107,7 @@ New Features * Removed the reporting of `rx_overruns` errors from xstats and instead updated `imissed` stat with its value. * Added support for sub-optimal configuration notifications from the device. + * Restructured fast release of mbufs when RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE optimization is enabled. * **Updated Atomic Rules' Arkville driver.** diff --git a/drivers/net/ena/ena_ethdev.c b/drivers/net/ena/ena_ethdev.c index 3157237c0d..537ee9f8c3 100644 --- a/drivers/net/ena/ena_ethdev.c +++ b/drivers/net/ena/ena_ethdev.c @@ -3122,8 +3122,7 @@ ena_tx_cleanup_mbuf_fast(struct rte_mbuf **mbufs_to_clean, m_next = mbuf->next; mbufs_to_clean[mbuf_cnt++] = mbuf; if (mbuf_cnt == buf_size) { - rte_mempool_put_bulk(mbufs_to_clean[0]->pool, (void **)mbufs_to_clean, - (unsigned int)mbuf_cnt); + rte_pktmbuf_free_bulk(mbufs_to_clean, mbuf_cnt); mbuf_cnt = 0; } mbuf = m_next; @@ -3191,8 +3190,7 @@ static int ena_tx_cleanup(void *txp, uint32_t free_pkt_cnt) } if (mbuf_cnt != 0) - rte_mempool_put_bulk(mbufs_to_clean[0]->pool, - (void **)mbufs_to_clean, mbuf_cnt); + rte_pktmbuf_free_bulk(mbufs_to_clean, mbuf_cnt); /* Notify completion handler that full cleanup was performed */ if (free_pkt_cnt == 0 || total_tx_pkts < cleanup_budget) From patchwork Tue Mar 12 18:06:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Brandes, Shai" X-Patchwork-Id: 138255 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5D75843C94; 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12 Mar 2024 18:07:40 +0000 Received: from EX19MTAEUC001.ant.amazon.com [10.0.10.100:15920] by smtpin.naws.eu-west-1.prod.farcaster.email.amazon.dev [10.0.21.118:2525] with esmtp (Farcaster) id 18af2330-8e3e-4913-84e9-b32ffd6a21d0; Tue, 12 Mar 2024 18:07:38 +0000 (UTC) X-Farcaster-Flow-ID: 18af2330-8e3e-4913-84e9-b32ffd6a21d0 Received: from EX19D007EUB002.ant.amazon.com (10.252.51.117) by EX19MTAEUC001.ant.amazon.com (10.252.51.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Tue, 12 Mar 2024 18:07:38 +0000 Received: from EX19MTAUWA001.ant.amazon.com (10.250.64.204) by EX19D007EUB002.ant.amazon.com (10.252.51.117) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Tue, 12 Mar 2024 18:07:37 +0000 Received: from HFA15-CG15235BS.amazon.com (10.85.143.174) by mail-relay.amazon.com (10.250.64.204) with Microsoft SMTP Server id 15.2.1258.28 via Frontend Transport; Tue, 12 Mar 2024 18:07:36 +0000 From: To: CC: , Shai Brandes Subject: [PATCH v4 06/31] net/ena: restructure the llq policy setting process Date: Tue, 12 Mar 2024 20:06:51 +0200 Message-ID: <20240312180716.8515-7-shaibran@amazon.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240312180716.8515-1-shaibran@amazon.com> References: <20240312180716.8515-1-shaibran@amazon.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Shai Brandes The driver will set the size of the LLQ header size according to the recommendation from the device. The user can bypass the recommendation via devargs: - The existing devarg 'large_llq_hdr' (default 0) allows user to enforce large llq header policy. - The existing devarg 'enable_llq' (default 1) allows user to disable llq usage. - A new devarg 'normal_llq_hdr' (default 0) allows user to enforce normal llq header policy. Signed-off-by: Shai Brandes Reviewed-by: Amit Bernstein --- doc/guides/nics/ena.rst | 4 ++ doc/guides/rel_notes/release_24_03.rst | 1 + drivers/net/ena/ena_ethdev.c | 60 ++++++++++++++++++++++---- drivers/net/ena/ena_ethdev.h | 11 ++++- 4 files changed, 67 insertions(+), 9 deletions(-) diff --git a/doc/guides/nics/ena.rst b/doc/guides/nics/ena.rst index b039e75ead..725215b36d 100644 --- a/doc/guides/nics/ena.rst +++ b/doc/guides/nics/ena.rst @@ -113,6 +113,10 @@ Runtime Configuration effect only if the device also supports large LLQ headers. Otherwise, the default value will be used. + * **normal_llq_hdr** (default 0) + + Enforce normal LLQ policy. + * **miss_txc_to** (default 5) Number of seconds after which the Tx packet will be considered missing. diff --git a/doc/guides/rel_notes/release_24_03.rst b/doc/guides/rel_notes/release_24_03.rst index cbd4669cbb..58d092194e 100644 --- a/doc/guides/rel_notes/release_24_03.rst +++ b/doc/guides/rel_notes/release_24_03.rst @@ -108,6 +108,7 @@ New Features * Removed the reporting of `rx_overruns` errors from xstats and instead updated `imissed` stat with its value. * Added support for sub-optimal configuration notifications from the device. * Restructured fast release of mbufs when RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE optimization is enabled. + * Added `normal_llq_hdr` devarg that enforce normal llq header policy. * **Updated Atomic Rules' Arkville driver.** diff --git a/drivers/net/ena/ena_ethdev.c b/drivers/net/ena/ena_ethdev.c index 537ee9f8c3..e23edd4bd2 100644 --- a/drivers/net/ena/ena_ethdev.c +++ b/drivers/net/ena/ena_ethdev.c @@ -40,6 +40,8 @@ #define BITS_PER_TYPE(type) (sizeof(type) * BITS_PER_BYTE) +#define DECIMAL_BASE 10 + /* * We should try to keep ENA_CLEANUP_BUF_SIZE lower than * RTE_MEMPOOL_CACHE_MAX_SIZE, so we can fit this in mempool local cache. @@ -75,6 +77,7 @@ struct ena_stats { /* Device arguments */ #define ENA_DEVARG_LARGE_LLQ_HDR "large_llq_hdr" +#define ENA_DEVARG_NORMAL_LLQ_HDR "normal_llq_hdr" /* Timeout in seconds after which a single uncompleted Tx packet should be * considered as a missing. */ @@ -297,6 +300,8 @@ static int ena_rx_queue_intr_disable(struct rte_eth_dev *dev, static int ena_configure_aenq(struct ena_adapter *adapter); static int ena_mp_primary_handle(const struct rte_mp_msg *mp_msg, const void *peer); +static ena_llq_policy ena_define_llq_hdr_policy(struct ena_adapter *adapter); +static bool ena_use_large_llq_hdr(struct ena_adapter *adapter, uint8_t recommended_entry_size); static const struct eth_dev_ops ena_dev_ops = { .dev_configure = ena_dev_configure, @@ -1135,6 +1140,7 @@ ena_calc_io_queue_size(struct ena_calc_queue_size_ctx *ctx, ctx->max_tx_queue_size = max_tx_queue_size; ctx->max_rx_queue_size = max_rx_queue_size; + PMD_DRV_LOG(INFO, "tx queue size %u\n", max_tx_queue_size); return 0; } @@ -2034,7 +2040,7 @@ ena_set_queues_placement_policy(struct ena_adapter *adapter, int rc; u32 llq_feature_mask; - if (!adapter->enable_llq) { + if (adapter->llq_header_policy == ENA_LLQ_POLICY_DISABLED) { PMD_DRV_LOG(WARNING, "NOTE: LLQ has been disabled as per user's request. " "This may lead to a huge performance degradation!\n"); @@ -2241,12 +2247,16 @@ static int eth_ena_dev_init(struct rte_eth_dev *eth_dev) adapter->missing_tx_completion_to = ENA_TX_TIMEOUT; adapter->enable_llq = true; adapter->use_large_llq_hdr = false; + adapter->use_normal_llq_hdr = false; + /* Get user bypass */ rc = ena_parse_devargs(adapter, pci_dev->device.devargs); if (rc != 0) { PMD_INIT_LOG(CRIT, "Failed to parse devargs\n"); goto err; } + adapter->llq_header_policy = ena_define_llq_hdr_policy(adapter); + rc = ena_com_allocate_customer_metrics_buffer(ena_dev); if (rc != 0) { PMD_INIT_LOG(CRIT, "Failed to allocate customer metrics buffer\n"); @@ -2264,8 +2274,9 @@ static int eth_ena_dev_init(struct rte_eth_dev *eth_dev) if (!(adapter->all_aenq_groups & BIT(ENA_ADMIN_LINK_CHANGE))) adapter->edev_data->dev_flags &= ~RTE_ETH_DEV_INTR_LSC; - set_default_llq_configurations(&llq_config, &get_feat_ctx.llq, - adapter->use_large_llq_hdr); + bool use_large_llq_hdr = ena_use_large_llq_hdr(adapter, + get_feat_ctx.llq.entry_size_recommended); + set_default_llq_configurations(&llq_config, &get_feat_ctx.llq, use_large_llq_hdr); rc = ena_set_queues_placement_policy(adapter, ena_dev, &get_feat_ctx.llq, &llq_config); if (unlikely(rc)) { @@ -2273,18 +2284,19 @@ static int eth_ena_dev_init(struct rte_eth_dev *eth_dev) return rc; } - if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) + if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) { queue_type_str = "Regular"; - else + } else { queue_type_str = "Low latency"; + PMD_DRV_LOG(INFO, "LLQ entry size %uB\n", llq_config.llq_ring_entry_size_value); + } PMD_DRV_LOG(INFO, "Placement policy: %s\n", queue_type_str); calc_queue_ctx.ena_dev = ena_dev; calc_queue_ctx.get_feat_ctx = &get_feat_ctx; max_num_io_queues = ena_calc_max_io_queue_num(ena_dev, &get_feat_ctx); - rc = ena_calc_io_queue_size(&calc_queue_ctx, - adapter->use_large_llq_hdr); + rc = ena_calc_io_queue_size(&calc_queue_ctx, use_large_llq_hdr); if (unlikely((rc != 0) || (max_num_io_queues == 0))) { rc = -EFAULT; goto err_device_destroy; @@ -3632,7 +3644,7 @@ static int ena_process_uint_devarg(const char *key, char *str_end; uint64_t uint_value; - uint_value = strtoull(value, &str_end, 10); + uint_value = strtoull(value, &str_end, DECIMAL_BASE); if (value == str_end) { PMD_INIT_LOG(ERR, "Invalid value for key '%s'. Only uint values are accepted.\n", @@ -3685,6 +3697,8 @@ static int ena_process_bool_devarg(const char *key, /* Now, assign it to the proper adapter field. */ if (strcmp(key, ENA_DEVARG_LARGE_LLQ_HDR) == 0) adapter->use_large_llq_hdr = bool_value; + else if (strcmp(key, ENA_DEVARG_NORMAL_LLQ_HDR) == 0) + adapter->use_normal_llq_hdr = bool_value; else if (strcmp(key, ENA_DEVARG_ENABLE_LLQ) == 0) adapter->enable_llq = bool_value; @@ -3696,6 +3710,7 @@ static int ena_parse_devargs(struct ena_adapter *adapter, { static const char * const allowed_args[] = { ENA_DEVARG_LARGE_LLQ_HDR, + ENA_DEVARG_NORMAL_LLQ_HDR, ENA_DEVARG_MISS_TXC_TO, ENA_DEVARG_ENABLE_LLQ, NULL, @@ -3717,6 +3732,10 @@ static int ena_parse_devargs(struct ena_adapter *adapter, ena_process_bool_devarg, adapter); if (rc != 0) goto exit; + rc = rte_kvargs_process(kvlist, ENA_DEVARG_NORMAL_LLQ_HDR, + ena_process_bool_devarg, adapter); + if (rc != 0) + goto exit; rc = rte_kvargs_process(kvlist, ENA_DEVARG_MISS_TXC_TO, ena_process_uint_devarg, adapter); if (rc != 0) @@ -3943,6 +3962,7 @@ RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map); RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci"); RTE_PMD_REGISTER_PARAM_STRING(net_ena, ENA_DEVARG_LARGE_LLQ_HDR "=<0|1> " + ENA_DEVARG_NORMAL_LLQ_HDR "=<0|1> " ENA_DEVARG_ENABLE_LLQ "=<0|1> " ENA_DEVARG_MISS_TXC_TO "="); RTE_LOG_REGISTER_SUFFIX(ena_logtype_init, init, NOTICE); @@ -4129,3 +4149,27 @@ ena_mp_primary_handle(const struct rte_mp_msg *mp_msg, const void *peer) /* Return just IPC processing status */ return rte_mp_reply(&mp_rsp, peer); } + +static ena_llq_policy ena_define_llq_hdr_policy(struct ena_adapter *adapter) +{ + if (!adapter->enable_llq) + return ENA_LLQ_POLICY_DISABLED; + if (adapter->use_large_llq_hdr) + return ENA_LLQ_POLICY_LARGE; + if (adapter->use_normal_llq_hdr) + return ENA_LLQ_POLICY_NORMAL; + return ENA_LLQ_POLICY_RECOMMENDED; +} + +static bool ena_use_large_llq_hdr(struct ena_adapter *adapter, uint8_t recommended_entry_size) +{ + if (adapter->llq_header_policy == ENA_LLQ_POLICY_LARGE) { + return true; + } else if (adapter->llq_header_policy == ENA_LLQ_POLICY_RECOMMENDED) { + PMD_DRV_LOG(INFO, "Recommended device entry size policy %u\n", + recommended_entry_size); + if (recommended_entry_size == ENA_ADMIN_LIST_ENTRY_SIZE_256B) + return true; + } + return false; +} diff --git a/drivers/net/ena/ena_ethdev.h b/drivers/net/ena/ena_ethdev.h index 20b8307836..7358f28caf 100644 --- a/drivers/net/ena/ena_ethdev.h +++ b/drivers/net/ena/ena_ethdev.h @@ -85,6 +85,14 @@ enum ena_ring_type { ENA_RING_TYPE_TX = 2, }; +typedef enum ena_llq_policy_t { + ENA_LLQ_POLICY_DISABLED = 0, /* Host queues */ + ENA_LLQ_POLICY_RECOMMENDED = 1, /* Device recommendation */ + ENA_LLQ_POLICY_NORMAL = 2, /* 128B long LLQ entry */ + ENA_LLQ_POLICY_LARGE = 3, /* 256B long LLQ entry */ + ENA_LLQ_POLICY_LAST, +} ena_llq_policy; + struct ena_tx_buffer { struct rte_mbuf *mbuf; unsigned int tx_descs; @@ -328,9 +336,10 @@ struct ena_adapter { uint32_t active_aenq_groups; bool trigger_reset; - bool enable_llq; bool use_large_llq_hdr; + bool use_normal_llq_hdr; + ena_llq_policy llq_header_policy; uint32_t last_tx_comp_qid; uint64_t missing_tx_completion_to; From patchwork Tue Mar 12 18:06:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Brandes, Shai" X-Patchwork-Id: 138263 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 83B4F43C94; Tue, 12 Mar 2024 19:08:58 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1131842E4B; Tue, 12 Mar 2024 19:08:05 +0100 (CET) Received: from smtp-fw-9102.amazon.com (smtp-fw-9102.amazon.com [207.171.184.29]) by mails.dpdk.org (Postfix) with ESMTP id 90BBF42E39 for ; Tue, 12 Mar 2024 19:08:01 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.com; 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Tue, 12 Mar 2024 18:07:40 +0000 Received: from EX19MTAUWA001.ant.amazon.com (10.250.64.204) by EX19D007EUA001.ant.amazon.com (10.252.50.133) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Tue, 12 Mar 2024 18:07:39 +0000 Received: from HFA15-CG15235BS.amazon.com (10.85.143.174) by mail-relay.amazon.com (10.250.64.204) with Microsoft SMTP Server id 15.2.1258.28 via Frontend Transport; Tue, 12 Mar 2024 18:07:38 +0000 From: To: CC: , Shai Brandes Subject: [PATCH v4 07/31] net/ena/base: limit exponential backoff exp Date: Tue, 12 Mar 2024 20:06:52 +0200 Message-ID: <20240312180716.8515-8-shaibran@amazon.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240312180716.8515-1-shaibran@amazon.com> References: <20240312180716.8515-1-shaibran@amazon.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Shai Brandes Limit the value of the exponent used for this backoff at (1<<16) to prevent it from reaching to an excessive value (1<<32) or potentially even overflowing. In addition, for uniformity and readability purposes, the min/max parameter in the calls of ENA_MIN32 and ENA_MAX32 macros was changed to be first. Signed-off-by: Shai Brandes Reviewed-by: Amit Bernstein --- drivers/net/ena/base/ena_com.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/net/ena/base/ena_com.c b/drivers/net/ena/base/ena_com.c index 6953a1fa33..31c37b0ab3 100644 --- a/drivers/net/ena/base/ena_com.c +++ b/drivers/net/ena/base/ena_com.c @@ -34,6 +34,8 @@ #define ENA_REGS_ADMIN_INTR_MASK 1 +#define ENA_MAX_BACKOFF_DELAY_EXP 16U + #define ENA_MIN_ADMIN_POLL_US 100 #define ENA_MAX_ADMIN_POLL_US 5000 @@ -545,8 +547,9 @@ static int ena_com_comp_status_to_errno(struct ena_com_admin_queue *admin_queue, static void ena_delay_exponential_backoff_us(u32 exp, u32 delay_us) { + exp = ENA_MIN32(ENA_MAX_BACKOFF_DELAY_EXP, exp); delay_us = ENA_MAX32(ENA_MIN_ADMIN_POLL_US, delay_us); - delay_us = ENA_MIN32(delay_us * (1U << exp), ENA_MAX_ADMIN_POLL_US); + delay_us = ENA_MIN32(ENA_MAX_ADMIN_POLL_US, delay_us * (1U << exp)); ENA_USLEEP(delay_us); } From patchwork Tue Mar 12 18:06:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Brandes, Shai" X-Patchwork-Id: 138257 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4A51843C94; Tue, 12 Mar 2024 19:08:17 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D99CB42E24; Tue, 12 Mar 2024 19:07:50 +0100 (CET) Received: from smtp-fw-80006.amazon.com (smtp-fw-80006.amazon.com [99.78.197.217]) by mails.dpdk.org (Postfix) with ESMTP id 8A0FB42E24 for ; Tue, 12 Mar 2024 19:07:49 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.com; i=@amazon.com; q=dns/txt; s=amazon201209; t=1710266869; x=1741802869; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=gd0ASrsx8aZNQeOiCvWZiIFFiKM6zWGLmHurF5ObY84=; b=RF6k7hUCS2tooneXOG2N0EY5IkQKa5szvKR4FQdETO89wGkd+E7mrVh6 O0eefrHGPqAVJSVIynQhSw12efM4TipIuwOBt7yDsxzanUkyMrbxE2/ps htJeV9CMaSuHs+julYCeuKoZdLvggJOjjSkydSNboYWNlEI7DVImlfpMO w=; X-IronPort-AV: E=Sophos;i="6.07,119,1708387200"; d="scan'208";a="279565838" Received: from pdx4-co-svc-p1-lb2-vlan3.amazon.com (HELO smtpout.prod.us-west-2.prod.farcaster.email.amazon.dev) ([10.25.36.214]) by smtp-border-fw-80006.pdx80.corp.amazon.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Mar 2024 18:07:46 +0000 Received: from EX19MTAEUC001.ant.amazon.com [10.0.10.100:59696] by smtpin.naws.eu-west-1.prod.farcaster.email.amazon.dev [10.0.13.227:2525] with esmtp (Farcaster) id 8c4054d5-557b-4f40-85cd-e831c1939e3d; Tue, 12 Mar 2024 18:07:45 +0000 (UTC) X-Farcaster-Flow-ID: 8c4054d5-557b-4f40-85cd-e831c1939e3d Received: from EX19D007EUA002.ant.amazon.com (10.252.50.68) by EX19MTAEUC001.ant.amazon.com (10.252.51.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Tue, 12 Mar 2024 18:07:42 +0000 Received: from EX19MTAUWA001.ant.amazon.com (10.250.64.204) by EX19D007EUA002.ant.amazon.com (10.252.50.68) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Tue, 12 Mar 2024 18:07:42 +0000 Received: from HFA15-CG15235BS.amazon.com (10.85.143.174) by mail-relay.amazon.com (10.250.64.204) with Microsoft SMTP Server id 15.2.1258.28 via Frontend Transport; Tue, 12 Mar 2024 18:07:40 +0000 From: To: CC: , Shai Brandes Subject: [PATCH v4 08/31] net/ena/base: add a new csum offload bit Date: Tue, 12 Mar 2024 20:06:53 +0200 Message-ID: <20240312180716.8515-9-shaibran@amazon.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240312180716.8515-1-shaibran@amazon.com> References: <20240312180716.8515-1-shaibran@amazon.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Shai Brandes Add a new driver supported feature bit for TX IPv6 checksum offload. Signed-off-by: Shai Brandes Reviewed-by: Amit Bernstein --- .../net/ena/base/ena_defs/ena_admin_defs.h | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/drivers/net/ena/base/ena_defs/ena_admin_defs.h b/drivers/net/ena/base/ena_defs/ena_admin_defs.h index 4172916551..670e794c98 100644 --- a/drivers/net/ena/base/ena_defs/ena_admin_defs.h +++ b/drivers/net/ena/base/ena_defs/ena_admin_defs.h @@ -985,7 +985,8 @@ struct ena_admin_host_info { * 4 : rss_configurable_function_key * 5 : reserved * 6 : rx_page_reuse - * 31:7 : reserved + * 7 : tx_ipv6_csum_offload + * 31:8 : reserved */ uint32_t driver_supported_features; }; @@ -1377,6 +1378,8 @@ struct ena_admin_phc_resp { #define ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_MASK BIT(4) #define ENA_ADMIN_HOST_INFO_RX_PAGE_REUSE_SHIFT 6 #define ENA_ADMIN_HOST_INFO_RX_PAGE_REUSE_MASK BIT(6) +#define ENA_ADMIN_HOST_INFO_TX_IPV6_CSUM_OFFLOAD_SHIFT 7 +#define ENA_ADMIN_HOST_INFO_TX_IPV6_CSUM_OFFLOAD_MASK BIT(7) /* feature_rss_ind_table */ #define ENA_ADMIN_FEATURE_RSS_IND_TABLE_ONE_ENTRY_UPDATE_MASK BIT(0) @@ -1851,6 +1854,20 @@ static inline void set_ena_admin_host_info_rx_page_reuse(struct ena_admin_host_i ENA_ADMIN_HOST_INFO_RX_PAGE_REUSE_MASK; } +static inline +uint32_t get_ena_admin_host_info_tx_ipv6_csum_offload(const struct ena_admin_host_info *p) +{ + return (p->driver_supported_features & ENA_ADMIN_HOST_INFO_TX_IPV6_CSUM_OFFLOAD_MASK) >> + ENA_ADMIN_HOST_INFO_TX_IPV6_CSUM_OFFLOAD_SHIFT; +} + +static inline void set_ena_admin_host_info_tx_ipv6_csum_offload(struct ena_admin_host_info *p, + uint32_t val) +{ + p->driver_supported_features |= (val << ENA_ADMIN_HOST_INFO_TX_IPV6_CSUM_OFFLOAD_SHIFT) & + ENA_ADMIN_HOST_INFO_TX_IPV6_CSUM_OFFLOAD_MASK; +} + static inline uint8_t get_ena_admin_feature_rss_ind_table_one_entry_update(const struct ena_admin_feature_rss_ind_table *p) { return p->flags & ENA_ADMIN_FEATURE_RSS_IND_TABLE_ONE_ENTRY_UPDATE_MASK; From patchwork Tue Mar 12 18:06:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Brandes, Shai" X-Patchwork-Id: 138258 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C83E143C94; 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12 Mar 2024 18:07:50 +0000 Received: from EX19MTAEUA001.ant.amazon.com [10.0.17.79:47481] by smtpin.naws.eu-west-1.prod.farcaster.email.amazon.dev [10.0.19.132:2525] with esmtp (Farcaster) id 9040ccfe-aad2-43b4-9cfe-1cc828ad0bed; Tue, 12 Mar 2024 18:07:49 +0000 (UTC) X-Farcaster-Flow-ID: 9040ccfe-aad2-43b4-9cfe-1cc828ad0bed Received: from EX19D007EUB002.ant.amazon.com (10.252.51.117) by EX19MTAEUA001.ant.amazon.com (10.252.50.192) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Tue, 12 Mar 2024 18:07:44 +0000 Received: from EX19MTAUWA001.ant.amazon.com (10.250.64.204) by EX19D007EUB002.ant.amazon.com (10.252.51.117) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Tue, 12 Mar 2024 18:07:44 +0000 Received: from HFA15-CG15235BS.amazon.com (10.85.143.174) by mail-relay.amazon.com (10.250.64.204) with Microsoft SMTP Server id 15.2.1258.28 via Frontend Transport; Tue, 12 Mar 2024 18:07:42 +0000 From: To: CC: , Shai Brandes Subject: [PATCH v4 09/31] net/ena/base: optimize Rx ring submission queue Date: Tue, 12 Mar 2024 20:06:54 +0200 Message-ID: <20240312180716.8515-10-shaibran@amazon.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240312180716.8515-1-shaibran@amazon.com> References: <20240312180716.8515-1-shaibran@amazon.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Shai Brandes RX ring submission queue descriptors are always located in host memory This optimization replaces the generic descriptor retrieval method with a tailored method for host memory type descriptors to avoid unnecessary if statement. Signed-off-by: Shai Brandes Reviewed-by: Amit Bernstein --- drivers/net/ena/base/ena_eth_com.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/net/ena/base/ena_eth_com.c b/drivers/net/ena/base/ena_eth_com.c index 32090259cd..875d55b00d 100644 --- a/drivers/net/ena/base/ena_eth_com.c +++ b/drivers/net/ena/base/ena_eth_com.c @@ -630,9 +630,8 @@ int ena_com_add_single_rx_desc(struct ena_com_io_sq *io_sq, if (unlikely(!ena_com_sq_have_enough_space(io_sq, 1))) return ENA_COM_NO_SPACE; - desc = get_sq_desc(io_sq); - if (unlikely(!desc)) - return ENA_COM_FAULT; + /* virt_addr allocation success is checked before calling this function */ + desc = get_sq_desc_regular_queue(io_sq); memset(desc, 0x0, sizeof(struct ena_eth_io_rx_desc)); From patchwork Tue Mar 12 18:06:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Brandes, Shai" X-Patchwork-Id: 138261 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A8F3443C94; Tue, 12 Mar 2024 19:08:44 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 49BEB42E39; Tue, 12 Mar 2024 19:08:02 +0100 (CET) Received: from smtp-fw-9106.amazon.com (smtp-fw-9106.amazon.com [207.171.188.206]) by mails.dpdk.org (Postfix) with ESMTP id 1BC3242E36 for ; Tue, 12 Mar 2024 19:07:58 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.com; i=@amazon.com; q=dns/txt; s=amazon201209; t=1710266880; x=1741802880; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=zxFpeBcIJgRDIT9Fg+32XdJNN2VjRYdczFWSJiA7Eh8=; b=kjetZRuI0cvORCkeCP/Hy3/dvjZCXMjkt9erIE/Gp0k0hRwAfoEsR90/ DxQ1jsKZZvsUGcg2qgE6XNILcDdwt0/sOs4etSegyQ8yJpZlKw1OVu7J3 WwaGIforgcwURFzJt+OZILmKbV+5pdNRTZaSZ63n8yi0eZp/iHg31gWPL M=; X-IronPort-AV: E=Sophos;i="6.07,119,1708387200"; d="scan'208";a="710508041" Received: from pdx4-co-svc-p1-lb2-vlan2.amazon.com (HELO smtpout.prod.us-west-2.prod.farcaster.email.amazon.dev) ([10.25.36.210]) by smtp-border-fw-9106.sea19.amazon.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Mar 2024 18:07:52 +0000 Received: from EX19MTAEUC002.ant.amazon.com [10.0.10.100:21062] by smtpin.naws.eu-west-1.prod.farcaster.email.amazon.dev [10.0.21.118:2525] with esmtp (Farcaster) id 6fff58b9-9c95-4273-9bf3-41f21f3366fe; Tue, 12 Mar 2024 18:07:50 +0000 (UTC) X-Farcaster-Flow-ID: 6fff58b9-9c95-4273-9bf3-41f21f3366fe Received: from EX19D007EUA001.ant.amazon.com (10.252.50.133) by EX19MTAEUC002.ant.amazon.com (10.252.51.181) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Tue, 12 Mar 2024 18:07:46 +0000 Received: from EX19MTAUWA001.ant.amazon.com (10.250.64.204) by EX19D007EUA001.ant.amazon.com (10.252.50.133) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Tue, 12 Mar 2024 18:07:46 +0000 Received: from HFA15-CG15235BS.amazon.com (10.85.143.174) by mail-relay.amazon.com (10.250.64.204) with Microsoft SMTP Server id 15.2.1258.28 via Frontend Transport; Tue, 12 Mar 2024 18:07:44 +0000 From: To: CC: , Shai Brandes Subject: [PATCH v4 10/31] net/ena/base: rename fields in completion descriptors Date: Tue, 12 Mar 2024 20:06:55 +0200 Message-ID: <20240312180716.8515-11-shaibran@amazon.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240312180716.8515-1-shaibran@amazon.com> References: <20240312180716.8515-1-shaibran@amazon.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Shai Brandes Several reserved bits in ena_eth_io_tx_cdesc and ena_eth_io_rx_cdesc_base have been renamed explicitly to MBZ (Must Be Zero). These bits are set by the device to zero before being sent to the driver. The fields are used as an integrity check in order to ensure that the received descriptor is not corrupted. Signed-off-by: Shai Brandes Reviewed-by: Amit Bernstein --- .../net/ena/base/ena_defs/ena_admin_defs.h | 1 + .../net/ena/base/ena_defs/ena_eth_io_defs.h | 49 +++++++++++++++++-- 2 files changed, 47 insertions(+), 3 deletions(-) diff --git a/drivers/net/ena/base/ena_defs/ena_admin_defs.h b/drivers/net/ena/base/ena_defs/ena_admin_defs.h index 670e794c98..438e4a1085 100644 --- a/drivers/net/ena/base/ena_defs/ena_admin_defs.h +++ b/drivers/net/ena/base/ena_defs/ena_admin_defs.h @@ -84,6 +84,7 @@ enum ena_admin_aq_caps_id { ENA_ADMIN_ENA_SRD_INFO = 1, ENA_ADMIN_CUSTOMER_METRICS = 2, ENA_ADMIN_EXTENDED_RESET_REASONS = 3, + ENA_ADMIN_CDESC_MBZ = 4, }; enum ena_admin_placement_policy_type { diff --git a/drivers/net/ena/base/ena_defs/ena_eth_io_defs.h b/drivers/net/ena/base/ena_defs/ena_eth_io_defs.h index 2107d17fdf..f811dd261e 100644 --- a/drivers/net/ena/base/ena_defs/ena_eth_io_defs.h +++ b/drivers/net/ena/base/ena_defs/ena_eth_io_defs.h @@ -152,7 +152,8 @@ struct ena_eth_io_tx_cdesc { /* flags * 0 : phase - * 7:1 : reserved1 + * 5:1 : reserved1 + * 7:6 : mbz6 - MBZ */ uint8_t flags; @@ -198,7 +199,7 @@ struct ena_eth_io_rx_desc { struct ena_eth_io_rx_cdesc_base { /* 4:0 : l3_proto_idx * 6:5 : src_vlan_cnt - * 7 : reserved7 - MBZ + * 7 : mbz7 - MBZ * 12:8 : l4_proto_idx * 13 : l3_csum_err - when set, either the L3 * checksum error detected, or, the controller didn't @@ -214,7 +215,8 @@ struct ena_eth_io_rx_cdesc_base { * 16 : l4_csum_checked - L4 checksum was verified * (could be OK or error), when cleared the status of * checksum is unknown - * 23:17 : reserved17 - MBZ + * 17 : mbz17 - MBZ + * 23:18 : reserved18 * 24 : phase * 25 : l3_csum2 - second checksum engine result * 26 : first - Indicates first descriptor in @@ -341,6 +343,8 @@ struct ena_eth_io_numa_node_cfg_reg { /* tx_cdesc */ #define ENA_ETH_IO_TX_CDESC_PHASE_MASK BIT(0) +#define ENA_ETH_IO_TX_CDESC_MBZ6_SHIFT 6 +#define ENA_ETH_IO_TX_CDESC_MBZ6_MASK GENMASK(7, 6) /* rx_desc */ #define ENA_ETH_IO_RX_DESC_PHASE_MASK BIT(0) @@ -355,6 +359,8 @@ struct ena_eth_io_numa_node_cfg_reg { #define ENA_ETH_IO_RX_CDESC_BASE_L3_PROTO_IDX_MASK GENMASK(4, 0) #define ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_SHIFT 5 #define ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_MASK GENMASK(6, 5) +#define ENA_ETH_IO_RX_CDESC_BASE_MBZ7_SHIFT 7 +#define ENA_ETH_IO_RX_CDESC_BASE_MBZ7_MASK BIT(7) #define ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_SHIFT 8 #define ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_MASK GENMASK(12, 8) #define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_SHIFT 13 @@ -365,6 +371,8 @@ struct ena_eth_io_numa_node_cfg_reg { #define ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_MASK BIT(15) #define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_SHIFT 16 #define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_MASK BIT(16) +#define ENA_ETH_IO_RX_CDESC_BASE_MBZ17_SHIFT 17 +#define ENA_ETH_IO_RX_CDESC_BASE_MBZ17_MASK BIT(17) #define ENA_ETH_IO_RX_CDESC_BASE_PHASE_SHIFT 24 #define ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK BIT(24) #define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_SHIFT 25 @@ -731,6 +739,15 @@ static inline void set_ena_eth_io_tx_cdesc_phase(struct ena_eth_io_tx_cdesc *p, p->flags |= val & ENA_ETH_IO_TX_CDESC_PHASE_MASK; } +static inline uint8_t get_ena_eth_io_tx_cdesc_mbz6(const struct ena_eth_io_tx_cdesc *p) +{ + return (p->flags & ENA_ETH_IO_TX_CDESC_MBZ6_MASK) >> ENA_ETH_IO_TX_CDESC_MBZ6_SHIFT; +} +static inline void set_ena_eth_io_tx_cdesc_mbz6(struct ena_eth_io_tx_cdesc *p, uint8_t val) +{ + p->flags |= (val << ENA_ETH_IO_TX_CDESC_MBZ6_SHIFT) & ENA_ETH_IO_TX_CDESC_MBZ6_MASK; +} + static inline uint8_t get_ena_eth_io_rx_desc_phase(const struct ena_eth_io_rx_desc *p) { return p->ctrl & ENA_ETH_IO_RX_DESC_PHASE_MASK; @@ -791,6 +808,19 @@ static inline void set_ena_eth_io_rx_cdesc_base_src_vlan_cnt(struct ena_eth_io_r p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_MASK; } +static inline uint32_t get_ena_eth_io_rx_cdesc_base_mbz7(const struct ena_eth_io_rx_cdesc_base *p) +{ + return (p->status & ENA_ETH_IO_RX_CDESC_BASE_MBZ7_MASK) >> + ENA_ETH_IO_RX_CDESC_BASE_MBZ7_SHIFT; +} + +static inline void set_ena_eth_io_rx_cdesc_base_mbz7(struct ena_eth_io_rx_cdesc_base *p, + uint32_t val) +{ + p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_MBZ7_SHIFT) & + ENA_ETH_IO_RX_CDESC_BASE_MBZ7_MASK; +} + static inline uint32_t get_ena_eth_io_rx_cdesc_base_l4_proto_idx(const struct ena_eth_io_rx_cdesc_base *p) { return (p->status & ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_SHIFT; @@ -841,6 +871,19 @@ static inline void set_ena_eth_io_rx_cdesc_base_l4_csum_checked(struct ena_eth_i p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_MASK; } +static inline uint32_t get_ena_eth_io_rx_cdesc_base_mbz17(const struct ena_eth_io_rx_cdesc_base *p) +{ + return (p->status & ENA_ETH_IO_RX_CDESC_BASE_MBZ17_MASK) >> + ENA_ETH_IO_RX_CDESC_BASE_MBZ17_SHIFT; +} + +static inline void set_ena_eth_io_rx_cdesc_base_mbz17(struct ena_eth_io_rx_cdesc_base *p, + uint32_t val) +{ + p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_MBZ17_SHIFT) & + ENA_ETH_IO_RX_CDESC_BASE_MBZ17_MASK; +} + static inline uint32_t get_ena_eth_io_rx_cdesc_base_phase(const struct ena_eth_io_rx_cdesc_base *p) { return (p->status & ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_PHASE_SHIFT; From patchwork Tue Mar 12 18:06:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Brandes, Shai" X-Patchwork-Id: 138259 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9D98043C94; Tue, 12 Mar 2024 19:08:31 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2710342E2E; Tue, 12 Mar 2024 19:08:00 +0100 (CET) Received: from smtp-fw-2101.amazon.com (smtp-fw-2101.amazon.com [72.21.196.25]) by mails.dpdk.org (Postfix) with ESMTP id 8FA3542E34 for ; Tue, 12 Mar 2024 19:07:56 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.com; i=@amazon.com; q=dns/txt; s=amazon201209; t=1710266877; x=1741802877; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; 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Tue, 12 Mar 2024 18:07:48 +0000 Received: from EX19MTAUWA001.ant.amazon.com (10.250.64.204) by EX19D007EUA002.ant.amazon.com (10.252.50.68) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Tue, 12 Mar 2024 18:07:48 +0000 Received: from HFA15-CG15235BS.amazon.com (10.85.143.174) by mail-relay.amazon.com (10.250.64.204) with Microsoft SMTP Server id 15.2.1258.28 via Frontend Transport; Tue, 12 Mar 2024 18:07:46 +0000 From: To: CC: , Shai Brandes Subject: [PATCH v4 11/31] net/ena/base: use correct read once on u8 field Date: Tue, 12 Mar 2024 20:06:56 +0200 Message-ID: <20240312180716.8515-12-shaibran@amazon.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240312180716.8515-1-shaibran@amazon.com> References: <20240312180716.8515-1-shaibran@amazon.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Shai Brandes The flags field in ena_eth_io_tx_cdesc is 8-bits long. The current macro used is READ_ONCE16. Switching to READ_ONCE8 to avoid reading extra data. Given that there's an implicit cast to u8 in the assignment, the correct value is being read, but this change makes it even more accurate. Signed-off-by: Shai Brandes Reviewed-by: Amit Bernstein --- drivers/net/ena/base/ena_eth_com.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ena/base/ena_eth_com.h b/drivers/net/ena/base/ena_eth_com.h index cee4f35124..6a7c17f84f 100644 --- a/drivers/net/ena/base/ena_eth_com.h +++ b/drivers/net/ena/base/ena_eth_com.h @@ -219,7 +219,7 @@ static inline int ena_com_tx_comp_req_id_get(struct ena_com_io_cq *io_cq, * expected, it mean that the device still didn't update * this completion. */ - cdesc_phase = READ_ONCE16(cdesc->flags) & ENA_ETH_IO_TX_CDESC_PHASE_MASK; + cdesc_phase = READ_ONCE8(cdesc->flags) & ENA_ETH_IO_TX_CDESC_PHASE_MASK; if (cdesc_phase != expected_phase) return ENA_COM_TRY_AGAIN; From patchwork Tue Mar 12 18:06:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Brandes, Shai" X-Patchwork-Id: 138262 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 226BA43C94; Tue, 12 Mar 2024 19:08:53 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id DB2A442E46; Tue, 12 Mar 2024 19:08:03 +0100 (CET) Received: from smtp-fw-80008.amazon.com (smtp-fw-80008.amazon.com [99.78.197.219]) by mails.dpdk.org (Postfix) with ESMTP id DB0E042DDD for ; Tue, 12 Mar 2024 19:07:59 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.com; i=@amazon.com; q=dns/txt; s=amazon201209; t=1710266880; x=1741802880; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=qfEeyifkHLoYaR9tIJiyZflw2Jw9PNxSj66LdcsJwew=; b=TUaL9RbD4a9sl2K7m8PLD1B+2LE6wHVG9vmhPNYNWFWdnIZZ32ZwcOzj frrfaFPiR6xPmVQgPQrid4L4n8fMMthjvKzt78mxgrZcg09nosO5eGGW3 jqPSpRQB+madn3qpKRMZY6J7ijg7wuydnI7EobAgDGT9C2X8IzSgrbD02 4=; X-IronPort-AV: E=Sophos;i="6.07,119,1708387200"; d="scan'208";a="72647518" Received: from pdx4-co-svc-p1-lb2-vlan3.amazon.com (HELO smtpout.prod.us-east-1.prod.farcaster.email.amazon.dev) ([10.25.36.214]) by smtp-border-fw-80008.pdx80.corp.amazon.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Mar 2024 18:07:59 +0000 Received: from EX19MTAEUB001.ant.amazon.com [10.0.10.100:35817] by smtpin.naws.eu-west-1.prod.farcaster.email.amazon.dev [10.0.34.15:2525] with esmtp (Farcaster) id e2d9920f-cfd7-43b6-8f8a-b111fb6b55e2; Tue, 12 Mar 2024 18:07:56 +0000 (UTC) X-Farcaster-Flow-ID: e2d9920f-cfd7-43b6-8f8a-b111fb6b55e2 Received: from EX19D007EUA002.ant.amazon.com (10.252.50.68) by EX19MTAEUB001.ant.amazon.com (10.252.51.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Tue, 12 Mar 2024 18:07:50 +0000 Received: from EX19MTAUWA001.ant.amazon.com (10.250.64.204) by EX19D007EUA002.ant.amazon.com (10.252.50.68) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Tue, 12 Mar 2024 18:07:50 +0000 Received: from HFA15-CG15235BS.amazon.com (10.85.143.174) by mail-relay.amazon.com (10.250.64.204) with Microsoft SMTP Server id 15.2.1258.28 via Frontend Transport; Tue, 12 Mar 2024 18:07:49 +0000 From: To: CC: , Shai Brandes Subject: [PATCH v4 12/31] net/ena/base: add completion descriptor corruption check Date: Tue, 12 Mar 2024 20:06:57 +0200 Message-ID: <20240312180716.8515-13-shaibran@amazon.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240312180716.8515-1-shaibran@amazon.com> References: <20240312180716.8515-1-shaibran@amazon.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Shai Brandes Adding a check of the MBZ (Must Be Zero) fields in the incoming tx and rx completion descriptors in order to identify corrupted descriptors. Signed-off-by: Shai Brandes Reviewed-by: Amit Bernstein --- drivers/net/ena/base/ena_eth_com.c | 13 +++++++++++-- drivers/net/ena/base/ena_eth_com.h | 14 +++++++++++++- 2 files changed, 24 insertions(+), 3 deletions(-) diff --git a/drivers/net/ena/base/ena_eth_com.c b/drivers/net/ena/base/ena_eth_com.c index 875d55b00d..58d1cc68d9 100644 --- a/drivers/net/ena/base/ena_eth_com.c +++ b/drivers/net/ena/base/ena_eth_com.c @@ -236,6 +236,7 @@ static int ena_com_cdesc_rx_pkt_get(struct ena_com_io_cq *io_cq, u16 *first_cdesc_idx, u16 *num_descs) { + struct ena_com_dev *dev = ena_com_io_cq_to_ena_dev(io_cq); u16 count = io_cq->cur_rx_pkt_cdesc_count, head_masked; struct ena_eth_io_rx_cdesc_base *cdesc; u32 last = 0; @@ -251,13 +252,21 @@ static int ena_com_cdesc_rx_pkt_get(struct ena_com_io_cq *io_cq, ena_com_cq_inc_head(io_cq); if (unlikely((status & ENA_ETH_IO_RX_CDESC_BASE_FIRST_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_FIRST_SHIFT && count != 0)) { - struct ena_com_dev *dev = ena_com_io_cq_to_ena_dev(io_cq); - ena_trc_err(dev, "First bit is on in descriptor #%d on q_id: %d, req_id: %u\n", count, io_cq->qid, cdesc->req_id); return ENA_COM_FAULT; } + + if (unlikely((status & (ENA_ETH_IO_RX_CDESC_BASE_MBZ7_MASK | + ENA_ETH_IO_RX_CDESC_BASE_MBZ17_MASK)) && + ena_com_get_cap(dev, ENA_ADMIN_CDESC_MBZ))) { + ena_trc_err(dev, + "Corrupted RX descriptor #%d on q_id: %d, req_id: %u\n", + count, io_cq->qid, cdesc->req_id); + return ENA_COM_FAULT; + } + count++; last = (status & ENA_ETH_IO_RX_CDESC_BASE_LAST_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_LAST_SHIFT; diff --git a/drivers/net/ena/base/ena_eth_com.h b/drivers/net/ena/base/ena_eth_com.h index 6a7c17f84f..2fac10e678 100644 --- a/drivers/net/ena/base/ena_eth_com.h +++ b/drivers/net/ena/base/ena_eth_com.h @@ -204,9 +204,11 @@ static inline void ena_com_cq_inc_head(struct ena_com_io_cq *io_cq) static inline int ena_com_tx_comp_req_id_get(struct ena_com_io_cq *io_cq, u16 *req_id) { + struct ena_com_dev *dev = ena_com_io_cq_to_ena_dev(io_cq); u8 expected_phase, cdesc_phase; struct ena_eth_io_tx_cdesc *cdesc; u16 masked_head; + u8 flags; masked_head = io_cq->head & (io_cq->q_depth - 1); expected_phase = io_cq->phase; @@ -215,14 +217,24 @@ static inline int ena_com_tx_comp_req_id_get(struct ena_com_io_cq *io_cq, ((uintptr_t)io_cq->cdesc_addr.virt_addr + (masked_head * io_cq->cdesc_entry_size_in_bytes)); + flags = READ_ONCE8(cdesc->flags); + /* When the current completion descriptor phase isn't the same as the * expected, it mean that the device still didn't update * this completion. */ - cdesc_phase = READ_ONCE8(cdesc->flags) & ENA_ETH_IO_TX_CDESC_PHASE_MASK; + cdesc_phase = flags & ENA_ETH_IO_TX_CDESC_PHASE_MASK; if (cdesc_phase != expected_phase) return ENA_COM_TRY_AGAIN; + if (unlikely((flags & ENA_ETH_IO_TX_CDESC_MBZ6_MASK) && + ena_com_get_cap(dev, ENA_ADMIN_CDESC_MBZ))) { + ena_trc_err(dev, + "Corrupted TX descriptor on q_id: %d, req_id: %u\n", + io_cq->qid, cdesc->req_id); + return ENA_COM_FAULT; + } + dma_rmb(); *req_id = READ_ONCE16(cdesc->req_id); From patchwork Tue Mar 12 18:06:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Brandes, Shai" X-Patchwork-Id: 138260 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9D7D043C94; Tue, 12 Mar 2024 19:08:38 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3981642E36; Tue, 12 Mar 2024 19:08:01 +0100 (CET) Received: from smtp-fw-80008.amazon.com (smtp-fw-80008.amazon.com [99.78.197.219]) by mails.dpdk.org (Postfix) with ESMTP id 1B99D42E34 for ; Tue, 12 Mar 2024 19:07:58 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.com; i=@amazon.com; q=dns/txt; s=amazon201209; t=1710266879; x=1741802879; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; 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Tue, 12 Mar 2024 18:07:53 +0000 Received: from EX19MTAUWA001.ant.amazon.com (10.250.64.204) by EX19D007EUA002.ant.amazon.com (10.252.50.68) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Tue, 12 Mar 2024 18:07:52 +0000 Received: from HFA15-CG15235BS.amazon.com (10.85.143.174) by mail-relay.amazon.com (10.250.64.204) with Microsoft SMTP Server id 15.2.1258.28 via Frontend Transport; Tue, 12 Mar 2024 18:07:51 +0000 From: To: CC: , Shai Brandes Subject: [PATCH v4 13/31] net/ena/base: malformed Tx descriptor error reason Date: Tue, 12 Mar 2024 20:06:58 +0200 Message-ID: <20240312180716.8515-14-shaibran@amazon.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240312180716.8515-1-shaibran@amazon.com> References: <20240312180716.8515-1-shaibran@amazon.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Shai Brandes Adding ENA_REGS_RESET_TX_DESCRIPTOR_MALFORMED to identify cases where the returned TX completion descriptors are corrupted. Signed-off-by: Shai Brandes Reviewed-by: Amit Bernstein --- drivers/net/ena/base/ena_defs/ena_regs_defs.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/net/ena/base/ena_defs/ena_regs_defs.h b/drivers/net/ena/base/ena_defs/ena_regs_defs.h index 6a33f74812..a94025dc77 100644 --- a/drivers/net/ena/base/ena_defs/ena_regs_defs.h +++ b/drivers/net/ena/base/ena_defs/ena_regs_defs.h @@ -23,6 +23,7 @@ enum ena_regs_reset_reason_types { ENA_REGS_RESET_MISS_INTERRUPT = 14, ENA_REGS_RESET_SUSPECTED_POLL_STARVATION = 15, ENA_REGS_RESET_RX_DESCRIPTOR_MALFORMED = 16, + ENA_REGS_RESET_TX_DESCRIPTOR_MALFORMED = 17, ENA_REGS_RESET_LAST, }; From patchwork Tue Mar 12 18:06:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Brandes, Shai" X-Patchwork-Id: 138269 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D040943C94; Tue, 12 Mar 2024 19:09:31 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 954B042E6F; Tue, 12 Mar 2024 19:08:13 +0100 (CET) Received: from smtp-fw-9105.amazon.com (smtp-fw-9105.amazon.com [207.171.188.204]) by mails.dpdk.org (Postfix) with ESMTP id 7C4A142E2A for ; Tue, 12 Mar 2024 19:08:09 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.com; i=@amazon.com; q=dns/txt; s=amazon201209; t=1710266889; x=1741802889; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=wg+kuFpAhOsMOiHCWL5UpR8Q3whikiP6EqMAEE3yDUA=; b=cO6U1NY0eXh0AYQuEC5dK5jf8B/Nh8jSur1WLU8uGN5muXuZwWkM9lu6 DOBfP9B2S5AG86Pp9Uv+ahXkuDco5IRgeL4nlBuUHNhLSOsMFtfWKZCjP Ld+5/NNEgGdaxMCJ3r1SuBjpD7ebC3DCW8SZ7HOLol7jA1fP8yB/D0DZT 4=; X-IronPort-AV: E=Sophos;i="6.07,119,1708387200"; d="scan'208";a="711121136" Received: from pdx4-co-svc-p1-lb2-vlan2.amazon.com (HELO smtpout.prod.us-west-2.prod.farcaster.email.amazon.dev) ([10.25.36.210]) by smtp-border-fw-9105.sea19.amazon.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Mar 2024 18:07:57 +0000 Received: from EX19MTAEUC001.ant.amazon.com [10.0.10.100:25396] by smtpin.naws.eu-west-1.prod.farcaster.email.amazon.dev [10.0.0.5:2525] with esmtp (Farcaster) id 73530508-3703-494a-bc3c-747ffcd93c52; Tue, 12 Mar 2024 18:07:56 +0000 (UTC) X-Farcaster-Flow-ID: 73530508-3703-494a-bc3c-747ffcd93c52 Received: from EX19D007EUA002.ant.amazon.com (10.252.50.68) by EX19MTAEUC001.ant.amazon.com (10.252.51.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Tue, 12 Mar 2024 18:07:55 +0000 Received: from EX19MTAUWA001.ant.amazon.com (10.250.64.204) by EX19D007EUA002.ant.amazon.com (10.252.50.68) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Tue, 12 Mar 2024 18:07:54 +0000 Received: from HFA15-CG15235BS.amazon.com (10.85.143.174) by mail-relay.amazon.com (10.250.64.204) with Microsoft SMTP Server id 15.2.1258.28 via Frontend Transport; Tue, 12 Mar 2024 18:07:53 +0000 From: To: CC: , Shai Brandes Subject: [PATCH v4 14/31] net/ena/base: phc feature modifications Date: Tue, 12 Mar 2024 20:06:59 +0200 Message-ID: <20240312180716.8515-15-shaibran@amazon.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240312180716.8515-1-shaibran@amazon.com> References: <20240312180716.8515-1-shaibran@amazon.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Shai Brandes 1. PHC algorithm is updated to support reading new PHC values. 2. Update default PHC expiration timeout. 3. Fix a theoretical PHC destroy race. 4. Adjust PHC for multiple devices. 5. PHC activation version check point. Signed-off-by: Shai Brandes Reviewed-by: Amit Bernstein --- drivers/net/ena/base/ena_com.c | 111 ++++++++++++------ drivers/net/ena/base/ena_com.h | 31 +++-- .../net/ena/base/ena_defs/ena_admin_defs.h | 45 +++++-- 3 files changed, 135 insertions(+), 52 deletions(-) diff --git a/drivers/net/ena/base/ena_com.c b/drivers/net/ena/base/ena_com.c index 31c37b0ab3..fb3ad27d0a 100644 --- a/drivers/net/ena/base/ena_com.c +++ b/drivers/net/ena/base/ena_com.c @@ -41,10 +41,12 @@ #define ENA_MAX_ADMIN_POLL_US 5000 /* PHC definitions */ -#define ENA_PHC_DEFAULT_EXPIRE_TIMEOUT_USEC 20 +#define ENA_PHC_DEFAULT_EXPIRE_TIMEOUT_USEC 10 #define ENA_PHC_DEFAULT_BLOCK_TIMEOUT_USEC 1000 -#define ENA_PHC_TIMESTAMP_ERROR 0xFFFFFFFFFFFFFFFF +#define ENA_PHC_MAX_ERROR_BOUND 0xFFFFFFFF #define ENA_PHC_REQ_ID_OFFSET 0xDEAD +#define ENA_PHC_ERROR_FLAGS (ENA_ADMIN_PHC_ERROR_FLAG_TIMESTAMP | \ + ENA_ADMIN_PHC_ERROR_FLAG_ERROR_BOUND) /*****************************************************************************/ /*****************************************************************************/ @@ -1778,16 +1780,21 @@ int ena_com_phc_config(struct ena_com_dev *ena_dev) struct ena_admin_set_feat_cmd set_feat_cmd; int ret = 0; - /* Get device PHC default configuration */ - ret = ena_com_get_feature(ena_dev, &get_feat_resp, ENA_ADMIN_PHC_CONFIG, 0); + /* Get default device PHC configuration */ + ret = ena_com_get_feature(ena_dev, + &get_feat_resp, + ENA_ADMIN_PHC_CONFIG, + ENA_ADMIN_PHC_FEATURE_VERSION_0); if (unlikely(ret)) { ena_trc_err(ena_dev, "Failed to get PHC feature configuration, error: %d\n", ret); return ret; } - /* Supporting only readless PHC retrieval */ - if (get_feat_resp.u.phc.type != ENA_ADMIN_PHC_TYPE_READLESS) { - ena_trc_err(ena_dev, "Unsupported PHC type, error: %d\n", ENA_COM_UNSUPPORTED); + /* Supporting only PHC V0 (readless mode with error bound) */ + if (get_feat_resp.u.phc.version != ENA_ADMIN_PHC_FEATURE_VERSION_0) { + ena_trc_err(ena_dev, "Unsupported PHC version (0x%X), error: %d\n", + get_feat_resp.u.phc.version, + ENA_COM_UNSUPPORTED); return ENA_COM_UNSUPPORTED; } @@ -1804,11 +1811,11 @@ int ena_com_phc_config(struct ena_com_dev *ena_dev) get_feat_resp.u.phc.block_timeout_usec : ENA_PHC_DEFAULT_BLOCK_TIMEOUT_USEC; - /* Sanity check - expire timeout must not be above skip timeout */ + /* Sanity check - expire timeout must not exceed block timeout */ if (phc->expire_timeout_usec > phc->block_timeout_usec) phc->expire_timeout_usec = phc->block_timeout_usec; - /* Prepare PHC feature command with PHC output address */ + /* Prepare PHC config feature command */ memset(&set_feat_cmd, 0x0, sizeof(set_feat_cmd)); set_feat_cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE; set_feat_cmd.feat_common.feature_id = ENA_ADMIN_PHC_CONFIG; @@ -1840,13 +1847,16 @@ int ena_com_phc_config(struct ena_com_dev *ena_dev) void ena_com_phc_destroy(struct ena_com_dev *ena_dev) { struct ena_com_phc_info *phc = &ena_dev->phc; - - phc->active = false; + unsigned long flags = 0; /* In case PHC is not supported by the device, silently exiting */ if (!phc->virt_addr) return; + ENA_SPINLOCK_LOCK(phc->lock, flags); + phc->active = false; + ENA_SPINLOCK_UNLOCK(phc->lock, flags); + ENA_MEM_FREE_COHERENT(ena_dev->dmadev, sizeof(*phc->virt_addr), phc->virt_addr, @@ -1857,15 +1867,14 @@ void ena_com_phc_destroy(struct ena_com_dev *ena_dev) ENA_SPINLOCK_DESTROY(phc->lock); } -int ena_com_phc_get(struct ena_com_dev *ena_dev, u64 *timestamp) +int ena_com_phc_get_timestamp(struct ena_com_dev *ena_dev, u64 *timestamp) { volatile struct ena_admin_phc_resp *read_resp = ena_dev->phc.virt_addr; + const ena_time_high_res_t zero_system_time = ENA_TIME_INIT_HIGH_RES(); struct ena_com_phc_info *phc = &ena_dev->phc; - ena_time_high_res_t initial_time = ENA_TIME_INIT_HIGH_RES(); - static ena_time_high_res_t start_time; - unsigned long flags = 0; ena_time_high_res_t expire_time; ena_time_high_res_t block_time; + unsigned long flags = 0; int ret = ENA_COM_OK; if (!phc->active) { @@ -1876,9 +1885,10 @@ int ena_com_phc_get(struct ena_com_dev *ena_dev, u64 *timestamp) ENA_SPINLOCK_LOCK(phc->lock, flags); /* Check if PHC is in blocked state */ - if (unlikely(ENA_TIME_COMPARE_HIGH_RES(start_time, initial_time))) { + if (unlikely(ENA_TIME_COMPARE_HIGH_RES(phc->system_time, zero_system_time))) { /* Check if blocking time expired */ - block_time = ENA_GET_SYSTEM_TIMEOUT_HIGH_RES(start_time, phc->block_timeout_usec); + block_time = ENA_GET_SYSTEM_TIMEOUT_HIGH_RES(phc->system_time, + phc->block_timeout_usec); if (!ENA_TIME_EXPIRE_HIGH_RES(block_time)) { /* PHC is still in blocked state, skip PHC request */ phc->stats.phc_skp++; @@ -1886,22 +1896,23 @@ int ena_com_phc_get(struct ena_com_dev *ena_dev, u64 *timestamp) goto skip; } - /* PHC is in active state, update statistics according to req_id and timestamp */ + /* PHC is in active state, update statistics according to req_id and error_flags */ if ((READ_ONCE16(read_resp->req_id) != phc->req_id) || - read_resp->timestamp == ENA_PHC_TIMESTAMP_ERROR) + (read_resp->error_flags & ENA_PHC_ERROR_FLAGS)) { /* Device didn't update req_id during blocking time or timestamp is invalid, * this indicates on a device error */ phc->stats.phc_err++; - else + } else { /* Device updated req_id during blocking time with valid timestamp */ phc->stats.phc_exp++; + } } /* Setting relative timeouts */ - start_time = ENA_GET_SYSTEM_TIME_HIGH_RES(); - block_time = ENA_GET_SYSTEM_TIMEOUT_HIGH_RES(start_time, phc->block_timeout_usec); - expire_time = ENA_GET_SYSTEM_TIMEOUT_HIGH_RES(start_time, phc->expire_timeout_usec); + phc->system_time = ENA_GET_SYSTEM_TIME_HIGH_RES(); + block_time = ENA_GET_SYSTEM_TIMEOUT_HIGH_RES(phc->system_time, phc->block_timeout_usec); + expire_time = ENA_GET_SYSTEM_TIMEOUT_HIGH_RES(phc->system_time, phc->expire_timeout_usec); /* We expect the device to return this req_id once the new PHC timestamp is updated */ phc->req_id++; @@ -1918,35 +1929,45 @@ int ena_com_phc_get(struct ena_com_dev *ena_dev, u64 *timestamp) while (1) { if (unlikely(ENA_TIME_EXPIRE_HIGH_RES(expire_time))) { /* Gave up waiting for updated req_id, PHC enters into blocked state until - * passing blocking time + * passing blocking time, during this time any get PHC timestamp or + * error bound requests will fail with device busy error */ + phc->error_bound = ENA_PHC_MAX_ERROR_BOUND; ret = ENA_COM_DEVICE_BUSY; break; } /* Check if req_id was updated by the device */ if (READ_ONCE16(read_resp->req_id) != phc->req_id) { - /* req_id was not updated by the device, check again on next loop */ + /* req_id was not updated by the device yet, check again on next loop */ continue; } - /* req_id was updated which indicates that PHC timestamp was updated too */ - *timestamp = read_resp->timestamp; - - /* PHC timestamp validty check */ - if (unlikely(*timestamp == ENA_PHC_TIMESTAMP_ERROR)) { - /* Retrieved invalid PHC timestamp, PHC enters into blocked state until - * passing blocking time + /* req_id was updated by the device which indicates that PHC timestamp, error_bound + * and error_flags are updated too, checking errors before retrieving timestamp and + * error_bound values + */ + if (unlikely(read_resp->error_flags & ENA_PHC_ERROR_FLAGS)) { + /* Retrieved timestamp or error bound errors, PHC enters into blocked state + * until passing blocking time, during this time any get PHC timestamp or + * error bound requests will fail with device busy error */ + phc->error_bound = ENA_PHC_MAX_ERROR_BOUND; ret = ENA_COM_DEVICE_BUSY; break; } - /* Retrieved valid PHC timestamp */ + /* PHC timestamp value is returned to the caller */ + *timestamp = read_resp->timestamp; + + /* Error bound value is cached for future retrieval by caller */ + phc->error_bound = read_resp->error_bound; + + /* Update statistic on valid PHC timestamp retrieval */ phc->stats.phc_cnt++; /* This indicates PHC state is active */ - start_time = initial_time; + phc->system_time = zero_system_time; break; } @@ -1956,6 +1977,24 @@ int ena_com_phc_get(struct ena_com_dev *ena_dev, u64 *timestamp) return ret; } +int ena_com_phc_get_error_bound(struct ena_com_dev *ena_dev, u32 *error_bound) +{ + struct ena_com_phc_info *phc = &ena_dev->phc; + u32 local_error_bound = phc->error_bound; + + if (!phc->active) { + ena_trc_err(ena_dev, "PHC feature is not active in the device\n"); + return ENA_COM_UNSUPPORTED; + } + + if (local_error_bound == ENA_PHC_MAX_ERROR_BOUND) + return ENA_COM_DEVICE_BUSY; + + *error_bound = local_error_bound; + + return ENA_COM_OK; +} + int ena_com_mmio_reg_read_request_init(struct ena_com_dev *ena_dev) { struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read; @@ -2453,9 +2492,9 @@ int ena_com_dev_reset(struct ena_com_dev *ena_dev, reset_val |= reset_reason_lsb << ENA_REGS_DEV_CTL_RESET_REASON_SHIFT; - if (ena_com_get_cap(ena_dev, ENA_ADMIN_EXTENDED_RESET_REASONS)) { + if (ena_com_get_cap(ena_dev, ENA_ADMIN_EXTENDED_RESET_REASONS)) reset_val |= reset_reason_msb << ENA_REGS_DEV_CTL_RESET_REASON_EXT_SHIFT; - } else if (reset_reason_msb) { + else if (reset_reason_msb) { /* In case the device does not support intended * extended reset reason fallback to generic */ diff --git a/drivers/net/ena/base/ena_com.h b/drivers/net/ena/base/ena_com.h index cd054595d7..c62016cc06 100644 --- a/drivers/net/ena/base/ena_com.h +++ b/drivers/net/ena/base/ena_com.h @@ -274,6 +274,9 @@ struct ena_com_phc_info { /* PHC shared memory - virtual address */ struct ena_admin_phc_resp *virt_addr; + /* System time of last PHC request */ + ena_time_high_res_t system_time; + /* Spin lock to ensure a single outstanding PHC read */ ena_spinlock_t lock; @@ -293,17 +296,20 @@ struct ena_com_phc_info { */ u32 block_timeout_usec; + /* PHC shared memory - physical address */ + dma_addr_t phys_addr; + + /* PHC shared memory handle */ + ena_mem_handle_t mem_handle; + + /* Cached error bound per timestamp sample */ + u32 error_bound; + /* Request id sent to the device */ u16 req_id; /* True if PHC is active in the device */ bool active; - - /* PHC shared memory - memory handle */ - ena_mem_handle_t mem_handle; - - /* PHC shared memory - physical address */ - dma_addr_t phys_addr; }; struct ena_rss { @@ -468,12 +474,19 @@ int ena_com_phc_config(struct ena_com_dev *ena_dev); */ void ena_com_phc_destroy(struct ena_com_dev *ena_dev); -/* ena_com_phc_get - Retrieve PHC timestamp +/* ena_com_phc_get_timestamp - Retrieve PHC timestamp + * @ena_dev: ENA communication layer struct + * @timestamp: Retrieved PHC timestamp + * @return - 0 on success, negative value on failure + */ +int ena_com_phc_get_timestamp(struct ena_com_dev *ena_dev, u64 *timestamp); + +/* ena_com_phc_get_error_bound - Retrieve cached PHC error bound * @ena_dev: ENA communication layer struct - * @timestamp: Retrieve PHC timestamp + * @error_bound: Cached PHC error bound * @return - 0 on success, negative value on failure */ -int ena_com_phc_get(struct ena_com_dev *ena_dev, u64 *timestamp); +int ena_com_phc_get_error_bound(struct ena_com_dev *ena_dev, u32 *error_bound); /* ena_com_set_mmio_read_mode - Enable/disable the indirect mmio reg read mechanism * @ena_dev: ENA communication layer struct diff --git a/drivers/net/ena/base/ena_defs/ena_admin_defs.h b/drivers/net/ena/base/ena_defs/ena_admin_defs.h index 438e4a1085..ce8a26721e 100644 --- a/drivers/net/ena/base/ena_defs/ena_admin_defs.h +++ b/drivers/net/ena/base/ena_defs/ena_admin_defs.h @@ -144,8 +144,14 @@ enum ena_admin_get_stats_scope { ENA_ADMIN_ETH_TRAFFIC = 1, }; -enum ena_admin_get_phc_type { - ENA_ADMIN_PHC_TYPE_READLESS = 0, +enum ena_admin_phc_feature_version { + /* Readless with error_bound */ + ENA_ADMIN_PHC_FEATURE_VERSION_0 = 0, +}; + +enum ena_admin_phc_error_flags { + ENA_ADMIN_PHC_ERROR_FLAG_TIMESTAMP = BIT(0), + ENA_ADMIN_PHC_ERROR_FLAG_ERROR_BOUND = BIT(1), }; /* ENA SRD configuration for ENI */ @@ -987,7 +993,8 @@ struct ena_admin_host_info { * 5 : reserved * 6 : rx_page_reuse * 7 : tx_ipv6_csum_offload - * 31:8 : reserved + * 8 : phc + * 31:9 : reserved */ uint32_t driver_supported_features; }; @@ -1073,10 +1080,10 @@ struct ena_admin_queue_ext_feature_desc { }; struct ena_admin_feature_phc_desc { - /* PHC type as defined in enum ena_admin_get_phc_type, - * used only for GET command. + /* PHC version as defined in enum ena_admin_phc_feature_version, + * used only for GET command as max supported PHC version by the device. */ - uint8_t type; + uint8_t version; /* Reserved - MBZ */ uint8_t reserved1[3]; @@ -1272,13 +1279,23 @@ struct ena_admin_ena_mmio_req_read_less_resp { }; struct ena_admin_phc_resp { + /* Request Id, received from DB register */ uint16_t req_id; uint8_t reserved1[6]; + /* PHC timestamp (nsec) */ uint64_t timestamp; - uint8_t reserved2[48]; + uint8_t reserved2[8]; + + /* Timestamp error limit (nsec) */ + uint32_t error_bound; + + /* Bit field of enum ena_admin_phc_error_flags */ + uint32_t error_flags; + + uint8_t reserved3[32]; }; /* aq_common_desc */ @@ -1381,6 +1398,8 @@ struct ena_admin_phc_resp { #define ENA_ADMIN_HOST_INFO_RX_PAGE_REUSE_MASK BIT(6) #define ENA_ADMIN_HOST_INFO_TX_IPV6_CSUM_OFFLOAD_SHIFT 7 #define ENA_ADMIN_HOST_INFO_TX_IPV6_CSUM_OFFLOAD_MASK BIT(7) +#define ENA_ADMIN_HOST_INFO_PHC_SHIFT 8 +#define ENA_ADMIN_HOST_INFO_PHC_MASK BIT(8) /* feature_rss_ind_table */ #define ENA_ADMIN_FEATURE_RSS_IND_TABLE_ONE_ENTRY_UPDATE_MASK BIT(0) @@ -1879,6 +1898,18 @@ static inline void set_ena_admin_feature_rss_ind_table_one_entry_update(struct e p->flags |= val & ENA_ADMIN_FEATURE_RSS_IND_TABLE_ONE_ENTRY_UPDATE_MASK; } +static inline uint32_t get_ena_admin_host_info_phc(const struct ena_admin_host_info *p) +{ + return (p->driver_supported_features & + ENA_ADMIN_HOST_INFO_PHC_MASK) >> ENA_ADMIN_HOST_INFO_PHC_SHIFT; +} + +static inline void set_ena_admin_host_info_phc(struct ena_admin_host_info *p, uint32_t val) +{ + p->driver_supported_features |= (val << ENA_ADMIN_HOST_INFO_PHC_SHIFT) & + ENA_ADMIN_HOST_INFO_PHC_MASK; +} + static inline uint8_t get_ena_admin_aenq_common_desc_phase(const struct ena_admin_aenq_common_desc *p) { return p->flags & ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK; From patchwork Tue Mar 12 18:07:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Brandes, Shai" X-Patchwork-Id: 138264 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 550B843C94; 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12 Mar 2024 18:07:59 +0000 Received: from EX19MTAEUB001.ant.amazon.com [10.0.10.100:58120] by smtpin.naws.eu-west-1.prod.farcaster.email.amazon.dev [10.0.39.71:2525] with esmtp (Farcaster) id e4a0a989-9a3a-41f7-b820-943df7057a5e; Tue, 12 Mar 2024 18:07:58 +0000 (UTC) X-Farcaster-Flow-ID: e4a0a989-9a3a-41f7-b820-943df7057a5e Received: from EX19D007EUB002.ant.amazon.com (10.252.51.117) by EX19MTAEUB001.ant.amazon.com (10.252.51.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Tue, 12 Mar 2024 18:07:58 +0000 Received: from EX19MTAUWA001.ant.amazon.com (10.250.64.204) by EX19D007EUB002.ant.amazon.com (10.252.51.117) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Tue, 12 Mar 2024 18:07:57 +0000 Received: from HFA15-CG15235BS.amazon.com (10.85.143.174) by mail-relay.amazon.com (10.250.64.204) with Microsoft SMTP Server id 15.2.1258.28 via Frontend Transport; Tue, 12 Mar 2024 18:07:55 +0000 From: To: CC: , Shai Brandes Subject: [PATCH v4 15/31] net/ena/base: restructure interrupt handling Date: Tue, 12 Mar 2024 20:07:00 +0200 Message-ID: <20240312180716.8515-16-shaibran@amazon.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240312180716.8515-1-shaibran@amazon.com> References: <20240312180716.8515-1-shaibran@amazon.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Shai Brandes When invoking an admin command, in interrupt mode, if the interrupt is received after timeout and also after the calling function finished running, the response will be written into a memory that is no longer valid. Signed-off-by: Shai Brandes Reviewed-by: Amit Bernstein --- drivers/net/ena/base/ena_com.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/net/ena/base/ena_com.c b/drivers/net/ena/base/ena_com.c index fb3ad27d0a..a0c88b1a0e 100644 --- a/drivers/net/ena/base/ena_com.c +++ b/drivers/net/ena/base/ena_com.c @@ -181,6 +181,7 @@ static int ena_com_admin_init_aenq(struct ena_com_dev *ena_dev, static void comp_ctxt_release(struct ena_com_admin_queue *queue, struct ena_comp_ctx *comp_ctx) { + comp_ctx->user_cqe = NULL; comp_ctx->occupied = false; ATOMIC32_DEC(&queue->outstanding_cmds); } @@ -474,6 +475,9 @@ static void ena_com_handle_single_admin_completion(struct ena_com_admin_queue *a return; } + if (!comp_ctx->occupied) + return; + comp_ctx->status = ENA_CMD_COMPLETED; comp_ctx->comp_status = cqe->acq_common_descriptor.status; From patchwork Tue Mar 12 18:07:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Brandes, Shai" X-Patchwork-Id: 138267 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 6C22043C94; Tue, 12 Mar 2024 19:09:20 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id BAF5442E5B; Tue, 12 Mar 2024 19:08:10 +0100 (CET) Received: from smtp-fw-9105.amazon.com (smtp-fw-9105.amazon.com [207.171.188.204]) by mails.dpdk.org (Postfix) with ESMTP id 2038442E55 for ; Tue, 12 Mar 2024 19:08:07 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.com; i=@amazon.com; q=dns/txt; s=amazon201209; t=1710266888; x=1741802888; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=UR6rZ8hd7glM83SlM3yKVHaQrZ5PbZYuOirsSYBbpXM=; b=s2KKHXS87nqyxPjarsjPKuK+v8xHSTWaw+3z+wAB43gJO5UwEL7diV2v ct4k4NQxSsiXlWAWJ6PdLEhoKNHtGINxtvGR4T8ASfBtwZlCD1KGbtl2v Ucbv++kZDqKkvbOJaREeDVUX6R7hQi1jvhNL9qER8feK9io8/R9/ZSY5H U=; X-IronPort-AV: E=Sophos;i="6.07,119,1708387200"; d="scan'208";a="711121165" Received: from pdx4-co-svc-p1-lb2-vlan2.amazon.com (HELO smtpout.prod.us-east-1.prod.farcaster.email.amazon.dev) ([10.25.36.210]) by smtp-border-fw-9105.sea19.amazon.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Mar 2024 18:08:01 +0000 Received: from EX19MTAEUB002.ant.amazon.com [10.0.43.254:36534] by smtpin.naws.eu-west-1.prod.farcaster.email.amazon.dev [10.0.0.5:2525] with esmtp (Farcaster) id fa2566dc-a365-4a07-afce-c1b4e9256e2d; Tue, 12 Mar 2024 18:08:00 +0000 (UTC) X-Farcaster-Flow-ID: fa2566dc-a365-4a07-afce-c1b4e9256e2d Received: from EX19D007EUB002.ant.amazon.com (10.252.51.117) by EX19MTAEUB002.ant.amazon.com (10.252.51.79) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Tue, 12 Mar 2024 18:08:00 +0000 Received: from EX19MTAUWA001.ant.amazon.com (10.250.64.204) by EX19D007EUB002.ant.amazon.com (10.252.51.117) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Tue, 12 Mar 2024 18:07:59 +0000 Received: from HFA15-CG15235BS.amazon.com (10.85.143.174) by mail-relay.amazon.com (10.250.64.204) with Microsoft SMTP Server id 15.2.1258.28 via Frontend Transport; Tue, 12 Mar 2024 18:07:58 +0000 From: To: CC: , Shai Brandes Subject: [PATCH v4 16/31] net/ena/base: add unlikely to error checks Date: Tue, 12 Mar 2024 20:07:01 +0200 Message-ID: <20240312180716.8515-17-shaibran@amazon.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240312180716.8515-1-shaibran@amazon.com> References: <20240312180716.8515-1-shaibran@amazon.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Shai Brandes The unlikely mechanism is used to reduce pipe flush, caused by a wrong branch prediction. Moreover, it increases readability by wrapping unexpected errors. This commit adds unlikely to error checks that are unlikely to happen. Signed-off-by: Shai Brandes Reviewed-by: Amit Bernstein --- drivers/net/ena/base/ena_com.c | 56 +++++++++++++++--------------- drivers/net/ena/base/ena_eth_com.c | 2 +- 2 files changed, 29 insertions(+), 29 deletions(-) diff --git a/drivers/net/ena/base/ena_com.c b/drivers/net/ena/base/ena_com.c index a0c88b1a0e..d2de5e172d 100644 --- a/drivers/net/ena/base/ena_com.c +++ b/drivers/net/ena/base/ena_com.c @@ -79,7 +79,7 @@ static int ena_com_mem_addr_set(struct ena_com_dev *ena_dev, struct ena_common_mem_addr *ena_addr, dma_addr_t addr) { - if ((addr & GENMASK_ULL(ena_dev->dma_addr_bits - 1, 0)) != addr) { + if (unlikely((addr & GENMASK_ULL(ena_dev->dma_addr_bits - 1, 0)) != addr)) { ena_trc_err(ena_dev, "DMA address has more bits than the device supports\n"); return ENA_COM_INVAL; } @@ -99,7 +99,7 @@ static int ena_com_admin_init_sq(struct ena_com_admin_queue *admin_queue) ENA_MEM_ALLOC_COHERENT(admin_queue->q_dmadev, size, sq->entries, sq->dma_addr, sq->mem_handle); - if (!sq->entries) { + if (unlikely(!sq->entries)) { ena_trc_err(ena_dev, "Memory allocation failed\n"); return ENA_COM_NO_MEM; } @@ -122,7 +122,7 @@ static int ena_com_admin_init_cq(struct ena_com_admin_queue *admin_queue) ENA_MEM_ALLOC_COHERENT(admin_queue->q_dmadev, size, cq->entries, cq->dma_addr, cq->mem_handle); - if (!cq->entries) { + if (unlikely(!cq->entries)) { ena_trc_err(ena_dev, "Memory allocation failed\n"); return ENA_COM_NO_MEM; } @@ -147,7 +147,7 @@ static int ena_com_admin_init_aenq(struct ena_com_dev *ena_dev, aenq->dma_addr, aenq->mem_handle); - if (!aenq->entries) { + if (unlikely(!aenq->entries)) { ena_trc_err(ena_dev, "Memory allocation failed\n"); return ENA_COM_NO_MEM; } @@ -233,7 +233,7 @@ static struct ena_comp_ctx *__ena_com_submit_admin_cmd(struct ena_com_admin_queu /* In case of queue FULL */ cnt = (u16)ATOMIC32_READ(&admin_queue->outstanding_cmds); - if (cnt >= admin_queue->q_depth) { + if (unlikely(cnt >= admin_queue->q_depth)) { ena_trc_dbg(admin_queue->ena_dev, "Admin queue is full.\n"); admin_queue->stats.out_of_space++; return ERR_PTR(ENA_COM_NO_SPACE); @@ -357,7 +357,7 @@ static int ena_com_init_io_sq(struct ena_com_dev *ena_dev, io_sq->desc_addr.mem_handle); } - if (!io_sq->desc_addr.virt_addr) { + if (unlikely(!io_sq->desc_addr.virt_addr)) { ena_trc_err(ena_dev, "Memory allocation failed\n"); return ENA_COM_NO_MEM; } @@ -382,7 +382,7 @@ static int ena_com_init_io_sq(struct ena_com_dev *ena_dev, if (!io_sq->bounce_buf_ctrl.base_buffer) io_sq->bounce_buf_ctrl.base_buffer = ENA_MEM_ALLOC(ena_dev->dmadev, size); - if (!io_sq->bounce_buf_ctrl.base_buffer) { + if (unlikely(!io_sq->bounce_buf_ctrl.base_buffer)) { ena_trc_err(ena_dev, "Bounce buffer memory allocation failed\n"); return ENA_COM_NO_MEM; } @@ -447,7 +447,7 @@ static int ena_com_init_io_cq(struct ena_com_dev *ena_dev, ENA_CDESC_RING_SIZE_ALIGNMENT); } - if (!io_cq->cdesc_addr.virt_addr) { + if (unlikely(!io_cq->cdesc_addr.virt_addr)) { ena_trc_err(ena_dev, "Memory allocation failed\n"); return ENA_COM_NO_MEM; } @@ -577,7 +577,7 @@ static int ena_com_wait_and_process_admin_cq_polling(struct ena_comp_ctx *comp_c if (comp_ctx->status != ENA_CMD_SUBMITTED) break; - if (ENA_TIME_EXPIRE(timeout)) { + if (unlikely(ENA_TIME_EXPIRE(timeout))) { ena_trc_err(admin_queue->ena_dev, "Wait for completion (polling) timeout\n"); /* ENA didn't have any completion */ @@ -776,7 +776,7 @@ static int ena_com_config_llq_info(struct ena_com_dev *ena_dev, llq_default_cfg->llq_ring_entry_size_value; rc = ena_com_set_llq(ena_dev); - if (rc) + if (unlikely(rc)) ena_trc_err(ena_dev, "Cannot set LLQ configuration: %d\n", rc); return rc; @@ -882,7 +882,7 @@ static u32 ena_com_reg_bar_read32(struct ena_com_dev *ena_dev, u16 offset) goto err; } - if (read_resp->reg_off != offset) { + if (unlikely(read_resp->reg_off != offset)) { ena_trc_err(ena_dev, "Read failure: wrong offset provided\n"); ret = ENA_MMIO_READ_TIMEOUT; } else { @@ -1006,7 +1006,7 @@ static int wait_for_reset_state(struct ena_com_dev *ena_dev, u32 timeout, exp_state) return 0; - if (ENA_TIME_EXPIRE(timeout_stamp)) + if (unlikely(ENA_TIME_EXPIRE(timeout_stamp))) return ENA_COM_TIMER_EXPIRED; ena_delay_exponential_backoff_us(exp++, ena_dev->ena_min_poll_delay_us); @@ -1467,7 +1467,7 @@ int ena_com_get_io_handlers(struct ena_com_dev *ena_dev, u16 qid, struct ena_com_io_sq **io_sq, struct ena_com_io_cq **io_cq) { - if (qid >= ENA_TOTAL_NUM_QUEUES) { + if (unlikely(qid >= ENA_TOTAL_NUM_QUEUES)) { ena_trc_err(ena_dev, "Invalid queue number %d but the max is %d\n", qid, ENA_TOTAL_NUM_QUEUES); return ENA_COM_INVAL; @@ -1575,7 +1575,7 @@ int ena_com_set_aenq_config(struct ena_com_dev *ena_dev, u32 groups_flag) int ret; ret = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_AENQ_CONFIG, 0); - if (ret) { + if (unlikely(ret)) { ena_trc_info(ena_dev, "Can't get aenq configuration\n"); return ret; } @@ -1622,7 +1622,7 @@ int ena_com_get_dma_width(struct ena_com_dev *ena_dev) ena_trc_dbg(ena_dev, "ENA dma width: %d\n", width); - if ((width < 32) || width > ENA_MAX_PHYS_ADDR_SIZE_BITS) { + if (unlikely(width < 32 || width > ENA_MAX_PHYS_ADDR_SIZE_BITS)) { ena_trc_err(ena_dev, "DMA width illegal value: %d\n", width); return ENA_COM_INVAL; } @@ -2092,15 +2092,15 @@ int ena_com_admin_init(struct ena_com_dev *ena_dev, ENA_SPINLOCK_INIT(admin_queue->q_lock); ret = ena_com_init_comp_ctxt(admin_queue); - if (ret) + if (unlikely(ret)) goto error; ret = ena_com_admin_init_sq(admin_queue); - if (ret) + if (unlikely(ret)) goto error; ret = ena_com_admin_init_cq(admin_queue); - if (ret) + if (unlikely(ret)) goto error; admin_queue->sq.db_addr = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar + @@ -2133,7 +2133,7 @@ int ena_com_admin_init(struct ena_com_dev *ena_dev, ENA_REG_WRITE32(ena_dev->bus, aq_caps, ena_dev->reg_bar + ENA_REGS_AQ_CAPS_OFF); ENA_REG_WRITE32(ena_dev->bus, acq_caps, ena_dev->reg_bar + ENA_REGS_ACQ_CAPS_OFF); ret = ena_com_admin_init_aenq(ena_dev, aenq_handlers); - if (ret) + if (unlikely(ret)) goto error; admin_queue->ena_dev = ena_dev; @@ -2153,7 +2153,7 @@ int ena_com_create_io_queue(struct ena_com_dev *ena_dev, struct ena_com_io_cq *io_cq; int ret; - if (ctx->qid >= ENA_TOTAL_NUM_QUEUES) { + if (unlikely(ctx->qid >= ENA_TOTAL_NUM_QUEUES)) { ena_trc_err(ena_dev, "Qid (%d) is bigger than max num of queues (%d)\n", ctx->qid, ENA_TOTAL_NUM_QUEUES); return ENA_COM_INVAL; @@ -2184,18 +2184,18 @@ int ena_com_create_io_queue(struct ena_com_dev *ena_dev, ENA_MIN32(ena_dev->tx_max_header_size, SZ_256); ret = ena_com_init_io_sq(ena_dev, ctx, io_sq); - if (ret) + if (unlikely(ret)) goto error; ret = ena_com_init_io_cq(ena_dev, ctx, io_cq); - if (ret) + if (unlikely(ret)) goto error; ret = ena_com_create_io_cq(ena_dev, io_cq); - if (ret) + if (unlikely(ret)) goto error; ret = ena_com_create_io_sq(ena_dev, io_sq, io_cq->idx); - if (ret) + if (unlikely(ret)) goto destroy_io_cq; return 0; @@ -2212,7 +2212,7 @@ void ena_com_destroy_io_queue(struct ena_com_dev *ena_dev, u16 qid) struct ena_com_io_sq *io_sq; struct ena_com_io_cq *io_cq; - if (qid >= ENA_TOTAL_NUM_QUEUES) { + if (unlikely(qid >= ENA_TOTAL_NUM_QUEUES)) { ena_trc_err(ena_dev, "Qid (%d) is bigger than max num of queues (%d)\n", qid, ENA_TOTAL_NUM_QUEUES); return; @@ -2513,7 +2513,7 @@ int ena_com_dev_reset(struct ena_com_dev *ena_dev, rc = wait_for_reset_state(ena_dev, timeout, ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK); - if (rc != 0) { + if (unlikely(rc)) { ena_trc_err(ena_dev, "Reset indication didn't turn on\n"); return rc; } @@ -2521,7 +2521,7 @@ int ena_com_dev_reset(struct ena_com_dev *ena_dev, /* reset done */ ENA_REG_WRITE32(ena_dev->bus, 0, ena_dev->reg_bar + ENA_REGS_DEV_CTL_OFF); rc = wait_for_reset_state(ena_dev, timeout, 0); - if (rc != 0) { + if (unlikely(rc)) { ena_trc_err(ena_dev, "Reset indication didn't turn off\n"); return rc; } @@ -3383,7 +3383,7 @@ int ena_com_config_dev_mode(struct ena_com_dev *ena_dev, } rc = ena_com_config_llq_info(ena_dev, llq_features, llq_default_cfg); - if (rc) + if (unlikely(rc)) return rc; ena_dev->tx_max_header_size = llq_info->desc_list_entry_size - diff --git a/drivers/net/ena/base/ena_eth_com.c b/drivers/net/ena/base/ena_eth_com.c index 58d1cc68d9..f672df1001 100644 --- a/drivers/net/ena/base/ena_eth_com.c +++ b/drivers/net/ena/base/ena_eth_com.c @@ -454,7 +454,7 @@ int ena_com_prepare_tx(struct ena_com_io_sq *io_sq, /* If the caller doesn't want to send packets */ if (unlikely(!num_bufs && !header_len)) { rc = ena_com_close_bounce_buffer(io_sq); - if (rc) + if (unlikely(rc)) ena_trc_err(ena_com_io_sq_to_ena_dev(io_sq), "Failed to write buffers to LLQ\n"); *nb_hw_desc = io_sq->tail - start_tail; From patchwork Tue Mar 12 18:07:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Brandes, Shai" X-Patchwork-Id: 138265 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 865B943C94; Tue, 12 Mar 2024 19:09:09 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 7EA8B42E50; Tue, 12 Mar 2024 19:08:07 +0100 (CET) Received: from smtp-fw-6002.amazon.com (smtp-fw-6002.amazon.com [52.95.49.90]) by mails.dpdk.org (Postfix) with ESMTP id 6040542E34 for ; Tue, 12 Mar 2024 19:08:05 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.com; i=@amazon.com; q=dns/txt; s=amazon201209; t=1710266886; x=1741802886; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=0zCbWVvOGHHb6r+WZu6EBRMUKTe3CX0M4Z1LFrPpkMg=; b=uy4b62wdoE0ulWpC6wQr5l1jRLecJ0Srd9+zLZ8VjCHBqdwjuRI+JtmA 3Em+kN/Jm92bIpHFr+OaWSiIKEGJu0frrs1ABEPbbpXLqSGV2xm/j8DZh SpBoFi1xrw9ehyhpOBQOXtKhvh1bUYwlArBBHSHXCqtRCiv511D52ft9t k=; X-IronPort-AV: E=Sophos;i="6.07,119,1708387200"; d="scan'208";a="392781641" Received: from iad12-co-svc-p1-lb1-vlan3.amazon.com (HELO smtpout.prod.us-west-2.prod.farcaster.email.amazon.dev) ([10.43.8.6]) by smtp-border-fw-6002.iad6.amazon.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Mar 2024 18:08:04 +0000 Received: from EX19MTAEUC001.ant.amazon.com [10.0.10.100:59928] by smtpin.naws.eu-west-1.prod.farcaster.email.amazon.dev [10.0.34.15:2525] with esmtp (Farcaster) id 08eeda93-8290-4e4e-b05e-6fad42f600ab; Tue, 12 Mar 2024 18:08:02 +0000 (UTC) X-Farcaster-Flow-ID: 08eeda93-8290-4e4e-b05e-6fad42f600ab Received: from EX19D007EUA001.ant.amazon.com (10.252.50.133) by EX19MTAEUC001.ant.amazon.com (10.252.51.155) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Tue, 12 Mar 2024 18:08:02 +0000 Received: from EX19MTAUWA001.ant.amazon.com (10.250.64.204) by EX19D007EUA001.ant.amazon.com (10.252.50.133) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Tue, 12 Mar 2024 18:08:01 +0000 Received: from HFA15-CG15235BS.amazon.com (10.85.143.174) by mail-relay.amazon.com (10.250.64.204) with Microsoft SMTP Server id 15.2.1258.28 via Frontend Transport; Tue, 12 Mar 2024 18:08:00 +0000 From: To: CC: , Shai Brandes Subject: [PATCH v4 17/31] net/ena/base: missing admin interrupt reset reason Date: Tue, 12 Mar 2024 20:07:02 +0200 Message-ID: <20240312180716.8515-18-shaibran@amazon.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240312180716.8515-1-shaibran@amazon.com> References: <20240312180716.8515-1-shaibran@amazon.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Shai Brandes There can be cases when we trigger reset if an admin interrupt is missing. In order to identify this use-case specifically, this commit adds a new reset reason. Signed-off-by: Shai Brandes Reviewed-by: Amit Bernstein --- drivers/net/ena/base/ena_com.c | 2 ++ drivers/net/ena/base/ena_com.h | 12 ++++++++++++ drivers/net/ena/base/ena_defs/ena_regs_defs.h | 1 + 3 files changed, 15 insertions(+) diff --git a/drivers/net/ena/base/ena_com.c b/drivers/net/ena/base/ena_com.c index d2de5e172d..8e9c112715 100644 --- a/drivers/net/ena/base/ena_com.c +++ b/drivers/net/ena/base/ena_com.c @@ -803,6 +803,7 @@ static int ena_com_wait_and_process_admin_cq_interrupts(struct ena_comp_ctx *com ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags); if (comp_ctx->status == ENA_CMD_COMPLETED) { + admin_queue->is_missing_admin_interrupt = true; ena_trc_err(admin_queue->ena_dev, "The ena device sent a completion but the driver didn't receive a MSI-X interrupt (cmd %d), autopolling mode is %s\n", comp_ctx->cmd_opcode, admin_queue->auto_polling ? "ON" : "OFF"); @@ -2138,6 +2139,7 @@ int ena_com_admin_init(struct ena_com_dev *ena_dev, admin_queue->ena_dev = ena_dev; admin_queue->running_state = true; + admin_queue->is_missing_admin_interrupt = false; return 0; error: diff --git a/drivers/net/ena/base/ena_com.h b/drivers/net/ena/base/ena_com.h index c62016cc06..c999cd2381 100644 --- a/drivers/net/ena/base/ena_com.h +++ b/drivers/net/ena/base/ena_com.h @@ -237,6 +237,8 @@ struct ena_com_admin_queue { */ bool running_state; + bool is_missing_admin_interrupt; + /* Count the number of outstanding admin commands */ ena_atomic32_t outstanding_cmds; @@ -1089,6 +1091,16 @@ int ena_com_config_dev_mode(struct ena_com_dev *ena_dev, struct ena_admin_feature_llq_desc *llq_features, struct ena_llq_configurations *llq_default_config); +/* ena_com_get_missing_admin_interrupt - Return if there is a missing admin interrupt + * @ena_dev: ENA communication layer struct + * + * @return - true if there is a missing admin interrupt or false otherwise + */ +static inline bool ena_com_get_missing_admin_interrupt(struct ena_com_dev *ena_dev) +{ + return ena_dev->admin_queue.is_missing_admin_interrupt; +} + /* ena_com_io_sq_to_ena_dev - Extract ena_com_dev using contained field io_sq. * @io_sq: IO submit queue struct * diff --git a/drivers/net/ena/base/ena_defs/ena_regs_defs.h b/drivers/net/ena/base/ena_defs/ena_regs_defs.h index a94025dc77..db6a97d675 100644 --- a/drivers/net/ena/base/ena_defs/ena_regs_defs.h +++ b/drivers/net/ena/base/ena_defs/ena_regs_defs.h @@ -24,6 +24,7 @@ enum ena_regs_reset_reason_types { ENA_REGS_RESET_SUSPECTED_POLL_STARVATION = 15, ENA_REGS_RESET_RX_DESCRIPTOR_MALFORMED = 16, ENA_REGS_RESET_TX_DESCRIPTOR_MALFORMED = 17, + ENA_REGS_RESET_MISSING_ADMIN_INTERRUPT = 18, ENA_REGS_RESET_LAST, }; From patchwork Tue Mar 12 18:07:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Brandes, Shai" X-Patchwork-Id: 138268 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B166743C94; 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12 Mar 2024 18:08:06 +0000 Received: from EX19MTAEUA001.ant.amazon.com [10.0.17.79:6038] by smtpin.naws.eu-west-1.prod.farcaster.email.amazon.dev [10.0.26.159:2525] with esmtp (Farcaster) id 49492acd-b1b2-4fdc-8ef6-80b3ec2ce72e; Tue, 12 Mar 2024 18:08:05 +0000 (UTC) X-Farcaster-Flow-ID: 49492acd-b1b2-4fdc-8ef6-80b3ec2ce72e Received: from EX19D007EUA001.ant.amazon.com (10.252.50.133) by EX19MTAEUA001.ant.amazon.com (10.252.50.192) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Tue, 12 Mar 2024 18:08:04 +0000 Received: from EX19MTAUWA001.ant.amazon.com (10.250.64.204) by EX19D007EUA001.ant.amazon.com (10.252.50.133) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Tue, 12 Mar 2024 18:08:03 +0000 Received: from HFA15-CG15235BS.amazon.com (10.85.143.174) by mail-relay.amazon.com (10.250.64.204) with Microsoft SMTP Server id 15.2.1258.28 via Frontend Transport; Tue, 12 Mar 2024 18:08:02 +0000 From: To: CC: , Shai Brandes Subject: [PATCH v4 18/31] net/ena/base: check for existing keep alive notification Date: Tue, 12 Mar 2024 20:07:03 +0200 Message-ID: <20240312180716.8515-19-shaibran@amazon.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240312180716.8515-1-shaibran@amazon.com> References: <20240312180716.8515-1-shaibran@amazon.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Shai Brandes This commit adds an API to query the aenq on whether there is a pending keep alive notification. Signed-off-by: Shai Brandes Reviewed-by: Amit Bernstein --- drivers/net/ena/base/ena_com.c | 39 ++++++++++++++++++++++++++++++++++ drivers/net/ena/base/ena_com.h | 10 +++++++++ 2 files changed, 49 insertions(+) diff --git a/drivers/net/ena/base/ena_com.c b/drivers/net/ena/base/ena_com.c index 8e9c112715..f9613f7807 100644 --- a/drivers/net/ena/base/ena_com.c +++ b/drivers/net/ena/base/ena_com.c @@ -2456,6 +2456,45 @@ void ena_com_aenq_intr_handler(struct ena_com_dev *ena_dev, void *data) mmiowb(); } +bool ena_com_aenq_has_keep_alive(struct ena_com_dev *ena_dev) +{ + struct ena_admin_aenq_common_desc *aenq_common; + struct ena_com_aenq *aenq = &ena_dev->aenq; + struct ena_admin_aenq_entry *aenq_e; + u8 phase = aenq->phase; + u16 masked_head; + + masked_head = aenq->head & (aenq->q_depth - 1); + aenq_e = &aenq->entries[masked_head]; /* Get first entry */ + aenq_common = &aenq_e->aenq_common_desc; + + /* Go over all the events */ + while ((READ_ONCE8(aenq_common->flags) & + ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK) == phase) { + /* Make sure the device finished writing the rest of the descriptor + * before reading it. + */ + dma_rmb(); + + if (aenq_common->group == ENA_ADMIN_KEEP_ALIVE) + return true; + + /* Get next event entry */ + masked_head++; + + if (unlikely(masked_head == aenq->q_depth)) { + masked_head = 0; + phase = !phase; + } + + aenq_e = &aenq->entries[masked_head]; + aenq_common = &aenq_e->aenq_common_desc; + } + + return false; +} + + int ena_com_dev_reset(struct ena_com_dev *ena_dev, enum ena_regs_reset_reason_types reset_reason) { diff --git a/drivers/net/ena/base/ena_com.h b/drivers/net/ena/base/ena_com.h index c999cd2381..737747f64b 100644 --- a/drivers/net/ena/base/ena_com.h +++ b/drivers/net/ena/base/ena_com.h @@ -639,6 +639,16 @@ void ena_com_admin_q_comp_intr_handler(struct ena_com_dev *ena_dev); */ void ena_com_aenq_intr_handler(struct ena_com_dev *ena_dev, void *data); +/* ena_com_aenq_has_keep_alive - Retrieve if there is a keep alive notification in the aenq + * @ena_dev: ENA communication layer struct + * + * This method goes over the async event notification queue and returns if there + * is a keep alive notification. + * + * @return - true if there is a keep alive notification in the aenq or false otherwise + */ +bool ena_com_aenq_has_keep_alive(struct ena_com_dev *ena_dev); + /* ena_com_abort_admin_commands - Abort all the outstanding admin commands. * @ena_dev: ENA communication layer struct * From patchwork Tue Mar 12 18:07:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Brandes, Shai" X-Patchwork-Id: 138266 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id EC2B543C94; Tue, 12 Mar 2024 19:09:14 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9979B42E58; Tue, 12 Mar 2024 19:08:09 +0100 (CET) Received: from smtp-fw-6002.amazon.com (smtp-fw-6002.amazon.com [52.95.49.90]) by mails.dpdk.org (Postfix) with ESMTP id 4755B42E57 for ; Tue, 12 Mar 2024 19:08:08 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.com; i=@amazon.com; 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Tue, 12 Mar 2024 18:08:06 +0000 Received: from EX19MTAUWA001.ant.amazon.com (10.250.64.204) by EX19D007EUA002.ant.amazon.com (10.252.50.68) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Tue, 12 Mar 2024 18:08:05 +0000 Received: from HFA15-CG15235BS.amazon.com (10.85.143.174) by mail-relay.amazon.com (10.250.64.204) with Microsoft SMTP Server id 15.2.1258.28 via Frontend Transport; Tue, 12 Mar 2024 18:08:04 +0000 From: To: CC: , Shai Brandes Subject: [PATCH v4 19/31] net/ena/base: modify memory barrier comment Date: Tue, 12 Mar 2024 20:07:04 +0200 Message-ID: <20240312180716.8515-20-shaibran@amazon.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240312180716.8515-1-shaibran@amazon.com> References: <20240312180716.8515-1-shaibran@amazon.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Shai Brandes The dma_rmb() memory barrier guarantees that the device set the phase bit before continuing to read the rest of the descriptor. Because the phase bit and the rest of the descriptor are in the same cache line this ensures coherency of the data from the descriptor. Signed-off-by: Shai Brandes Reviewed-by: Amit Bernstein --- drivers/net/ena/base/ena_com.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/ena/base/ena_com.c b/drivers/net/ena/base/ena_com.c index f9613f7807..053e095585 100644 --- a/drivers/net/ena/base/ena_com.c +++ b/drivers/net/ena/base/ena_com.c @@ -2412,8 +2412,8 @@ void ena_com_aenq_intr_handler(struct ena_com_dev *ena_dev, void *data) /* Go over all the events */ while ((READ_ONCE8(aenq_common->flags) & ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK) == phase) { - /* Make sure the phase bit (ownership) is as expected before - * reading the rest of the descriptor. + /* Make sure the device finished writing the rest of the descriptor + * before reading it. */ dma_rmb(); From patchwork Tue Mar 12 18:07:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Brandes, Shai" X-Patchwork-Id: 138270 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A40A543C94; Tue, 12 Mar 2024 19:09:37 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id DAAC342E61; Tue, 12 Mar 2024 19:08:19 +0100 (CET) Received: from smtp-fw-52005.amazon.com (smtp-fw-52005.amazon.com [52.119.213.156]) by mails.dpdk.org (Postfix) with ESMTP id 244D742E60 for ; Tue, 12 Mar 2024 19:08:11 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.com; i=@amazon.com; q=dns/txt; s=amazon201209; t=1710266892; x=1741802892; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=wglF1FOUVFVsi3SN5vF/fcXUTnQk3TUXxuchcU4t1Jc=; b=CUkUl4qrQOfkYQVw6GOfGHnl8bKxytQVQaYZ3BKw3BMVAKBDjM2qt885 T+JMUvogU+ErWpcud3qlsHyazNIzKkAg+tKLHOXpSndHSA2XG9zfqD7ym w28tqdk5lEf2yBQed1lZYhPZKYONi7HBZZmHiKuuNQHruGJc8TGN+ZTml M=; X-IronPort-AV: E=Sophos;i="6.07,119,1708387200"; d="scan'208";a="640378436" Received: from iad12-co-svc-p1-lb1-vlan3.amazon.com (HELO smtpout.prod.us-west-2.prod.farcaster.email.amazon.dev) ([10.43.8.6]) by smtp-border-fw-52005.iad7.amazon.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Mar 2024 18:08:10 +0000 Received: from EX19MTAEUC002.ant.amazon.com [10.0.10.100:40347] by smtpin.naws.eu-west-1.prod.farcaster.email.amazon.dev [10.0.41.28:2525] with esmtp (Farcaster) id d9c411ad-2a2d-4ad2-b44c-46abbee2fe26; Tue, 12 Mar 2024 18:08:08 +0000 (UTC) X-Farcaster-Flow-ID: d9c411ad-2a2d-4ad2-b44c-46abbee2fe26 Received: from EX19D007EUB002.ant.amazon.com (10.252.51.117) by EX19MTAEUC002.ant.amazon.com (10.252.51.245) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Tue, 12 Mar 2024 18:08:08 +0000 Received: from EX19MTAUWA001.ant.amazon.com (10.250.64.204) by EX19D007EUB002.ant.amazon.com (10.252.51.117) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Tue, 12 Mar 2024 18:08:08 +0000 Received: from HFA15-CG15235BS.amazon.com (10.85.143.174) by mail-relay.amazon.com (10.250.64.204) with Microsoft SMTP Server id 15.2.1258.28 via Frontend Transport; Tue, 12 Mar 2024 18:08:06 +0000 From: To: CC: , Shai Brandes Subject: [PATCH v4 20/31] net/ena/base: rework Rx ring submission queue Date: Tue, 12 Mar 2024 20:07:05 +0200 Message-ID: <20240312180716.8515-21-shaibran@amazon.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240312180716.8515-1-shaibran@amazon.com> References: <20240312180716.8515-1-shaibran@amazon.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Shai Brandes RX ring submission queue descriptors are always located in host memory This optimization replaces the generic update tail method with a tailored method for host memory type descriptors to avoid unnecessary if statement. Signed-off-by: Shai Brandes Reviewed-by: Amit Bernstein --- drivers/net/ena/base/ena_eth_com.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/net/ena/base/ena_eth_com.c b/drivers/net/ena/base/ena_eth_com.c index f672df1001..ce25e60ac4 100644 --- a/drivers/net/ena/base/ena_eth_com.c +++ b/drivers/net/ena/base/ena_eth_com.c @@ -209,11 +209,8 @@ static int ena_com_sq_update_llq_tail(struct ena_com_io_sq *io_sq) return ENA_COM_OK; } -static int ena_com_sq_update_tail(struct ena_com_io_sq *io_sq) +static int ena_com_sq_update_reqular_queue_tail(struct ena_com_io_sq *io_sq) { - if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) - return ena_com_sq_update_llq_tail(io_sq); - io_sq->tail++; /* Switch phase bit in case of wrap around */ @@ -223,6 +220,14 @@ static int ena_com_sq_update_tail(struct ena_com_io_sq *io_sq) return ENA_COM_OK; } +static int ena_com_sq_update_tail(struct ena_com_io_sq *io_sq) +{ + if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) + return ena_com_sq_update_llq_tail(io_sq); + + return ena_com_sq_update_reqular_queue_tail(io_sq); +} + static struct ena_eth_io_rx_cdesc_base * ena_com_rx_cdesc_idx_to_ptr(struct ena_com_io_cq *io_cq, u16 idx) { @@ -661,7 +666,7 @@ int ena_com_add_single_rx_desc(struct ena_com_io_sq *io_sq, desc->buff_addr_hi = ((ena_buf->paddr & GENMASK_ULL(io_sq->dma_addr_bits - 1, 32)) >> 32); - return ena_com_sq_update_tail(io_sq); + return ena_com_sq_update_reqular_queue_tail(io_sq); } bool ena_com_cq_empty(struct ena_com_io_cq *io_cq) From patchwork Tue Mar 12 18:07:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Brandes, Shai" X-Patchwork-Id: 138271 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3C04343C94; Tue, 12 Mar 2024 19:09:43 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 209F942E73; Tue, 12 Mar 2024 19:08:21 +0100 (CET) Received: from smtp-fw-6002.amazon.com (smtp-fw-6002.amazon.com [52.95.49.90]) by mails.dpdk.org (Postfix) with ESMTP id 577FD42DD9 for ; Tue, 12 Mar 2024 19:08:13 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.com; i=@amazon.com; q=dns/txt; s=amazon201209; t=1710266894; x=1741802894; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=xscEPhSkqzaD0+f8bLJewcNb8diTfZTrb8/cA+ZVlZA=; b=qlymI/0KwXGmdaxOL5vwaJ6zzDiRb8WHi6ccFCEMUZYO2tAT9VPjSefF z0+mupIRVEqoqw+7PLrsERbl6Uta28qwPz2o2vCREmIcMly+CnzzG97G5 pgLFXIfL5sSQwUsK2NEMQJSO25nq76yZCrJ9eMLJ4qT1sMYa6jGtcZM4n A=; X-IronPort-AV: E=Sophos;i="6.07,119,1708387200"; d="scan'208";a="392781679" Received: from iad12-co-svc-p1-lb1-vlan3.amazon.com (HELO smtpout.prod.us-west-2.prod.farcaster.email.amazon.dev) ([10.43.8.6]) by smtp-border-fw-6002.iad6.amazon.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Mar 2024 18:08:13 +0000 Received: from EX19MTAEUA002.ant.amazon.com [10.0.43.254:15243] by smtpin.naws.eu-west-1.prod.farcaster.email.amazon.dev [10.0.34.15:2525] with esmtp (Farcaster) id 53e15850-bb88-41ac-a243-d63daa0c87d2; Tue, 12 Mar 2024 18:08:10 +0000 (UTC) X-Farcaster-Flow-ID: 53e15850-bb88-41ac-a243-d63daa0c87d2 Received: from EX19D007EUA002.ant.amazon.com (10.252.50.68) by EX19MTAEUA002.ant.amazon.com (10.252.50.124) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Tue, 12 Mar 2024 18:08:10 +0000 Received: from EX19MTAUWA001.ant.amazon.com (10.250.64.204) by EX19D007EUA002.ant.amazon.com (10.252.50.68) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Tue, 12 Mar 2024 18:08:10 +0000 Received: from HFA15-CG15235BS.amazon.com (10.85.143.174) by mail-relay.amazon.com (10.250.64.204) with Microsoft SMTP Server id 15.2.1258.28 via Frontend Transport; Tue, 12 Mar 2024 18:08:08 +0000 From: To: CC: , Shai Brandes Subject: [PATCH v4 21/31] net/ena/base: remove operating system type enum Date: Tue, 12 Mar 2024 20:07:06 +0200 Message-ID: <20240312180716.8515-22-shaibran@amazon.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240312180716.8515-1-shaibran@amazon.com> References: <20240312180716.8515-1-shaibran@amazon.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Shai Brandes remove all other operating system enumeration as they are unrelated to DPDK. Use a constant value instead. Signed-off-by: Shai Brandes Reviewed-by: Amit Bernstein --- drivers/net/ena/base/ena_defs/ena_admin_defs.h | 13 +------------ drivers/net/ena/base/ena_plat_dpdk.h | 1 + 2 files changed, 2 insertions(+), 12 deletions(-) diff --git a/drivers/net/ena/base/ena_defs/ena_admin_defs.h b/drivers/net/ena/base/ena_defs/ena_admin_defs.h index ce8a26721e..c3910c50cc 100644 --- a/drivers/net/ena/base/ena_defs/ena_admin_defs.h +++ b/drivers/net/ena/base/ena_defs/ena_admin_defs.h @@ -933,19 +933,8 @@ struct ena_admin_feature_rss_flow_hash_input { uint16_t enabled_input_sort; }; -enum ena_admin_os_type { - ENA_ADMIN_OS_LINUX = 1, - ENA_ADMIN_OS_WIN = 2, - ENA_ADMIN_OS_DPDK = 3, - ENA_ADMIN_OS_FREEBSD = 4, - ENA_ADMIN_OS_IPXE = 5, - ENA_ADMIN_OS_ESXI = 6, - ENA_ADMIN_OS_MACOS = 7, - ENA_ADMIN_OS_GROUPS_NUM = 7, -}; - struct ena_admin_host_info { - /* defined in enum ena_admin_os_type */ + /* Host OS type defined as ENA_ADMIN_OS_* */ uint32_t os_type; /* os distribution string format */ diff --git a/drivers/net/ena/base/ena_plat_dpdk.h b/drivers/net/ena/base/ena_plat_dpdk.h index 14bf582a45..bb21e1bf01 100644 --- a/drivers/net/ena/base/ena_plat_dpdk.h +++ b/drivers/net/ena/base/ena_plat_dpdk.h @@ -340,5 +340,6 @@ static __rte_always_inline int ena_bits_per_u64(uint64_t bitmap) return count; } +#define ENA_ADMIN_OS_DPDK 3 #endif /* DPDK_ENA_COM_ENA_PLAT_DPDK_H_ */ From patchwork Tue Mar 12 18:07:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Brandes, Shai" X-Patchwork-Id: 138272 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 6FAD843C94; Tue, 12 Mar 2024 19:09:48 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 39E7B42E1A; Tue, 12 Mar 2024 19:08:22 +0100 (CET) Received: from smtp-fw-80007.amazon.com (smtp-fw-80007.amazon.com [99.78.197.218]) by mails.dpdk.org (Postfix) with ESMTP id 4729D42E61 for ; Tue, 12 Mar 2024 19:08:15 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.com; i=@amazon.com; q=dns/txt; s=amazon201209; t=1710266896; x=1741802896; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=V3uQWF6PQDFOJODcK0oOYiiiJZRazooBFTlP+e5/xv8=; b=s+cwsMlSVsGwiE8Z/t+6LWGIUs+XL7UnRSSqVqk7wSzdXRX4q83Y2ZFP CnQLgZ0UXLi1BX8aMTMLHTj7nZgY2zNdsVvdjC1zzRBTW9IgKdaRlAtiP JBCtHJOYyUqYKGwVDqHYOuGYOCXE/GPa3xZoswG5KifP3P4EcsXbaUh1q I=; X-IronPort-AV: E=Sophos;i="6.07,119,1708387200"; d="scan'208";a="280481711" Received: from pdx4-co-svc-p1-lb2-vlan2.amazon.com (HELO smtpout.prod.us-east-1.prod.farcaster.email.amazon.dev) ([10.25.36.210]) by smtp-border-fw-80007.pdx80.corp.amazon.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Mar 2024 18:08:14 +0000 Received: from EX19MTAEUC001.ant.amazon.com [10.0.10.100:1570] by smtpin.naws.eu-west-1.prod.farcaster.email.amazon.dev [10.0.24.76:2525] with esmtp (Farcaster) id efb86f2f-500f-456c-ba23-4891f48bf478; Tue, 12 Mar 2024 18:08:12 +0000 (UTC) X-Farcaster-Flow-ID: efb86f2f-500f-456c-ba23-4891f48bf478 Received: from EX19D007EUB002.ant.amazon.com (10.252.51.117) by EX19MTAEUC001.ant.amazon.com (10.252.51.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Tue, 12 Mar 2024 18:08:12 +0000 Received: from EX19MTAUWA001.ant.amazon.com (10.250.64.204) by EX19D007EUB002.ant.amazon.com (10.252.51.117) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Tue, 12 Mar 2024 18:08:12 +0000 Received: from HFA15-CG15235BS.amazon.com (10.85.143.174) by mail-relay.amazon.com (10.250.64.204) with Microsoft SMTP Server id 15.2.1258.28 via Frontend Transport; Tue, 12 Mar 2024 18:08:10 +0000 From: To: CC: , Shai Brandes Subject: [PATCH v4 22/31] net/ena/base: handle command abort Date: Tue, 12 Mar 2024 20:07:07 +0200 Message-ID: <20240312180716.8515-23-shaibran@amazon.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240312180716.8515-1-shaibran@amazon.com> References: <20240312180716.8515-1-shaibran@amazon.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Shai Brandes Currently admin_queue->stats.aborted_cmd counter is incremented if an admin command status is ENA_CMD_ABORTED and only if the admin queue is in polling mode. This commit fixes handling the case of incrementing admin_queue->stats.aborted_cmd if the admin queue is in interrupt mode as well. Also added a verification that the command status is a valid completion status which is currently verified only if the admin queue is in polling mode. Signed-off-by: Shai Brandes Reviewed-by: Amit Bernstein --- drivers/net/ena/base/ena_com.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/net/ena/base/ena_com.c b/drivers/net/ena/base/ena_com.c index 053e095585..b98540ba63 100644 --- a/drivers/net/ena/base/ena_com.c +++ b/drivers/net/ena/base/ena_com.c @@ -824,8 +824,19 @@ static int ena_com_wait_and_process_admin_cq_interrupts(struct ena_comp_ctx *com ret = ENA_COM_TIMER_EXPIRED; goto err; } + } else if (unlikely(comp_ctx->status == ENA_CMD_ABORTED)) { + ena_trc_err(admin_queue->ena_dev, "Command was aborted\n"); + ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags); + admin_queue->stats.aborted_cmd++; + ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags); + ret = ENA_COM_NO_DEVICE; + goto err; } + ENA_WARN(comp_ctx->status != ENA_CMD_COMPLETED, + admin_queue->ena_dev, "Invalid comp status %d\n", + comp_ctx->status); + ret = ena_com_comp_status_to_errno(admin_queue, comp_ctx->comp_status); err: comp_ctxt_release(admin_queue, comp_ctx); From patchwork Tue Mar 12 18:07:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Brandes, Shai" X-Patchwork-Id: 138273 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A690C43C94; Tue, 12 Mar 2024 19:09:53 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 81DEB42E7F; Tue, 12 Mar 2024 19:08:23 +0100 (CET) Received: from smtp-fw-80009.amazon.com (smtp-fw-80009.amazon.com [99.78.197.220]) by mails.dpdk.org (Postfix) with ESMTP id C875042E68 for ; Tue, 12 Mar 2024 19:08:16 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.com; i=@amazon.com; q=dns/txt; s=amazon201209; t=1710266897; x=1741802897; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=NEmqtAyiNujNoejNSgRDm/etosDbphqoaeBoF2YrNtQ=; b=RDcNnMH+bwwv4b9GwK4h1MRrBK91E3DcOJavL5YCilmfRiSXnmkT84zT 5EkLiDcW5bkB2mqsFQmz/yNdW1VcvJupnYGHYuNW+s/Q9P46h1V9JXh5A WjtuHJO0DEIuOejH0w7HCDv+xR10zfEpCf+vWgzx7FYmqAcX9GoZVxSC6 0=; X-IronPort-AV: E=Sophos;i="6.07,119,1708387200"; d="scan'208";a="72672095" Received: from pdx4-co-svc-p1-lb2-vlan2.amazon.com (HELO smtpout.prod.us-east-1.prod.farcaster.email.amazon.dev) ([10.25.36.210]) by smtp-border-fw-80009.pdx80.corp.amazon.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Mar 2024 18:08:15 +0000 Received: from EX19MTAEUB002.ant.amazon.com [10.0.43.254:59707] by smtpin.naws.eu-west-1.prod.farcaster.email.amazon.dev [10.0.41.28:2525] with esmtp (Farcaster) id bfa1eea5-7758-456a-804d-cb55d8404c5d; Tue, 12 Mar 2024 18:08:14 +0000 (UTC) X-Farcaster-Flow-ID: bfa1eea5-7758-456a-804d-cb55d8404c5d Received: from EX19D007EUA002.ant.amazon.com (10.252.50.68) by EX19MTAEUB002.ant.amazon.com (10.252.51.79) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Tue, 12 Mar 2024 18:08:14 +0000 Received: from EX19MTAUWA001.ant.amazon.com (10.250.64.204) by EX19D007EUA002.ant.amazon.com (10.252.50.68) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Tue, 12 Mar 2024 18:08:14 +0000 Received: from HFA15-CG15235BS.amazon.com (10.85.143.174) by mail-relay.amazon.com (10.250.64.204) with Microsoft SMTP Server id 15.2.1258.28 via Frontend Transport; Tue, 12 Mar 2024 18:08:12 +0000 From: To: CC: , Shai Brandes Subject: [PATCH v4 23/31] net/ena/base: add support for device reset request Date: Tue, 12 Mar 2024 20:07:08 +0200 Message-ID: <20240312180716.8515-24-shaibran@amazon.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240312180716.8515-1-shaibran@amazon.com> References: <20240312180716.8515-1-shaibran@amazon.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Shai Brandes Adds support for reset request message from the device to the driver, over AENQ, which in turn should cause the driver to trigger reset. Signed-off-by: Shai Brandes Reviewed-by: Amit Bernstein --- drivers/net/ena/base/ena_defs/ena_admin_defs.h | 3 ++- drivers/net/ena/base/ena_defs/ena_regs_defs.h | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/net/ena/base/ena_defs/ena_admin_defs.h b/drivers/net/ena/base/ena_defs/ena_admin_defs.h index c3910c50cc..2adce75ed3 100644 --- a/drivers/net/ena/base/ena_defs/ena_admin_defs.h +++ b/drivers/net/ena/base/ena_defs/ena_admin_defs.h @@ -1213,7 +1213,8 @@ enum ena_admin_aenq_group { ENA_ADMIN_KEEP_ALIVE = 4, ENA_ADMIN_REFRESH_CAPABILITIES = 5, ENA_ADMIN_CONF_NOTIFICATIONS = 6, - ENA_ADMIN_AENQ_GROUPS_NUM = 7, + ENA_ADMIN_DEVICE_REQUEST_RESET = 7, + ENA_ADMIN_AENQ_GROUPS_NUM = 8, }; enum ena_admin_aenq_notification_syndrome { diff --git a/drivers/net/ena/base/ena_defs/ena_regs_defs.h b/drivers/net/ena/base/ena_defs/ena_regs_defs.h index db6a97d675..dd9b629f10 100644 --- a/drivers/net/ena/base/ena_defs/ena_regs_defs.h +++ b/drivers/net/ena/base/ena_defs/ena_regs_defs.h @@ -25,6 +25,7 @@ enum ena_regs_reset_reason_types { ENA_REGS_RESET_RX_DESCRIPTOR_MALFORMED = 16, ENA_REGS_RESET_TX_DESCRIPTOR_MALFORMED = 17, ENA_REGS_RESET_MISSING_ADMIN_INTERRUPT = 18, + ENA_REGS_RESET_DEVICE_REQUEST = 19, ENA_REGS_RESET_LAST, }; From patchwork Tue Mar 12 18:07:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Brandes, Shai" X-Patchwork-Id: 138274 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7725643C94; Tue, 12 Mar 2024 19:10:00 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2568F42E87; Tue, 12 Mar 2024 19:08:25 +0100 (CET) Received: from smtp-fw-33001.amazon.com (smtp-fw-33001.amazon.com [207.171.190.10]) by mails.dpdk.org (Postfix) with ESMTP id 5A30E42E61 for ; Tue, 12 Mar 2024 19:08:19 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.com; i=@amazon.com; q=dns/txt; s=amazon201209; t=1710266900; x=1741802900; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=WDV+hmSACMmsqqM212UqY/9dnqWFLG9PFU2PQ6KH3R4=; b=FdTKljlSUu55TPwOQU4t79SsOoYXlGZHJNjapUiVrOEAvqPxL/R5f9VD RbjEFispjdNhdtttwDlmZX4O2qSHviLxvUhFcX2P8V91+t00EbSSMHvnj SsvDBoMFcQRDk+KDY9ePqljN8JNS0F+P5mXKhvSxbA7PUImlJ4O9eYERC c=; X-IronPort-AV: E=Sophos;i="6.07,119,1708387200"; d="scan'208";a="332398345" Received: from iad12-co-svc-p1-lb1-vlan3.amazon.com (HELO smtpout.prod.us-east-1.prod.farcaster.email.amazon.dev) ([10.43.8.6]) by smtp-border-fw-33001.sea14.amazon.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Mar 2024 18:08:19 +0000 Received: from EX19MTAEUA001.ant.amazon.com [10.0.17.79:25751] by smtpin.naws.eu-west-1.prod.farcaster.email.amazon.dev [10.0.1.140:2525] with esmtp (Farcaster) id c5e67311-9915-4c8d-99c2-36c3a3fa1b4e; Tue, 12 Mar 2024 18:08:16 +0000 (UTC) X-Farcaster-Flow-ID: c5e67311-9915-4c8d-99c2-36c3a3fa1b4e Received: from EX19D007EUB002.ant.amazon.com (10.252.51.117) by EX19MTAEUA001.ant.amazon.com (10.252.50.192) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Tue, 12 Mar 2024 18:08:16 +0000 Received: from EX19MTAUWA001.ant.amazon.com (10.250.64.204) by EX19D007EUB002.ant.amazon.com (10.252.51.117) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Tue, 12 Mar 2024 18:08:16 +0000 Received: from HFA15-CG15235BS.amazon.com (10.85.143.174) by mail-relay.amazon.com (10.250.64.204) with Microsoft SMTP Server id 15.2.1258.28 via Frontend Transport; Tue, 12 Mar 2024 18:08:14 +0000 From: To: CC: , Shai Brandes Subject: [PATCH v4 24/31] net/ena: cosmetic changes Date: Tue, 12 Mar 2024 20:07:09 +0200 Message-ID: <20240312180716.8515-25-shaibran@amazon.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240312180716.8515-1-shaibran@amazon.com> References: <20240312180716.8515-1-shaibran@amazon.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Shai Brandes This patch makes several changes to improve the style and readability of the code. Signed-off-by: Shai Brandes Reviewed-by: Amit Bernstein --- drivers/net/ena/base/ena_com.c | 13 +++++-------- drivers/net/ena/base/ena_plat_dpdk.h | 2 +- 2 files changed, 6 insertions(+), 9 deletions(-) diff --git a/drivers/net/ena/base/ena_com.c b/drivers/net/ena/base/ena_com.c index b98540ba63..2db21e7895 100644 --- a/drivers/net/ena/base/ena_com.c +++ b/drivers/net/ena/base/ena_com.c @@ -1914,15 +1914,14 @@ int ena_com_phc_get_timestamp(struct ena_com_dev *ena_dev, u64 *timestamp) /* PHC is in active state, update statistics according to req_id and error_flags */ if ((READ_ONCE16(read_resp->req_id) != phc->req_id) || - (read_resp->error_flags & ENA_PHC_ERROR_FLAGS)) { + (read_resp->error_flags & ENA_PHC_ERROR_FLAGS)) /* Device didn't update req_id during blocking time or timestamp is invalid, * this indicates on a device error */ phc->stats.phc_err++; - } else { + else /* Device updated req_id during blocking time with valid timestamp */ phc->stats.phc_exp++; - } } /* Setting relative timeouts */ @@ -2431,7 +2430,7 @@ void ena_com_aenq_intr_handler(struct ena_com_dev *ena_dev, void *data) timestamp = (u64)aenq_common->timestamp_low | ((u64)aenq_common->timestamp_high << 32); - ena_trc_dbg(ena_dev, "AENQ! Group[%x] Syndrome[%x] timestamp: [%" ENA_PRIU64 "s]\n", + ena_trc_dbg(ena_dev, "AENQ! Group[%x] Syndrome[%x] timestamp: [%" ENA_PRIu64 "s]\n", aenq_common->group, aenq_common->syndrome, timestamp); @@ -3233,16 +3232,15 @@ int ena_com_allocate_customer_metrics_buffer(struct ena_com_dev *ena_dev) { struct ena_customer_metrics *customer_metrics = &ena_dev->customer_metrics; + customer_metrics->buffer_len = ENA_CUSTOMER_METRICS_BUFFER_SIZE; ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev, customer_metrics->buffer_len, customer_metrics->buffer_virt_addr, customer_metrics->buffer_dma_addr, customer_metrics->buffer_dma_handle); - if (unlikely(customer_metrics->buffer_virt_addr == NULL)) + if (unlikely(!customer_metrics->buffer_virt_addr)) return ENA_COM_NO_MEM; - customer_metrics->buffer_len = ENA_CUSTOMER_METRICS_BUFFER_SIZE; - return 0; } @@ -3285,7 +3283,6 @@ void ena_com_delete_customer_metrics_buffer(struct ena_com_dev *ena_dev) customer_metrics->buffer_dma_addr, customer_metrics->buffer_dma_handle); customer_metrics->buffer_virt_addr = NULL; - customer_metrics->buffer_len = 0; } } diff --git a/drivers/net/ena/base/ena_plat_dpdk.h b/drivers/net/ena/base/ena_plat_dpdk.h index bb21e1bf01..9e365b0f3b 100644 --- a/drivers/net/ena/base/ena_plat_dpdk.h +++ b/drivers/net/ena/base/ena_plat_dpdk.h @@ -40,7 +40,7 @@ typedef uint64_t dma_addr_t; #define ETIME ETIMEDOUT #endif -#define ENA_PRIU64 PRIu64 +#define ENA_PRIu64 PRIu64 #define ena_atomic32_t rte_atomic32_t #define ena_mem_handle_t const struct rte_memzone * From patchwork Tue Mar 12 18:07:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Brandes, Shai" X-Patchwork-Id: 138275 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D63D043C94; Tue, 12 Mar 2024 19:10:04 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 43B9642E8C; Tue, 12 Mar 2024 19:08:26 +0100 (CET) Received: from smtp-fw-52005.amazon.com (smtp-fw-52005.amazon.com [52.119.213.156]) by mails.dpdk.org (Postfix) with ESMTP id C702D42E00 for ; Tue, 12 Mar 2024 19:08:20 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.com; i=@amazon.com; q=dns/txt; s=amazon201209; t=1710266901; x=1741802901; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=xcqI7RwpJElhtFuceQzDmvHSLRqzymfwaBoNapYdKbA=; b=p3qhBgo6OX7lQLXhaC/1Ha/c85RVnh6ViY0Gcu5HkiK0kjJuLU3Y8TQ3 gpbSEF3pGDLvUDadpDBiG2N99kxnr9vsx1Z3YmAZ9SsRIYdmUcunNLzoo rQhCkFM7WP2FDOOSlquRWHG5wS3V8GWOVDqCavHMSlSCtOATeshk7JcNL Y=; X-IronPort-AV: E=Sophos;i="6.07,119,1708387200"; d="scan'208";a="640378461" Received: from iad12-co-svc-p1-lb1-vlan3.amazon.com (HELO smtpout.prod.us-west-2.prod.farcaster.email.amazon.dev) ([10.43.8.6]) by smtp-border-fw-52005.iad7.amazon.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Mar 2024 18:08:20 +0000 Received: from EX19MTAEUA002.ant.amazon.com [10.0.43.254:18893] by smtpin.naws.eu-west-1.prod.farcaster.email.amazon.dev [10.0.26.159:2525] with esmtp (Farcaster) id f03e0ddf-c187-426e-be76-bcc56409a9fc; Tue, 12 Mar 2024 18:08:19 +0000 (UTC) X-Farcaster-Flow-ID: f03e0ddf-c187-426e-be76-bcc56409a9fc Received: from EX19D007EUB002.ant.amazon.com (10.252.51.117) by EX19MTAEUA002.ant.amazon.com (10.252.50.126) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Tue, 12 Mar 2024 18:08:18 +0000 Received: from EX19MTAUWA001.ant.amazon.com (10.250.64.204) by EX19D007EUB002.ant.amazon.com (10.252.51.117) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Tue, 12 Mar 2024 18:08:18 +0000 Received: from HFA15-CG15235BS.amazon.com (10.85.143.174) by mail-relay.amazon.com (10.250.64.204) with Microsoft SMTP Server id 15.2.1258.28 via Frontend Transport; Tue, 12 Mar 2024 18:08:17 +0000 From: To: CC: , Shai Brandes Subject: [PATCH v4 25/31] net/ena/base: modify customer metrics memory management Date: Tue, 12 Mar 2024 20:07:10 +0200 Message-ID: <20240312180716.8515-26-shaibran@amazon.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240312180716.8515-1-shaibran@amazon.com> References: <20240312180716.8515-1-shaibran@amazon.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Shai Brandes 1. Set buffer length to zero in case memory allocation failed and after memory is released. 2. The driver checks buffer_virt_addr for customer allocation success. In case the allocation fails, buffer_virt_addr may not necessarily be NULL. Signed-off-by: Shai Brandes Reviewed-by: Amit Bernstein --- drivers/net/ena/base/ena_com.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/net/ena/base/ena_com.c b/drivers/net/ena/base/ena_com.c index 2db21e7895..24756e5e76 100644 --- a/drivers/net/ena/base/ena_com.c +++ b/drivers/net/ena/base/ena_com.c @@ -3233,13 +3233,17 @@ int ena_com_allocate_customer_metrics_buffer(struct ena_com_dev *ena_dev) struct ena_customer_metrics *customer_metrics = &ena_dev->customer_metrics; customer_metrics->buffer_len = ENA_CUSTOMER_METRICS_BUFFER_SIZE; + customer_metrics->buffer_virt_addr = NULL; + ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev, customer_metrics->buffer_len, customer_metrics->buffer_virt_addr, customer_metrics->buffer_dma_addr, customer_metrics->buffer_dma_handle); - if (unlikely(!customer_metrics->buffer_virt_addr)) + if (unlikely(!customer_metrics->buffer_virt_addr)) { + customer_metrics->buffer_len = 0; return ENA_COM_NO_MEM; + } return 0; } @@ -3283,6 +3287,7 @@ void ena_com_delete_customer_metrics_buffer(struct ena_com_dev *ena_dev) customer_metrics->buffer_dma_addr, customer_metrics->buffer_dma_handle); customer_metrics->buffer_virt_addr = NULL; + customer_metrics->buffer_len = 0; } } From patchwork Tue Mar 12 18:07:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Brandes, Shai" X-Patchwork-Id: 138276 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id AB5FC43C94; Tue, 12 Mar 2024 19:10:10 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 78B6F42E20; Tue, 12 Mar 2024 19:08:27 +0100 (CET) Received: from smtp-fw-33001.amazon.com (smtp-fw-33001.amazon.com [207.171.190.10]) by mails.dpdk.org (Postfix) with ESMTP id 3512A42E00 for ; Tue, 12 Mar 2024 19:08:23 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.com; i=@amazon.com; q=dns/txt; s=amazon201209; t=1710266904; x=1741802904; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=Weonxet92ItnHruX57tqybY1v4KCuFUMGvoKZcA2A7o=; b=ExBN+58xlfODpA7p8nVtndOQ2aG48SkSOfIIM/JQjVAeNDy7CW8+andZ s42hcMRiDXdAtaXvgR/LWRStCTKYAH/0M/+IsrZCJl6YmwRP0ans62txM /EGHlLdVRQaH6OdU+orf2HfFVkkTx+k+eWecRURfbt6TNUPMfuLMwv6JP Q=; X-IronPort-AV: E=Sophos;i="6.07,119,1708387200"; d="scan'208";a="332398357" Received: from iad12-co-svc-p1-lb1-vlan3.amazon.com (HELO smtpout.prod.us-west-2.prod.farcaster.email.amazon.dev) ([10.43.8.6]) by smtp-border-fw-33001.sea14.amazon.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Mar 2024 18:08:23 +0000 Received: from EX19MTAEUC002.ant.amazon.com [10.0.10.100:55401] by smtpin.naws.eu-west-1.prod.farcaster.email.amazon.dev [10.0.24.76:2525] with esmtp (Farcaster) id 38fb4eb7-bcaf-4b47-a015-86446b89e85d; Tue, 12 Mar 2024 18:08:21 +0000 (UTC) X-Farcaster-Flow-ID: 38fb4eb7-bcaf-4b47-a015-86446b89e85d Received: from EX19D007EUA002.ant.amazon.com (10.252.50.68) by EX19MTAEUC002.ant.amazon.com (10.252.51.245) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Tue, 12 Mar 2024 18:08:21 +0000 Received: from EX19MTAUWA001.ant.amazon.com (10.250.64.204) by EX19D007EUA002.ant.amazon.com (10.252.50.68) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Tue, 12 Mar 2024 18:08:20 +0000 Received: from HFA15-CG15235BS.amazon.com (10.85.143.174) by mail-relay.amazon.com (10.250.64.204) with Microsoft SMTP Server id 15.2.1258.28 via Frontend Transport; Tue, 12 Mar 2024 18:08:19 +0000 From: To: CC: , Shai Brandes Subject: [PATCH v4 26/31] net/ena/base: modify logs to use unsigned format specifier Date: Tue, 12 Mar 2024 20:07:11 +0200 Message-ID: <20240312180716.8515-27-shaibran@amazon.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240312180716.8515-1-shaibran@amazon.com> References: <20240312180716.8515-1-shaibran@amazon.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Shai Brandes Modify log prints to use correct format specifier for unsigned variables and removed line breaks for lines that do not exceed maximal line length. Signed-off-by: Shai Brandes Reviewed-by: Amit Bernstein --- drivers/net/ena/base/ena_eth_com.c | 22 +++++++++++----------- drivers/net/ena/base/ena_plat_dpdk.h | 3 +-- 2 files changed, 12 insertions(+), 13 deletions(-) diff --git a/drivers/net/ena/base/ena_eth_com.c b/drivers/net/ena/base/ena_eth_com.c index ce25e60ac4..0de736fbe0 100644 --- a/drivers/net/ena/base/ena_eth_com.c +++ b/drivers/net/ena/base/ena_eth_com.c @@ -64,7 +64,7 @@ static int ena_com_write_bounce_buffer_to_dev(struct ena_com_io_sq *io_sq, io_sq->entries_in_tx_burst_left--; ena_trc_dbg(ena_com_io_sq_to_ena_dev(io_sq), - "Decreasing entries_in_tx_burst_left of queue %d to %d\n", + "Decreasing entries_in_tx_burst_left of queue %u to %u\n", io_sq->qid, io_sq->entries_in_tx_burst_left); } @@ -258,7 +258,7 @@ static int ena_com_cdesc_rx_pkt_get(struct ena_com_io_cq *io_cq, if (unlikely((status & ENA_ETH_IO_RX_CDESC_BASE_FIRST_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_FIRST_SHIFT && count != 0)) { ena_trc_err(dev, - "First bit is on in descriptor #%d on q_id: %d, req_id: %u\n", + "First bit is on in descriptor #%u on q_id: %u, req_id: %u\n", count, io_cq->qid, cdesc->req_id); return ENA_COM_FAULT; } @@ -267,7 +267,7 @@ static int ena_com_cdesc_rx_pkt_get(struct ena_com_io_cq *io_cq, ENA_ETH_IO_RX_CDESC_BASE_MBZ17_MASK)) && ena_com_get_cap(dev, ENA_ADMIN_CDESC_MBZ))) { ena_trc_err(dev, - "Corrupted RX descriptor #%d on q_id: %d, req_id: %u\n", + "Corrupted RX descriptor #%u on q_id: %u, req_id: %u\n", count, io_cq->qid, cdesc->req_id); return ENA_COM_FAULT; } @@ -287,7 +287,7 @@ static int ena_com_cdesc_rx_pkt_get(struct ena_com_io_cq *io_cq, io_cq->cur_rx_pkt_cdesc_start_idx = head_masked; ena_trc_dbg(ena_com_io_cq_to_ena_dev(io_cq), - "ENA q_id: %d packets were completed. first desc idx %u descs# %d\n", + "ENA q_id: %u packets were completed. first desc idx %u descs# %u\n", io_cq->qid, *first_cdesc_idx, count); } else { io_cq->cur_rx_pkt_cdesc_count = count; @@ -393,7 +393,7 @@ static void ena_com_rx_set_flags(struct ena_com_io_cq *io_cq, ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_SHIFT; ena_trc_dbg(ena_com_io_cq_to_ena_dev(io_cq), - "l3_proto %d l4_proto %d l3_csum_err %d l4_csum_err %d hash %d frag %d cdesc_status %x\n", + "l3_proto %d l4_proto %d l3_csum_err %d l4_csum_err %d hash %u frag %d cdesc_status %x\n", ena_rx_ctx->l3_proto, ena_rx_ctx->l4_proto, ena_rx_ctx->l3_csum_err, @@ -433,7 +433,7 @@ int ena_com_prepare_tx(struct ena_com_io_sq *io_sq, if (unlikely(header_len > io_sq->tx_max_header_size)) { ena_trc_err(ena_com_io_sq_to_ena_dev(io_sq), - "Header size is too large %d max header: %d\n", + "Header size is too large %u max header: %u\n", header_len, io_sq->tx_max_header_size); return ENA_COM_INVAL; } @@ -591,12 +591,12 @@ int ena_com_rx_pkt(struct ena_com_io_cq *io_cq, } ena_trc_dbg(ena_com_io_cq_to_ena_dev(io_cq), - "Fetch rx packet: queue %d completed desc: %d\n", + "Fetch rx packet: queue %u completed desc: %u\n", io_cq->qid, nb_hw_desc); if (unlikely(nb_hw_desc > ena_rx_ctx->max_bufs)) { ena_trc_err(ena_com_io_cq_to_ena_dev(io_cq), - "Too many RX cdescs (%d) > MAX(%d)\n", + "Too many RX cdescs (%u) > MAX(%u)\n", nb_hw_desc, ena_rx_ctx->max_bufs); return ENA_COM_NO_SPACE; } @@ -621,7 +621,7 @@ int ena_com_rx_pkt(struct ena_com_io_cq *io_cq, io_sq->next_to_comp += nb_hw_desc; ena_trc_dbg(ena_com_io_cq_to_ena_dev(io_cq), - "[%s][QID#%d] Updating SQ head to: %d\n", __func__, + "Updating Queue %u, SQ head to: %u\n", io_sq->qid, io_sq->next_to_comp); /* Get rx flags from the last pkt */ @@ -659,8 +659,8 @@ int ena_com_add_single_rx_desc(struct ena_com_io_sq *io_sq, desc->req_id = req_id; ena_trc_dbg(ena_com_io_sq_to_ena_dev(io_sq), - "[%s] Adding single RX desc, Queue: %u, req_id: %u\n", - __func__, io_sq->qid, req_id); + "Adding single RX desc, Queue: %u, req_id: %u\n", + io_sq->qid, req_id); desc->buff_addr_lo = (u32)ena_buf->paddr; desc->buff_addr_hi = diff --git a/drivers/net/ena/base/ena_plat_dpdk.h b/drivers/net/ena/base/ena_plat_dpdk.h index 9e365b0f3b..dffe60705d 100644 --- a/drivers/net/ena/base/ena_plat_dpdk.h +++ b/drivers/net/ena/base/ena_plat_dpdk.h @@ -73,8 +73,7 @@ typedef uint64_t dma_addr_t; /* Redefine memcpy with caution: rte_memcpy can be simply aliased to memcpy, so * make the redefinition only if it's safe (and beneficial) to do so. */ -#if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64_MEMCPY) || \ - defined(RTE_ARCH_ARM_NEON_MEMCPY) +#if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64_MEMCPY) || defined(RTE_ARCH_ARM_NEON_MEMCPY) #undef memcpy #define memcpy rte_memcpy #endif From patchwork Tue Mar 12 18:07:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Brandes, Shai" X-Patchwork-Id: 138277 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id BE3ED43C94; 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12 Mar 2024 18:08:25 +0000 Received: from EX19MTAEUB001.ant.amazon.com [10.0.10.100:26640] by smtpin.naws.eu-west-1.prod.farcaster.email.amazon.dev [10.0.1.140:2525] with esmtp (Farcaster) id b0693108-4c00-43b0-be2b-c99fe19fabb0; Tue, 12 Mar 2024 18:08:23 +0000 (UTC) X-Farcaster-Flow-ID: b0693108-4c00-43b0-be2b-c99fe19fabb0 Received: from EX19D007EUB002.ant.amazon.com (10.252.51.117) by EX19MTAEUB001.ant.amazon.com (10.252.51.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Tue, 12 Mar 2024 18:08:23 +0000 Received: from EX19MTAUWA001.ant.amazon.com (10.250.64.204) by EX19D007EUB002.ant.amazon.com (10.252.51.117) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Tue, 12 Mar 2024 18:08:22 +0000 Received: from HFA15-CG15235BS.amazon.com (10.85.143.174) by mail-relay.amazon.com (10.250.64.204) with Microsoft SMTP Server id 15.2.1258.28 via Frontend Transport; Tue, 12 Mar 2024 18:08:21 +0000 From: To: CC: , Shai Brandes Subject: [PATCH v4 27/31] net/ena: update device-preferred size of rings Date: Tue, 12 Mar 2024 20:07:12 +0200 Message-ID: <20240312180716.8515-28-shaibran@amazon.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240312180716.8515-1-shaibran@amazon.com> References: <20240312180716.8515-1-shaibran@amazon.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Shai Brandes Update the device-preferred size of the Tx ring to fall within the valid range when a large LLQ is enabled. For consistency, align the device-preferred size of the Rx ring accordingly. Signed-off-by: Shai Brandes Reviewed-by: Amit Bernstein --- drivers/net/ena/ena_ethdev.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/net/ena/ena_ethdev.c b/drivers/net/ena/ena_ethdev.c index e23edd4bd2..2dba5069b0 100644 --- a/drivers/net/ena/ena_ethdev.c +++ b/drivers/net/ena/ena_ethdev.c @@ -2596,8 +2596,10 @@ static int ena_infos_get(struct rte_eth_dev *dev, dev_info->tx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS, adapter->max_tx_sgl_size); - dev_info->default_rxportconf.ring_size = ENA_DEFAULT_RING_SIZE; - dev_info->default_txportconf.ring_size = ENA_DEFAULT_RING_SIZE; + dev_info->default_rxportconf.ring_size = RTE_MIN(ENA_DEFAULT_RING_SIZE, + dev_info->rx_desc_lim.nb_max); + dev_info->default_txportconf.ring_size = RTE_MIN(ENA_DEFAULT_RING_SIZE, + dev_info->tx_desc_lim.nb_max); dev_info->err_handle_mode = RTE_ETH_ERROR_HANDLE_MODE_PASSIVE; From patchwork Tue Mar 12 18:07:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Brandes, Shai" X-Patchwork-Id: 138278 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 176F943C94; Tue, 12 Mar 2024 19:10:22 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3838B42E9A; Tue, 12 Mar 2024 19:08:30 +0100 (CET) Received: from smtp-fw-52005.amazon.com (smtp-fw-52005.amazon.com [52.119.213.156]) by mails.dpdk.org (Postfix) with ESMTP id 537CC42DFE for ; Tue, 12 Mar 2024 19:08:27 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.com; i=@amazon.com; q=dns/txt; s=amazon201209; t=1710266908; x=1741802908; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=LSC1eMiWYIbejV4JZeDs5Ja0RG2QiAVWWKzyj1zss7w=; b=bAYGCLIGU3yyT47/09nTwpiTFockUQ6cGSWLjXWP/gx08wIZlQJKcF4J m2dmLKZVq5kDbiR9Vi2YIYuIpqc6F4CEt6hVD/1dPi3GF9aMqkgABKNm1 pEFmYX83l4JL2v+cOJunSEd/p7kwnGXqGJ/4GTjTs1uhY3yshbUZIFS2q M=; X-IronPort-AV: E=Sophos;i="6.07,119,1708387200"; d="scan'208";a="640378483" Received: from iad12-co-svc-p1-lb1-vlan3.amazon.com (HELO smtpout.prod.us-west-2.prod.farcaster.email.amazon.dev) ([10.43.8.6]) by smtp-border-fw-52005.iad7.amazon.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Mar 2024 18:08:27 +0000 Received: from EX19MTAEUB002.ant.amazon.com [10.0.43.254:63194] by smtpin.naws.eu-west-1.prod.farcaster.email.amazon.dev [10.0.0.5:2525] with esmtp (Farcaster) id f3e9e741-05c4-4c47-95f0-71362e51f956; Tue, 12 Mar 2024 18:08:25 +0000 (UTC) X-Farcaster-Flow-ID: f3e9e741-05c4-4c47-95f0-71362e51f956 Received: from EX19D007EUB002.ant.amazon.com (10.252.51.117) by EX19MTAEUB002.ant.amazon.com (10.252.51.79) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Tue, 12 Mar 2024 18:08:25 +0000 Received: from EX19MTAUWA001.ant.amazon.com (10.250.64.204) by EX19D007EUB002.ant.amazon.com (10.252.51.117) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Tue, 12 Mar 2024 18:08:24 +0000 Received: from HFA15-CG15235BS.amazon.com (10.85.143.174) by mail-relay.amazon.com (10.250.64.204) with Microsoft SMTP Server id 15.2.1258.28 via Frontend Transport; Tue, 12 Mar 2024 18:08:23 +0000 From: To: CC: , Shai Brandes Subject: [PATCH v4 28/31] net/ena: exhaust interrupt callbacks in device close Date: Tue, 12 Mar 2024 20:07:13 +0200 Message-ID: <20240312180716.8515-29-shaibran@amazon.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240312180716.8515-1-shaibran@amazon.com> References: <20240312180716.8515-1-shaibran@amazon.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Shai Brandes Change rte_intr_callback_unregister to its synchronous variant to ensure all active interrupt callbacks are completed before proceeding with the flow. Relocate the interrupt deregistration to precede the release of stats memory, thereby preventing the interrupt handler from accessing memory that has already been freed. Signed-off-by: Shai Brandes Reviewed-by: Amit Bernstein --- drivers/net/ena/ena_ethdev.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/net/ena/ena_ethdev.c b/drivers/net/ena/ena_ethdev.c index 2dba5069b0..a640a3bc07 100644 --- a/drivers/net/ena/ena_ethdev.c +++ b/drivers/net/ena/ena_ethdev.c @@ -867,6 +867,7 @@ static int ena_close(struct rte_eth_dev *dev) struct rte_intr_handle *intr_handle = pci_dev->intr_handle; struct ena_adapter *adapter = dev->data->dev_private; int ret = 0; + int rc; if (rte_eal_process_type() != RTE_PROC_PRIMARY) return 0; @@ -875,17 +876,17 @@ static int ena_close(struct rte_eth_dev *dev) ret = ena_stop(dev); adapter->state = ENA_ADAPTER_STATE_CLOSED; + rte_intr_disable(intr_handle); + rc = rte_intr_callback_unregister_sync(intr_handle, ena_interrupt_handler_rte, dev); + if (unlikely(rc != 0)) + PMD_INIT_LOG(ERR, "Failed to unregister interrupt handler\n"); + ena_rx_queue_release_all(dev); ena_tx_queue_release_all(dev); rte_free(adapter->drv_stats); adapter->drv_stats = NULL; - rte_intr_disable(intr_handle); - rte_intr_callback_unregister(intr_handle, - ena_interrupt_handler_rte, - dev); - /* * MAC is not allocated dynamically. Setting NULL should prevent from * release of the resource in the rte_eth_dev_release_port(). From patchwork Tue Mar 12 18:07:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Brandes, Shai" X-Patchwork-Id: 138279 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3374543C94; Tue, 12 Mar 2024 19:10:27 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 633B542EA0; Tue, 12 Mar 2024 19:08:31 +0100 (CET) Received: from smtp-fw-52003.amazon.com (smtp-fw-52003.amazon.com [52.119.213.152]) by mails.dpdk.org (Postfix) with ESMTP id 8117F42E51 for ; Tue, 12 Mar 2024 19:08:28 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.com; i=@amazon.com; q=dns/txt; s=amazon201209; t=1710266909; x=1741802909; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=2g0XM/eMw4F67JKk0iZuZ6Wp7aXQC9YOCEO6f2AO+BI=; b=G7bExIJyB8gQJNCA8icPXtdn9BwNtiFtopx9j02N7CEjpGkd1Kb83tJ/ mi6rw3oALNQPD6V8MgVws93asXMiTI3bx1yjo+dtfyepUXglfQSN4gxu4 515apYlQMZAZkH+AHxGm4FhiV7BL2vj08XSJ9VCqJTEsVIpP5raCbr4uE Y=; X-IronPort-AV: E=Sophos;i="6.07,119,1708387200"; d="scan'208";a="644224063" Received: from iad12-co-svc-p1-lb1-vlan3.amazon.com (HELO smtpout.prod.us-east-1.prod.farcaster.email.amazon.dev) ([10.43.8.6]) by smtp-border-fw-52003.iad7.amazon.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Mar 2024 18:08:29 +0000 Received: from EX19MTAEUA001.ant.amazon.com [10.0.17.79:47710] by smtpin.naws.eu-west-1.prod.farcaster.email.amazon.dev [10.0.21.118:2525] with esmtp (Farcaster) id 770fd129-a119-4aba-af83-823d31434acd; Tue, 12 Mar 2024 18:08:27 +0000 (UTC) X-Farcaster-Flow-ID: 770fd129-a119-4aba-af83-823d31434acd Received: from EX19D007EUA002.ant.amazon.com (10.252.50.68) by EX19MTAEUA001.ant.amazon.com (10.252.50.50) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Tue, 12 Mar 2024 18:08:27 +0000 Received: from EX19MTAUWA001.ant.amazon.com (10.250.64.204) by EX19D007EUA002.ant.amazon.com (10.252.50.68) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Tue, 12 Mar 2024 18:08:26 +0000 Received: from HFA15-CG15235BS.amazon.com (10.85.143.174) by mail-relay.amazon.com (10.250.64.204) with Microsoft SMTP Server id 15.2.1258.28 via Frontend Transport; Tue, 12 Mar 2024 18:08:25 +0000 From: To: CC: , Shai Brandes Subject: [PATCH v4 29/31] net/ena: support max large llq depth from the device Date: Tue, 12 Mar 2024 20:07:14 +0200 Message-ID: <20240312180716.8515-30-shaibran@amazon.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240312180716.8515-1-shaibran@amazon.com> References: <20240312180716.8515-1-shaibran@amazon.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Shai Brandes Selected AWS instances from later generations enable large LLQ by default, allowing the transmission of packets with headers exceeding 96 bytes. Due to the overall ENA memory BAR size limitation, large LLQ has the side effect of halving the maximum number of LLQ entries (from 1024 to 512). ENA-Express, powered by AWS Scalable Reliable Datagram (SRD) technology, requires Tx queue with 1024 entries. Selected AWS instances from upcoming generations will have double the size of the ENA memory BAR, enabling ENA-Express to work with a large LLQ of 1024 entries. The initial default large LLQ size will remain 512. Signed-off-by: Shai Brandes Reviewed-by: Amit Bernstein --- doc/guides/rel_notes/release_24_03.rst | 2 + .../net/ena/base/ena_defs/ena_admin_defs.h | 4 +- drivers/net/ena/ena_ethdev.c | 38 ++++++++++++------- 3 files changed, 29 insertions(+), 15 deletions(-) diff --git a/doc/guides/rel_notes/release_24_03.rst b/doc/guides/rel_notes/release_24_03.rst index 58d092194e..bee2429ba0 100644 --- a/doc/guides/rel_notes/release_24_03.rst +++ b/doc/guides/rel_notes/release_24_03.rst @@ -109,6 +109,8 @@ New Features * Added support for sub-optimal configuration notifications from the device. * Restructured fast release of mbufs when RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE optimization is enabled. * Added `normal_llq_hdr` devarg that enforce normal llq header policy. + * Added support for LLQ header size recommendation from the device. + * Allowed large LLQ with 1024 entries when the device supports enlarged memory BAR. * **Updated Atomic Rules' Arkville driver.** diff --git a/drivers/net/ena/base/ena_defs/ena_admin_defs.h b/drivers/net/ena/base/ena_defs/ena_admin_defs.h index 2adce75ed3..cff6451c96 100644 --- a/drivers/net/ena/base/ena_defs/ena_admin_defs.h +++ b/drivers/net/ena/base/ena_defs/ena_admin_defs.h @@ -696,8 +696,8 @@ struct ena_admin_feature_llq_desc { */ uint8_t entry_size_recommended; - /* reserved */ - uint8_t reserved1[2]; + /* max depth of wide llq, or 0 for N/A */ + uint16_t max_wide_llq_depth; /* accelerated low latency queues requirement. driver needs to * support those requirements in order to use accelerated llq diff --git a/drivers/net/ena/ena_ethdev.c b/drivers/net/ena/ena_ethdev.c index a640a3bc07..c7c2eef92f 100644 --- a/drivers/net/ena/ena_ethdev.c +++ b/drivers/net/ena/ena_ethdev.c @@ -42,6 +42,8 @@ #define DECIMAL_BASE 10 +#define MAX_WIDE_LLQ_DEPTH_UNSUPPORTED 0 + /* * We should try to keep ENA_CLEANUP_BUF_SIZE lower than * RTE_MEMPOOL_CACHE_MAX_SIZE, so we can fit this in mempool local cache. @@ -1067,7 +1069,7 @@ static int ena_calc_io_queue_size(struct ena_calc_queue_size_ctx *ctx, bool use_large_llq_hdr) { - struct ena_admin_feature_llq_desc *llq = &ctx->get_feat_ctx->llq; + struct ena_admin_feature_llq_desc *dev = &ctx->get_feat_ctx->llq; struct ena_com_dev *ena_dev = ctx->ena_dev; uint32_t max_tx_queue_size; uint32_t max_rx_queue_size; @@ -1082,7 +1084,7 @@ ena_calc_io_queue_size(struct ena_calc_queue_size_ctx *ctx, if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) { max_tx_queue_size = RTE_MIN(max_tx_queue_size, - llq->max_llq_depth); + dev->max_llq_depth); } else { max_tx_queue_size = RTE_MIN(max_tx_queue_size, max_queue_ext->max_tx_sq_depth); @@ -1102,7 +1104,7 @@ ena_calc_io_queue_size(struct ena_calc_queue_size_ctx *ctx, if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) { max_tx_queue_size = RTE_MIN(max_tx_queue_size, - llq->max_llq_depth); + dev->max_llq_depth); } else { max_tx_queue_size = RTE_MIN(max_tx_queue_size, max_queues->max_sq_depth); @@ -1118,18 +1120,28 @@ ena_calc_io_queue_size(struct ena_calc_queue_size_ctx *ctx, max_rx_queue_size = rte_align32prevpow2(max_rx_queue_size); max_tx_queue_size = rte_align32prevpow2(max_tx_queue_size); - if (use_large_llq_hdr) { - if ((llq->entry_size_ctrl_supported & - ENA_ADMIN_LIST_ENTRY_SIZE_256B) && - (ena_dev->tx_mem_queue_type == - ENA_ADMIN_PLACEMENT_POLICY_DEV)) { - max_tx_queue_size /= 2; - PMD_INIT_LOG(INFO, - "Forcing large headers and decreasing maximum Tx queue size to %d\n", + if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV && use_large_llq_hdr) { + /* intersection between driver configuration and device capabilities */ + if (dev->entry_size_ctrl_supported & ENA_ADMIN_LIST_ENTRY_SIZE_256B) { + if (dev->max_wide_llq_depth == MAX_WIDE_LLQ_DEPTH_UNSUPPORTED) { + /* Devices that do not support the double-sized ENA memory BAR will + * report max_wide_llq_depth as 0. In such case, driver halves the + * queue depth when working in large llq policy. + */ + max_tx_queue_size >>= 1; + PMD_INIT_LOG(INFO, + "large LLQ policy requires limiting Tx queue size to %u entries\n", max_tx_queue_size); + } else if (dev->max_wide_llq_depth < max_tx_queue_size) { + /* In case the queue depth that the driver calculated exceeds + * the maximal value that the device allows, it will be limited + * to that maximal value + */ + max_tx_queue_size = dev->max_wide_llq_depth; + } } else { - PMD_INIT_LOG(ERR, - "Forcing large headers failed: LLQ is disabled or device does not support large headers\n"); + PMD_INIT_LOG(INFO, + "Forcing large LLQ headers failed since device lacks this support\n"); } } From patchwork Tue Mar 12 18:07:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Brandes, Shai" X-Patchwork-Id: 138280 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 57F3843C94; Tue, 12 Mar 2024 19:10:32 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 7746C42E94; Tue, 12 Mar 2024 19:08:34 +0100 (CET) Received: from smtp-fw-80008.amazon.com (smtp-fw-80008.amazon.com [99.78.197.219]) by mails.dpdk.org (Postfix) with ESMTP id 5CD2742E9D for ; Tue, 12 Mar 2024 19:08:32 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.com; i=@amazon.com; q=dns/txt; s=amazon201209; t=1710266912; x=1741802912; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=ja3svov/9/rsXrw/sAw2OMYUt04O3A9qcwdHAxw/1EM=; b=s1onGYFjNiAY9X1HL73OB9jIPdonxBzG7wyzKqg4HuvGsEPO249D+5mP iuIL1+hKTMw4vWhR1LtiwNUQgvBfPB4ovPa3ee5GriKDI/vWJ8mnNari6 Z8/mlFRB9NzrwHqO1f45Fsum647hqPheRM1aXeum3Yky8/WQicHonJ7Bf E=; X-IronPort-AV: E=Sophos;i="6.07,119,1708387200"; d="scan'208";a="72647620" Received: from pdx4-co-svc-p1-lb2-vlan3.amazon.com (HELO smtpout.prod.us-east-1.prod.farcaster.email.amazon.dev) ([10.25.36.214]) by smtp-border-fw-80008.pdx80.corp.amazon.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Mar 2024 18:08:31 +0000 Received: from EX19MTAEUB001.ant.amazon.com [10.0.10.100:29174] by smtpin.naws.eu-west-1.prod.farcaster.email.amazon.dev [10.0.41.28:2525] with esmtp (Farcaster) id dceba6e2-d83c-4760-bffe-f54f1597027f; Tue, 12 Mar 2024 18:08:29 +0000 (UTC) X-Farcaster-Flow-ID: dceba6e2-d83c-4760-bffe-f54f1597027f Received: from EX19D007EUA001.ant.amazon.com (10.252.50.133) by EX19MTAEUB001.ant.amazon.com (10.252.51.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Tue, 12 Mar 2024 18:08:29 +0000 Received: from EX19MTAUWA001.ant.amazon.com (10.250.64.204) by EX19D007EUA001.ant.amazon.com (10.252.50.133) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Tue, 12 Mar 2024 18:08:28 +0000 Received: from HFA15-CG15235BS.amazon.com (10.85.143.174) by mail-relay.amazon.com (10.250.64.204) with Microsoft SMTP Server id 15.2.1258.28 via Frontend Transport; Tue, 12 Mar 2024 18:08:27 +0000 From: To: CC: , Shai Brandes Subject: [PATCH v4 30/31] net/ena: control path pure polling mode Date: Tue, 12 Mar 2024 20:07:15 +0200 Message-ID: <20240312180716.8515-31-shaibran@amazon.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240312180716.8515-1-shaibran@amazon.com> References: <20240312180716.8515-1-shaibran@amazon.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Shai Brandes This commit implements a new operation mode that enables purely polling-based functionality, eliminating the need for interrupts in the control path. This mode is not activated by default and can be toggled using the "control_poll_interval" devarg. When operating in this mode, periodic alarms are used to monitor the control queues. A non-zero value for this devarg is mandatory for control path functionality when binding ports to uio_pci_generic kernel module which lacks interrupt support. Signed-off-by: Shai Brandes Reviewed-by: Amit Bernstein --- doc/guides/nics/ena.rst | 43 ++++++--- doc/guides/rel_notes/release_24_03.rst | 2 + drivers/net/ena/ena_ethdev.c | 115 ++++++++++++++++++++----- drivers/net/ena/ena_ethdev.h | 5 ++ 4 files changed, 132 insertions(+), 33 deletions(-) diff --git a/doc/guides/nics/ena.rst b/doc/guides/nics/ena.rst index 725215b36d..f1dc6996ca 100644 --- a/doc/guides/nics/ena.rst +++ b/doc/guides/nics/ena.rst @@ -135,6 +135,19 @@ Runtime Configuration huge performance degradation. In general disabling LLQ is highly not recommended!** + * **control_poll_interval** (default 0) + + Enable polling-based functionality of the admin queues, eliminating the + need for interrupts in the control-path: + + 0 - Disable (Admin queue will work in interrupt mode). + + [1..1000] - Number of milliseconds to wait between periodic inspection of the admin queues. + + **A non-zero value for this devarg is mandatory for control path functionality + when binding ports to uio_pci_generic kernel module which lacks interrupt support.** + + ENA Configuration Parameters ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -173,23 +186,23 @@ Prerequisites #. Prepare the system as recommended by DPDK suite. This includes environment variables, hugepages configuration, tool-chains and configuration. -#. ENA PMD can operate with ``vfio-pci``(*) or ``igb_uio`` driver. +#. ENA PMD can operate with ``vfio-pci`` (*), ``igb_uio``, or ``uio_pci_generic`` driver. (*) ENAv2 hardware supports Low Latency Queue v2 (LLQv2). This feature reduces the latency of the packets by pushing the header directly through the PCI to the device, before the DMA is even triggered. For proper work - kernel PCI driver must support write combining (WC). + kernel PCI driver must support write-combining (WC). In DPDK ``igb_uio`` it must be enabled by loading module with ``wc_activate=1`` flag (example below). However, mainline's vfio-pci - driver in kernel doesn't have WC support yet (planed to be added). + driver in kernel doesn't have WC support yet (planned to be added). If vfio-pci is used user should follow `AWS ENA PMD documentation `_. -#. Insert ``vfio-pci`` or ``igb_uio`` kernel module using the command - ``modprobe vfio-pci`` or ``modprobe uio; insmod igb_uio.ko wc_activate=1`` - respectively. +#. For ``igb_uio``: + Insert ``igb_uio`` kernel module using the command ``modprobe uio; insmod igb_uio.ko wc_activate=1`` -#. For ``vfio-pci`` users only: +#. For ``vfio-pci``: + Insert ``vfio-pci`` kernel module using the command ``modprobe vfio-pci`` Please make sure that ``IOMMU`` is enabled in your system, or use ``vfio`` driver in ``noiommu`` mode:: @@ -198,7 +211,17 @@ Prerequisites To use ``noiommu`` mode, the ``vfio-pci`` must be built with flag ``CONFIG_VFIO_NOIOMMU``. -#. Bind the intended ENA device to ``vfio-pci`` or ``igb_uio`` module. +#. For ``uio_pci_generic``: + Insert ``uio_pci_generic`` kernel module using the command ``modprobe uio_pci_generic``. + Make sure that the IOMMU is disabled or is in passthrough mode. + For example: ``modprobe uio_pci_generic intel_iommu=off``. + + Note that when launching the application, the ``control_poll_interval`` devarg must be used with a non-zero value (1000 is recommended) + as ``uio_pci_generic`` lacks interrupt support. The control-path (admin queues) of the ENA require poll-mode + to process command completion and asynchronous notification from the device. + For example: ``dpdk-app -a "00:06.0,control_path_poll_interval=1000"``. + +#. Bind the intended ENA device to ``vfio-pci``, ``igb_uio``, or ``uio_pci_generic`` module. At this point the system should be ready to run DPDK applications. Once the application runs to completion, the ENA can be detached from attached module if @@ -207,7 +230,7 @@ necessary. **Rx interrupts support** ENA PMD supports Rx interrupts, which can be used to wake up lcores waiting for -input. Please note that it won't work with ``igb_uio``, so to use this feature, +input. Please note that it won't work with ``igb_uio`` and ``uio_pci_generic`` so to use this feature, the ``vfio-pci`` should be used. ENA handles admin interrupts and AENQ notifications on separate interrupt. @@ -218,7 +241,7 @@ will fail. **Note about usage on \*.metal instances** On AWS, the metal instances are supporting IOMMU for both arm64 and x86_64 -hosts. +hosts. Note that ``uio_pci_generic`` lacks IOMMU support and cannot be used for metal instances. * x86_64 (e.g. c5.metal, i3.metal): IOMMU should be disabled by default. In that situation, the ``igb_uio`` can diff --git a/doc/guides/rel_notes/release_24_03.rst b/doc/guides/rel_notes/release_24_03.rst index bee2429ba0..33d094a645 100644 --- a/doc/guides/rel_notes/release_24_03.rst +++ b/doc/guides/rel_notes/release_24_03.rst @@ -111,6 +111,8 @@ New Features * Added `normal_llq_hdr` devarg that enforce normal llq header policy. * Added support for LLQ header size recommendation from the device. * Allowed large LLQ with 1024 entries when the device supports enlarged memory BAR. + * Added `control_poll_interval` devarg that configure control-path to work in poll-mode. + * Added support for binding ports to `uio_pci_generic` kernel module. * **Updated Atomic Rules' Arkville driver.** diff --git a/drivers/net/ena/ena_ethdev.c b/drivers/net/ena/ena_ethdev.c index c7c2eef92f..1707d5f2c2 100644 --- a/drivers/net/ena/ena_ethdev.c +++ b/drivers/net/ena/ena_ethdev.c @@ -3,6 +3,7 @@ * All rights reserved. */ +#include #include #include #include @@ -36,6 +37,8 @@ #define ENA_MIN_RING_DESC 128 +#define USEC_PER_MSEC 1000UL + #define BITS_PER_BYTE 8 #define BITS_PER_TYPE(type) (sizeof(type) * BITS_PER_BYTE) @@ -90,6 +93,14 @@ struct ena_stats { * huge performance degradation on 6th generation AWS instances. */ #define ENA_DEVARG_ENABLE_LLQ "enable_llq" +/* + * Controls the period of time (in milliseconds) between two consecutive inspections of + * the control queues when the driver is in poll mode and not using interrupts. + * By default, this value is zero, indicating that the driver will not be in poll mode and will + * use interrupts. A non-zero value for this argument is mandatory when using uio_pci_generic + * driver. + */ +#define ENA_DEVARG_CONTROL_PATH_POLL_INTERVAL "control_path_poll_interval" /* * Each rte_memzone should have unique name. @@ -266,7 +277,8 @@ static uint64_t ena_get_rx_queue_offloads(struct ena_adapter *adapter); static uint64_t ena_get_tx_queue_offloads(struct ena_adapter *adapter); static int ena_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info); -static void ena_interrupt_handler_rte(void *cb_arg); +static void ena_control_path_handler(void *cb_arg); +static void ena_control_path_poll_handler(void *cb_arg); static void ena_timer_wd_callback(struct rte_timer *timer, void *arg); static void ena_destroy_device(struct rte_eth_dev *eth_dev); static int eth_ena_dev_init(struct rte_eth_dev *eth_dev); @@ -878,10 +890,14 @@ static int ena_close(struct rte_eth_dev *dev) ret = ena_stop(dev); adapter->state = ENA_ADAPTER_STATE_CLOSED; - rte_intr_disable(intr_handle); - rc = rte_intr_callback_unregister_sync(intr_handle, ena_interrupt_handler_rte, dev); - if (unlikely(rc != 0)) - PMD_INIT_LOG(ERR, "Failed to unregister interrupt handler\n"); + if (!adapter->control_path_poll_interval) { + rte_intr_disable(intr_handle); + rc = rte_intr_callback_unregister_sync(intr_handle, ena_control_path_handler, dev); + if (unlikely(rc != 0)) + PMD_INIT_LOG(ERR, "Failed to unregister interrupt handler\n"); + } else { + rte_eal_alarm_cancel(ena_control_path_poll_handler, dev); + } ena_rx_queue_release_all(dev); ena_tx_queue_release_all(dev); @@ -1885,15 +1901,33 @@ static int ena_device_init(struct ena_adapter *adapter, return rc; } -static void ena_interrupt_handler_rte(void *cb_arg) +static void ena_control_path_handler(void *cb_arg) { struct rte_eth_dev *dev = cb_arg; struct ena_adapter *adapter = dev->data->dev_private; struct ena_com_dev *ena_dev = &adapter->ena_dev; - ena_com_admin_q_comp_intr_handler(ena_dev); - if (likely(adapter->state != ENA_ADAPTER_STATE_CLOSED)) + if (likely(adapter->state != ENA_ADAPTER_STATE_CLOSED)) { + ena_com_admin_q_comp_intr_handler(ena_dev); ena_com_aenq_intr_handler(ena_dev, dev); + } +} + +static void ena_control_path_poll_handler(void *cb_arg) +{ + struct rte_eth_dev *dev = cb_arg; + struct ena_adapter *adapter = dev->data->dev_private; + int rc; + + if (likely(adapter->state != ENA_ADAPTER_STATE_CLOSED)) { + ena_control_path_handler(cb_arg); + rc = rte_eal_alarm_set(adapter->control_path_poll_interval, + ena_control_path_poll_handler, cb_arg); + if (unlikely(rc != 0)) { + PMD_DRV_LOG(ERR, "Failed to retrigger control path alarm\n"); + ena_trigger_reset(adapter, ENA_REGS_RESET_GENERIC); + } + } } static void check_for_missing_keep_alive(struct ena_adapter *adapter) @@ -2363,20 +2397,29 @@ static int eth_ena_dev_init(struct rte_eth_dev *eth_dev) rte_spinlock_init(&adapter->admin_lock); - rte_intr_callback_register(intr_handle, - ena_interrupt_handler_rte, - eth_dev); - rte_intr_enable(intr_handle); - ena_com_set_admin_polling_mode(ena_dev, false); + if (!adapter->control_path_poll_interval) { + /* Control path interrupt mode */ + rte_intr_callback_register(intr_handle, ena_control_path_handler, eth_dev); + rte_intr_enable(intr_handle); + ena_com_set_admin_polling_mode(ena_dev, false); + } else { + /* Control path polling mode */ + rc = rte_eal_alarm_set(adapter->control_path_poll_interval, + ena_control_path_poll_handler, eth_dev); + if (unlikely(rc != 0)) { + PMD_DRV_LOG(ERR, "Failed to set control path alarm\n"); + goto err_control_path_destroy; + } + } ena_com_admin_aenq_enable(ena_dev); - rte_timer_init(&adapter->timer_wd); adapters_found++; adapter->state = ENA_ADAPTER_STATE_INIT; return 0; - +err_control_path_destroy: + rte_free(adapter->drv_stats); err_rss_destroy: ena_com_rss_destroy(ena_dev); err_delete_debug_area: @@ -3657,9 +3700,9 @@ static int ena_process_uint_devarg(const char *key, { struct ena_adapter *adapter = opaque; char *str_end; - uint64_t uint_value; + uint64_t uint64_value; - uint_value = strtoull(value, &str_end, DECIMAL_BASE); + uint64_value = strtoull(value, &str_end, DECIMAL_BASE); if (value == str_end) { PMD_INIT_LOG(ERR, "Invalid value for key '%s'. Only uint values are accepted.\n", @@ -3668,12 +3711,12 @@ static int ena_process_uint_devarg(const char *key, } if (strcmp(key, ENA_DEVARG_MISS_TXC_TO) == 0) { - if (uint_value > ENA_MAX_TX_TIMEOUT_SECONDS) { + if (uint64_value > ENA_MAX_TX_TIMEOUT_SECONDS) { PMD_INIT_LOG(ERR, "Tx timeout too high: %" PRIu64 " sec. Maximum allowed: %d sec.\n", - uint_value, ENA_MAX_TX_TIMEOUT_SECONDS); + uint64_value, ENA_MAX_TX_TIMEOUT_SECONDS); return -EINVAL; - } else if (uint_value == 0) { + } else if (uint64_value == 0) { PMD_INIT_LOG(INFO, "Check for missing Tx completions has been disabled.\n"); adapter->missing_tx_completion_to = @@ -3681,9 +3724,27 @@ static int ena_process_uint_devarg(const char *key, } else { PMD_INIT_LOG(INFO, "Tx packet completion timeout set to %" PRIu64 " seconds.\n", - uint_value); + uint64_value); adapter->missing_tx_completion_to = - uint_value * rte_get_timer_hz(); + uint64_value * rte_get_timer_hz(); + } + } else if (strcmp(key, ENA_DEVARG_CONTROL_PATH_POLL_INTERVAL) == 0) { + if (uint64_value > ENA_MAX_CONTROL_PATH_POLL_INTERVAL_MSEC) { + PMD_INIT_LOG(ERR, + "Control path polling interval is too long: %" PRIu64 " msecs. " + "Maximum allowed: %d msecs.\n", + uint64_value, ENA_MAX_CONTROL_PATH_POLL_INTERVAL_MSEC); + return -EINVAL; + } else if (uint64_value == 0) { + PMD_INIT_LOG(INFO, + "Control path polling interval is set to zero. Operating in " + "interrupt mode.\n"); + adapter->control_path_poll_interval = 0; + } else { + PMD_INIT_LOG(INFO, + "Control path polling interval is set to %" PRIu64 " msecs.\n", + uint64_value); + adapter->control_path_poll_interval = uint64_value * USEC_PER_MSEC; } } @@ -3728,6 +3789,7 @@ static int ena_parse_devargs(struct ena_adapter *adapter, ENA_DEVARG_NORMAL_LLQ_HDR, ENA_DEVARG_MISS_TXC_TO, ENA_DEVARG_ENABLE_LLQ, + ENA_DEVARG_CONTROL_PATH_POLL_INTERVAL, NULL, }; struct rte_kvargs *kvlist; @@ -3757,6 +3819,12 @@ static int ena_parse_devargs(struct ena_adapter *adapter, goto exit; rc = rte_kvargs_process(kvlist, ENA_DEVARG_ENABLE_LLQ, ena_process_bool_devarg, adapter); + if (rc != 0) + goto exit; + rc = rte_kvargs_process(kvlist, ENA_DEVARG_CONTROL_PATH_POLL_INTERVAL, + ena_process_uint_devarg, adapter); + if (rc != 0) + goto exit; exit: rte_kvargs_free(kvlist); @@ -3979,7 +4047,8 @@ RTE_PMD_REGISTER_PARAM_STRING(net_ena, ENA_DEVARG_LARGE_LLQ_HDR "=<0|1> " ENA_DEVARG_NORMAL_LLQ_HDR "=<0|1> " ENA_DEVARG_ENABLE_LLQ "=<0|1> " - ENA_DEVARG_MISS_TXC_TO "="); + ENA_DEVARG_MISS_TXC_TO "=" + ENA_DEVARG_CONTROL_PATH_POLL_INTERVAL "=<0-1000>"); RTE_LOG_REGISTER_SUFFIX(ena_logtype_init, init, NOTICE); RTE_LOG_REGISTER_SUFFIX(ena_logtype_driver, driver, NOTICE); #ifdef RTE_ETHDEV_DEBUG_RX diff --git a/drivers/net/ena/ena_ethdev.h b/drivers/net/ena/ena_ethdev.h index 7358f28caf..7513a3f6d5 100644 --- a/drivers/net/ena/ena_ethdev.h +++ b/drivers/net/ena/ena_ethdev.h @@ -44,6 +44,8 @@ #define ENA_MONITORED_TX_QUEUES 3 #define ENA_DEFAULT_MISSING_COMP 256U +#define ENA_MAX_CONTROL_PATH_POLL_INTERVAL_MSEC 1000 + /* While processing submitted and completed descriptors (rx and tx path * respectively) in a loop it is desired to: * - perform batch submissions while populating submission queue @@ -348,6 +350,9 @@ struct ena_adapter { uint64_t memzone_cnt; + /* Time (in microseconds) of the control path queues monitoring interval */ + uint64_t control_path_poll_interval; + /* * Helper variables for holding the information about the supported * metrics. From patchwork Tue Mar 12 18:07:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Brandes, Shai" X-Patchwork-Id: 138281 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9309C43C94; Tue, 12 Mar 2024 19:10:39 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3A4D142E9E; Tue, 12 Mar 2024 19:08:36 +0100 (CET) Received: from smtp-fw-52004.amazon.com (smtp-fw-52004.amazon.com [52.119.213.154]) by mails.dpdk.org (Postfix) with ESMTP id 8569142EA3 for ; Tue, 12 Mar 2024 19:08:34 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.com; i=@amazon.com; q=dns/txt; s=amazon201209; t=1710266915; x=1741802915; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=h42vkGU9TMOP5wIVfHUwkHftGyF0gjO2jLt7vAK9Hxk=; b=Eoi4t4JFDH/0jUhY/VB5fhwo9EzmZpPtUd/4C0HzZSSrHcdHIYO5rIqd 3k+aE5OcrKi0GGOQD+9pTkKf8RGUb3TYL04NqAM/dzN/+QpPhMrkELpNE fcEQHFXhYucqXxEGcWarQG0GqvAMXVhXzVKOyEGaTiLc2DaUMN3Xhn4vw o=; X-IronPort-AV: E=Sophos;i="6.07,119,1708387200"; d="scan'208";a="191067730" Received: from iad12-co-svc-p1-lb1-vlan2.amazon.com (HELO smtpout.prod.us-east-1.prod.farcaster.email.amazon.dev) ([10.43.8.2]) by smtp-border-fw-52004.iad7.amazon.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Mar 2024 18:08:32 +0000 Received: from EX19MTAEUB002.ant.amazon.com [10.0.43.254:58418] by smtpin.naws.eu-west-1.prod.farcaster.email.amazon.dev [10.0.39.71:2525] with esmtp (Farcaster) id 296f1fd4-cb96-4a4c-a8e1-0a3ca99324bf; Tue, 12 Mar 2024 18:08:31 +0000 (UTC) X-Farcaster-Flow-ID: 296f1fd4-cb96-4a4c-a8e1-0a3ca99324bf Received: from EX19D007EUA001.ant.amazon.com (10.252.50.133) by EX19MTAEUB002.ant.amazon.com (10.252.51.79) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Tue, 12 Mar 2024 18:08:31 +0000 Received: from EX19MTAUWA001.ant.amazon.com (10.250.64.204) by EX19D007EUA001.ant.amazon.com (10.252.50.133) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Tue, 12 Mar 2024 18:08:31 +0000 Received: from HFA15-CG15235BS.amazon.com (10.85.143.174) by mail-relay.amazon.com (10.250.64.204) with Microsoft SMTP Server id 15.2.1258.28 via Frontend Transport; Tue, 12 Mar 2024 18:08:29 +0000 From: To: CC: , Shai Brandes Subject: [PATCH v4 31/31] net/ena: upgrade driver version to 2.9.0 Date: Tue, 12 Mar 2024 20:07:16 +0200 Message-ID: <20240312180716.8515-32-shaibran@amazon.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240312180716.8515-1-shaibran@amazon.com> References: <20240312180716.8515-1-shaibran@amazon.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Shai Brandes upgrade driver version to 2.9.0. Signed-off-by: Shai Brandes Reviewed-by: Amit Bernstein --- drivers/net/ena/ena_ethdev.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ena/ena_ethdev.c b/drivers/net/ena/ena_ethdev.c index 1707d5f2c2..7b697c150a 100644 --- a/drivers/net/ena/ena_ethdev.c +++ b/drivers/net/ena/ena_ethdev.c @@ -22,7 +22,7 @@ #include #define DRV_MODULE_VER_MAJOR 2 -#define DRV_MODULE_VER_MINOR 8 +#define DRV_MODULE_VER_MINOR 9 #define DRV_MODULE_VER_SUBMINOR 0 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l)